Three-level inverter DPWM and SVPWM smooth switching method, system, device and medium

Abstract

The invention relates to the technical field of energy storage converters, in particular to a three-level inverter DPWM and SVPWM smooth switching method and system, a medium and equipment, and the method comprises the steps: determining a current modulation mode which comprises the SVPWM and the DPWM; a first modulation coefficient and a second modulation coefficient are set, the first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage, the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage, and the sum of the first modulation coefficient and the second modulation coefficient is constantly 1; determining values of a first modulation coefficient and a second modulation coefficient based on the current modulation mode in response to a switching instruction of switching from the current modulation mode to a target modulation mode; and combining the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient and the DPWM common-mode voltage to generate a total modulation wave. According to the invention, non-stop switching of SVPWM and DPWM is realized, fast and stable neutral-point voltage and smooth transition of neutral-line current and three-phase current are ensured when two modulation modes are switched, and the smooth transition requirement of mode switching is met.

Description

Technical Field

[0001] This application relates to the field of energy storage converter technology, and in particular to a method, system, device and medium for smooth switching between DPWM and SVPWM in a three-level inverter. Background Technology

[0002] As new energy power generation systems develop towards medium- and high power levels, diode-clamped three-level inverters (INPCs) have become the core converter topology for megawatt-level photovoltaic and wind power grid connection due to their advantages such as high output waveform quality and low voltage stress on switching devices. Modulation technology is key to optimizing INPC performance, with mainstream solutions including Space Vector Pulse Width Modulation (SVPWM) and Discontinuous Pulse Width Modulation (DPWM).

[0003] Existing SVPWM (Sinusoidal Pulse Width Modulation) systems inject a zero-sequence voltage onto a SPWM modulation platform. The zero-sequence voltage is related to the maximum and minimum values ​​of the three-phase SPWM modulation waves, and the total modulation wave is the sum of the three-phase SPWM modulation waves and the zero-sequence voltage. DPWM (Distributed Mode Modulation) systems superimpose a common-mode voltage onto the SPWM modulation wave. The determination of the common-mode voltage is related to the sign of the three-phase SPWM modulation waves and is obtained by comparing the minimum values ​​of relevant parameters. The total modulation wave is the sum of the SPWM modulation wave and the common-mode voltage. Existing INPC (Integrated National Circuit) systems typically employ a single modulation strategy from either SVPWM or DPWM.

[0004] However, a fixed single modulation strategy cannot simultaneously meet the efficiency and power quality requirements across a wide load range. SVPWM, due to its fixed switching frequency, suffers from high losses and significant efficiency degradation under light loads; DPWM's harmonic characteristics are greatly affected by the power factor, easily leading to excessive common-mode current when the grid voltage is unbalanced. When switching from SVPWM to DPWM, traditional solutions require shutdown to update modulation parameters, resulting in grid interruption and violating grid regulations for continuous operation. If a forced switch is made during operation, the nonlinear differences between the vector sequences and zero vector distributions of the two modulation waves can cause problems such as slow DC bus midpoint potential stabilization, excessive neutral current surges, and inverter-side current distortion. Summary of the Invention

[0005] In order to solve the problems of existing INPC in modulation strategy application and switching process, this application provides a method, system, device and medium for smooth switching of DPWM and SVPWM in a three-level inverter.

[0006] In a first aspect, this application provides a method for smooth switching between DPWM and SVPWM in a three-level inverter, applied to a converter, including: Determine the current modulation mode, which includes SVPWM and DPWM; A first modulation coefficient and a second modulation coefficient are set. The first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage, and the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage. The sum of the first modulation coefficient and the second modulation coefficient is always 1. In response to a switching command to switch from the current modulation mode to the target modulation mode, the values ​​of the first modulation coefficient and the second modulation coefficient are determined based on the current modulation mode; The instantaneous voltage amplitude of the total modulation wave is generated by combining the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient, and the DPWM common-mode voltage.

[0007] By adopting the above technical solutions, the problem of shutdown required for switching modulation strategies in traditional INPC systems is solved, enabling non-stop switching between SVPWM and DPWM to meet the requirements of continuous grid operation. By merging the two common-mode voltages with weighting coefficients, problems such as DC bus midpoint potential fluctuations and neutral current surges during switching are avoided. Efficiency and power quality are balanced across a wide load range, adapting to the grid connection needs of megawatt-level photovoltaic or wind power.

[0008] In one specific implementation, the switching instruction includes: Within the set switching cycle, the first modulation coefficient and the second modulation coefficient are controlled to change continuously and smoothly in a linear trend; If switching from SVPWM to DPWM, the first modulation coefficient decreases by the first step increment starting from the initial value 1, and the second modulation coefficient increases by the first step increment starting from the initial value 0; If switching from DPWM to SVPWM, the first modulation coefficient increases with a second step value starting from the initial value of 0, and the second modulation coefficient decreases with a second step value starting from the initial value of 1. Wherein, the first step value is greater than the second step value.

[0009] By adopting the above technical solutions, the modulation coefficient is adjusted linearly to ensure that the coefficient changes without sudden changes, thus avoiding system impact caused by sudden changes in common-mode voltage; the coefficient increases or decreases synchronously when switching between SVPWM and DPWM, always keeping the sum of the coefficients at 1, ensuring a smooth transition of the total modulation wave; the impact of the switching process on the inverter output current and DC bus voltage is shortened, and the system stability during switching is improved.

[0010] In one specific implementation, the switching instruction further includes: Within the set switching period, the first modulation coefficient and the second modulation coefficient are controlled to change continuously and smoothly according to a non-linear trend; If switching from SVPWM to DPWM, the second modulation coefficient increases from an initial value of 0 to 1 according to the first curve rule, and the first modulation coefficient decreases from an initial value of 1 to 0 based on the constraint relationship between it and the second modulation coefficient. If switching from DPWM to SVPWM, the first modulation coefficient increases from an initial value of 0 to 1 according to the second curve rule, and the second modulation coefficient decreases from an initial value of 1 to 0 based on the constraint relationship between it and the first modulation coefficient.

[0011] By adopting the above technical solution, the nonlinear curve adjustment adapts to the needs of different switching stages. In the initial stage, it quickly leaves the initial mode to reduce the performance loss in the initial mode; in the later stage, it slowly converges to the target mode to avoid parameter overshoot. Compared with linear adjustment, it further reduces the inverter side current distortion rate during switching, improves grid-connected power quality, and adapts to grid voltage distortion scenarios.

[0012] In one specific feasible implementation, the smooth switching method for three-level inverter DPWM and SVPWM also includes: During the switching cycle, at least one state variable characterizing the stability of the system is monitored in real time, including the amplitude of DC bus midpoint voltage fluctuation or the rate of change of neutral current. When the state variable is greater than or equal to the safety threshold, the adjustment speed of the first modulation coefficient and the second modulation coefficient is reduced; When the state variable is less than the safety threshold, the adjustment speed of the first modulation coefficient and the second modulation coefficient is increased.

[0013] By adopting the above technical solution, key system state variables are monitored in real time, and the coefficient adjustment speed is dynamically adjusted to achieve adaptive control of the switching process; when the state variables exceed the standard, the speed is reduced to protect the safety of hardware such as clamping diodes and power switching transistors; when the state variables are normal, the speed is increased to shorten the switching cycle and reduce the transient losses during the switching process while ensuring stability.

[0014] In one specific feasible implementation, the smooth switching method for three-level inverter DPWM and SVPWM also includes: The process of reducing or increasing the adjustment speed is divided into a first stage and a second stage; In the first stage, the first modulation coefficient and the second modulation coefficient are adjusted using a first rate of change so that the modulation mode enters a hybrid mode between SVPWM and DPWM. In the second stage, the first modulation coefficient and the second modulation coefficient are adjusted using a second change rate to switch the modulation mode from the mixed mode to the target modulation mode.

[0015] By adopting the above technical solution, the efficiency and stability of the switching are adjusted in stages. In the first stage, the system quickly enters the hybrid mode and gets rid of the disadvantages of the initial mode. In the second stage, the system smoothly switches to the target mode to avoid system fluctuations when approaching the target mode. This solves the efficiency problem of single-rate adjustment and adapts to the wide operating conditions of INPC.

[0016] In one specific implementation scheme, the division between the first stage and the second stage is based on at least one of the following: The stage division node is defined by the fact that the values ​​of the first modulation coefficient and the second modulation coefficient reach a preset intermediate threshold. The fixed time proportion of the switching cycle is used as the stage division node; The state variable entering a preset stable interval is used as the stage division node; In the first stage, the first rate of change is configured to prioritize causing the system to deviate from the initial modulation mode; in the second stage, the second rate of change is configured to prioritize causing the system to stably converge to the target modulation mode.

[0017] By adopting the above technical solutions, the multi-dimensional stage division is flexibly adapted to the system state. When the coefficient reaches the intermediate threshold, it accurately enters the hybrid mode. When the time ratio meets the standard, it ensures the switching progress. When the state variables are stable, it converges in advance. It avoids the stage division deviation caused by relying on a single basis, ensures that the first stage leaves the initial mode and the second stage converges stably, and improves the controllability of the switching.

[0018] In one specific implementation scheme, the instantaneous voltage amplitude of the total modulated wave generated by combining the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient, and the DPWM common-mode voltage includes: The SVPWM common-mode voltage is calculated based on the maximum and minimum values ​​of the three-phase SPWM modulation wave; The DPWM common-mode voltage is calculated based on the polarity and magnitude relationship of the three-phase SPWM modulation wave; The formula for calculating the instantaneous voltage amplitude of the total modulated wave includes: U abcMOD =U abc +n*U svpwm_z +m*U dpwm_z ; Among them, U abcMOD It is the instantaneous voltage amplitude of the total modulated wave; U abcIt is the three-phase SPWM modulated wave voltage; n is the first modulation coefficient, m is the second modulation coefficient; U svpwm_z It is the SVPWM common-mode voltage, U dpwm_z It is the DPWM common-mode voltage.

[0019] By adopting the above technical solution, the calculation logic of the two common-mode voltages is clarified, and the weighted fusion is used to generate a continuous and smooth synthetic common-mode voltage, avoiding sudden changes in common-mode voltage during switching; this provides a basis for the smoothness of the total modulation waveform, and ultimately ensures the quality of the grid-connected current waveform, which meets the requirements of the power grid specifications.

[0020] Secondly, this application also provides a smooth switching system for DPWM and SVPWM in a three-level inverter, comprising: The mode determination module is used to determine the current modulation mode, which includes SVPWM and DPWM. A coefficient configuration module is used to set a first modulation coefficient and a second modulation coefficient, wherein the first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage and the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage; The coefficient adjustment module is used to respond to the switching command from the current modulation mode to another modulation mode and adjust the values ​​of the first modulation coefficient and the second modulation coefficient based on the current modulation mode. The control module is used to generate the total modulation wave and to complete the switching when the first modulation coefficient and the second modulation coefficient reach the values ​​corresponding to the target modulation mode.

[0021] Thirdly, this application also provides an electronic device, including a processor, a memory, a user interface, and a network interface. The memory is used to store instructions, the user interface and the network interface are used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to enable the electronic device to perform a three-level inverter DPWM and SVPWM smooth switching method.

[0022] Fourthly, this application also provides a computer-readable storage medium storing multiple instructions adapted for loading and executing by a processor a smooth switching method for a three-level inverter DPWM and SVPWM.

[0023] In summary, this application includes at least one of the following beneficial effects: 1. This application solves the problem of grid interruption or forced switching caused by the need to shut down the traditional INPC system for switching modulation strategies; by dynamically adjusting the weighting coefficients and smoothly transitioning the common-mode voltage, the switching between the two modulation modes is uninterrupted, and the DC bus neutral point potential stabilizes quickly, the neutral current is not impacted, and the inverter side current is not distorted, thus meeting the grid's requirements for continuous operation.

[0024] 2. This application breaks through the limitations of a single modulation strategy. Under light load, it switches to DPWM to reduce switching losses by reducing switching actions; under heavy load or grid voltage distortion, it switches to SVPWM to ensure power quality by relying on its low current distortion characteristics, which is suitable for the wide load conditions of megawatt-level photovoltaic or wind power grid connection.

[0025] 3. This application avoids the risks of slow and stable neutral point potential threatening clamping diodes, large neutral current surges, and inverter-side current distortion during traditional forced switching. During the switching process, the modulation wave is always in a mixed adaptation state, and the three-phase current on the grid side can smoothly transition. It ensures the stability and reliability of the INPC system from both hardware protection and operational status aspects, and meets the safety operation standards of medium and high power level new energy power generation systems. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating a smooth switching method for DPWM and SVPWM in a three-level inverter provided in an embodiment of this application; Figure 2 This is a circuit diagram of a diode-clamped three-level inverter provided in an embodiment of this application; Figure 3 This is a simulated signal diagram of the neutral current using traditional methods; Figure 4 This is a simulated signal diagram of the neutral current provided in an embodiment of this application; Figure 5 This is a simulated signal diagram of the midpoint voltage using the traditional method; Figure 6 This is a simulated signal diagram of the midpoint voltage provided in the embodiments of this application; Figure 7 This is a simulated signal diagram of the inverter-side current using traditional methods; Figure 8 This is a simulated signal diagram of the inverter-side current provided in an embodiment of this application; Figure 9 This is a diagram of the analog signal of the modulated wave provided in the embodiments of this application; Figure 10 This is a simulated signal diagram of three-phase current provided in the embodiments of this application. Detailed Implementation

[0027] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to any or all possible combinations including one or more of the listed items.

[0028] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0030] refer to Figure 1 , Figure 1 This illustration shows a flowchart of a smooth switching method for DPWM and SVPWM in a three-level inverter according to an embodiment of this application. This method can be implemented using a computer program, a microcontroller, or run on a three-level inverter DPWM and SVPWM smooth switching system. The computer program can be integrated into a computer device or run as a standalone utility application. Specifically, the method includes steps S100 to S400, as follows: S100: Determine the current modulation mode, which includes SVPWM and DPWM; In some embodiments, the modulation mode of INPC operation is determined, which includes both SVPWM and DPWM.

[0031] refer to Figure 2 The INPC comprises a bus capacitor module, a three-phase bridge arm module, and a filter module connected in sequence. The bus capacitor module includes a DC voltage source U. dc upper bus capacitor C up Lower bus capacitor U down Upper bus capacitor C up The first terminal is connected to a DC voltage source U dc The positive terminal is connected to the second terminal, which is connected to the lower bus capacitor U. down The first end forms the midpoint O of the DC bus. The lower bus capacitor U... down The second terminal is connected to a DC voltage source U dc The negative electrode.

[0032] The three-phase bridge arm module includes three identical phase A, phase B, and phase C bridge arm units. Each bridge arm unit includes four insulated-gate bipolar transistors (IGBTs), namely S11-S14, S21-S24, and S31-S34. Each IGBT is connected in anti-parallel to one freewheeling diode, namely D11-D14, D21-D24, and D31-D34.

[0033] Phase A bridge arm unit includes two clamping diodes, D1 and D2. The anode of D1 is connected to the output terminal of phase A, and the cathode is connected to the junction of the lower end of S11 and the upper end of S12, used to clamp the output level of phase A to near the upper bus voltage level Udc / 2. The cathode of D2 is connected to the output terminal of phase A, and the anode is connected to the junction of the lower end of S13 and the upper end of S14, used to clamp the output level of phase A to near the lower bus voltage level -Udc / 2. The upper end of S11 is connected to C... up The lower end of S11 connects to the upper end of S12, and this node connects to the cathode of clamping diode D1; the lower end of S12 connects to the upper end of S13, forming phase A output terminal A; this point connects to the anode of D1 and the cathode of D2. The lower end of S13 connects to the upper end of S14, and this node connects to the anode of D2; the lower end of S14 connects to C. down Top.

[0034] The B-phase bridge arm unit includes two clamping diodes D3 and D4, and the C-phase bridge arm unit includes two clamping diodes D5 and D6. The connection logic is the same as that of D1 and D2 in phase A, which respectively realizes the level clamping of phase B and phase C.

[0035] In the filter module, resistor r a One end is connected to A, and the other end is connected to inductor L. a One end; L a The other end is connected to a filter capacitor C. a One end is the current i on the A-phase bridge arm side. La Load side current i a The flow through the node; resistance r b One end is connected to B, and the other end is connected to inductor L. b One end; L b The other end is connected to a filter capacitor C. b One end is the B-phase bridge arm side current i Lb Load side current i b The flow through the node; resistance r c One end is connected to C, and the other end is connected to inductor L. c One end; L c The other end is connected to a filter capacitor C. c One end is the current i on the C-phase bridge arm side. Lc Load side current i c The nodes through which the flow passes. Ca C b C c The other end is connected to the neutral point N, forming a star-shaped filter structure; the neutral inductor L n Connected in series between the midpoints O and N of the DC bus, the neutral current i n Flowing through L n The three-phase load is connected between the filter output terminals of phases A, B, and C and N, and receives the filtered AC power.

[0036] After system startup and initialization, or during normal grid-connected operation, the inverter's core control unit performs the current modulation mode determination operation. This core control unit may include an embedded MCU, FPGA, or dedicated digital signal processor (DSP). The modulation mode determination operation may include: The control unit detects the modulation mode identifier information stored internally. Specifically, the non-volatile storage module of the control unit has a preset modulation mode identifier bit. This identifier bit uses binary encoding or a specific numerical encoding. The control unit reads the current value of this identifier bit to preliminarily determine the operating mode. The non-volatile storage module can include EEPROM or Flash, and the encoding can include: "01" corresponding to SVPWM, and "10" corresponding to DPWM. Verify the current status of the relevant control parameters. Specifically, retrieve the control parameters corresponding to SVPWM and DPWM respectively: for SVPWM, the control parameters include the zero-sequence voltage injection enable flag and the corresponding zero-sequence voltage calculation parameters; for DPWM, the control parameters include the zero vector redistribution parameters. By checking the enable status and current value of the parameters, confirm the modulation mode a second time. The inverter output signal characteristics are collected and analyzed. Specifically, the three-phase current and three-phase voltage signals at the inverter output terminal are collected in real time using the inverter's AC side current and voltage sensors and transmitted to the signal processing module. The signal processing module performs harmonic analysis on the collected signals and calculates the total harmonic distortion (THD). If the THD conforms to SVPWM, it is initially determined to be SVPWM. The switching frequency is calculated by detecting the drive signal period of the power switching transistors. If the switching frequency conforms to DPWM, it is further determined to be DPWM.

[0037] By cross-validating through at least two of the above methods, the current stable modulation mode is determined to be SVPWM or DPWM. The determination result is stored in the real-time data register of the control unit, providing a clear initial state basis for coefficient adjustment after receiving the switching command, and avoiding abnormal switching process due to misjudgment of the initial mode.

[0038] S200. Set the first modulation coefficient and the second modulation coefficient. The first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage, and the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage. The sum of the first modulation coefficient and the second modulation coefficient is always 1. Based on the current operating mode, the first modulation coefficient (denoted as n, associated with SVPWM common-mode voltage) and the second modulation coefficient (denoted as m, associated with DPWM common-mode voltage) are initially configured.

[0039] If the current mode is SVPWM, the initial value of the first modulation coefficient n is configured to a preset value that fully carries the SVPWM common-mode voltage weight, and the initial value of the second modulation coefficient m is configured to a preset value that has no DPWM common-mode voltage contribution. If the current mode is DPWM, then the configuration is reversed, setting the initial value of n to a preset value with no SVPWM common-mode voltage contribution, and setting the initial value of m to a preset value that fully carries the DPWM common-mode voltage weight.

[0040] In some embodiments, a logic circuit composed of an adder and a comparator is used to collect the current values ​​of n and m in real time and perform a summation operation. If the result deviates from 1, the value of m is automatically corrected through a feedback circuit. A constraint statement is implanted in the coefficient adjustment program. After each update of the value of n or m, the assignment operation of m=1-n is automatically executed to ensure that the sum of the two is still 1 after the update.

[0041] Through the above configuration and constraints, the values ​​of n and m can always accurately reflect the contribution ratio of the two common-mode voltages in the total modulated wave.

[0042] S300, in response to a switching command to switch from the current modulation mode to the target modulation mode, determine the values ​​of the first modulation coefficient and the second modulation coefficient based on the current modulation mode; In some embodiments, the switching command is triggered and transmitted to the control unit in any of the following ways: Users input switching commands through the human-computer interaction interface, and the commands are transmitted to the control unit via the communication module. The system's load detection module collects the load power signal from the DC or AC side of the inverter in real time, calculates the current load rate, and compares it with a preset load threshold. When the load rate is lower than the light load threshold, it automatically triggers a "SVPWM to DPWM" switching command; when the load rate is higher than the heavy load threshold, it automatically triggers a "DPWM to SVPWM" switching command. The load detection module may include a current sensor and a power calculation unit.

[0043] Based on the above embodiments, as another optional embodiment, the switching instruction may include: S301. Within the set switching cycle, control the first modulation coefficient and the second modulation coefficient to change continuously and smoothly in a linear trend; In some embodiments, the switching cycle is preset by the control unit through simulation calculation based on the inverter's hardware inertia parameters and grid specifications. During the simulation, it is ensured that the midpoint voltage fluctuation amplitude and neutral current surge value within the switching cycle are both less than the voltage safety threshold and current safety threshold. The final determined total switching cycle is stored in the control unit's cycle register. The hardware inertia parameters may include the inductance and capacitance values ​​of the LCL filter and the switching speed of the power switch transistors; the grid specifications may include grid current interruption time limits. The control unit calculates the coefficient change per unit time, i.e., the linear change slope, based on the total switching cycle and the total coefficient adjustment (e.g., when switching from SVPWM to DPWM, the total adjustment of n is "initial value - target value", and the total adjustment of m is "target value - initial value"). Change = Total adjustment / Total switching cycle.

[0044] Among them, the change is a constant value to ensure that the change of n and m is consistent in each unit of time; The control unit starts a timer. The trigger period of the timer, which is also the coefficient adjustment interval, is synchronized with the switching cycle of the inverter to avoid conflict with the switching action. Each time the timer is triggered, the control unit reads the current values ​​of n and m from the coefficient register and adjusts n and m according to the preset linear change amount (e.g., when switching from SVPWM to DPWM, n = current n - change amount, m = current m + change amount). The adjusted n and m are written to the coefficient register, and the constraint logic checks whether the sum of the two is 1. If there is a deviation, the value of m is automatically corrected. Through the above operations, it is ensured that n and m always change linearly within the total switching cycle, avoiding sudden changes in the common-mode voltage caused by abrupt changes in the coefficients, thereby ensuring the stability of the total modulation wave and reducing the impact on the inverter output current and DC bus voltage.

[0045] S302. If switching from SVPWM to DPWM, the first modulation coefficient decreases by one step from the initial value of 1, and the second modulation coefficient increases by one step from the initial value of 0. According to the operating requirements of SVPWM mode, the initial value of n is set to the standard initial value of SVPWM mode, where n=1, so that the SVPWM common-mode voltage accounts for 100% of the total mode voltage, reflecting the low THD characteristics of SVPWM; the initial value of m is set to the standard initial value of DPWM coefficient in SVPWM mode, where m=0, so that the DPWM common-mode voltage has no contribution and does not affect the modulation effect of SVPWM. The first step value is preset by the control unit based on the maximum allowable switching frequency change rate of the switching transistor and the maximum allowable recovery speed of the neutral point voltage, and is specifically determined through experimental testing. During the test, the step size is gradually adjusted, and the neutral current impact value under different step sizes is recorded. The step size with the smallest impact value that meets the switching cycle requirement is selected as the first step value and stored in the step size register. The timer of the control unit is triggered synchronously with the switching cycle according to the preset adjustment interval, and then reads the current values ​​of n and m, as well as the first step value; Perform a decrement operation on n: n new =n current - First step input value; Perform an increment operation on m: m new =m current +First step value; Where, n new It is the value of n after execution. current It is the current value of n; m new This is the value of m after execution. current It is the current value of m.

[0046] Call constraint logic to verify n new +m new If n equals 1, then n is set to 1. new m new Write to the coefficient register; if not equal, force m to be written. new Corrected to 1-n new Then write it into the register; Collect the current midpoint voltage and neutral current signals, and calculate the signal fluctuation amplitude. If the signal fluctuation amplitude is less than the signal safety threshold, continue to adjust according to the first step value; if the fluctuation amplitude is greater than or equal to the signal safety threshold, temporarily multiply the first step value by the first proportional coefficient (such as 0.8) until the fluctuation returns to normal. By adjusting synchronously and in equal steps, the constraint relationship that n and m always sum to 1 is ensured. The SVPWM characteristics in the total modulation wave gradually weaken and the DPWM characteristics gradually strengthen, achieving a smooth transition.

[0047] S303. If switching from DPWM to SVPWM, the first modulation coefficient increases with a second step value starting from the initial value of 0, and the second modulation coefficient decreases with a second step value starting from the initial value of 1; wherein, the first step value is greater than the second step value.

[0048] Based on the operational requirements of DPWM mode, the initial value of n is set to the standard initial value of SVPWM coefficient in DPWM mode, where n=0, to ensure that the SVPWM common-mode voltage makes no contribution and fully preserves the low switching loss characteristics of DPWM; the initial value of m is set to the standard initial value of DPWM mode, where m=1, to ensure that the DPWM common-mode voltage accounts for 100% of the total common-mode voltage, reflecting the zero vector redistribution effect of DPWM. The determination logic for the second step value is similar to that of the first step value, and it is combined with the preset system response characteristics when switching from DPWM to SVPWM. Through experimental testing, the THD of the inverter side current under different step lengths is recorded. The step length with the smallest THD and that meets the switching cycle requirements is selected as the second step value. The second step value can be the same as or different from the first step value. It is determined according to the actual test results and stored in the step length register. The timer of the control unit is triggered synchronously with the switching cycle according to the preset adjustment interval, and then reads the current values ​​of n and m, as well as the second step value; Increment n: new =n current +Second step value; Perform a decrement operation on m: m new =m current -Second step value; Call constraint logic to verify n new +m new If n equals 1, then n is set to 1. new m new Write to the coefficient register; if not equal, force m to be written. new Corrected to 1-n new Then write it into the register; The three-phase voltage on the grid side is collected in real time by a voltage sensor, and the unbalance of the three-phase voltage is calculated. If the unbalance is less than the preset balance threshold, the adjustment continues according to the second step value. If the unbalance is greater than or equal to the preset balance threshold, the second step value is temporarily multiplied by the second proportional coefficient (such as 0.7) to avoid the common mode current from exceeding the standard. By synchronously increasing or decreasing, the DPWM characteristics in the total modulation waveform are gradually weakened and the SVPWM characteristics are gradually strengthened, and the switching losses and current THD are controlled within the allowable range during the switching process.

[0049] Combining the characteristics of SVPWM and DPWM modes, the first step value is usually larger than the second step value. The core advantage of SVPWM is its low THD, but the fixed switching frequency leads to high losses under light loads. DPWM's advantage is low switching losses, but its harmonic characteristics are significantly affected by the power factor. Switching from SVPWM to DPWM often occurs under light loads, with the goal of quickly reducing switching losses. In this case, the system's need to quickly escape the high-loss mode takes precedence over extreme stability, allowing for a larger step size to accelerate the switching, i.e., a larger first step value. Switching from DPWM to SVPWM often occurs under heavy loads or in scenarios with grid voltage distortion, with the goal of restoring low harmonic characteristics. In this case, strict control of current distortion is necessary to avoid exceeding THD limits during switching, thus requiring a smaller step size to ensure a smooth transition, i.e., a smaller second step value. Furthermore, under light loads, the system inertia is lower, and the risk of current surges during SVPWM to DPWM switching is smaller, allowing for larger step sizes; however, under heavy loads, the system energy is higher, and a large step size during DPWM to SVPWM switching can cause sudden current changes, triggering neutral current surges or neutral point voltage fluctuations. Therefore, the second step value needs to be smaller to ensure stability. Based on the above embodiments, as another optional embodiment, the switching instruction may further include: S304. Within the set switching cycle, control the first modulation coefficient and the second modulation coefficient to change continuously and smoothly according to a non-linear trend; Based on the different requirements of the switching phase, at least two nonlinear change rules are preset and stored in the function table. The nonlinear change rules may include: The exponential variation law, such as n=1-e^(-kt), where k is a preset decay coefficient, is used to achieve rapid coefficient changes, quickly exiting the initial mode and reducing performance loss in the initial mode. The trigonometric function variation pattern, such as n = 1 - cos(πt / T) / 2, where T is the total switching period, is used to achieve slow coefficient changes. This ensures the system converges stably to the target mode and avoids parameter overshoot when approaching the target mode.

[0050] The parameters of the nonlinear function are adjusted based on the current system state. The system state includes the amplitude of the midpoint voltage fluctuation and the rate of change of the neutral current; the parameters include the k value in the exponential law and the T value in the trigonometric function law.

[0051] If the system is stable, for example, if the midpoint voltage fluctuation amplitude is less than 50% of the voltage safety threshold, then increase the value of k to accelerate the initial change; If the system is unstable, for example, if the midpoint voltage fluctuation amplitude is greater than or equal to 50% of the voltage safety threshold, then decrease the value of k to slow down the initial changes.

[0052] Specifically, the control unit starts a timer, with the trigger cycle synchronized with the switching cycle. It reads the cumulative time from the start of the switching to the present and calculates the proportion t / T of the current time to the total switching cycle. Based on the time proportion, it determines the applicable nonlinear law, for example, using an exponential law when t / T < 30% and a trigonometric function law when t / T ≥ 30%. It substitutes the time proportion into the corresponding nonlinear function to calculate the target values ​​of n and m. It reads the current values ​​of n and m and gradually adjusts them to the target values, with each adjustment not exceeding the preset maximum allowable rate of change to avoid abrupt changes. It verifies whether the adjusted coefficients meet the requirements of weakening the current mode characteristics and enhancing the target mode characteristics. If they meet the requirements, they are written to the register; otherwise, the target values ​​are recalculated.

[0053] By using nonlinear adjustment, the rate of change of coefficients is adapted to the stability requirements of different switching stages of the system, ensuring that the common-mode voltage and total modulation wave always transition smoothly, and avoiding system fluctuations that may be caused by linear adjustment in local stages.

[0054] S305. If switching from SVPWM to DPWM, the second modulation coefficient increases from the initial value of 0 to 1 according to the first curve rule, and the first modulation coefficient decreases from the initial value of 1 to 0 based on the constraint relationship between the first and second modulation coefficients. An INPC inverter simulation model was built using simulation tools, and different nonlinear curves were input, such as exponential rising curves and quadratic rising curves. During the simulation, the amplitude of the midpoint voltage fluctuation, the value of the midline current surge, and the inverter-side current THD were monitored. The curve with the smallest fluctuation amplitude, the smallest surge value, and THD that conforms to the grid specifications was selected as the first curve. The mathematical expression of the first curve is stored in the curve parameter register of the control unit, including: m = 1 - cos(πt / (2T)).

[0055] Where T is the total switching period. This expression is used to ensure that n increases slowly in the initial stage of switching to avoid sudden current changes, and that n increases rapidly in the later stage to shorten the switching time; The initial value of n is the standard initial value of SVPWM mode (1), and the target value is the target value of SVPWM coefficient in DPWM mode (0); the initial value of m is the standard initial value of DPWM coefficient in SVPWM mode (0), and the target value is the standard target value of DPWM mode (1). After the timer is triggered, the current switching time t is read, and the ratio t / T is calculated; t / T is substituted into the first curve expression to calculate the target values ​​of n and m, including: m target =1-cos(πt / (2T)); n target =1-m target .

[0056] Where, m target The target value of m, n target It is the target value of n.

[0057] Read the current values ​​of n and m, and calculate the difference between the current value and the target value, including: Δn=n target -n current ; Δm=m target -m current .

[0058] Where, n current Δn is the current value of n, and Δn is the difference between the target value and the current value of n; m current Δm is the current value of m, and Δm is the difference between the target value of m and the current value.

[0059] If the absolute value of the difference is less than the first preset allowable deviation (e.g., 0.01), the target value is directly written to the register; if the absolute value of the difference is greater than or equal to the preset allowable deviation, it is readjusted to ensure that n decreases and m increases after each adjustment.

[0060] Guided by the first curve, the changes in n and m are always matched with the system response characteristics when switching from SVPWM to DPWM, ensuring that the SVPWM characteristics in the total modulation wave are smoothly weakened and the DPWM characteristics are smoothly enhanced.

[0061] S306. If switching from DPWM to SVPWM, the first modulation coefficient increases from the initial value of 0 to 1 according to the second curve, and the second modulation coefficient decreases from the initial value of 1 to 0 based on the constraint relationship between it and the first modulation coefficient.

[0062] The logic for determining the second curve is the same as that for the first curve. Different nonlinear curves are input into the simulation model, the THD of the inverter side current is monitored, and the curve with the smallest THD and the fastest recovery of the midpoint voltage is selected as the second curve. The mathematical expression for the second curve is stored in the curve parameter register, including: n = 1 - cos(πt / (2T)).

[0063] Where T is the total switching period. This expression is used to ensure that n increases slowly in the initial stage of switching to avoid sudden current changes, and that n increases rapidly in the later stage to shorten the switching time.

[0064] The initial value of n is the standard initial value of SVPWM coefficient in DPWM mode (0), and the target value is the standard target value of SVPWM mode (1); the initial value of m is the standard initial value of DPWM mode (1), and the target value is the target value of DPWM coefficient in SVPWM mode (0). After the timer is triggered, the current switching time t is read, and the ratio t / T is calculated; t / T is substituted into the second curve expression to calculate the target values ​​of n and m, including: n target =1-cos(πt / (2T)); m target =1-n target .

[0065] Where, m target The target value of m, n target It is the target value of n.

[0066] Read the current values ​​of n and m, and calculate the difference between the current value and the target value, including: Δn=n target -n current ; Δm=m target -m current .

[0067] Where, n current Δn is the current value of n, and Δn is the difference between the target value and the current value of n; m current Δm is the current value of m, and Δm is the difference between the target value of m and the current value.

[0068] If the absolute value of the difference is less than the second preset allowable deviation (e.g., 0.01), the target value is directly written to the register; if the absolute value of the difference is greater than or equal to the preset allowable deviation, it is readjusted to ensure that n increases and m decreases after each adjustment.

[0069] Guided by the second curve, the current distortion rate is always kept within the allowable range of the power grid specifications during the switch from DPWM to SVPWM, while ensuring rapid stabilization of the midpoint voltage.

[0070] S400, combined with the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient, and the DPWM common-mode voltage, generates the instantaneous voltage amplitude of the total modulation wave; Based on the above embodiments, as another optional embodiment, the instantaneous voltage amplitude of the total modulated wave is generated by combining the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient, and the DPWM common-mode voltage, including: The SVPWM common-mode voltage is calculated based on the maximum and minimum values ​​of the three-phase SPWM modulation wave. The DPWM common-mode voltage is calculated based on the polarity and magnitude relationship of the three-phase SPWM modulation wave. The formulas for calculating the instantaneous voltage amplitude of the total modulated wave include: U abcMOD =U abc +n*Usvpwm_z +m*U dpwm_z ; Among them, U abcMOD It is the instantaneous voltage amplitude of the total modulated wave; U abc It is a three-phase SPWM modulated wave voltage; n is the first modulation coefficient, m is the second modulation coefficient; U svpwm_z It is the SVPWM common-mode voltage, U dpwm_z It is the DPWM common-mode voltage.

[0071] In some embodiments, the SPWM generation module generates the instantaneous value U of the three-phase SPWM modulation wave based on the voltage command from the grid side and the output power requirement of the inverter. a U b U c This instantaneous value is transmitted to the common-mode voltage calculation module in real time; The maximum and minimum value extraction algorithm is called to calculate the maximum value U among the three-phase instantaneous values. max =max(U a U b U c ) and minimum value U min =min(U a U b U c The formula for calculating the SVPWM common-mode voltage includes: U svpwm_z =-0.5×(U max +U min ).

[0072] Among them, U svpwm_z It is the SVPWM common-mode voltage.

[0073] For U svpwm_z Filtering is performed to remove high-frequency noise and obtain a smooth U. svpwm_z ; The instantaneous value U of the three-phase SPWM modulated wave a U b U c Perform polarity determination separately: compare with the preset polarity determination threshold 0; if it is greater than 0, it is positive; if it is less than 0, it is negative. If U abc (U) abc =[U a U b U c If ]) is positive, then U abcH =1-U abc U abcL =U abc ; If U abc If it is negative, then U abcH=-U abc U abcL =1+U abc ; Three-phase U abcH The minimum value H in min =min(U aH U bH U cH Three-phase U abcL The minimum value L in min =min(U aL U bL U cL ); Take H min With L min The smaller value in, i.e., U dpwm_z The instantaneous value of U; dpwm_z Filtering is performed to remove noise; the formula for calculating the total modulated wave includes: U abcMOD =U abc +n*U svpwm_z +m*U dpwm_z ; U a_MOD =U a +n*U svpwm_z +m*U dpwm_z ; U b_MOD =U b +n*U svpwm_z +m*U dpwm_z ; U c_MOD =U c +n*U svpwm_z +m*U dpwm_z .

[0074] Among them, U abcMOD It is the total modulated wave, U abcMOD =[U a_MOD U b_MOD U c_MOD ].

[0075] The total modulation wave is transmitted to the drive module of the power switch. The drive module generates the PWM drive signal of the IGBT according to the amplitude of the total modulation wave and the switching period, and controls the switching of the switch to turn on and off, so as to achieve smooth switching of the modulation mode.

[0076] In some embodiments, when both the first modulation coefficient and the second modulation coefficient reach the preset value range corresponding to the target modulation mode and stabilize, it is determined that the modulation mode switching is complete and the target modulation mode is maintained in stable operation.

[0077] Specifically, based on the performance requirements of the target modulation mode, the target value ranges for n and m are preset, including: If the target mode is SVPWM, the target value range of n is 1 ± allowable deviation, and the target value range of m is 0 ± allowable deviation. If the target mode is DPWM, the target value range of n is 0 ± allowable deviation, and the target value range of m is 1 ± allowable deviation.

[0078] The allowable deviation (e.g., 0.01) is used to ensure that n or m is close to the target value, which is determined experimentally; the target value range is stored in the threshold register of the control unit.

[0079] Read the current values ​​of n and m and compare them with the target value range respectively; if the current values ​​of n and m are both within the target value range, start stabilization counting; if either value is outside the range, reset the stabilization counting; when the stabilization counting reaches the preset number of stabilization judgment cycles (such as N switching cycles, used to ensure continuous system stability), the judgment coefficient has stabilized and reached the target value.

[0080] To avoid misjudgments caused by relying solely on coefficients, the control unit synchronously monitors key system state variables: the amplitude of the midpoint voltage fluctuation must be less than the voltage safety threshold under the target mode; the rate of change of the neutral current must be less than the current safety threshold under the target mode; and the inverter-side current THD must be less than the THD allowable value under the target mode (e.g., <3% under SVPWM, <5% under DPWM).

[0081] If all state variables meet the requirements, the switchover is confirmed to be complete; if any variable does not meet the requirements, the coefficients are adjusted until the variable meets the criteria.

[0082] After the switch is completed, a switch completion command is generated and transmitted to the human-machine interface to prompt the user that the switch was successful; the values ​​of n and m are locked and set as fixed operating parameters in the target mode; the stable operation monitoring program of the target mode is started to collect parameters such as load power, grid voltage, and switching transistor temperature in real time. If the parameter changes exceed the preset operating threshold (such as load rate change > 10%), the mode re-evaluation is triggered to determine whether another switch is needed; if the parameters are normal, the current coefficient and modulation mode are maintained to ensure that the inverter continuously outputs electrical energy that complies with grid specifications.

[0083] By using multi-dimensional judgment and monitoring, we ensure the accuracy of the switchover and avoid system instability caused by prematurely locking the coefficients.

[0084] Based on the above embodiments, as another optional embodiment, the smooth switching method for DPWM and SVPWM in a three-level inverter further includes: S601. During the switching cycle, at least one state variable characterizing the stability of the system is monitored in real time. The state variable includes the amplitude of the DC bus midpoint voltage fluctuation or the rate of change of the neutral current. Specifically, the DC bus midpoint voltage is acquired using a DC bus midpoint voltage sensor (such as a Hall voltage sensor), and the neutral current is acquired using a neutral current sensor (such as a Hall current sensor). The analog signals acquired by the sensors are amplified and filtered, and then converted into digital signals using an ADC module. The digital signals converted by the ADC are read, and the actual values ​​of the state variables are calculated, including: The amplitude of the midpoint voltage fluctuation is calculated by taking the maximum and minimum values ​​of the midpoint voltage within the current sampling period, and the difference between the two values ​​is the fluctuation amplitude. The rate of change of the neutral current is calculated by dividing the difference between the current value of the neutral current in the current sampling period and the current value in the previous sampling period by the sampling period. The calculated state variable values ​​are stored in a data buffer with a depth sufficient to store at least 10 sampling periods of data. The real-time state variable values ​​are transmitted to the control unit via an internal communication bus, with the transmission period synchronized with the sampling period, ensuring that the control unit can monitor the stability of the system during the switching process in real time.

[0085] S602. When the state variable is greater than or equal to the safety threshold, reduce the adjustment speed of the first modulation coefficient and the second modulation coefficient. The safety threshold is set based on the inverter's hardware tolerance and grid specifications, including: The voltage safety threshold is set according to the maximum withstand voltage of the clamping diode. It can be set to 80% of the diode's reverse repetitive peak voltage VRRM to prevent the diode from being damaged by overvoltage. The current safety threshold is set according to the maximum allowable current change rate of the power switching transistor. It can be set to 70% of the maximum allowable current change rate to avoid damage to the switching transistor caused by excessive current change. Once the safety threshold is verified experimentally (e.g., by gradually increasing the load and recording the critical values ​​of the state variables), it is stored in the threshold register of the control unit.

[0086] Each sampling period reads the status variable value transmitted by the status monitoring module and compares it with the corresponding safety threshold, including: If any state variable value is greater than or equal to the corresponding safety threshold, the system is determined to be at risk of instability, and a speed reduction instruction is generated. If all state variable values ​​are less than the corresponding safety threshold, then maintain the current adjustment rate.

[0087] Upon receiving the speed reduction instruction, for the first and second modulation coefficients that exhibit linear trend changes, the first or second step value is read and multiplied by the first reduction ratio (e.g., 0.8) to obtain a new adjustment step size. The new step size is greater than or equal to the preset minimum step size to avoid adjustment stagnation. The current timer trigger period is read and multiplied by the second reduction ratio (e.g., 1.2, used to reduce the frequency of coefficient changes) to obtain a new timer trigger period. The new trigger period is less than or equal to the preset maximum interval to avoid excessively long switching cycles. The new adjustment step size and trigger period are written into the parameter register of the coefficient adjustment subroutine to update subsequent coefficient adjustment parameters.

[0088] After the speed is reduced, the status variables continue to be collected through the status monitoring module. If the status variable value is still ≥ the corresponding safety threshold, the step size reduction and cycle extension operations are repeated, with the same reduction ratio each time, until the status variable value is < the corresponding safety threshold. If the status variable value recovers to the safe range, the current reduction adjustment speed is maintained to avoid excessive reduction that leads to an excessively long switching cycle. Through the above closed-loop control, the system can quickly reduce the coefficient adjustment speed when instability risks occur, suppress abnormal fluctuations of state variables, and ensure the safe operation of hardware such as clamping diodes and power switching transistors.

[0089] S603. When the state variable is less than the safety threshold, increase the adjustment speed of the first modulation coefficient and the second modulation coefficient.

[0090] A preset stability threshold is set, which is a first percentage (e.g., 50%) of the safety threshold. This means that when the state variable value is less than the corresponding stability threshold, the system is considered to be in a stable state and ready to increase its adjustment speed. The state variable value is read and compared with the stability threshold every sampling period, including: If all state variable values ​​are less than the corresponding stability threshold, and the system maintains this state for multiple consecutive sampling periods (e.g., 3 periods), then the system is considered stable, and a speed increase instruction is generated. If the value of any state variable is greater than or equal to the corresponding stability threshold, the current adjustment speed will be maintained to avoid premature speed increases that could lead to fluctuations.

[0091] Upon receiving the speed increase instruction, for the first and second modulation coefficients that exhibit linear trend changes, the first or second step value is read and multiplied by the first increase ratio (e.g., 1.2) to obtain a new adjustment step size. The new step size is less than or equal to the preset maximum step size to avoid abrupt changes in the coefficients. The current timer trigger period is read and multiplied by the second increase ratio (e.g., 0.8, used to increase the frequency of coefficient changes) to obtain a new trigger period. The new trigger period is greater than or equal to the preset minimum interval to avoid conflicts with switching actions. The new step size and new interval are written to the parameter register of the coefficient adjustment subroutine to update subsequent adjustment parameters.

[0092] After the speed is increased, the status variables are collected through the status monitoring module. If the status variable value is still less than the corresponding stability judgment threshold, the increased speed is maintained. If the status variable value is greater than or equal to the corresponding stability judgment threshold, but less than the corresponding safety threshold, the speed is adjusted back to the level before the increase. If the status variable value is greater than or equal to the corresponding safety threshold, the speed is reduced. By employing a process of stability assessment, speed enhancement, and closed-loop monitoring, the switching cycle is shortened to the minimum and performance loss during the switching process is reduced while ensuring system stability.

[0093] Based on the above embodiments, as another optional embodiment, the smooth switching method for DPWM and SVPWM in a three-level inverter further includes: S604. The process of reducing or increasing the adjustment speed is divided into a first stage and a second stage. Based on the above embodiments, as another optional embodiment, the division between the first stage and the second stage includes at least one of the following criteria: The stage division node is defined by the fact that the values ​​of the first modulation coefficient and the second modulation coefficient reach a preset intermediate threshold. The fixed time proportion of the switching cycle is used as the stage division node; The stage division node is defined by the state variable entering the preset stable interval; In the first stage, the first rate of change is configured to prioritize causing the system to deviate from the initial modulation mode; in the second stage, the second rate of change is configured to prioritize causing the system to stably converge to the target modulation mode.

[0094] Three pre-defined criteria for stage division are used, with priorities assigned from highest to lowest, including: The first criterion is the intermediate threshold of the coefficient value. A preset intermediate threshold for the first coefficient is set (e.g., 0.5, which is the coefficient dividing point of the hybrid mode, at which point n and m each account for about 50%, and the modulation mode is a hybrid mode of SVPWM and DPWM); when n reaches the intermediate threshold, the stage switching is triggered. The second criterion is the switching time ratio. A preset threshold for the total switching cycle time ratio is used (e.g., 50%); when the current switching time reaches the specified ratio for the total switching cycle, a phased switching is triggered. The third criterion is the stable range of state variables. A preset stable range for state variables is established (e.g., midpoint voltage fluctuation amplitude < 30% of the corresponding safety threshold, neutral current change rate < 30% of the corresponding safety threshold); when a state variable enters this range, a phase switch is triggered. If the condition of the first criterion is met first, then switch according to the first criterion; if the first criterion is not met but the second criterion is met, then switch according to the second criterion; if neither of the first two conditions is met but the third criterion is met, then switch according to the third criterion.

[0095] Specifically, the current value of n is read to determine whether the intermediate threshold has been reached. If it has, a stage switching signal is generated and the switching time is recorded. If n has not reached the intermediate threshold, the ratio of the current switching time to the total switching cycle is read to determine whether the time ratio threshold has been reached. If it has, a stage switching signal is generated. If the time ratio threshold has not been reached, the current value of the state variable is read to determine whether the stable range has been entered. If it has, a stage switching signal is generated. After generating the stage switching signal, the stage flag bit is updated (e.g., flag bit 0 represents the first stage and 1 represents the second stage), and the switching time is stored in the stage data register.

[0096] S605. In the first stage, the first modulation coefficient and the second modulation coefficient are adjusted by the first change rate so that the modulation mode enters a mixed mode between SVPWM and DPWM. Based on the stage identifier bit, the first change rate parameter, including the first adjustment step size and the first adjustment interval, is called from the speed parameter register. After the call, the first adjustment step size is written into the step size register of the coefficient adjustment subroutine, and the first adjustment interval is written into the period register of the timer to complete the rate configuration.

[0097] At each first adjustment interval, read the current values ​​of n and m, and adjust according to the first adjustment step size, including: If the initial mode is SVPWM, then n=n current - First adjustment step size, m=m current +First adjustment step size; If the initial mode is DPWM, then n=n current + First adjustment step size, m=m current - First adjustment step size.

[0098] When initially set to SVPWM, check U svpwm_z Whether the contribution ratio (n×100%) decreases, to ensure that the low THD characteristic of SVPWM gradually weakens; When initially set to DPWM, check U dpwm_z Whether the contribution ratio (m×100%) decreases, ensuring that the low switching loss characteristics of DPWM gradually weaken; If the feature reduction requirement is met, the adjusted coefficients are written to the register; if not, the process is repeated to readjust the coefficients.

[0099] In some embodiments, monitoring of hybrid mode metrics during each adjustment period includes: The coefficient proportion, whether the current value of n is within the intermediate threshold ± allowable deviation range (e.g., 0.5 ± 0.05), at this time the contribution ratios of n and m are close, and the total modulated wave contains the characteristics of both modes simultaneously; Output characteristics: whether the THD of the inverter-side current is between the THD of SVPWM (e.g., <3%) and the THD of DPWM (e.g., <5%), and whether the switching frequency is between the switching frequencies of the two modes; If all the above hybrid mode indicators are met, it is determined that the transition to hybrid mode has been completed and the first stage ends. The control unit updates the stage flag bit to 1 and records the end time and final coefficient value of the first stage, providing a starting point for the adjustment of the second stage.

[0100] S606. In the second stage, the first modulation coefficient and the second modulation coefficient are adjusted using a second change rate so that the modulation mode is switched from the mixed mode to the target modulation mode.

[0101] Based on the stage identifier bit, the second change rate parameter is called from the speed parameter register, including the second adjustment step size and the second adjustment interval. After the call, the second adjustment step size is written to the step size register, and the second adjustment interval is written to the timer period register. The second adjustment step size is smaller than the first adjustment step size (e.g., 50% of the first adjustment step size), and the second adjustment interval is larger than the first adjustment interval (e.g., 200% of the first adjustment interval) to ensure a smoother adjustment. Every second adjustment interval, read the current values ​​of n and m, and adjust according to the second adjustment step size, including: If the target mode is DPWM, then n=n current - Second adjustment step size, m=m current +Second adjustment step size; If the target mode is SVPWM, then n=n current + Second adjustment step size, m=m current - Second adjustment step size.

[0102] When the target is DPWM, verify U dpwm_z Whether the contribution ratio (m×100%) increases, and whether the switching frequency gradually decreases to the typical frequency of DPWM; When the target is SVPWM, check U svpwm_z Whether the contribution ratio (n×100%) increases, and whether the current THD gradually decreases to the typical THD of SVPWM; If the feature enhancement requirements are met, the coefficients are written to the coefficient register; otherwise, the process is repeated to readjust the settings. In some embodiments, the current values ​​of n and m are read in each adjustment cycle to determine whether the target value range has been reached (e.g., when the target is SVPWM, n≥0.99, m≤0.01); the state variable values ​​are read to determine whether they are stable within the safe threshold range of the target mode; if the coefficients reach the target range and the state variables are stable, the convergence count continues; if the convergence count reaches the preset number of convergence determination cycles (e.g., 10 adjustment cycles), it is determined that the convergence to the target mode has been stable.

[0103] Once convergence to the target mode is determined, the second stage ends, generating a second stage end signal to trigger the final determination of the switchover completion; the adjustment process data of the second stage (such as coefficient change curves and state variable change curves) are recorded and stored in the fault diagnosis database for subsequent fault analysis; the stage flag bit is reset and the speed parameters are adjusted to prepare for the next possible switchover.

[0104] The second phase of gradual adjustment ensures a smooth transition from the hybrid mode to the target mode, and the system can quickly enter a stable operating state after the switch, meeting the requirements of power grid specifications and load.

[0105] refer to Figures 3 to 10 The smooth switching method between DPWM and SVPWM in a three-level inverter provided in this application ensures a smooth transition of the neutral current, rapid stabilization of the neutral point potential, and reduces the distortion of the inverter-side current. Simultaneously, the three-phase current on the grid side can also undergo a smooth transition.

[0106] This application embodiment also provides a three-level inverter DPWM and SVPWM smooth switching system, including: The mode determination module is used to determine the current modulation mode, which includes SVPWM and DPWM. The coefficient configuration module is used to set the first modulation coefficient and the second modulation coefficient. The first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage, and the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage. The coefficient adjustment module is used to respond to the switching command from the current modulation mode to another modulation mode and adjust the values ​​of the first modulation coefficient and the second modulation coefficient based on the current modulation mode. The control module is used to generate the total modulated wave and to switch when the first modulation coefficient and the second modulation coefficient reach the values ​​corresponding to the target modulation mode.

[0107] Based on the above embodiments, as another optional embodiment, this application embodiment may further include a computer storage medium, which may store multiple instructions adapted for loading and execution by a processor of a three-level inverter DPWM and SVPWM smooth switching method of the above embodiments. For the specific execution process, please refer to the detailed description of the above embodiments, which will not be repeated here.

[0108] Based on the above embodiments, as another optional embodiment, this application embodiment may further include an electronic device. The electronic device may include: at least one processor, at least one communication bus, a user interface, at least one network interface, and a memory.

[0109] The communication bus is used to enable communication between these components.

[0110] The user interface may include a display screen and a camera. Optional user interfaces may also include standard wired interfaces and wireless interfaces.

[0111] The network interface may include standard wired interfaces and wireless interfaces (such as Wi-Fi interfaces).

[0112] The processor may include one or more processing cores. It connects to various parts of the server via various interfaces and lines, executing instructions, programs, code sets, or instruction sets stored in memory, and accessing data stored in memory to perform various server functions and process data. Optionally, the processor may be implemented using at least one of the following hardware forms: Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor may integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content displayed on the screen; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor.

[0113] The memory may include random access memory (RAM) or read-only memory. Optionally, the memory may include a non-transitory computer-readable storage medium. The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor. As a computer storage medium, the memory may include an operating system, a network communication module, a user interface module, and an application program for a three-level inverter DPWM and SVPWM smooth switching method.

[0114] In electronic devices, the user interface is primarily used to provide an input interface for users and to acquire user input data. The processor can be used to call an application program stored in memory that stores a smooth switching method for a three-level inverter (DPWM) and SVPWM. When executed by one or more processors, this causes the electronic device to perform one or more methods as described in the above embodiments. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0115] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0116] In the various embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.

[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0118] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0119] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0120] The above are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Other embodiments of this disclosure will readily conceive of those skilled in the art upon consideration of the specification and the disclosure of practical truths.

[0121] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A method for smooth switching between DPWM and SVPWM in a three-level inverter, characterized in that, include: Determine the current modulation mode, which includes SVPWM and DPWM; A first modulation coefficient and a second modulation coefficient are set. The first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage, and the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage. The sum of the first modulation coefficient and the second modulation coefficient is always 1. In response to a switching command to switch from the current modulation mode to the target modulation mode, the values ​​of the first modulation coefficient and the second modulation coefficient are determined based on the current modulation mode; The instantaneous voltage amplitude of the total modulation wave is generated by combining the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient, and the DPWM common-mode voltage.

2. The method for smooth switching between DPWM and SVPWM in a three-level inverter according to claim 1, characterized in that, The switching instructions include: Within the set switching cycle, the first modulation coefficient and the second modulation coefficient are controlled to change continuously and smoothly in a linear trend; If switching from SVPWM to DPWM, the first modulation coefficient decreases by the first step increment starting from the initial value 1, and the second modulation coefficient increases by the first step increment starting from the initial value 0; If switching from DPWM to SVPWM, the first modulation coefficient increases with a second step value starting from the initial value of 0, and the second modulation coefficient decreases with a second step value starting from the initial value of 1. Wherein, the first step value is greater than the second step value.

3. The method for smooth switching between DPWM and SVPWM in a three-level inverter according to claim 1, characterized in that, The switching instruction also includes: Within the set switching period, the first modulation coefficient and the second modulation coefficient are controlled to change continuously and smoothly according to a non-linear trend; If switching from SVPWM to DPWM, the second modulation coefficient increases from an initial value of 0 to 1 according to the first curve rule, and the first modulation coefficient decreases from an initial value of 1 to 0 based on the constraint relationship between it and the second modulation coefficient. If switching from DPWM to SVPWM, the first modulation coefficient increases from an initial value of 0 to 1 according to the second curve, and the second modulation coefficient decreases from an initial value of 1 to 0 based on the constraint relationship between it and the first modulation coefficient.

4. The method for smooth switching between DPWM and SVPWM in a three-level inverter according to claim 1, characterized in that, include: During the switching cycle, at least one state variable characterizing the stability of the system is monitored in real time, including the amplitude of DC bus midpoint voltage fluctuation or the rate of change of neutral current. When the state variable is greater than or equal to the safety threshold, the adjustment speed of the first modulation coefficient and the second modulation coefficient is reduced; When the state variable is less than the safety threshold, the adjustment speed of the first modulation coefficient and the second modulation coefficient is increased.

5. The method for smooth switching between DPWM and SVPWM in a three-level inverter according to claim 4, characterized in that, include: The process of reducing or increasing the adjustment speed is divided into a first stage and a second stage; In the first stage, the first modulation coefficient and the second modulation coefficient are adjusted using a first rate of change so that the modulation mode enters a hybrid mode between SVPWM and DPWM. In the second stage, the first modulation coefficient and the second modulation coefficient are adjusted using a second change rate to switch the modulation mode from the mixed mode to the target modulation mode.

6. The method for smooth switching between DPWM and SVPWM in a three-level inverter according to claim 5, characterized in that, The division between the first stage and the second stage is based on at least one of the following criteria: The stage division node is defined by the fact that the values ​​of the first modulation coefficient and the second modulation coefficient reach a preset intermediate threshold. The fixed time proportion of the switching cycle is used as the stage division node; The state variable entering a preset stable interval is used as the stage division node; In the first stage, the first rate of change is configured to preferentially cause the system to exit the initial modulation mode. In the second phase, the second rate of change is configured to prioritize the system's stable convergence to the target modulation mode.

7. The method for smooth switching between DPWM and SVPWM in a three-level inverter according to claim 1, characterized in that, The process of combining the three-phase SPWM modulation wave, the first modulation coefficient, the SVPWM common-mode voltage, the second modulation coefficient, and the DPWM common-mode voltage to generate the instantaneous voltage amplitude of the total modulation wave includes: The SVPWM common-mode voltage is calculated based on the maximum and minimum values ​​of the three-phase SPWM modulation wave; The DPWM common-mode voltage is calculated based on the polarity and magnitude relationship of the three-phase SPWM modulation wave; The formula for calculating the instantaneous voltage amplitude of the total modulated wave includes: U abcMOD =U abc +n*U svpwm_z +m*U dpwm_z ; Among them, U abcMOD It is the instantaneous voltage amplitude of the total modulated wave; U abc It is the three-phase SPWM modulated wave voltage; n is the first modulation coefficient, m is the second modulation coefficient; U svpwm_z It is the SVPWM common-mode voltage, U dpwm_z It is the DPWM common-mode voltage.

8. A smooth switching system for DPWM and SVPWM in a three-level inverter, characterized in that, The method for smooth switching of DPWM and SVPWM in a three-level inverter as described in any one of claims 1-7 includes: The mode determination module is used to determine the current modulation mode, which includes SVPWM and DPWM. A coefficient configuration module is used to set a first modulation coefficient and a second modulation coefficient, wherein the first modulation coefficient corresponds to the weight of the SVPWM common-mode voltage and the second modulation coefficient corresponds to the weight of the DPWM common-mode voltage; The coefficient adjustment module is used to respond to the switching command from the current modulation mode to another modulation mode and adjust the values ​​of the first modulation coefficient and the second modulation coefficient based on the current modulation mode. The control module is used to generate the total modulation wave and to complete the switching when the first modulation coefficient and the second modulation coefficient reach the values ​​corresponding to the target modulation mode.

9. An electronic device, characterized in that, It includes a processor, a memory, a user interface, and a network interface. The memory is used to store instructions, the user interface and the network interface are used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores multiple instructions suitable for being loaded by a processor and executed as described in any one of claims 1-7.

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