Hardware delay control circuit

Abstract

The invention discloses a hardware time-delay control circuit, and the circuit comprises a hardware time-delay module which comprises a timer, an external resistor, and an external capacitor; the timer is arranged to be a monostable circuit, the external resistor is electrically connected with the external capacitor to form a delay loop, and the delay loop is connected to the trigger end and the threshold end of the timer; the discharge end of the timer outputs a delay signal; the optocoupler isolation module comprises an optocoupler device and a phototriode, the input end of the optocoupler device is electrically connected with the discharging end of the timer, and the phototriode is electrically connected with the output end of the optocoupler device; according to the invention, the time delay function is organically combined with electrical isolation and power driving, so that the load power supply can be ensured to be switched on after the set time delay, the influence of instantaneous impact on the system is avoided, and the safety, stability and reliability of power supply control are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a hardware delay control circuit. BACKGROUND

[0002] With the wide application of power electronic technology, more and more industrial control devices, new energy systems and intelligent devices need to realize delay start after power on to avoid the system instability or component damage caused by instantaneous large current impact. In the prior art, there are mainly two types of delay control methods: one is software delay relying on the internal timer of the microcontroller (MCU), which is flexible, but the output port of the MCU may be in a high resistance state or a random level state during the power-on reset or initialization stage, which may cause the output uncontrollable risk, resulting in power mis-triggering and system instability or even equipment damage; the other is directly using a relay or the like to control the power on-off, which is simple in structure, but the relay is easy to generate reverse electromotive force and electromagnetic interference when switching large current, and cannot realize the precise adjustable delay function. The existing circuits have deficiencies in reliability, delay accuracy and anti-interference performance, and are difficult to meet the application requirements of high voltage, large current or complex industrial environment. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a hardware delay control circuit which can improve the anti-interference ability of the circuit.

[0004] To solve the above technical problems, the technical scheme adopted by the present application is: A hardware delay control circuit, characterized in that it comprises: A hardware delay module comprising a timer, an external resistor and an external capacitor; the timer is set as a monostable circuit, the external resistor and the external capacitor are electrically connected to form a delay loop, the delay loop is connected to the trigger end and the threshold end of the timer respectively; the discharge end of the timer outputs a delay signal; An optical coupling isolation module comprising an optical coupling device and a photosensitive triode, the input end of the optical coupling device is electrically connected to the discharge end of the timer, and the photosensitive triode is electrically connected to the output end of the optical coupling device; A driving module comprising a MOS tube electrically connected to the photosensitive triode, the source of the MOS tube is grounded; A relay control module comprising a relay coil and its corresponding normally open contact, one end of the relay coil is connected to a power supply, the other end is connected to the drain of the MOS tube, and the normally open contact is connected in series between the power supply module and the load.

[0005] The beneficial effect of the present application is to provide a hardware delay control circuit, which generates a delay signal through a monostable delay module composed of a timer, a resistor and a capacitor, and then transmits the delay signal to a driving module through an optical coupling isolation module, so as to finally control the normally open contact of a relay and realize the delay connection of the power supply and the load. The circuit combines the delay function with electrical isolation and power driving organically, can ensure that the load power is turned on after setting the delay, avoids the influence of instantaneous impact on the system, and improves the safety, stability and reliability of the power supply control. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 The figure is a hardware delay module architecture diagram of a hardware delay control circuit of an embodiment of the present application. Figure 2 The figure is an architecture diagram of other modules of a hardware delay control circuit of an embodiment of the present application. Figure 3 The figure is an internal structure diagram of a 555 timer of an embodiment of the present application. Figure 4 The figure is a principle schematic diagram of a hardware delay control circuit of an embodiment of the present application. REFERENCE NUMERALS: 1, hardware delay module; 2, optical coupling isolation module; 3, driving module; 4, relay control module. U1, timer; R2, external resistor; C3, external capacitor; U2, optical coupling device; Q1, MOS tube; J1, relay coil; R4, current limiting resistor; R5, gate resistor; R6, pull-down resistor; D2, recovery diode; D1&D3, transient voltage suppression diode. DETAILED DESCRIPTION

[0007] To explain the technical content, the purpose and the effect of the present application in detail, the following will be explained in combination with the embodiments and the drawings.

[0008] Before introducing the embodiments of the present application in detail, some related concepts will be explained first: A timer is a circuit or device that can generate a pulse signal or maintain a certain time delay according to a set time parameter. Its essential function is to measure and control “time”. The timer can be realized based on a hardware circuit (such as a delay formed by resistor-capacitor charging and discharging), or by a software or internal module of a processor.

[0009] A delay circuit is a circuit structure that artificially introduces a time delay by using the characteristics of components (such as capacitor charging and discharging, crystal oscillation period, etc.). Its core function is that there is a controllable time difference between the input action and the output signal.

[0010] An optocoupler is an electronic device that transmits electrical signals through optical signals. There is no direct electrical connection between the input and output sections; instead, signal isolation is achieved through the emission and reception of light, thus effectively providing electrical isolation and interference immunity.

[0011] A phototransistor is a semiconductor device whose conduction state is controlled by a light signal. Unlike a regular transistor, its base is triggered by light rather than driven by current, thus converting light signals into electrical signals. Inside an optocoupler, when an LED emits light, the phototransistor receives the light signal, forming a current path between its collector and emitter, effectively converting the input light signal into an electrical signal. This characteristic makes it suitable for electrical isolation applications. For example, when a timer outputs a pulse to light up the optocoupler, the phototransistor conducts, thereby controlling the gate of a MOSFET.

[0012] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a semiconductor switching device that controls current through voltage. It determines whether the source and drain are conducting by controlling the gate voltage, and has advantages such as high input impedance, fast switching speed, and low on-resistance. In a relay driving circuit, the current signal from the phototransistor is fed into the gate of the MOSFET. When the gate voltage reaches a threshold, the MOSFET turns on, energizing the relay coil. For example, the commonly used low-power N-channel MOSFET 2N7002 can conduct at a gate-source voltage of around 2V, driving the relay coil to engage.

[0013] To at least solve the above problems, please refer to Figure 1 and Figure 2 This invention provides a hardware delay control circuit, characterized in that it includes: Hardware delay module 1 includes timer U1, external resistor R2, and external capacitor C3; timer U1 is configured as a monostable circuit, external resistor R2 and external capacitor C3 are electrically connected to form a delay loop, the delay loop is connected to the trigger terminal and threshold terminal of timer U1 respectively; the discharge terminal of timer U1 outputs a delay signal; Optical isolation module 2 includes an optical coupler U2 and a phototransistor. The input terminal of the optical coupler U2 is electrically connected to the discharge terminal of the timer U1, and the phototransistor is electrically connected to the output terminal of the optical coupler U2. The driving module 3 includes a MOS transistor Q1 electrically connected to the phototransistor, wherein the source of the MOS transistor Q1 is grounded; The relay control module 4 includes a relay coil J1 and its corresponding normally open contact. One end of the relay coil J1 is connected to the power supply, and the other end is connected to the drain of the MOSFET Q1. The normally open contact is connected in series between the power supply module and the load.

[0014] As described above, the beneficial effects of this invention are as follows: It provides a hardware delay control circuit that can achieve a set-time delay during power-on, ensuring that the load is reliably activated in a predetermined sequence and avoiding system instability and equipment damage caused by instantaneous impacts. Simultaneously, this circuit possesses electrical isolation and power drive functions, effectively suppressing electromagnetic interference, improving anti-interference capabilities and overall reliability, thereby meeting the high-safety and high-stability delay control requirements of fields such as industrial control, new energy, and power electronics. This circuit organically combines the delay function with electrical isolation and power drive, ensuring that the load power supply is turned on only after the set delay, avoiding the impact of instantaneous impacts on the system, and improving the safety, stability, and reliability of power supply control.

[0015] Please refer to Figure 3 Specifically, the timer U1 is a 555 timer U1. Using the 555 timer U1 as the core delay device ensures the maturity and stability of the delay circuit. The 555 timer U1 has a simple structure, low cost, adjustable parameters, and high delay accuracy, making it suitable for delay requirements in different application scenarios.

[0016] In some embodiments, one end of the external resistor R2 is connected to a power supply, and the other end is connected to one end of the external capacitor C3. The other end of the external capacitor C3 is grounded, and the trigger terminal and threshold terminal of the timer U1 are both connected to the connection point of the external resistor R2 and the external capacitor C3.

[0017] As described above, by simultaneously connecting the resistor and capacitor to the trigger and threshold terminals of timer U1, the delay characteristics are directly determined by the capacitor's charging and discharging process. This structure is simple and intuitive, the delay time calculation is clear, and it can guarantee delay accuracy and consistency, facilitating rapid adjustment and adaptation to different application scenarios.

[0018] In some embodiments, a current-limiting resistor R4 is connected in series at the input terminal of the optocoupler U2.

[0019] As can be seen from the above description, setting series protection measures at the input of the optocoupler can limit the current flowing into the optocoupler, ensure the long-term stable operation of the optocoupler, avoid overcurrent damage, and thus maintain the reliability of circuit isolation and signal transmission.

[0020] In some embodiments, the driving module 3 further includes a gate resistor R5 and a pull-down resistor R6. The gate resistor R5 is connected in series between the gate of the phototransistor and the gate of the MOSFET Q1, and one end of the pull-down resistor R6 is connected to the gate of the MOSFET Q1, while the other end is grounded.

[0021] As can be seen from the above description, by setting an auxiliary resistor network at the gate end in the drive module 3, the MOSFET Q1 is kept in the off state when there is no input signal and can be stably turned on when there is an input signal, avoiding malfunctions and incomplete turn-off, thereby ensuring that the relay coil J1 is reliably controlled and improving the stability of the system operation.

[0022] In some implementations, a fast recovery diode D2 is connected in parallel across the relay coil J1.

[0023] As can be seen from the above description, adding measures to suppress reverse electromotive force at both ends of the relay coil J1 can eliminate the surge voltage generated when the coil is de-energized, protect the preceding drive components, extend the circuit service life, and improve the overall circuit reliability.

[0024] In some implementations, an absorption circuit consisting of a resistor and a capacitor connected in series is connected in parallel across the two ends of the normally open contact.

[0025] As can be seen from the above description, adding an energy absorption branch at both ends of the normally open contact can effectively suppress the electric arc and electromagnetic interference generated when the contact is opened, reduce contact loss and jitter, extend the service life of the relay coil J1, and maintain the stability of the power output.

[0026] In some embodiments, a transient voltage suppression diode D3 is connected in parallel across the relay coil J1.

[0027] As can be seen from the above description, adding a transient voltage suppression diode D3 across the relay coil J1 can quickly clamp the circuit when a transient voltage spike occurs, preventing damage to the drive circuit and coil insulation, thereby improving the stability and safety of the circuit in complex environments.

[0028] In some implementations, a transient voltage suppression diode D1 is connected in parallel across the normally open contact.

[0029] As can be seen from the above description, adding a transient voltage suppression diode D1 across the normally open contact can absorb and limit high voltage spikes during contact switching, preventing impact on the load or other parts of the circuit, and improving the stability and anti-interference capability of the power supply output.

[0030] In some embodiments, the normally open contact of the relay coil J1 remains open before the delay module outputs the delay signal, and closes after the delay module outputs the delay signal.

[0031] As can be seen from the above description, by limiting the normally open contact of relay coil J1 to remain open before the delay signal is generated and to close after the delay, it can be ensured that the power supply sequence of the load meets the preset requirements, avoid damage to the equipment caused by instantaneous impact, and achieve orderly and safe power management.

[0032] Please refer to Figures 1 to 3 Embodiment 1 of the present invention is as follows: A hardware delay control circuit is provided, the overall structure of which includes a hardware delay module 1, an optocoupler isolation module 2, a driver module 3, and a relay control module 4. Through the organic cooperation of these modules, a delayed connection between the power supply and the load can be achieved, and it has high reliability, anti-interference ability, and applicability.

[0033] Specifically, the hardware delay module 1 includes a timer U1, an external resistor R2, and an external capacitor C3. The timer U1 operates in monostable circuit mode. The external resistor R2 and the external capacitor C3 are interconnected to form a delay loop. The common node of this delay loop is connected to the trigger terminal and the threshold terminal of the timer U1, respectively, thereby utilizing the charging and discharging process of the capacitor to generate controllable delay characteristics. The discharge terminal of the timer U1 outputs a delay signal, which serves as the input control signal for subsequent modules. In this embodiment, the timer U1 can be a 555 timer U1, due to its maturity, stability, high delay accuracy, low cost, and convenient adjustment, which can meet the delay requirements of different application scenarios. By adjusting the values ​​of the resistor and capacitor, the length of the delay can be accurately controlled, ensuring the stability and repeatability of the delay output.

[0034] The optocoupler isolation module 2 includes an optocoupler U2 and a phototransistor. The discharge terminal of timer U1 is electrically connected to the input terminal of optocoupler U2. Optocoupler U2 contains an internal light-emitting diode (LED), which conducts and emits light when the delayed signal arrives. The phototransistor, as the output terminal of optocoupler U2, receives the light signal from the LED and then conducts, transmitting the signal to the subsequent driver module 3. A current-limiting resistor R4 is connected in series at the input terminal of optocoupler U2 to ensure that the current entering the LED inside the optocoupler is within a safe range, preventing damage to the device due to overcurrent. This isolation structure effectively achieves electrical isolation between the preceding and following circuits, reduces interference from high-voltage, high-current circuits to the control circuit, and improves the overall system's anti-interference capability and reliability.

[0035] The driving module 3 includes a MOSFET Q1, and further includes a gate resistor R5 and a pull-down resistor R6. The output signal of the phototransistor is input to the gate of the MOSFET Q1 through the gate resistor R5, while one end of the pull-down resistor R6 is connected to the gate and the other end is grounded. This design ensures that the MOSFET Q1 remains off when there is no signal input, preventing malfunction due to floating. When there is a signal input, the gate resistor R5 suppresses the transient inrush current during gate charging and discharging, allowing the MOSFET Q1 to conduct smoothly. The source of the MOSFET Q1 is grounded, and the drain is connected to the relay coil J1, thus controlling the energization of the relay coil J1 by switching the MOSFET Q1 on and off. The MOSFET Q1 has strong driving capability and fast switching speed, ensuring that the relay coil J1 quickly and reliably engages after being energized, guaranteeing smooth control of the subsequent power supply and load.

[0036] The relay control module 4 includes a relay coil J1 and its corresponding normally open contact. One end of the relay coil J1 is connected to a power supply, and the other end is connected to the drain of a MOSFET Q1. When the MOSFET Q1 is turned on, the relay coil J1 is energized and closes, thus connecting the power supply module to the load. When the MOSFET Q1 is turned off, the relay coil J1 is de-energized and opens, disconnecting the load power supply. A fast recovery diode D2 is connected in parallel across the relay coil J1 to provide a freewheeling path for the current when the coil is de-energized, eliminating the reverse electromotive force generated by the release of inductor energy, avoiding impact on the MOSFET Q1 and optocouplers, and extending the service life of the entire circuit.

[0037] In addition, a transient voltage suppressor diode D3 (TVS) is connected in parallel across the relay coil J1, which can quickly clamp the circuit when a high-amplitude transient voltage occurs, further protecting the safety of the drive circuit and enhancing the system's stable operation in complex electromagnetic environments.

[0038] An absorption circuit consisting of a resistor and a capacitor connected in series is connected in parallel across the normally open contacts of relay coil J1. This absorption circuit effectively dissipates the energy generated when the contacts open, reduces the electric arc and electromagnetic interference generated between the contacts, protects the contacts from burning, and extends the mechanical and electrical life of relay coil J1. Simultaneously, a transient voltage suppression diode D1 can also be connected in parallel across the normally open contacts to suppress transient high voltages generated during contact switching, ensuring a stable output of the load power supply and preventing impact on downstream equipment.

[0039] The normally open contact of relay coil J1 remains open until the delay module outputs the delay signal, and closes only after the delay module generates the delay signal, thus achieving a delayed power-on to the load. This feature ensures that the load devices can start according to a preset sequence and timing, avoiding inrush current, overvoltage, or system instability caused by simultaneous startup, and improving the overall system safety and orderliness.

[0040] Please refer to Figures 1 to 3 Embodiment 2 of the present invention is as follows: A hardware delay control circuit includes a hardware delay module, an optocoupler isolation module, a driver module, and a relay control module. This circuit utilizes the RC delay principle and optocoupler isolation in conjunction with a relay to achieve delayed power-on.

[0041] First, the hardware delay module includes a 555 timer, an external resistor R2, and an external capacitor C3. The timer is configured in monostable circuit mode, with its RESET pin (PIN4) directly connected to a +5V power supply (active low) to ensure that the timing process is not interrupted by a reset signal. The timer's discharge terminal (PIN7, DISCH) is directly used as the delay signal output to drive the optocoupler input. In contrast, the timer's output terminal (PIN3, OUT) requires processing by an internal RS flip-flop, which may introduce additional delay. Therefore, the OUT terminal is not used in this circuit; instead, the discharge terminal is used directly, resulting in faster and more direct signal transmission.

[0042] The timer's control voltage terminal (PIN5, CONT) is grounded through a bypass capacitor to filter high-frequency noise and stabilize the threshold voltage. The timer's power supply terminal (PIN8) is connected to +5V, and its ground terminal (PIN1) is grounded. One end of external resistor R2 is connected to the +5V power supply, and the other end is connected to external capacitor C3, with the other end of C3 grounded. The connection point of R2 and C3 is simultaneously connected to the timer's trigger input (PIN2, TRIG) and threshold input (PIN6, THRES), thus forming an external RC delay circuit. By adjusting the values ​​of R2 and C3, the delay length can be flexibly set. The delay formula is: ; Where T is the delay time (seconds), R2 is in ohms (KΩ), and C3 is in farads (μF).

[0043] Secondly, the optocoupler isolation module includes an optocoupler TLP290 device. The anode of the LED at its input terminal is connected to a +5V power supply, and the cathode is connected to the delay signal terminal via a current-limiting resistor R4. R4 limits the current flowing through the LED to prevent damage due to overcurrent. Referring to the TLP290 chip datasheet, the typical forward voltage drop V of its LED is... FThe voltage is 1.25V. Based on the output voltage of the delay circuit and the resistance value of R4, the input current IF of the optocoupler can be calculated to ensure it is within the appropriate operating range. An example is shown below:

[0044] The optocoupler output is a phototransistor, with its collector connected to a +24V power supply via a current-limiting resistor R1, and its emitter connected to the driver circuit. R1 protects the phototransistor from burnout due to overcurrent. The phototransistor's output is further connected to the gate of the MOSFET Q1 via a gate resistor R5, and the gate is grounded via a pull-down resistor R6. R5 is typically chosen between 100Ω and 500Ω to suppress the inrush current generated by the MOSFET's gate capacitance during charging and discharging, protecting the driver source. R6 ensures that the MOSFET's gate potential is quickly pulled low when there is no input signal, keeping it off, and simultaneously helps the gate discharge quickly when the signal is removed, ensuring the MOSFET is turned off promptly.

[0045] When the phototransistor of the optocoupler is turned on, the gate-source voltage VGS of the MOSFET can be obtained through the resistor network composed of R1, R5, and R6. According to the formula, VGS is approximately 2.136V, which is within the threshold voltage range (1V~2.5V) of the MOSFET (2N7002), thus enabling the MOSFET Q1 to be reliably turned on.

[0046] The source of the MOSFET Q1 in the drive module is grounded, and its drain is connected to the relay coil. When the MOSFET is turned on, a voltage difference is generated across the relay coil, thereby activating the relay coil.

[0047] The relay control module includes a relay coil and normally open contacts. One end of the relay coil is connected to the power supply, and the other end is connected to the drain of a MOSFET. The normally open contact of the relay is connected in series between the power supply module and the load. To suppress the reverse electromotive force generated when the relay coil is de-energized, a fast recovery diode D2 is connected in parallel across the coil. This diode has a low forward voltage drop and a fast switching speed, providing a freewheeling path for the coil and preventing damage to the driving components.

[0048] In addition, an absorption circuit consisting of a resistor R3 and a capacitor C2 connected in series is connected in parallel across the normally open contacts of the relay to absorb the arc energy generated when the contacts open, reduce electromagnetic interference, and extend the contact life. Simultaneously, transient voltage suppression diodes (TVS diodes D3 and D1) are connected in parallel across both the relay coil and the contacts to absorb transient high voltages, reduce electromagnetic interference (EMI), and ensure stable circuit operation.

[0049] Please refer to Figure 4 The working process of the above circuit is as follows: When the system is powered on, the timer starts counting, and the external capacitor C3 begins charging. During the delay period, the timer's discharge terminal remains off, the optocoupler is not conducting, the subsequent circuit remains off, and the load power supply is disconnected.

[0050] When the timing is complete, the timer discharge terminal is turned on, outputting a low-level signal to the optocoupler input, driving the optocoupler's LED to light up. The phototransistor at the optocoupler output then turns on, which in turn drives the gate voltage of the MOSFET to rise, causing the MOSFET to conduct. At this time, the relay coil is energized and clicks, the normally open contact closes, and the power module is connected to the load.

[0051] This achieves delayed power-on to the load, avoiding inrush current and voltage fluctuations caused by instantaneous startup, and ensuring the safety and reliability of system operation.

[0052] In summary, this invention provides a hardware delay control circuit that integrates a multi-stage structure of timer, RC delay circuit, optocoupler isolation, MOSFET drive, and relay control to achieve delayed power-on of the load. By using hardware delay, the uncontrollable risks of traditional software-based delays are avoided. The delay accuracy is determined by component parameters, ensuring stability and reliability. The optocoupler module provides electrical isolation, effectively suppressing electromagnetic interference and ensuring safe signal transmission; the MOSFET has strong driving capability, ensuring reliable relay engagement. The relay control module, combined with protection measures such as fast recovery diodes, RC snubber circuits, and TVS diodes, effectively suppresses back electromotive force and transient overvoltage, extends relay life, and improves system anti-interference capabilities.

[0053] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A hardware delay control circuit, characterized in that, include: The hardware delay module includes a timer, an external resistor, and an external capacitor; the timer is configured as a monostable circuit, and the external resistor and external capacitor are electrically connected to form a delay loop, which is connected to the trigger terminal and the threshold terminal of the timer respectively; the discharge terminal of the timer outputs a delay signal. An optocoupler isolation module includes an optocoupler and a phototransistor. The input terminal of the optocoupler is electrically connected to the discharge terminal of the timer, and the phototransistor is electrically connected to the output terminal of the optocoupler. The driving module includes a MOS transistor electrically connected to the phototransistor, wherein the source of the MOS transistor is grounded; The relay control module includes a relay coil and its corresponding normally open contact. One end of the relay coil is connected to a power supply, and the other end is connected to the drain of the MOSFET. The normally open contact is connected in series between the power supply module and the load.

2. The hardware delay control circuit according to claim 1, characterized in that, One end of the external resistor is connected to the power supply, and the other end is connected to one end of the external capacitor. The other end of the external capacitor is grounded. The trigger terminal and the threshold terminal of the timer are both connected to the connection point of the external resistor and the external capacitor.

3. The hardware delay control circuit according to claim 1, characterized in that, A current-limiting resistor is connected in series at the input terminal of the optocoupler.

4. The hardware delay control circuit according to claim 1, characterized in that, The driving module further includes a gate resistor and a pull-down resistor. The gate resistor is connected in series between the gates of the phototransistor and the MOSFET. One end of the pull-down resistor is connected to the gate of the MOSFET, and the other end is grounded.

5. The hardware delay control circuit according to claim 1, characterized in that, A fast recovery diode is connected in parallel across the two ends of the relay coil.

6. The hardware delay control circuit according to claim 1, characterized in that, The normally open contact is connected in parallel to an absorption circuit consisting of a resistor and a capacitor connected in series.

7. The hardware delay control circuit according to claim 1, characterized in that, A transient voltage suppression diode is connected in parallel across the relay coil.

8. The hardware delay control circuit according to claim 1, characterized in that, A transient voltage suppression diode is connected in parallel across the normally open contact.

9. The hardware delay control circuit according to claim 1, characterized in that, The normally open contact of the relay remains open before the delay module outputs the delay signal, and closes after the delay module outputs the delay signal.

10. The hardware delay control circuit according to claim 1, characterized in that, The timer is a 555 timer.

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