Cadence Skill-based automatic creation method and system for depth-controlled milling groove distribution forbidding area of PCB connector, and medium

Abstract

The invention discloses a Cadence Skill-based automatic creation method and system for a depth-controlled milling groove distribution forbidding area of a PCB connector, and a medium, and belongs to the technical field of electronic printed circuit board design, and the method comprises the steps: generating the lamination number and depth of the milling distribution forbidding area corresponding to a hollow area according to the creation data, processing parameters, geometric shape and installation hierarchy of a target PCB connector; carrying out groove milling processing on the target PCB connector according to the lamination number and depth of the milling distribution forbidding area, and simultaneously carrying out error reporting prompt on wiring, via holes and copper sheets in the hollowed area; the overhanging amount of the pins of the processed target PCB connector is greater than or equal to a preset welding pin safety distance, and the residual board thickness of the non-milling area is smaller than the effective embedding length of the pins. According to the invention, the problems of low efficiency, high miscalculation risk, poor groove milling consistency and signal failure caused by the fact that the establishment of the existing PCB connector pin distribution forbidding area depends on manual operation are solved.

Description

Technical Field

[0001] This invention relates to a method, system, and medium for automatically creating restricted areas in controlled-depth milling slots for PCB connectors based on Cadence Skill, belonging to the field of electronic printed circuit board design technology. Background Technology

[0002] As 5G base stations, server backplanes, and high-voltage power supplies evolve towards higher power, the thickness of PCB boards has increased from the conventional 1.6mm to 3.0–8.0mm, such as the Class III thick boards in the IPC-2221B standard, to accommodate the mounting requirements of high-current connectors such as power terminals and high-speed backplane connectors. Currently, industry technology relies heavily on manual operation and experience-based judgment: engineers manually compare pin lengths with board thickness, or calculate board thickness layer by layer and mark cutout areas, then inform the board manufacturer; the manufacturing process relies on the board manufacturer's experience for milling; and if the pin length is insufficient, the pins must be manually lengthened during soldering. In existing methods, designers must load the PCB file, determine the pin length compliance for each connector, and for devices with pin lengths less than the board thickness, call the layer stack manager and perform compensation calculations in conjunction with conductor and planar layers, ultimately creating a route keepout in the corresponding layer stack area.

[0003] Existing technologies suffer from significant efficiency and accuracy issues: manual operation is inefficient and carries a high risk of miscalculation (such as over- or under-digging of areas), easily leading to defects such as cold solder joints and poor soldering (according to the IPC-A-610G standard, solder joints with less than 50% solder climb height are considered failures). The design phase relies on manual comparison and layer-by-layer calculations, resulting in a cumbersome process; the manufacturing phase suffers from poor milling consistency, high communication costs, and potential damage to the impedance layer, directly impacting project timelines; and when manually lengthening pins during soldering, high-speed connector differential lines are prone to signal failure due to length errors. Furthermore, in scenarios with complex layer stacks and large board thicknesses, existing methods require frequent calls to the layer stack manager and the creation of numerous keep-out areas, leading to time-consuming calculations and a high risk of errors, further exacerbating efficiency bottlenecks. Summary of the Invention

[0004] The purpose of this invention is to provide a method, system, and medium for automatically creating controlled-depth milling keep-out zones for PCB connectors based on Cadence Skill. By automatically comparing pin lengths and stack-up structures, this invention solves the problems of low efficiency, high risk of miscalculation, poor milling consistency, and signal failure caused by manual operation in the creation of keep-out zones for existing PCB connectors.

[0005] To solve the above-mentioned technical problems, the present invention is implemented using the following technical solution.

[0006] In a first aspect, the present invention provides a method for automatically creating the restricted area of ​​a PCB connector controlled-depth milling slot based on Cadence Skill, comprising:

[0007] Obtain the creation data and processing parameters of the target PCB connector;

[0008] The creation data includes the number of target PCB connector packages, the actual size of the target PCB connector package, vertex coordinates, design measurement unit, mounting surface, design measurement accuracy, tag number, wire mesh, inspection range, pin length, and target pin keep-out area.

[0009] The processing parameters include the thickness of the PCB board to be milled, as well as the thickness of each planar layer, conductor layer, and dielectric layer in the PCB board.

[0010] Generate the number and depth of the milling keep-out area corresponding to the cut-out area based on the creation data, processing parameters, geometry and mounting level of the target PCB connector;

[0011] The target PCB connector is milled according to the number and depth of the stacked layers in the milling restricted area, and error prompts are given for the traces, vias and copper foil in the cut-out area.

[0012] Among them, the pin overhang of the target PCB connector after processing is greater than or equal to the preset safe distance for soldering pins, and the remaining board thickness of the unmilled area is less than the effective embedding length of the pins.

[0013] Furthermore, if the number of target PCB connectors selected by the user is greater than 1, an error message will be output.

[0014] Furthermore, based on the creation data, processing parameters, geometry, and mounting level of the target PCB connector, the number and depth of the corresponding milled keep-out layers in the cut-out area are generated, including:

[0015] Determine the number of geometric shapes in the target PCB connector:

[0016] If it contains only one geometric shape, then determine the geometry of the target PCB connector:

[0017] If the target PCB connector is rectangular, then obtain the vertex coordinates of the target PCB connector and determine the installation level of the target PCB connector:

[0018] If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0019] If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacking in the milling forbidden area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0020] If the target PCB connector is circular, then obtain the midpoint coordinates and radius of the target PCB connector and determine the mounting level of the target PCB connector:

[0021] If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0022] If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacking in the milling restricted area based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0023] If multiple geometric shapes are involved, they are merged into one geometric shape. The vertex coordinates of the target PCB connector are obtained, and the mounting level of the target PCB connector is determined.

[0024] If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0025] If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacks for milling the restricted area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0026] Further, based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled, the number and depth of the milling keep-out area are calculated, including:

[0027] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0028] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates of the actual package size, and the DB value of the package pattern;

[0029] Based on the vertex coordinates of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0030] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0031] Subtract the thickness of each planar layer, dielectric layer, and conductor layer from the thickness of the entire PCB board, sequentially from top to bottom.

[0032] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0033] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0034] Determine the parity of the number of stacks of milled forbidden regions read:

[0035] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0036] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0037] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0038] Furthermore, using reverse stacking operations, the number and depth of stacks for the milling keep-out area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled, including:

[0039] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0040] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates of the actual package size, and the DB value of the package pattern;

[0041] Based on the vertex coordinates of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0042] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0043] The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer;

[0044] The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board.

[0045] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0046] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0047] Determine the parity of the number of stacks of milled forbidden regions read:

[0048] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0049] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0050] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0051] Further, based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled, the number and depth of the milling keep-away region are calculated, including:

[0052] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0053] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates and radius of the actual package size, and the DB value of the package pattern;

[0054] Based on the vertex coordinates and radius of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0055] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0056] The thickness of each planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom based on the overall thickness of the PCB board.

[0057] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0058] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0059] Determine the parity of the number of stacks of milled forbidden regions read:

[0060] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0061] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0062] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0063] Furthermore, using reverse stacking calculations, the number and depth of stacks for the milling keep-out area are calculated based on the midpoint coordinates and radius of the target PCB connector, as well as the thickness difference between the pin length and the thickness of the PCB board to be milled. This includes:

[0064] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0065] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates and radius of the actual package size, and the DB value of the package pattern;

[0066] Based on the vertex coordinates and radius of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0067] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0068] The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer;

[0069] The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board.

[0070] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0071] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0072] Determine the parity of the number of stacks of milled forbidden regions read:

[0073] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0074] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0075] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0076] Furthermore, the target PCB connector is milled according to the number and depth of the stacked layers in the milled containment area, including:

[0077] The number of milling allowable regions is determined based on the number and depth of the milling allowable regions.

[0078] If the number of milled keep-out areas is greater than or equal to 1, then the milled keep-out areas on each stack of the target PCB connector are merged and then milled.

[0079] If the number of milled placebound areas is less than 1, the information display area will show the message: "PCB connector is missing placebound, please check the package file".

[0080] Secondly, the present invention provides an automatic creation system for controlled depth milling slots and restricted areas of PCB connectors based on Cadence Skill, characterized in that it implements the automatic creation method for controlled depth milling slots and restricted areas of PCB connectors based on Cadence Skill as described in the first aspect.

[0081] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it implements the method for automatically creating a controlled-depth milling groove forbidden zone for PCB connectors based on Cadence Skill as described in the first aspect.

[0082] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0083] This invention, by integrating the Cadence Skill scripting language, realizes a fully automated creation process for PCB connector pin keep-out zones. It can accurately calculate the coordinates of the milled keep-out zone based on pin length, board thickness parameters, and mounting layer, and simultaneously provide real-time error prompts for traces, vias, and copper within the cut-out area. This ensures that the pin overhang after processing is greater than or equal to the preset safe distance for soldering pins, and that the remaining board thickness is less than the effective pin embedding length. This significantly improves the efficiency and calculation accuracy of keep-out zone design, avoids problems such as miscalculations, over-cutting / under-cutting caused by manual operation, and ensures the integrity of high-speed differential signals and the safety of the impedance layer structure. Furthermore, this invention reduces the original 2 minutes of operation time for designers on a single connector to 0.1 seconds. Attached Figure Description

[0084] Figure 1 This is a flowchart illustrating an automatic creation method for controlled-depth milling groove forbidden zones of PCB connectors based on Cadence Skill, provided in an embodiment of the present invention.

[0085] Figure 2This is a schematic diagram of the application process of an automatic creation method for controlled-depth milling groove forbidden zones of PCB connectors based on Cadence Skill, provided in an embodiment of the present invention.

[0086] Figure 3 This is a schematic diagram of the application interface of an automatic creation method for controlled-depth milling groove forbidden zones of PCB connectors based on Cadence Skill, provided in an embodiment of the present invention.

[0087] Figure 4 This is a partial schematic diagram of the main program code of a method for automatically creating a restricted area for PCB connector controlled-depth milling grooves based on Cadence Skill, provided in an embodiment of the present invention. Detailed Implementation

[0088] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0089] Example 1

[0090] like Figure 1 As shown in the figure, this embodiment introduces a method for automatically creating the controlled-depth milling slot keep-away zone of a PCB connector based on Cadence Skill, including:

[0091] Step 1: Obtain the creation data and processing parameters of the target PCB connector.

[0092] In this embodiment, the creation data includes the number of target PCB connector packages, the actual size of the target PCB connector package, vertex coordinates, design measurement unit, mounting surface, design measurement accuracy, tag number, wire mesh, inspection range, pin length, and target pin keep-out area.

[0093] In this embodiment, the processing parameters include the thickness of the PCB board to be milled, as well as the thickness of each planar layer, conductor layer, and dielectric layer in the PCB board.

[0094] Step 2: Based on the creation data, processing parameters, geometry, and mounting level of the target PCB connector, generate the number and depth of the corresponding milling keep-out areas for the cut-out region.

[0095] In this embodiment, if the number of target PCB connectors selected by the user is greater than 1, an error message will be output.

[0096] Step 2.1: Determine the number of geometric shapes in the target PCB connector:

[0097] Step 2.1.1: If it contains only one geometric shape, then determine the geometry of the target PCB connector:

[0098] If the target PCB connector is rectangular, then obtain the vertex coordinates of the target PCB connector and determine the installation level of the target PCB connector:

[0099] If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0100] In this embodiment, the number and depth of the milling keep-out area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled, including:

[0101] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates of the actual package size, and the DB value of the package pattern;

[0102] Based on the vertex coordinates of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0103] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0104] Subtract the thickness of each planar layer, dielectric layer, and conductor layer from the thickness of the entire PCB board, sequentially from top to bottom.

[0105] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0106] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0107] Determine the parity of the number of stacks of milled forbidden regions read:

[0108] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0109] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0110] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0111] If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacking in the milling forbidden area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0112] In this embodiment, a reverse stacking operation is used to calculate the number and depth of stacks for the milling keep-out area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. This includes:

[0113] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0114] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates of the actual package size, and the DB value of the package pattern;

[0115] Based on the vertex coordinates of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0116] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0117] The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer;

[0118] The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board.

[0119] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0120] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0121] Determine the parity of the number of stacks of milled forbidden regions read:

[0122] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0123] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0124] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0125] If the target PCB connector is circular, then obtain the midpoint coordinates and radius of the target PCB connector and determine the mounting level of the target PCB connector:

[0126] If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0127] In this embodiment, the number and depth of the milling keep-away region are calculated based on the midpoint coordinates and radius of the target PCB connector, as well as the thickness difference between the pin length and the thickness of the PCB board to be milled, including:

[0128] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0129] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates and radius of the actual package size, and the DB value of the package pattern;

[0130] Based on the vertex coordinates and radius of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0131] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0132] The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer;

[0133] The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board.

[0134] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0135] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0136] Determine the parity of the number of stacks of milled forbidden regions read:

[0137] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0138] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0139] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0140] If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacking in the milling restricted area based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0141] In this embodiment, a reverse stacking operation is used to calculate the number and depth of stacks in the milling keep-out area based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. This includes:

[0142] Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation;

[0143] Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates and radius of the actual package size, and the DB value of the package pattern;

[0144] Based on the vertex coordinates and radius of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0145] Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly;

[0146] The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer;

[0147] The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board.

[0148] Calculate the difference between the pin length and the preset safe distance for soldering pins;

[0149] When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area.

[0150] Determine the parity of the number of stacks of milled forbidden regions read:

[0151] If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions.

[0152] If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions.

[0153] Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

[0154] Step 2.1.2: If multiple geometric shapes are involved, merge them into one geometric shape, obtain the vertex coordinates of the target PCB connector, and determine the mounting level of the target PCB connector.

[0155] If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0156] If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacks for milling the restricted area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

[0157] Step 3: Mill grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, and at the same time, provide error prompts for the traces, vias and copper foil in the cut-out area.

[0158] In this embodiment, milling is performed on the target PCB connector according to the number and depth of the stacked layers in the milling ban area, including:

[0159] The number of milling allowable regions is determined based on the number and depth of the milling allowable regions.

[0160] If the number of milled keep-out areas is greater than or equal to 1, then the milled keep-out areas on each stack of the target PCB connector are merged and then milled.

[0161] If the number of milled placebound areas is less than 1, the information display area will show the message: "PCB connector is missing placebound, please check the package file".

[0162] Among them, the pin overhang of the target PCB connector after processing is greater than or equal to the preset safe distance for soldering pins, and the remaining board thickness of the unmilled area is less than the effective embedding length of the pins.

[0163] Example 2

[0164] Based on the same inventive concept as Embodiment 1, this embodiment describes the application steps of an automatic creation method for controlled depth milling groove forbidden zones of PCB connectors based on CadenceSkill.

[0165] in, Figure 2 This is a schematic diagram of the application process of an automatic creation method for controlled-depth milling slots and keep-away zones of PCB connectors based on Cadence Skill, provided in an embodiment of the present invention. S1, S2, S3, and S4 are user interaction operations, and S5 is the main application process of the automatic creation method for controlled-depth milling slots and keep-away zones of PCB connectors based on Cadence Skill. Part of the main program code for the application process is shown below. Figure 4 As shown.

[0166] Figure 3 This is a schematic diagram of the application interface of an automatic creation method for controlled-depth milling grooves and forbidden zones of PCB connectors based on Cadence Skill, provided by an embodiment of the present invention. It includes an operation area, a component area, an execution area, and a range area. The operation area is used to configure creation and processing parameters; the component area is used to display the reference designator of the target PCB connector; the execution area is used to judge the target based on the creation and processing parameters and the running program; and the range area is used for users to fill in the range that needs to be expanded according to their needs.

[0167] This embodiment first copies the Cadence Skill script to the Cadence pcbenv directory and adds a loading command to the startup file to ensure it can be called when the software starts. Then, using a text editor, opens the Cadence background menu configuration. The program code for the automatic creation method of PCB connector controlled-depth milling slot forbidden zones based on Cadence Skill, as provided in this embodiment, is added to the Skill menu, saved, and the software is restarted. The corresponding... Figure 3 The interactive interface and corresponding menu buttons allow users to activate the automatic creation method for controlled-depth milling grooves and restricted areas of PCB connectors based on Cadence Skill. After the program starts, users can enter the specified command in the Command window or directly click the menu button to activate the method. Users can select the PCB devices to be operated, set the pin length and expansion range of the PCB devices, and click "Create" to start running the program.

[0168] S1: The user invokes the Cadence Skill script via the command Createsymrko to launch the form and obtain the creation data of all PCB connectors, including the tag number, net, and inspection range;

[0169] S2: When the user clicks the "Get thickness" button, they can obtain the creation data for all PCB connectors, including the thickness of the entire PCB board to be milled.

[0170] S3: The user clicks the "Select" button and selects the target PCB connectors for which a no-hide zone needs to be created.

[0171] S4: User sets the pin length and target pin keepout area;

[0172] S5: Based on the creation data and processing parameters of the target PCB connector, click the "Create" button. The program will generate the number and depth of the milling ban area stack corresponding to the cut-out area based on the creation data, processing parameters, geometry and installation level of the target PCB connector.

[0173] This embodiment primarily addresses the issue of manually checking and confirming the pin length of each connector device during purely manual operations, especially when the pin length is less than the board thickness, requiring repeated calculations. This embodiment, however, automatically identifies the board thickness after the Create command is submitted, and automatically calculates the optimal number of cut-out layers based on pre-set pin extension distances and pin lengths. This reduces manual intervention time in repetitive tasks, improves design efficiency and accuracy, and avoids irreversible errors caused by calculations by designers or PCB manufacturers.

[0174] This embodiment primarily addresses the challenge of automatically identifying the vertices of the geometry and the mounting surfaces of PCB connectors when dealing with complex PCB components or those with multiple combined geometric shapes during purely manual operation. It uses these vertices as a basis to obtain the coordinates of the milling keepout areas, automatically generating and merging complex geometric shapes. Compared to purely manual operation, this approach guarantees both accuracy and efficiency. Taking a single connector as an example, the above operations can be completed in 0.1 seconds after the Create command is submitted. This is significantly faster than manually calculating and creating the Routekeepout graphic and copying it to multiple specified layers, which takes at least 2 minutes. The time saved will be even greater depending on the number of connectors.

[0175] Example 3

[0176] Based on the same inventive concept as other embodiments, this embodiment introduces an automatic creation system for controlled-depth milling grooves and restricted areas of PCB connectors based on CadenceSkill, characterized in that it implements the method described in Embodiment 1 or 2.

[0177] Example 4

[0178] Based on the same inventive concept as other embodiments, this embodiment describes a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the steps of the methods of Embodiment 1 or 2 described above.

[0179] In summary, this invention, by integrating the Cadence Skill scripting language, achieves a fully automated creation process for PCB connector pin keep-out zones. It can accurately calculate the coordinates of the milled keep-out zone based on pin length, board thickness parameters, and mounting layer, and simultaneously provide real-time error alerts for traces, vias, and copper within the cut-out area. This ensures that the pin overhang after processing is greater than or equal to the preset safe distance for soldering pins, and that the remaining board thickness is less than the effective pin embedding length. This significantly improves the efficiency and accuracy of keep-out zone design, avoiding problems such as miscalculations, over-cutting / under-cutting caused by manual operation. It also ensures the integrity of high-speed differential signals and the safety of the impedance layer structure. Furthermore, this invention reduces the original 2-minute operation time for a single connector to 0.1 seconds.

[0180] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0181] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0182] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0183] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0184] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for automatically creating restricted areas in PCB connector controlled-depth milling slots based on Cadence Skill, characterized in that, include: Obtain the creation data and processing parameters of the target PCB connector; The creation data includes the number of target PCB connector packages, the actual size of the target PCB connector package, vertex coordinates, design measurement unit, mounting surface, design measurement accuracy, tag number, wire mesh, inspection range, pin length, and target pin keep-out area. The processing parameters include the thickness of the PCB board to be milled, as well as the thickness of each planar layer, conductor layer, and dielectric layer in the PCB board. Generate the number and depth of the milling keep-out area corresponding to the cut-out area based on the creation data, processing parameters, geometry and mounting level of the target PCB connector; The target PCB connector is milled according to the number and depth of the stacked layers in the milling restricted area, and error prompts are given for the traces, vias and copper foil in the cut-out area. Among them, the pin overhang of the target PCB connector after processing is greater than or equal to the preset safe distance for soldering pins, and the remaining board thickness of the unmilled area is less than the effective embedding length of the pins.

2. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 1, characterized in that, If the number of target PCB connectors selected by the user is greater than 1, an error message will be output.

3. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 1, characterized in that, Based on the target PCB connector's creation data, processing parameters, geometry, and mounting layer, generate the number and depth of milled keep-away layers corresponding to the cut-out area, including: Determine the number of geometric shapes in the target PCB connector: If it contains only one geometric shape, then determine the geometry of the target PCB connector: If the target PCB connector is rectangular, then obtain the vertex coordinates of the target PCB connector and determine the installation level of the target PCB connector: If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacking in the milling forbidden area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. If the target PCB connector is circular, then obtain the midpoint coordinates and radius of the target PCB connector and determine the mounting level of the target PCB connector: If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacking in the milling restricted area based on the midpoint coordinates and radius of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. If multiple geometric shapes are involved, they are merged into one geometric shape. The vertex coordinates of the target PCB connector are obtained, and the mounting level of the target PCB connector is determined. If the target PCB connector is installed on the Top layer, after reserving a pin overhang of a preset thickness, the number and depth of the stacked layers for milling the restricted area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled. If the target PCB connector is installed on the Bottom layer, after reserving a preset thickness of pin overhang, a reverse stacking operation is used to calculate the number and depth of stacks for milling the restricted area based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled.

4. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 3, characterized in that, The number and depth of the milling keep-away region are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the PCB board to be milled, including: Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation; Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates of the actual package size, and the DB value of the package pattern; Based on the vertex coordinates of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled. Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly; Subtract the thickness of each planar layer, dielectric layer, and conductor layer from the thickness of the entire PCB board, sequentially from top to bottom. Calculate the difference between the pin length and the preset safe distance for soldering pins; When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the thickness difference between the pin length and the thickness of the PCB board to be milled, the number and depth of the stacked layers of the milling restricted area are obtained.

5. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 3, characterized in that, Using reverse stacking operations, the number and depth of stacks for milling the keep-out area are calculated based on the vertex coordinates of the target PCB connector and the thickness difference between the pin length and the thickness of the overall PCB board to be milled, including: Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation; Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates of the actual package size, and the DB value of the package pattern; Based on the vertex coordinates of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled. Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly; The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer; The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board. Calculate the difference between the pin length and the preset safe distance for soldering pins; When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area. Determine the parity of the number of stacks of milled forbidden regions read: If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions. If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions. Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

6. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 3, characterized in that, The number and depth of the milling keep-away region are calculated based on the midpoint coordinates and radius of the target PCB connector, and the thickness difference between the pin length and the thickness of the PCB board to be milled, including: Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation; Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates and radius of the actual package size, and the DB value of the package pattern; Based on the vertex coordinates and radius of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled. Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly; The thickness of each planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom based on the overall thickness of the PCB board. Calculate the difference between the pin length and the preset safe distance for soldering pins; When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset safe distance for soldering pins and the difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area. Determine the parity of the number of stacks of milled forbidden regions read: If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions. If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions. Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

7. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 3, characterized in that, Using reverse stacking calculations, the number and depth of stacks for the milling keep-out area are calculated based on the midpoint coordinates and radius of the target PCB connector, as well as the thickness difference between the pin length and the thickness of the overall PCB board to be milled. This includes: Read the design measurement unit and design measurement accuracy of the target PCB connector and convert them to millimeters for calculation; Based on the thickness of the PCB board, the reference designation, the mounting surface, the pin length, the actual size of the target PCB connector package, and the number of target PCB connector packages, obtain the package pattern of the target PCB connector, the vertex coordinates and radius of the actual package size, and the DB value of the package pattern; Based on the vertex coordinates and radius of the actual package size and the DB value of the package pattern, calculate the thickness difference between the pin length and the thickness of the PCB board to be milled. Read the thickness of each planar layer, dielectric layer, and conductor layer in the PCB assembly; The reverse stacking operation is used to reverse the thickness of the PCB board to be milled, as well as the thickness of each planar layer, dielectric layer and conductor layer; The thickness of each inverted planar layer, dielectric layer, and conductor layer is subtracted sequentially from top to bottom using the thickness of the inverted PCB overall board. Calculate the difference between the pin length and the preset safe distance for soldering pins; When the remaining thickness of the PCB board is less than the sum of the difference between the pin length and the preset solder pin safety distance and the thickness difference between the pin length and the thickness of the PCB board to be milled, read the number and depth of the stacked layers in the milling restricted area. Determine the parity of the number of stacks of milled forbidden regions read: If the number of stacks of milling allowable regions read is even, divide the number of stacks of milling allowable regions read by 2 to obtain the actual number of stacks of milling allowable regions. If the number of stacks of milling allowable regions read is odd, subtract 1 from the number of stacks of milling allowable regions read and then divide by 2 to obtain the actual number of stacks of milling allowable regions. Specifically, when milling grooves on the target PCB connector according to the number and depth of the stacked layers in the milling restricted area, only the planar layer and conductor layer are milled, and the dielectric layer does not need to be milled.

8. The method for automatically creating the restricted area of ​​PCB connector controlled-depth milling slots based on Cadence Skill according to claim 3, characterized in that, The target PCB connector is milled according to the number and depth of the stacked layers in the milling ban area, including: The number of milling allowable regions is determined based on the number and depth of the milling allowable regions. If the number of milled keep-out areas is greater than or equal to 1, then the milled keep-out areas on each stack of the target PCB connector are merged and then milled. If the number of milled placebound areas is less than 1, the information display area will show the message: "PCB connector is missing placebound, please check the package file".

9. An automatic creation system for controlled-depth milling slots and forbidden zones of PCB connectors based on Cadence Skill, characterized in that, Implement the method for automatically creating the restricted area of ​​PCB connector controlled depth milling slots based on Cadence Skill as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method for automatically creating the restricted area of ​​the controlled depth milling slot for PCB connectors based on Cadence Skill as described in any one of claims 1-8.

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