Power semiconductor device with low electromagnetic interference

Abstract

The invention relates to a power semiconductor device with low electromagnetic interference. The second conductive type well region comprises an active region, a central region distributed in the semiconductor substrate and a plurality of cells distributed in parallel, each cell comprises a cell groove, the cell groove penetrates through the second conductive type well region in the active region, and each cell groove is filled with a groove gate; in the active region, a groove partition unit is arranged on one side of at least one cell, and the groove partition unit is in contact with one side wall of a cell groove in the cell, so that the cell groove is isolated from the second conductive type well region on the corresponding side through the groove partition unit; and the trench gates in all the cells are electrically connected with the front surface first electrode metal above the front surface of the semiconductor substrate. According to the invention, the input capacitance of the power semiconductor device can be reduced under the condition that the feedback capacitance is maintained, so that the electromagnetic interference and the voltage stress to the load when the power semiconductor device is turned on are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of power semiconductor devices, especially a low electromagnetic interference power semiconductor device. BACKGROUND

[0002] IGBT (Insulated Gate Bipolar Transistor) is a representative class of devices in power semiconductor devices, because it has high voltage, low on-state voltage drop, easy to drive, switching speed and other advantages, in switching power supply, frequency conversion, new energy motor drive and many power fields have important applications.

[0003] With the development of IGBT technology, trench gate IGBT devices gradually become mainstream. In order to improve the current density of trench gate IGBT device, and reduce the loss of trench gate IGBT device, the trench gate density of the trench gate IGBT device is getting larger and larger at present; When the density of the channel gate is large, it will cause the input capacitance of the IGBT device to become large, when the input capacitance becomes large, the gate curve oscillation is easy to produce at the moment of IGBT device opening, thereby causing strong electromagnetic interference, affecting the running environment and safety of working scene.

[0004] In order to reduce the risk of gate curve oscillation of IGBT device opening, in the prior art, part of the polycrystalline trench is connected to the emitter metal, so as to reduce the input capacitance, and alleviate the risk of electromagnetic interference failure of high-density trench IGBT device opening. But this way will also cause feedback reduction.

[0005] When the feedback capacitance of the IGBT device is reduced, the collector voltage rate of change of the IGBT device will increase when it is opened under low load working condition, and high voltage stress will be generated, which will cause irreversible damage to the load. SUMMARY

[0006] The purpose of the present application is to overcome the shortcomings in the prior art, and to provide a low electromagnetic interference power semiconductor device, which can reduce the input capacitance of the power semiconductor device while maintaining the feedback capacitance, thereby reducing the electromagnetic interference of the power semiconductor device when it is opened and the voltage stress on the load.

[0007] According to the technical scheme provided by the present application, a low electromagnetic interference power semiconductor device, the power semiconductor device comprises: a semiconductor substrate, which is of a first conductivity type; an active region, which is distributed in the central region of the semiconductor substrate and includes a plurality of cells arranged in parallel, wherein, each cell includes a cell trench, the cell trench penetrates the second conductivity type well region in the active region, and a trench gate is filled in each cell trench; In the active region, at least one side of one cell is provided with a trench isolation unit, which is in contact with a sidewall of the cell trench in the cell, so as to isolate the cell trench from the second-conductivity-type well region on the corresponding side by the trench isolation unit; All the trench gates in the cells are electrically connected with the front surface first electrode metal above the front surface of the semiconductor substrate.

[0008] For any cell, when a trench isolation unit is only provided on one side of the cell, a first-conductivity-type source region is provided on the other side of the cell, wherein, The first-conductivity-type source region is located in the second-conductivity-type well region, and the first-conductivity-type source region is in contact with the sidewall of the cell trench in the cell; The first-conductivity-type source region and the second-conductivity-type well region are both electrically connected with the front surface second electrode metal above the first main surface of the semiconductor substrate.

[0009] For any cell, when a trench isolation unit is provided on both sides of the cell, a first-conductivity-type source region is provided outside one trench isolation unit, or first-conductivity-type source regions are provided outside both trench isolation units; When a first-conductivity-type source region is provided outside one trench isolation unit, the first-conductivity-type source region is located in the second-conductivity-type well region, and the first-conductivity-type source region is in contact with the corresponding trench isolation unit; The first-conductivity-type source region and the second-conductivity-type well region are both electrically connected with the front surface second electrode metal above the first main surface of the semiconductor substrate, and a conductive channel can be formed on the corresponding side of the cell trench based on the first-conductivity-type source region, the trench isolation unit in contact with the first-conductivity-type source region, and the trench gate in the cell trench.

[0010] When a first-conductivity-type source region is provided outside one trench isolation unit, the first-conductivity-type source region is located in the second-conductivity-type well region, and the first-conductivity-type source region is in contact with the corresponding trench isolation unit; The first-conductivity-type source region and the second-conductivity-type well region are both electrically connected with the front surface second electrode metal above the first main surface of the semiconductor substrate, and a conductive channel can be formed on the corresponding side of the cell trench based on the first-conductivity-type source region, the trench isolation unit in contact with the first-conductivity-type source region, and the trench gate in the cell trench.

[0011] The trench isolation unit comprises an isolation trench and an isolation conductive polysilicon filled in the isolation trench, wherein, The isolation trench extends vertically from the front surface of the semiconductor substrate to the bottom of the cell trench, the bottom of the isolation trench is located below the second-conductivity-type well region, and the bottom of the isolation trench is located above the bottom of the cell trench. The isolation between the isolation trench and the inner wall of the isolation trench is achieved by insulating the isolation trench from the inner wall of the isolation trench. When a first conductive type source region is arranged outside the trench isolation unit and a conductive channel is formed based on the first conductive type source region and the trench gate, the isolation conductive polysilicon in the trench isolation unit is electrically connected to the front first electrode metal, otherwise, the isolation conductive polysilicon in the isolation isolation unit is in a floating state.

[0012] When a first conductive type source region is arranged outside the trench isolation unit and a conductive channel is formed based on the first conductive type source region and the trench gate, the isolation conductive polysilicon in the trench isolation unit is in contact with the trench gate in the corresponding cell trench through one or more trench holes, and the isolation conductive polysilicon and the trench gate are electrically connected to the front first electrode metal.

[0013] When there are multiple trench holes, the multiple trench holes are arranged in sequence along the length direction of the cell trench, and the depth of each trench hole does not exceed the groove depth of the isolation trench.

[0014] The trench hole penetrates the cell isolation gate oxide layer in the cell trench and the isolation dielectric layer in the corresponding isolation trench, wherein, The cell isolation gate oxide layer covers the inner wall of the cell trench, and the trench gate is insulated and isolated from the inner wall of the cell trench through the cell isolation gate oxide layer; The isolation dielectric layer covers the corresponding inner wall of the isolation trench, and the isolation conductive polysilicon is insulated and isolated from the inside of the isolation trench through the isolation dielectric layer.

[0015] The cell trench is in a strip shape, and the length direction of the isolation trench is consistent with the length direction of the cell trench.

[0016] A first conductive type carrier storage layer is further arranged in the semiconductor substrate, wherein, The first conductive type carrier storage layer transversely crosses the active region, and the upper end of the first conductive type carrier storage layer is in contact with the second conductive type well region; The bottom of the isolation trench is located in the first conductive type carrier storage layer, and the bottom of the cell trench is located below the first conductive type carrier storage layer.

[0017] When the power semiconductor device is an IGBT type device, a back electrode structure is further arranged on the back surface of the semiconductor substrate, wherein the back electrode structure at least includes a second conductive type collector region.

[0018] The advantages of the present application are as follows: the cells in the active region adopt trench type cells, a trench isolation unit is arranged on one side of at least one cell, the trench isolation unit is in contact with the side of the cell trench, the depth of the cell trench is greater than the depth of the isolation trench in the trench isolation unit; all the trench gates in the cell trench are electrically connected with the front first electrode metal, when the first conductive type source region is arranged outside the trench isolation unit, the isolation conductive polysilicon in the trench isolation unit is electrically connected with the front first electrode metal, otherwise, the isolation conductive polysilicon in the trench isolation unit is configured to be in a floating state, so that the cell trench and the second conductive type well region on the corresponding side can be effectively isolated, thereby the input capacitance can be greatly reduced, and the ratio of the input capacitance to the feedback capacitance can also be effectively reduced, so it can be known that not only the risk of strong electromagnetic interference caused by gate voltage oscillation when the power semiconductor device is turned on can be reduced, but also the rate of change of the collector voltage when the power semiconductor device is turned on can be effectively reduced, and the voltage stress on the load can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is an embodiment structure schematic diagram of the power semiconductor device of the present application.

[0020] Figure 2 It is an embodiment schematic diagram of the front view of the power semiconductor device of the present application.

[0021] Figure 3 It is an embodiment sectional view of A-A direction in Figure 2 .

[0022] Explanation of reference signs: 1-N type base region, 2-P+ collector region, 3-N+ field stop buffer layer, 4-N type carrier storage layer, 5-P type well region, 6-contact hole, 7-N+ source region, 8-cell trench, 9-trench gate, 10-isolation conductive polysilicon, 11-P+ emission region, 12-isolation trench, 13-cell insulated gate oxide layer, 14-trench hole, 15-isolation dielectric layer. DETAILED DESCRIPTION

[0023] The present application will be further described below in combination with specific drawings and embodiments.

[0024] In order to reduce the input capacitance of the power semiconductor device, thereby reducing the electromagnetic interference when the power semiconductor device is turned on, while maintaining the feedback capacitance, taking the first conductive type as N type as an example, the present application provides a low electromagnetic interference power semiconductor device, specifically, the power semiconductor device comprises: a semiconductor substrate, which is of N conductive type; an active region, which is distributed in the central region of the semiconductor substrate and comprises a plurality of cells arranged in parallel, wherein, Each cell includes a cell trench 8 which penetrates the P-type well region 5 within the active region, and a trench gate 9 is filled in each cell trench 8; Within the active region, a trench isolation unit is arranged at least at one side of one cell, which is in contact with a side wall of the cell trench 8 within the cell, so as to isolate the cell trench 8 from the P-type well region 5 at the corresponding side by the trench isolation unit; The trench gate 9 within all the cells is electrically connected with the front first electrode metal above the front surface of the semiconductor substrate.

[0025] It should be understood that the power semiconductor device should include a semiconductor substrate, which can adopt a commonly used semiconductor material, such as silicon, SiC or other material types, and the material of the semiconductor substrate can be selected as needed, which will not be repeated here. The conductivity type of the semiconductor substrate can be selected as needed, such as N conductivity type.

[0026] In order to form a power semiconductor device, an active region should be prepared in the central region of the semiconductor, and the active region includes a plurality of parallel distributed cells, and the number of cells in the active region can be selected as needed, such as determined according to process conditions, which will not be repeated here. The cell of the present application adopts a trench type cell, which at least includes a cell trench 8, and generally, the cell trench 8 extends vertically from the front surface of the semiconductor substrate, and a trench gate 9 is filled in the cell trench 8, which can be formed by conductive polysilicon, of course, it can also be other forms, which can be selected as needed. In addition, a P-type well region 5 is arranged in the active region, which is generally distributed in the entire active region.

[0027] In order to maintain the feedback capacitance unchanged, the trench gate 9 within all the cells should be electrically connected with the front first electrode metal above the front surface of the semiconductor substrate, and the electrical connection between the trench gate 9 and the front first electrode metal can be at least ohmic contact, and the form of electrical connection can be selected as needed, which will not be repeated here. The front first electrode of the power semiconductor device can be formed by the front first electrode metal, and the type of the front first electrode corresponds to the type of the power semiconductor device, such as MOSFET or IGBT, so the front first electrode should be a gate electrode, and when the power semiconductor device is of other types, the formation of the front first electrode can be referred to the description here, which will not be repeated here.

[0028] In order to reduce the input capacitance of the power semiconductor device, at least one trench isolation unit is arranged on one side of a cell, the trench isolation unit is in contact with a sidewall of a cell trench 8 in the corresponding cell, and the cell trench 8 is isolated from the P-type well region 5 on the corresponding side by the trench isolation unit. For example, when the trench isolation unit is in contact with the first side sidewall of the cell trench 8, the cell trench 8 is isolated from the P-type well region 5 distributed on the first side of the cell trench 8 by the trench isolation unit. According to the formation mechanism of the input capacitance, the input capacitance of the power semiconductor device can be reduced at this time.

[0029] As can be seen from the above description, when the input capacitance is reduced, the ratio of the input capacitance to the feedback capacitance is also reduced, without changing the feedback capacitance of the power semiconductor device. Therefore, when the power semiconductor device is working, the risk of strong electromagnetic interference caused by gate voltage oscillation when the power semiconductor device is turned on can be reduced.

[0030] In one embodiment of the present application, for any cell, when a trench isolation unit is arranged on one side of the cell, an N+ source region 7 is arranged on the other side of the cell, wherein, The N+ source region 7 is located in the P-type well region 5, and the N+ source region 7 is in contact with the sidewall of the cell trench 8 in the cell. The N+ source region 7 and the P-type well region 5 are both electrically connected to the front second electrode metal above the first main surface of the semiconductor substrate.

[0031] As can be seen from the above description, the trench isolation unit can be arranged on one side of a cell, and therefore, when a trench isolation unit is arranged on one side of the cell, an N+ source region 7 is arranged on the other side of the cell. The N+ source region 7 is located in the P-type well region 5, and the N+ source region 7 is in contact with the sidewall of the cell trench 8 in the cell. At this time, a conductive channel can be formed on the side where the cell trench 8 is in contact with the N+ source region 7. Of course, the N+ source region 7 can not be arranged on the other side of the cell, and at this time, a conductive channel cannot be formed on both sidewalls of the cell trench 8.

[0032] The N+ source region 7 and the P-type well region 5 should be electrically connected to the front second electrode metal, and at this time, the front second electrode can be formed by using the front second electrode metal. The front second electrode is related to the type of the power semiconductor device. For example, when the power semiconductor device is a MOSFET device, the front second electrode should be a source electrode. When the power semiconductor device is an IGBT device, the front second electrode should be an emitter electrode. Other cases can be referred to the description herein, and will not be described here.

[0033] In one embodiment of the present application, for any cell, when groove isolation units are arranged on both sides of the cell, N+ source region 7 is arranged outside one groove isolation unit, or N+ source region 7 is arranged outside both groove isolation units; When N+ source region 7 is arranged outside one groove isolation unit, the N+ source region 7 is located in P-type well region 5, and the N+ source region 7 is in contact with the corresponding groove isolation unit. N+ source region 7 and P-type well region 5 are electrically connected with the front second electrode metal above the first main surface of the semiconductor substrate, and based on N+ source region 7, the groove isolation unit in contact with N+ source region 7, and the groove gate 9 in the cell trench 8, a conductive channel can be formed on the corresponding side of the cell trench 8.

[0034] It should be understood that groove isolation units can also be arranged on both sides of the cell, and when groove isolation units are arranged on both sides of the cell, the groove isolation units on both sides are symmetrically distributed. In addition, when groove isolation units are arranged on both sides of the cell, N+ source region 7 can be arranged outside one groove isolation unit, or N+ source region 7 can be formed outside both groove isolation units. Of course, N+ source region 7 can also not be arranged outside both groove isolation units. The arrangement of N+ source region 7 can be selected as needed, and the arrangement of N+ source region 7 will be described below.

[0035] When N+ source region 7 is arranged outside one groove isolation unit, the N+ source region 7 should be located in P-type well region 5, and the N+ source region 7 should be in contact with the corresponding groove isolation unit. The corresponding groove isolation unit specifically refers to the groove isolation unit outside which N+ source region 7 is arranged. When a groove unit is arranged on one side of the cell trench 8, the sidewall on the corresponding side of the cell trench will not be in contact with P-type well region 5, but P-type well region 5 will be in contact with the groove isolation unit.

[0036] In specific implementation, N+ source region 7 outside the groove isolation unit and the corresponding P-type well region 5 should be configured to be electrically connected with the front second electrode metal. At this time, based on N+ source region 7, the groove isolation unit in contact with N+ source region 7, and the groove gate 9 in the cell trench 8, a conductive channel can be formed on the corresponding side of the cell trench 8. The way of forming the conductive channel is consistent with the prior art.

[0037] It can be understood that when N+ source region 7 is not arranged outside the groove isolation unit, a conductive channel cannot be formed on the corresponding side of the cell trench 8. Therefore, when groove isolation units are arranged on both sides of all cells, N+ source region 7 should be arranged outside part of the groove isolation units and configured to form a conductive channel. When the groove isolation units are distributed in other ways on the side of the cell, at least a corresponding number of conductive channels should be ensured to exist, so as not to affect the normal function of the power semiconductor device.Figure 1 The figure illustrates an embodiment of the power semiconductor device of the present invention. The figure shows a case with two cells, with trench isolation units provided on both sides of the trench 8 in each cell. For the cell on the left side of the figure, an N+ source region 7 is provided outside one trench isolation unit, while for the cell on the right side of the figure, no N+ source region 7 is provided outside either of the two trench isolation units. Other cases can be referred to... Figure 1 And the explanation here.

[0038] In one embodiment of the present invention, the trench isolation unit includes an isolation trench 12 and an isolation conductive polycrystalline silicon 10 filled within the isolation trench 12, wherein, The isolation trench 12 extends vertically from the front side of the semiconductor substrate toward the bottom of the cell trench 8. The bottom of the isolation trench 12 is located below the P-type well region 5 and above the bottom of the cell trench 8. The conductive polycrystalline silicon 10 is insulated from the inner wall of the isolation trench 12; When an N+ source region 7 is provided on the outside of the trench isolation unit, and a conductive channel is formed based on the N+ source region 7 and the trench gate 9, the isolation conductive polysilicon 10 in the trench isolation unit is at least electrically connected to the front first electrode metal; otherwise, the isolation conductive polysilicon 10 in the isolation unit is in a floating state.

[0039] Figures 1-3 An embodiment of a trench isolation unit is shown in the figure. As can be seen from the figure, the trench isolation unit may include an isolation trench 12 and an isolation conductive polysilicon 10. The depth direction of the isolation trench 12 is consistent with the depth direction of the cell trench 8, such that the depth direction of the cell trench 8 is along the front side of the semiconductor substrate pointing towards the back side of the semiconductor substrate. Although the depth direction of the isolation trench 12 is consistent with the depth direction of the cell trench 8, the depth of the isolation trench 12 should be less than the depth of the cell trench 8. Therefore, the bottom of the isolation trench 12 should be located above the bottom of the cell trench 8, so as to minimize the input capacitance while keeping the feedback capacitance constant. In addition, the cell trench 8 is elongated, and the length direction of the isolation trench 12 is consistent with the length direction of the cell trench 8, such as... Figure 2 As shown.

[0040] When an N+ source region 7 is provided on the outer side of the trench isolation unit, a conductive channel can be formed. Therefore, the bottom of the isolation trench 12 should be located below the P-type well region 5. Simultaneously, the N+ source region 7 should be in contact with the outer wall of the isolation trench 12, and the N+ source region 7 should also be located above the bottom of the isolation trench 12. When a conductive channel needs to be formed, the isolation conductive polysilicon 10 within the trench isolation unit should be electrically connected to at least the front first electrode metal. Specifically, the trench isolation unit refers to the trench isolation unit with the N+ source region 7 on its outer side. Therefore, when a conductive channel is not required, the isolation conductive polysilicon 10 within the isolation trench 12 on the corresponding side of the cell trench 8 should be configured in a floating state to reduce the input capacitance. Specifically, being in a floating state means that the corresponding isolation conductive polysilicon 10 is neither electrically connected to the front first electrode metal nor to the front second electrode metal.

[0041] In order to form the second electrode on the front side, by Figure 1 and Figure 3 It is known that a contact hole 6 should be provided on the front side of the semiconductor substrate, and a P+ emitter region 11 should be provided at the bottom of the contact hole 6. The doping concentration of the P+ emitter region 11 is greater than that of the P-type well region 5. The P+ emitter region 11 is in contact with the N+ source region 7. The N+ source region 7 and the P+ emitter region 11 can be exposed through the contact hole 6. Thus, when performing the front side metal process, the front side second electrode metal can be filled in the contact hole 6, thereby achieving ohmic contact between the front side second electrode metal and the N+ source region 7 and the P+ emitter region 11.

[0042] When the trench isolation unit adopts the example described above, the sidewall corresponding to the cell trench 8 cannot contact the P-type well region 5, and no N+ source region 7 is provided on the outer side of the corresponding trench isolation unit. This achieves isolation between the cell trench 8 and the corresponding P-type well region 5. When the power semiconductor device is an IGBT-type device, because the ratio of the input capacitance to the feedback capacitance is relatively small, the rate of change of the collector voltage during turn-on can be effectively reduced, thus reducing the voltage stress on the load.

[0043] In one embodiment of the present invention, when an N+ source region 7 is provided on the outer side of the trench isolation unit, and a conductive channel is formed based on the N+ source region 7 and the trench gate 9, the isolation conductive polysilicon 10 in the trench isolation unit contacts the trench gate 9 in the corresponding cell trench 8 through one or more trench holes 14, and both the isolation conductive polysilicon 10 and the trench gate 9 are electrically connected to the front first electrode metal.

[0044] As explained above, when a conductive channel needs to be formed, the corresponding isolation conductive polysilicon 10 should be electrically connected to the front first electrode metal. It is understood that when electrically connected to the front first electrode metal, the front first electrode metal can be in ohmic contact directly with the isolation conductive polysilicon 10. To improve the stability and reliability of the formed conductive channel, the isolation conductive polysilicon 10 should also be configured to contact the trench gate 9 through the trench via 14. Afterward, both the isolation conductive polysilicon 10 and the trench gate 9 will be in ohmic contact with the front first electrode metal.

[0045] Figures 1-3 The figure shows an embodiment in which the contact between the conductive polysilicon 10 and the trench gate 9 is blocked by the trench hole 14. As can be seen from the figure, when there are multiple trench holes 14, the multiple trench holes 14 are arranged sequentially along the length direction of the cell trench 8, and the depth of each trench hole 14 does not exceed the trench depth of the blocking trench 12.

[0046] In one embodiment of the present invention, the trench hole 14 penetrates the cell insulating gate oxide layer 13 within the cell trench 8 and the corresponding isolation dielectric layer 15 within the isolation trench 12, wherein, The cell insulating gate oxide layer 13 covers the inner wall of the cell trench 8, and the trench gate 9 is insulated and isolated from the inner wall of the cell trench 8 through the cell insulating gate oxide layer 13. The insulating dielectric layer 15 covers the corresponding inner wall of the insulating trench 12, and the insulating conductive polycrystalline silicon 10 is insulated and isolated from the interior of the insulating trench 12 through the insulating dielectric layer 15.

[0047] To achieve contact between the conductive polysilicon 10 and the trench gate 9, the trench via 14 should penetrate the cell insulating gate oxide layer 13 within the cell trench 8 and the corresponding isolation dielectric layer 15 within the isolation trench 12. Specifically, the cell insulating gate oxide layer 13 is disposed within the cell trench 8 and covers the inner wall of the cell trench 8, while the isolation dielectric layer 15 is disposed within the isolation trench 12 and covers the inner wall of the isolation trench 12. It should be noted that the cell insulating gate oxide layer 13 is a silicon dioxide layer, and the isolation dielectric layer 15 is generally also a silicon dioxide layer. When the isolation dielectric layer 15 is also a silicon dioxide layer, it can be prepared using the same process steps as the cell insulating gate oxide layer 13.

[0048] Generally, after the isolation dielectric layer 15 and the cell insulating gate oxide layer 13 are prepared, trench holes 14 can be prepared by etching processes, etc. Then, trench gate 9 and isolation conductive polysilicon 10 are filled, so that the isolation conductive polysilicon 10 can contact the trench gate 9. The trench gate 9 can also generally be made of conductive polysilicon.

[0049] In one embodiment of the present invention, an N-type carrier storage layer 4 is further disposed within the semiconductor substrate, wherein, The N-type carrier storage layer 4 traverses the active region, and the upper end of the N-type carrier storage layer 4 is in contact with the P-type well region 5. The bottom of the isolation trench 12 is located inside the N-type carrier storage layer 4, and the bottom of the cell trench 8 is located below the first conductivity type carrier storage layer.

[0050] Figure 1 and Figure 3 The figure illustrates an embodiment of a semiconductor substrate. As shown, the semiconductor substrate may include an N-type base region 1 and an N+ field-stop buffer layer 3. The N-type base region 1 is located on the N+ field-stop buffer layer 3. The front side of the semiconductor substrate is formed through the surface corresponding to the N-type base region 1, and the back side of the semiconductor substrate is formed through the surface corresponding to the N+ field-stop buffer layer 3. The front and back sides of the semiconductor substrate are directly opposite each other. Generally, the doping concentration of the N-type base region 1 is lower than the doping concentration of the N+ field-stop buffer layer 3.

[0051] Figure 1 and Figure 3 In this design, an N-type carrier storage layer 4 is also provided within the N-type base region 1. Generally, the N-type carrier storage layer 4 should be distributed throughout the entire active region. The upper end of the N-type carrier storage layer 4 contacts the P-type well region 5. The N-type carrier storage layer 4 can optimize the carrier distribution and improve the performance of power semiconductor devices. For example, it can effectively block the rapid extraction of hole carriers by the emitter, increase the carrier concentration in the N-type base region 1, and thus reduce the on-state loss of the IGBT. When the N-type carrier storage layer 4 is provided, the bottom of the isolation trench 12 is located within the N-type carrier storage layer 4, and the bottom of the cell trench 8 is located below the carrier storage layer of the first conductivity type. Figure 1 and Figure 3 As shown; at this point, the hole channel can be further narrowed, effectively blocking the extraction of hole carriers and further improving the carrier storage capacity.

[0052] In one embodiment of the present invention, when the power semiconductor device is an IGBT type device, a back electrode structure is further provided on the back side of the semiconductor substrate, wherein the back electrode structure includes at least a P+ collector region 2.

[0053] Figure 1 and Figure 3 The figure illustrates one embodiment of an IGBT-type power semiconductor device. As shown, a P+ collector region 2 is disposed on the N+ field cutoff buffer layer 3. The collector electrode of the IGBT-type device is formed through the ohmic contact between the P+ collector region 2 and the collector region metal. It should be understood that the collector region metal is not shown in the figure. Of course, the back electrode structure can also take other forms, which can be selected according to the specific needs. Examples will not be given here.

Claims

1. A power semiconductor device with low electromagnetic interference, characterized in that, The power semiconductor device includes: The semiconductor substrate exhibits a first conductivity type; The active region, located in the central region of the semiconductor substrate, comprises several cells arranged in parallel, wherein... Each cell includes a cell trench that penetrates a second conductivity type well region within the active region, and each cell trench is filled with a trench gate. Within the active region, a trench isolation unit is provided on one side of at least one cell, the trench isolation unit being in contact with one side wall of the cell trench within the cell, so as to isolate the cell trench from the second conductivity type well region on the corresponding side using the trench isolation unit. All trench gates within each cell are electrically connected to the first front electrode metal above the front side of the semiconductor substrate.

2. The low electromagnetic interference power semiconductor device according to claim 1, characterized in that: For any cell, when a trench isolation unit is provided only on one side of the cell, a first conductivity type source region is provided on the other side of the cell, wherein, The first conductivity type source region is located within the second conductivity type well region, and the first conductivity type source region is in contact with the sidewall of the cell trench within the cell. Both the source region of the first conductivity type and the well region of the second conductivity type are electrically connected to the front second electrode metal above the first main surface of the semiconductor substrate.

3. The low electromagnetic interference power semiconductor device according to claim 1, characterized in that: For any cell, when trench isolation units are provided on both sides of the cell, a first conductivity type source region is provided on the outside of one trench isolation unit, or a first conductivity type source region is provided on the outside of both trench isolation units. When a first conductive type source region is provided on the outside of a trench partition unit, the first conductive type source region is located within a second conductive type well region, and the first conductive type source region is in contact with the corresponding trench partition unit. Both the first conductivity type source region and the second conductivity type well region are electrically connected to the front second electrode metal above the first main surface of the semiconductor substrate, and conductive channels can be formed on the corresponding side of the cell trench based on the first conductivity type source region, the trench isolation unit in contact with the first conductivity type source region, and the trench gate in the cell trench.

4. The low electromagnetic interference power semiconductor device according to claim 3, characterized in that: The trench isolation unit includes an isolation trench and isolation conductive polycrystalline silicon filled within the isolation trench, wherein... The isolation trench extends vertically from the front side of the semiconductor substrate toward the bottom of the cell trench. The bottom of the isolation trench is located below the second conductivity type well region and above the bottom of the cell trench. The conductive polycrystalline silicon is insulated from the inner wall of the isolation trench; When a first conductivity type source region is provided on the outside of the trench isolation unit, and a conductive channel is formed based on the first conductivity type source region and the trench gate, the isolation conductive polysilicon in the trench isolation unit is at least electrically connected to the front first electrode metal; otherwise, the isolation conductive polysilicon in the isolation unit is in a floating state.

5. The low electromagnetic interference power semiconductor device according to claim 4, characterized in that: When a first conductivity type source region is provided on the outside of the trench isolation unit, and a conductive channel is formed based on the first conductivity type source region and the trench gate, the isolation conductive polysilicon in the trench isolation unit contacts the trench gate in the corresponding cell trench through one or more trench holes, and both the isolation conductive polysilicon and the trench gate are electrically connected to the front first electrode metal.

6. The low electromagnetic interference power semiconductor device according to claim 5, characterized in that: When there are multiple groove holes, the multiple groove holes are arranged sequentially along the length direction of the cell groove, and the depth of each groove hole does not exceed the groove depth of the partition groove.

7. The low electromagnetic interference power semiconductor device according to claim 6, characterized in that: The trench holes penetrate the cell insulating gate oxide layer within the cell trench and the corresponding isolation dielectric layer within the isolation trench, wherein... The cell insulating gate oxide layer covers the inner wall of the cell trench, and the trench gate is insulated and isolated from the inner wall of the cell trench through the cell insulating gate oxide layer; The insulating dielectric layer covers the corresponding inner wall of the insulating trench, and the insulating conductive polycrystalline silicon is insulated and isolated from the interior of the insulating trench through the insulating dielectric layer.

8. The low electromagnetic interference power semiconductor device according to claim 4, characterized in that: The cell groove is elongated, and the length direction of the partition groove is consistent with the length direction of the cell groove.

9. The low electromagnetic interference power semiconductor device according to any one of claims 4 to 8, characterized in that: in The semiconductor substrate further comprises a first conductivity type carrier storage layer, wherein... The first type of conductivity carrier storage layer traverses the active region, and the upper end of the first type of conductivity carrier storage layer is in contact with the second type of conductivity well region. The bottom of the isolation trench is located within the first conductivity type carrier storage layer, and the bottom of the cell trench is located below the first conductivity type carrier storage layer.

10. The low electromagnetic interference power semiconductor device according to any one of claims 1 to 8, characterized in that: When the power semiconductor device is an IGBT type device, a back electrode structure is also provided on the back side of the semiconductor substrate, wherein the back electrode structure includes at least a collector region of a second conductivity type.

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