First electrode structure of infrared focal plane detector chip and preparation method

Abstract

According to the first electrode structure of the infrared focal plane detector chip and the preparation method, an N-type substrate forms a junction in a diffusion or ion implantation mode, and a mesa structure is prepared and formed through wet etching or dry etching; the electrode layer is directly prepared on the table top of the substrate material and forms ohmic contact with the table top of the substrate; the passivation layer is of a double-layer passivation film structure, and the indium column layer is prepared through photoetching development, a coating machine and a stripping process and is in direct contact with the exposed electrode layer; the infrared focal plane array photoelectric sensor is based on mature semiconductor processes such as magnetron sputtering, photoetching and wet etching, does not need to add special equipment, can directly adapt to an existing production line, reduces the cost of technology upgrading and industrial application, and lays a foundation for large-scale application of low-cost, large-size and small-pixel infrared focal plane array photoelectric sensors.

Description

Technical Field

[0001] This invention relates to the field of infrared detection technology, specifically to the electrode structure and fabrication method of an infrared focal plane detector chip. Background Technology

[0002] In the field of infrared detection, with the continuous improvement of requirements for detection distance and spatial resolution, cooled infrared detectors are rapidly developing towards large arrays and small pixels, which places more stringent demands on the performance of infrared focal plane array chips. The passivation effect of the semiconductor substrate material surface is a key factor in ensuring the stable photoelectric performance of infrared focal plane array chips—the passivation layer on the chip surface can effectively insulate the mesa sidewall channels of the semiconductor substrate material, avoid leakage current, and at the same time protect the material surface in subsequent processes.

[0003] However, as pixel size decreases, the passivation process becomes significantly more difficult, and leakage problems become increasingly prominent. Current mainstream passivation methods have obvious drawbacks: When preparing alumina or silicon oxide / silicon nitride passivation layers using plasma-enhanced chemical vapor deposition or atomic layer deposition, defects are easily formed at the interface due to lattice mismatch between materials, leading to leakage current. After the passivation layer is prepared by anodizing, during the subsequent wet etching process for opening holes, especially for small pixel structures, the corrosion rate is too fast, which can easily cause excessive corrosion of the anodized passivation layer on the substrate material surface, which then erodes to the mesa sidewalls and eventually leads to the electrical failure of the PN junction. While dry etching for passivation layer openings can reduce lateral drilling, high-energy particle bombardment can easily cause lattice damage to the semiconductor substrate material, affecting the chip's optoelectronic performance.

[0004] Therefore, improving the surface passivation effect of small-pixel infrared focal plane array chips, reducing leakage current problems, and enhancing device stability through structural design optimization and process control has significant technical value and application significance. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a first electrode structure and fabrication method for an infrared focal plane detector chip. Based on mature semiconductor processes such as magnetron sputtering, photolithography, and wet etching, it does not require additional special equipment and can be directly adapted to existing production lines, reducing the cost of technology upgrades and industrial applications. This lays the foundation for the large-scale application of low-cost, large-size, small-pixel infrared focal plane array photoelectric sensors.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: an electrode structure for an infrared focal plane detector chip, comprising: an N-type substrate, an electrode layer, a passivation layer, and an indium pillar layer; The N-type substrate is formed by diffusion or ion implantation, and a mesa structure is prepared by wet etching or dry etching. The electrode layer is directly fabricated on the mesa of the substrate material and is processed by photolithography, development, etching or stripping processes to form an ohmic contact with the substrate mesa. The passivation layer is a double-layer passivation film structure, which is prepared by anodizing, magnetron sputtering, chemical vapor deposition or atomic layer deposition. During the preparation process, the electrode layer is protected by an insulating medium. The indium pillar layer is prepared by photolithography, coating machine and stripping process, and is in direct contact with the exposed electrode layer.

[0007] Furthermore, the infrared focal plane array corresponding to the substrate material is a 320×256 array or above, with a pixel size of less than 30μm, and its material is one of InSb, HgCdTe, InAsSb or a superlattice, and the thickness of the substrate material is 500μm.

[0008] Furthermore, the electrode layer is made of one or more of Ti, Ti / Ni composite metal, Au, Cr, or Al, and has a thickness of 100nm-300nm.

[0009] Furthermore, the insulating medium is selected from photoresist, silicon oxide, silicon nitride, or aluminum oxide; the thickness of the indium pillar layer is 3-7 μm.

[0010] A method for fabricating the electrode structure of an infrared focal plane detector chip includes the following steps: Step 1: Select a substrate material of the target specifications, form a junction through diffusion or ion implantation, and then fabricate a mesa structure through photolithography and wet etching or dry etching processes; Step 2: A metal thin film is prepared on the mesa of the substrate material using a magnetron sputtering coating machine. After photolithography and development, an electrode layer with ohmic contact with the substrate mesa is formed by etching or stripping processes. Step 3: Photolithography and development are performed on the electrode layer with an insulating medium. The first passivation film is prepared by anodizing, magnetron sputtering, chemical vapor deposition or atomic layer deposition. After removing the insulating medium, the second passivation film is prepared to form a double-layer passivation layer. Step 4: The passivation layer is opened by photolithography and wet etching to expose the target area of ​​the electrode layer; Step 5: Define the indium pillar pattern by photolithography and development, prepare an indium thin film by evaporation deposition, and form an indium pillar layer in contact with the electrode layer by a lift-off process.

[0011] Furthermore, in step 2, the etching solution used in the etching process is a mixture of buffered hydrofluoric acid, concentrated hydrochloric acid and water, or an etching solution of Au and Cr in a conventional ratio in the art.

[0012] The beneficial effects of the present invention are as follows: Compared with the prior art, the present invention has the following significant beneficial effects: Structural innovation improves passivation effect: This invention proposes a hierarchical structure of electrode first and passivation later, which directly prepares the electrode layer on the substrate mesa, changing the traditional process sequence of passivation first and then electrode. This structure allows the electrode layer to act as a hidden marker or barrier layer when the passivation layer is opened by wet etching, effectively improving the process margin, accurately monitoring the amount of etching, avoiding excessive etching of the mesa sidewall, and significantly reducing leakage problems.

[0013] Improving interconnect accuracy and ensuring device stability: The indium pillar layer is in direct contact with the pre-prepared electrode layer. The pattern accuracy of the electrode layer provides a clear positioning reference for the growth of the indium pillar, which greatly improves the consistency of the indium pillar growth position, thereby improving the alignment accuracy of subsequent flip-chip interconnects, reducing the risk of interconnect failure, and ensuring the long-term operational stability of the device.

[0014] Compatible with existing processes and reducing application costs: The preparation method of this invention is based on mature semiconductor processes such as magnetron sputtering, photolithography, and wet etching. No new special equipment is required, and it can be directly adapted to existing production lines, reducing the cost of technology upgrades and industrial applications. This lays the foundation for the large-scale application of low-cost, large-size, small-pixel infrared focal plane array photoelectric sensors. Areas not described in detail in this invention are commonly used existing technologies. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the cross-sectional structure; Figure 2 This is a top-down perspective structural diagram; In the figure: N-type substrate 1, electrode layer 2, passivation layer 3, indium pillar layer 4. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to embodiments and specific implementation methods: Example 1

[0017] Substrate pretreatment and mesa fabrication: An InSb substrate material with an array size of 320×256, a pixel center-to-center distance of 30μm, and a thickness of 500μm was selected. After forming a PN junction on the InSb substrate material using a diffusion process, a mesa junction was fabricated by wet etching after photolithography.

[0018] Electrode layer preparation: Ti thin film was prepared by magnetron sputtering with a sputtering power of 360W and a thickness of 100nm. After defining the electrode pattern by photolithography, a mixture of buffered hydrofluoric acid, concentrated hydrochloric acid and water was used for wet etching to form the Ti electrode layer, which forms an ohmic contact with the substrate mesa.

[0019] Passivation layer preparation: After resist removal, the Ti electrode layer is protected by photoresist as an insulating medium, and an anodized layer is prepared as the first passivation film using an anodizing process; after resist removal, the second passivation film is prepared by magnetron sputtering to form a double passivation layer.

[0020] Passivation layer opening: Photolithography defines the opening location, wet etching removes the passivation film in the target area, and exposes the Ti electrode layer.

[0021] Indium pillar layer preparation: Photolithography defines the indium pillar pattern, evaporation deposits a 3-7 μm thick indium film, and after stripping, an indium pillar array is formed, which contacts the Ti electrode layer. Example 2

[0022] Substrate pretreatment and mesa fabrication: An InSb substrate material with an array size of 640×512, a pixel center-to-center distance of 15μm, and a thickness of 500μm was selected. After forming a PN junction on the InSb substrate material using ion implantation, the mesa structure was fabricated by dry etching after photolithography.

[0023] Electrode layer fabrication: Photolithography defines the electrode pattern, and magnetron sputtering is used to deposit a Ti / Ni composite thin film with a sputtering power of 360W for Ti and 500W for Ni, resulting in a total thickness of 300nm. Excess metal is removed by a lift-off process to form the Ti / Ni electrode layer.

[0024] Passivation layer preparation: After resist removal, the Ti / Ni electrode layer is protected with photoresist and anodized to prepare the first passivation film; after resist removal, the second passivation film is prepared by magnetron sputtering to form a double passivation layer.

[0025] Passivation layer opening: After photolithography and development, wet etching is used to open the passivation layer to expose the Ti / Ni electrode layer.

[0026] Indium pillar layer fabrication: Indium pillar patterns are defined by photolithography, 3-7 μm thick indium films are deposited by evaporation, and indium pillar arrays are formed by peeling and contact with Ti / Ni electrode layers. Example 3

[0027] The difference from Example 1 is that in step 3, a silicon oxide / silicon nitride film layer is prepared by PECVD as an insulating medium, and the metal electrode is protected by a peeling method. Example 4

[0028] The difference from Example 2 is that in step 2, an aluminum thin film is prepared by magnetron sputtering with a sputtering power of 500W and a thickness of 300nm, and a metal electrode layer is prepared by peeling.

[0029] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A first electrode structure for an infrared focal plane detector chip, characterized in that, The components include: N-type substrate (1), electrode layer (2), passivation layer (3), indium pillar layer (4); The N-type substrate (1) is formed by diffusion or ion implantation, and a mesa structure is prepared by wet etching or dry etching. The electrode layer (2) is directly fabricated on the mesa of the substrate material (1) and forms an ohmic contact with the mesa by photolithography, development and etching or stripping processes. The passivation layer (3) is a double-layer passivation film structure, which is prepared by anodizing, magnetron sputtering, chemical vapor deposition or atomic layer deposition. During the preparation process, the electrode layer (2) is protected by an insulating medium. The indium pillar layer (4) is prepared by photolithography, coating machine and stripping process, and is in direct contact with the exposed electrode layer (2).

2. The electrode structure of the infrared focal plane detector chip according to claim 1, characterized in that, The infrared focal plane array corresponding to the substrate material (1) is a 320×256 array or above, with a pixel size of less than 30μm. Its material is one of InSb, HgCdTe, InAsSb or superlattice, and the thickness of the substrate material (1) is 500μm.

3. The first electrode structure of the infrared focal plane detector chip according to claim 1, characterized in that, The electrode layer (2) is made of one or more of Ti, Ti / Ni composite metal, Au, Cr or Al, and has a thickness of 100nm-300nm.

4. The electrode structure of the infrared focal plane detector chip according to claim 1, characterized in that, The insulating medium is selected from photoresist, silicon oxide, silicon nitride or aluminum oxide; the thickness of the indium pillar layer (4) is 3-7 μm.

5. A method for fabricating the electrode structure of an infrared focal plane detector chip as described in any one of claims 1-4, characterized in that, Includes the following steps: Step 1: Select a substrate material of the target specification (1), and after forming a junction by diffusion or ion implantation, prepare a mesa structure by photolithography and wet etching or dry etching process; Step 2: A metal thin film is prepared on the mesa of the substrate material (1) using a magnetron sputtering coating machine. After photolithography and development, an electrode layer (2) that is in ohmic contact with the mesa of the substrate is formed by etching or stripping processes. Step 3: Photolithography is performed on the electrode layer (2) with an insulating medium for protection. The first passivation film is prepared by anodizing, magnetron sputtering, chemical vapor deposition or atomic layer deposition. After removing the insulating medium, the second passivation film is prepared to form a double-layer passivation layer (3). Step 4: The passivation layer (3) is opened by photolithography and wet etching to expose the target area of ​​the electrode layer (2); Step 5: Define the indium pillar pattern by photolithography and development, prepare an indium thin film by evaporation deposition, and form an indium pillar layer (4) in contact with the electrode layer (2) by a stripping process.

6. The preparation method according to claim 5, characterized in that, In step 2, the etching solution used in the etching process is a mixture of buffered hydrofluoric acid, concentrated hydrochloric acid and water, or an etching solution of Au and Cr. The etching solution of Au and Cr adopts the conventional ratio in the art.

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