A dry etching method for indium-containing III-V compound semiconductor materials

Abstract

A dry etching method for indium-containing III-V compound semiconductor materials, relating to the field of semiconductor laser processing technology, solves the problem of volatile InCl during etching of indium-containing compound semiconductor laser materials in existing technologies. x Deposition leads to decreased etching rates, cavity contamination, and high-temperature assisted etching causes mask loss, morphology degradation, and process instability. This invention addresses these issues by setting a cycle program that alternates between etching and rinsing pulses. During the etching stage, H2 is introduced to suppress the formation of non-volatile InCl3 products and simultaneously convert InCl3 products into InCl2, effectively inhibiting byproduct formation and improving etching efficiency. During the physical rinsing stage, Ar is used to effectively remove non-volatile InCl3 adhering to the surface of the etched material. x The product exposes the semiconductor substrate, promoting chemical pulses to carry out chemical reactions to etch the substrate, effectively preventing cavity contamination and a decrease in etching uniformity, and significantly improving the controllability and repeatability of the etching morphology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, and specifically to a dry etching method for indium-containing III-V compound semiconductor materials. Background Technology

[0002] Semiconductor lasers are optoelectronic devices that can directly convert electrical energy into optical energy. Their core principle is to utilize semiconductor materials as the active region, achieving stimulated emission under applied current injection, thereby generating laser output with high directionality, monochromaticity, and coherence. Compared to solid-state and gas lasers, semiconductor lasers possess significant advantages such as high electro-optical conversion efficiency, fast start-up response, small size, long lifetime, and ease of integration, and have been widely applied in optical communication, optical storage, laser ranging, industrial precision machining, biosensing, and environmental monitoring. A typical semiconductor laser structure consists of multiple layers of III-V compound semiconductor epitaxial materials, such as GaAs, InP, AlGaAs, InGaAsP, and their alloys. The overall structure typically includes an active region, waveguide layer, confinement layer, cladding, and electrode contact layer. The active region often employs a quantum well structure to achieve quantum confinement of charge carriers and high-efficiency radiative recombination; the waveguide layer and confinement layer form an optical confinement structure through refractive index differences to ensure effective focusing and stable output of the light field within the active region.

[0003] In the fabrication of semiconductor lasers, etching is a crucial step in realizing micro- and nano-structure processing. Etching selectively removes areas of material not masked by the resist layer through chemical reactions, physical sputtering, or a combination of both, thereby forming a structural pattern on the thin film surface that matches the mask pattern. Based on the removal mechanism and etching medium, etching methods can be broadly classified into wet etching and dry etching. Wet etching is a traditional method that relies on liquid-phase chemical reactions to immerse the sample in specific chemical reagents, causing the exposed material to react and dissolve. Its characteristics include a fast etching rate but strong isotropy, making precise depth and sidewall control difficult. In contrast, dry etching utilizes plasma or ion beams in the gas phase to react and sputter the material, exhibiting excellent anisotropic etching characteristics and producing vertical sidewalls and high-fidelity patterns. Therefore, dry etching has become the mainstream process for microstructure fabrication in semiconductor lasers.

[0004] In dry etching of antimonide and other indium (In)-containing III–V semiconductor laser materials, a commonly used etching system is a BCl3 / Cl2-based mixed gas, which can effectively react with and remove volatile chlorides formed by elements such as As, Ga, and Sb. However, when etching In-containing compounds (such as InP, InAs, InSb, InGaAsSb), the InCl generated by the reaction of In with Cl... xInCl3, in particular, has extremely low volatility, forming non-volatile residues or polymer films on the material surface. This hinders the continued etching reaction, leading to problems such as decreased etching rate, increased surface roughness, and cavity contamination. To mitigate this issue, current technologies typically employ increasing the substrate temperature (>130°C) to raise the etching temperature above that of InCl3. x The partial boiling point of InCl3 is used to promote its volatilization and removal. However, the vaporization temperature of InCl3 is as high as about 600℃, making it difficult to achieve complete vaporization in conventional etching equipment. At the same time, high-temperature etching also brings a series of problems such as accelerated mask layer loss leading to insufficient trench depth, increased chemical etching ratio leading to sidewall chamfering and edge diffusion, and local over-reaction causing surface morphology deterioration. These problems make high-temperature etching unsuitable for the fabrication process of lasers with delicate structures and high thermal sensitivity.

[0005] To address the aforementioned issues, an etching method capable of achieving efficient etching at room temperature is proposed, enabling controllable etching of In III–V compound materials. This is a core research direction for improving the processing quality and process controllability of antimonyide laser microstructures. Summary of the Invention

[0006] To address the issue of volatile InCl₂ released during the etching of In compound semiconductor laser materials in existing technologies. x Deposition leads to decreased etching rates and cavity contamination, while high-temperature assisted etching causes mask loss, morphology degradation, and process instability. This invention proposes a dry etching method for indium-containing III-V compound semiconductor materials. The technical solution of this invention is as follows:

[0007] A dry etching method for indium-containing III-V compound semiconductor materials includes the following preparation steps:

[0008] S1: Set the etching pulse parameters, and set the etching gases to BCl3, Cl2, H2, and Ar; wherein, set the H2 flow rate to 1 sccm~5 sccm, and the Ar flow rate to 1 sccm~10 sccm; set the rinsing pulse parameters;

[0009] S2: Start etching, set the cycle timing of alternating etching pulses and cleaning pulses until the etching depth reaches the target etching depth;

[0010] S3: The indium-containing III-V compound semiconductor material is immersed in an etching solution and acid-washed to obtain the etched indium-containing III-V compound semiconductor material.

[0011] Furthermore, the indium-containing III-V compound semiconductor material includes InP, InAs, InGaAs, InAlAs, InGaAsP, and InGaAsS.

[0012] Furthermore, the indium-containing III-V compound semiconductor material is cleaned before etching. The cleaning process involves sequentially cleaning with acetone, ethanol, and deionized water, followed by drying with high-purity nitrogen gas.

[0013] Furthermore, the etching pulse parameters are set as follows: the substrate etching temperature is set to 10 ℃~30 ℃; the internal cavity pressure is set to 2 mTorr~8 mTorr; the ICP power is set to 100 W~500 W; the RF bias voltage is set to 50 W~100 W; the BCl3 flow rate is set to 3 sccm~15 sccm; and the Cl2 flow rate is set to 5 sccm~20 sccm.

[0014] Furthermore, the flushing pulse parameters are set as follows: the substrate cleaning temperature is set to 10 ℃~30 ℃; the internal pressure of the cavity is set to 5 mTorr~15 mTorr; the ICP power is set to 300 W~500 W; the RF bias voltage is set to 100 W~300 W; the Ar flow rate is set to 10 sccm~20 sccm; the BCl3 flow rate is set to 0.5 sccm; and the Cl2 flow rate is set to 0.5 sccm.

[0015] Furthermore, the alternating timing of the etching pulse and cleaning pulse is as follows: etching pulse for 5 s to 30 s, pause for 0.5 s to 2 s to wait for the chamber to stabilize; after the chamber stabilizes, physical rinsing pulse for 1 s to 5 s, pause for 0.5 s to 2 s to wait for the chamber to stabilize, completing one cycle. The alternating timing of the etching pulse and cleaning pulse is repeated until the etching depth reaches the target etching depth.

[0016] Furthermore, the cyclic timing of alternating etching pulses and cleaning pulses is repeated 12 to 30 times.

[0017] Furthermore, the corrosion solution is a mixed aqueous solution of H3PO4 / HBr.

[0018] Compared with the prior art, the present invention solves the problem of volatile InCl during etching of In-containing compound semiconductor laser materials in the prior art. x Deposition leads to decreased etching rate and cavity contamination, while high-temperature assisted etching causes mask loss, morphology degradation, and process instability. Specific beneficial effects include:

[0019] 1. Suppressing Byproducts and Improving Etching Efficiency: This invention introduces H2 and Ar into the BCl3 and Cl2 etching gases to form an etching pulse for etching and cleaning In-containing semiconductor laser materials. The introduction of H2 can form volatile indium hydrides with metallic indium, thereby preventing InCl3 deposition. Simultaneously, the addition of H2 alters the proportion of active chlorine radicals in the plasma, making the reaction more inclined to generate volatile products. The H generated within the system... + A hydrogenation reaction occurs, inhibiting the formation of non-volatile InCl3 products and converting them into InCl2. This prevents their redeposition in the etched area, thereby improving the continuity, stability, controllability, and uniformity of the etching process, reducing the formation of non-volatile substances, and improving anisotropy and surface quality. This invention achieves efficient etching reactions at low temperatures and exhibits excellent process compatibility and interface quality control capabilities.

[0020] 2. Constructing a periodic etching mode alternating between etching pulses and physical rinsing pulses: This invention achieves the synergistic effect of chemical etching and physical cleaning by setting a periodic sequence of alternating etching pulses and rinsing pulses. During the etching stage, plasma dominated by BCl3 and Cl2 achieves rapid reactive etching of the material; during the physical rinsing stage, high-energy Ar generated by Ar is utilized... + Physical sputtering effectively removes non-volatile InCl adhering to the surface of etched materials. x The product exposes the semiconductor substrate, promoting chemical etching through a chemical pulse reaction. By alternating etching, intermittent etching, and rinsing stages, a periodic balance between etching reaction and cleaning is achieved in the time domain. This breaks through the unidirectional "reaction-deposition-blocking" process in traditional continuous dry etching, avoiding the mask corrosion and morphology degradation problems commonly found in high-temperature assisted etching. While retaining the selectivity and stability of dry etching, this invention effectively prevents cavity contamination and a decrease in etching uniformity, achieving simultaneous optimization of etching rate and surface quality, and significantly improving the controllability and repeatability of the etching morphology.

[0021] 3. Achieving High-Cleanliness Etched Interfaces through Acid Pickling: After etching, this invention further employs an etching solution to immerse and pickle the etched indium-containing III-V compound semiconductor material to remove any residual metal chlorides or surface oxide layers. The acid pickling process, used in conjunction with the aforementioned periodic etching pulses, achieves thorough removal of surface residues and reactivation of the lattice interface, providing a high-cleanliness interface for subsequent device epitaxy or electrode deposition. This invention achieves a balance between etching rate, surface smoothness, and structural integrity, significantly improving etching quality and process stability, and providing reliable process support for the fabrication of high-precision In-containing compound semiconductor laser materials. Attached Figure Description

[0022] Figure 1This is a process flow diagram for the preparation of indium-containing III-V compound semiconductor materials. Detailed Implementation

[0023] To make the technical solutions of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to better understand the technical solutions of the present invention and should not be construed as limiting the present invention.

[0024] Example 1.

[0025] S1: Under 50 ℃ conditions, the InP semiconductor material was cleaned sequentially with acetone, ethanol and deionized water, with acetone water bath for 10 min, ethanol water bath for 10 min and deionized water water bath for 10 min. Finally, it was dried with high-purity nitrogen and dried in a 50 ℃ drying oven for 30 min to obtain a sample with a dry and clean surface.

[0026] S2: Place the InP semiconductor material in the dry etching equipment chamber and set the etching pulse parameters: substrate etching temperature 25 ℃, internal chamber pressure 3 mTorr, ICP power 300 W, RF bias 100 W, BCl3 flow rate 10 sccm, Cl2 flow rate 5 sccm, H2 flow rate 3 sccm, Ar flow rate 10 sccm; set the cleaning pulse parameters: substrate cleaning temperature 25 ℃, internal chamber pressure 6 mTorr, ICP power 500 W, RF bias 150 W, Ar flow rate 15 sccm, BCl3 flow rate 0.5 sccm, Cl2 flow rate 0.5 sccm;

[0027] S3: Start etching the InP semiconductor material, setting a cycle sequence of alternating etching pulses and cleaning pulses until the etching depth reaches the target etching depth; the specific cycle sequence is as follows: etching pulse 10 s, stop for 2 s to wait for the chamber to stabilize; after the chamber stabilizes, perform physical rinsing pulse 3 s, stop for 2 s to wait for the chamber to stabilize, completing one cycle sequence. The above cycle sequence is repeated 6 times until the etching depth is 180 nm;

[0028] S4: The etched InP semiconductor material is immersed and acid-washed using an H3PO4 / HBr / H2O etching solution to make the etched interface smoother and flatter, thus achieving the etching of the InP semiconductor material. Figure 1 This is a process flow diagram for the preparation of indium-containing III-V compound semiconductor materials.

[0029] Example 2.

[0030] The difference between this embodiment and Embodiment 1 is that the hydrogen flow rate is 1 sccm and the chlorine flow rate is 5 sccm. The remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InP semiconductor material.

[0031] Example 3.

[0032] The difference between this embodiment and Embodiment 1 is that the hydrogen flow rate is 5 sccm and the chlorine flow rate is 20 sccm. The remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of InP semiconductor material.

[0033] Example 4.

[0034] The difference between this embodiment and Embodiment 1 is that the indium-containing III-V compound semiconductor material is InAs, while the remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InAs semiconductor material.

[0035] Example 5.

[0036] The difference between this embodiment and Embodiment 1 is that the indium-containing III-V compound semiconductor material is InGaAs, while the remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InGaAs semiconductor material.

[0037] Example 6.

[0038] The difference between this embodiment and Embodiment 1 is that the indium-containing III-V compound semiconductor material is InAlAs, while the remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InAlAs semiconductor material.

[0039] Example 7.

[0040] The difference between this embodiment and Embodiment 1 is that the indium-containing III-V compound semiconductor material is InGaAsP, while the remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InGaAsP semiconductor material.

[0041] Example 8.

[0042] The difference between this embodiment and Embodiment 1 is that the indium-containing III-V compound semiconductor material is InGaAsSb, while the remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InGaAsSb semiconductor material.

[0043] Example 9.

[0044] The difference between this embodiment and Embodiment 1 is that the etching pulse and cleaning pulse are alternated 12 times, while the remaining preparation steps and conditions are the same as in Embodiment 1, thereby achieving etching of the InP semiconductor material.

[0045] Comparative Example 1.

[0046] The difference between this comparative example and Example 1 is that H2 is not introduced into the pulse etching gas, while the rest of the preparation steps and conditions are the same as in Example 1, and the InP semiconductor material is etched.

[0047] Under the same temperature conditions as in Example 1, the etching rate of Comparative Example 1 was 30 nm / min, with non-volatile InCl3 covering 80% of the sample surface area, significantly inhibiting the reaction. In Example 1, the etching rate reached 180 nm / min after introducing H2, and the non-volatile InCl3 covered less than 7% of the sample surface area. This demonstrates that introducing H2 into the etching system can significantly improve the chemical kinetics of the etching reaction, generate volatile intermediate products, effectively reduce the amount of non-volatile residues on the surface, and effectively promote the etching reaction of indium-containing III-V compound semiconductor materials.

[0048] In summary, this invention etches indium-containing III-V compound semiconductor materials by setting a periodic timing sequence of alternating etching pulses and rinsing pulses. During the etching stage, H2 is introduced to suppress the formation of non-volatile InCl3 products and simultaneously convert InCl3 products into InCl2, effectively suppressing byproduct formation and improving etching efficiency. During the physical rinsing stage, Ar is used to effectively remove non-volatile InCl3 adhering to the surface of the etched material. x The product exposes the semiconductor substrate, promoting chemical etching through a chemical pulse reaction. This method breaks through the unidirectional "reaction-deposition-blocking" process in traditional continuous dry etching, avoiding the mask corrosion and morphology degradation problems common in high-temperature assisted etching. This invention effectively prevents cavity contamination and reduced etching uniformity while retaining the selectivity and stability of dry etching, achieving simultaneous optimization of etching rate and surface quality, and significantly improving the controllability and repeatability of the etching morphology.

[0049] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0050] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dry etching method of an indium-containing group III-V compound semiconductor material, characterized by, The preparation steps include the following: S1: setting etching pulse parameters, setting etching gas as BCl3, Cl2, H2 and Ar, setting the flow rate of H2 as 1 sccm~5 sccm, setting the flow rate of Ar as 1 sccm~10 sccm; setting flushing pulse parameters; S2: starting etching, setting the cycle timing of alternating etching pulse and cleaning pulse until the etching depth reaches the target etching depth; S3: soaking the indium-containing III-V compound semiconductor material in an etching solution for pickling to obtain the etched indium-containing III-V compound semiconductor material.

2. The dry etching method of an indium-containing III-V compound semiconductor material according to claim 1, wherein The indium-containing III-V compound semiconductor material includes InP, InAs, InGaAs, InAlAs, InGaAsP and InGaAsSb.

3. The dry etching method of an indium-containing III-V compound semiconductor material according to claim 1, wherein The indium-containing III-V compound semiconductor material is cleaned before etching, and the cleaning is sequentially performed with acetone, ethanol and deionized water, and dried with high-purity nitrogen.

4. The dry etching method of an indium-containing III-V compound semiconductor material according to Claim 1, wherein The setting of the etching pulse parameters is setting the substrate etching temperature as 10 ℃~30 ℃, setting the cavity internal pressure as 2 mTorr~8 mTorr, setting the ICP power as 100 W~500 W, setting the RF bias as 50 W~100 W, setting the flow rate of BCl3 as 3 sccm~15 sccm, and setting the flow rate of Cl2 as 5 sccm~20 sccm.

5. The dry etching method of an indium-containing III-V compound semiconductor material according to claim 4, wherein The setting of the flushing pulse parameters is setting the substrate cleaning temperature as 10 ℃~30 ℃, setting the cavity internal pressure as 5 mTorr~15 mTorr, setting the ICP power as 300~500 W, setting the RF bias as 100~300 W, setting the flow rate of Ar as 10 sccm~20 sccm, setting the flow rate of BCl3 as 0.5 sccm, and setting the flow rate of Cl2 as 0.5 sccm.

6. The dry etching method of an indium-containing III-V compound semiconductor material according to claim 5, wherein The cycle timing of alternating etching pulse and cleaning pulse is that the etching pulse is 5 s~30 s, stopped for 0.5 s~2 s to wait for the stabilization of the chamber; after the stabilization of the chamber, the physical flushing pulse is performed for 1 s~5 s, stopped for 0.5 s~2 s to wait for the stabilization of the chamber, to complete one cycle timing, and the cycle timing of alternating etching pulse and cleaning pulse is repeated until the etching depth reaches the target etching depth.

7. The dry etching method of an indium-containing III-V compound semiconductor material according to claim 6, wherein The cycle timing of alternating etching pulse and cleaning pulse is repeated for 12 times~30 times.

8. The dry etching method of an indium-containing III-V compound semiconductor material according to Claim 1, wherein The etching solution is a mixed aqueous solution of H3PO4 / HBr.

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