Resource board card and testing machine

Abstract

The invention relates to a resource board card and a test machine, and the resource board card comprises a test pattern memory which is used for storing test pattern information with different functions; the test pattern generator generates pattern data according to the test pattern information of the current target function, sends the pattern data to the time sequence module, calls the test pattern information of the read operation in the test pattern memory, generates pattern data based on the test pattern information of the read operation, and sends the pattern data to the time sequence module; receiving comparison result data obtained by processing a feedback signal for executing the read operation on the to-be-tested device by the time sequence module; the test pattern generator also reads test pattern information of a next target function from the test pattern memory after determining that the to-be-tested device completes an operation corresponding to the current target function according to the comparison result data, and the test pattern information serves as new test pattern information of the current target function to generate pattern data to be sent to the time sequence module; the waiting time can be reduced, and the test efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, in particular to a resource board card and a test machine. BACKGROUND

[0002] Semiconductor automatic testing refers to detecting various parameter indexes of a device under test (DUT) by using an automatic test equipment (ATE) to remove defective products to control the quality of semiconductor devices leaving the factory. A resource board card of a test machine is responsible for generating corresponding test signals according to test pattern information and sending the test signals to the DUT. When writing the test pattern information, the output level, output time, and sampling expected value of the current test period are generally directly written, and the generated pattern data is fixed, that is, only the consistency of the output of the DUT and the expected value at the set time can be compared. The actual output time of the DUT will fluctuate within a large time range, which leads to that the test efficiency is low because the test can only be performed after the maximum value of the time range and other pattern data is generated. SUMMARY

[0003] Therefore, it is necessary to provide a resource board card and a test machine capable of improving test efficiency in view of the above problems.

[0004] The first aspect of the present application provides a resource board card, comprising:

[0005] a test pattern storage unit configured to store test pattern information of different functions;

[0006] a test pattern generator connected to the test pattern storage unit and a timing module, and configured to generate corresponding pattern data according to the test pattern information stored in the test pattern storage unit and send the pattern data to the timing module;

[0007] the timing module connected to a DUT, and configured to generate corresponding timing signals according to the pattern data and send the timing signals to the DUT;

[0008] wherein, after the test pattern generator generates the pattern data according to the test pattern information of the current target function and sends the pattern data to the timing module, the test pattern generator calls the test pattern information of the read operation in the test pattern storage unit, generates the pattern data based on the test pattern information of the read operation, sends the pattern data to the timing module, and receives comparison result data obtained after the timing module processes a feedback signal of the read operation performed on the DUT;

[0009] The test pattern generator also determines, according to the comparison result data, test pattern information of a next target function after the device under test completes the operation corresponding to the current target function, reads the test pattern information from the test pattern memory as test pattern information of a new current target function, and generates pattern data and sends the pattern data to the timing module.

[0010] In one of the embodiments, the test pattern information includes test pattern flow control instructions, test pattern control instructions, and test pattern data; the test pattern generator reads next test pattern information from the test pattern memory according to the test pattern flow control instructions and / or the configuration state of the device under test; and the test pattern generator generates corresponding pattern data according to the test pattern control instructions and the test pattern data, and sends the pattern data to the timing module.

[0011] In one of the embodiments, the test pattern information of the target function further includes state instructions; after the test pattern generator generates corresponding pattern data according to the test pattern control instructions and the test pattern data of the test pattern corresponding to the current target function, and sends the pattern data to the timing module, the test pattern generator cyclically calls test pattern information of a read operation in the test pattern memory based on the state instructions, and generates pattern data and sends the pattern data to the timing module.

[0012] The test pattern generator stops calling test pattern information of a read operation in the test pattern memory after determining that the device under test completes the operation corresponding to the current target function, reads test pattern information of a next target function from the test pattern memory according to test pattern flow control instructions of the current target function, generates pattern data as test pattern information of a new current target function, and sends the pattern data to the timing module.

[0013] In one of the embodiments, after the test pattern generator generates corresponding pattern data according to the test pattern control instructions and the test pattern data of the test pattern corresponding to the current target function, and sends the pattern data to the timing module, the test pattern generator also acquires timing signals output by the timing module, repeatedly generates corresponding pattern data according to the test pattern control instructions and the test pattern data of the test pattern corresponding to the current target function, and sends the pattern data to the timing module until the timing signals output by the timing module meet the requirements of the current target function, and then cyclically calls test pattern information of a read operation in the test pattern memory based on the state instructions, generates pattern data, and sends the pattern data to the timing module.

[0014] In one of the embodiments, the test pattern generator judges whether a preset repeated output stop condition is reached when the acquired timing signal does not meet the requirement of the current target function; if not, the test pattern generator repeatedly generates corresponding pattern data according to the control instruction of the test pattern corresponding to the current target function and the data of the test pattern and sends the pattern data to the timing module until the timing signal output by the timing module meets the requirement of the current target function; if yes, the test pattern generator detects whether the type of the current target function is a preset specific type; the test pattern generator interrupts the test or performs a power-down process when the type of the current target function is the preset specific type, and the test pattern generator reads the test pattern information of the next target function from the test pattern memory as the test pattern information of a new current target function to generate pattern data and sends the pattern data to the timing module when the type of the current target function is not the preset specific type according to the test pattern flow control instruction corresponding to the current target function.

[0015] In one of the embodiments, the test pattern generator judges whether a preset repeated output stop condition is reached when the acquired timing signal does not meet the requirement of the current target function; if not, the test pattern generator repeatedly generates corresponding pattern data according to the control instruction of the test pattern corresponding to the current target function and the data of the test pattern and sends the pattern data to the timing module until the timing signal output by the timing module meets the requirement of the current target function; if yes, the test pattern generator detects whether the type of the current target function is a preset specific type; the test pattern generator interrupts the test or performs a power-down process when the type of the current target function is the preset specific type, and the test pattern generator reads the test pattern information of the next target function from the test pattern memory as the test pattern information of a new current target function to generate pattern data and sends the pattern data to the timing module when the type of the current target function is not the preset specific type according to the test pattern flow control instruction corresponding to the current target function.

[0016] In one of the embodiments, the test pattern flow control instruction comprises a sequential execution instruction and a jump execution instruction, and / or the state instruction comprises a state matching instruction.

[0017] In one of the embodiments, the state matching instruction includes a MATCH enable and a MATCH condition, which are located in the parameter configuration column of the test pattern information in the same row or different rows of the test pattern memory; when the MATCH enable is on and the MATCH condition is satisfied, jump to the test pattern information in the test pattern memory for reading operation in a loop to generate pattern data and send to the timing module.

[0018] In one of the embodiments, the test pattern generator further determines the working state of the device to be tested according to the comparison result data, and interrupts the test or performs power-off processing when it is determined that the device to be tested has a pin abnormality according to the working state.

[0019] In one of the embodiments, the test pattern generator includes a sequence controller, an address generator, a data generator and a signal mapper, the sequence controller is connected to the test pattern memory, the address generator, the data generator and the signal mapper, and the signal mapper is connected to the address generator, the data generator and the timing module.

[0020] The sequence controller issues corresponding signals according to the test pattern information; the address generator is configured to select a raw address for processing according to the signal issued by the sequence controller, and output processed address information to the signal mapper; the data generator is configured to select raw data for processing according to the signal issued by the sequence controller, and output processed data information to the signal mapper; and the signal mapper is configured to select specified physical mapped addresses and data from the processed address information and the processed data information according to the signal issued by the sequence controller, and output the physical mapped addresses and data to the timing module.

[0021] In one of the embodiments, the test pattern generator further includes a data output enable controller and a data comparison controller, the data output enable controller is connected to the sequence controller and the signal mapper, and the data comparison controller is connected to the sequence controller and the signal mapper; the data output enable controller generates output enable data and sends to the signal mapper according to the signal issued by the sequence controller, and the data comparison controller generates comparison enable data and sends to the signal mapper according to the signal issued by the sequence controller; and the signal mapper transmits the physical mapped addresses and data, the output enable data and the comparison enable data to the timing module.

[0022] In one of the embodiments, the address generator includes a raw address generation module, a scrambling module, a burst module and a check module connected in sequence, the raw address generation module is connected to the sequence controller, and the check module is connected to the signal mapper.

[0023] The original address generation module selects specified bits as original addresses according to a signal issued by the sequence controller; the scrambling module scrambles the original addresses to obtain scrambled addresses according to a signal issued by the sequence controller; the burst module replaces the scrambled addresses to obtain replaced addresses according to a signal issued by the sequence controller; and the checking module checks the replaced addresses according to a signal issued by the sequence controller and outputs a checking result and the replaced addresses to the signal mapper.

[0024] The original address source selection module, the scrambling module, the burst module and the checking module all receive output data of a previous module and a signal issued by the sequence controller, and perform corresponding processing on the output data of the previous module based on the signal issued by the sequence controller.

[0025] In one embodiment, the original address generation module selects values from set values and register values according to a selection logic address source instruction issued by the sequence controller, and generates original addresses by performing operations on the selected values based on a selection logic address operation rule sent by the column controller.

[0026] The scrambling module scrambles the original addresses to obtain scrambled addresses according to scrambling enable and scrambling rules issued by the sequence controller.

[0027] The burst module replaces the scrambled addresses to obtain replaced addresses according to burst enable and burst length issued by the sequence controller.

[0028] The checking module checks the replaced addresses according to a selection logic address issued by the sequence controller.

[0029] In one embodiment, the data generator includes an original data generation module, a data operation module, a flip module and a CRC checking module connected in sequence, the original data generation module is connected to the sequence controller, and the CRC checking module is connected to the signal mapper.

[0030] The original data generation module selects specified bits as original data according to a signal issued by the sequence controller; the data operation module performs operation on the original data to obtain operation data according to a signal issued by the sequence controller; the flip module flips logical values at specified positions of the operation data to obtain flipped data according to a signal issued by the sequence controller; and the CRC checking module performs CRC operation on the flipped data and outputs a CRC checking result to the signal mapper according to a signal issued by the sequence controller.

[0031] The original data generation module, the data operation module, the flip module and the CRC check module all receive the output data of the previous module and the signal issued by the sequence controller, and perform corresponding processing on the output data of the previous module based on the signal issued by the sequence controller.

[0032] In one of the embodiments, the timing module comprises a waveform controller and a timing controller, the waveform controller is connected to the signal mapper and the timing controller, and the timing controller is connected to the sequence controller and the device to be tested.

[0033] The waveform controller adjusts the signal waveform of the received address signal and data signal according to the waveform rule, the timing controller outputs the address signal according to the address signal output time, outputs the data signal according to the data signal output time, outputs the output enable according to the output enable output time, obtains the comparison result / sampling result according to the comparison expected value at the comparison time according to the comparison enable, and transmits the comparison result / sampling result to the sequence controller.

[0034] In one of the embodiments, the resource board card further comprises a peripheral control module and a PE chip, the timing module is connected to the device to be tested through the PE chip, and the peripheral control module is connected to the PE chip and the test pattern generator.

[0035] The test pattern generator further issues a comparison threshold to the PE chip through the peripheral control module according to the test pattern information, performs parameter configuration on the PE chip, and the PE chip converts the received timing signal to a level after the parameter configuration and then transmits the timing signal to the device to be tested; the peripheral control module further reads the configuration success signal of the PE chip in real time, and transmits the configuration success signal to the test pattern generator after obtaining the configuration success signal; during the period of reading the configuration success signal of the PE chip in real time, the peripheral control module does not stop transmitting the timing signal corresponding to the test pattern information of the target function to the device to be tested, and does not stop sampling the signal of the device to be tested; and / or

[0036] The peripheral control module is connected to a peripheral device, and the peripheral control module further receives the environment state data of the device to be tested sent by the peripheral device, and the environment state data is used to interrupt the test or perform power-off processing when it is determined that the set condition is not met.

[0037] The second aspect of the application provides a test machine comprising a peripheral device and the resource board card.

[0038] The resource board card and the test machine, the test pattern generator generates corresponding pattern data according to the test pattern information stored in the test pattern memory and sends the pattern data to the timing module, and the timing module generates corresponding timing signals according to the pattern data and sends the timing signals to the device to be tested. After the test pattern generator generates the pattern data according to the test pattern information of the current target function and sends the pattern data to the timing module, the test pattern information of the read operation in the test pattern memory is called, the pattern data is generated based on the test pattern information of the read operation and sent to the timing module, and the comparison result data obtained after the feedback signal of the timing module is processed after the read operation is performed on the device to be tested is received; the test pattern generator also determines the comparison result data after the device to be tested completes the operation corresponding to the current target function, reads the test pattern information of the next target function from the test pattern memory as the test pattern information of the new current target function, generates the pattern data and sends the pattern data to the timing module. By calling the test pattern information of the read operation to detect the configuration state of the device to be tested, after the device to be tested completes the operation corresponding to the current target function, the test pattern information of the next target function is read for testing, which can reduce the waiting time and improve the test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The structure block diagram of the resource board card in one embodiment is shown in the figure.

[0040] Figure 2 The structure schematic diagram of the resource board card in one embodiment is shown in the figure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0043] It can be understood that, in the following embodiments, "connection" between the circuits, modules, units, etc. connected to each other should be understood as "electrical connection", "communication connection" and the like if there is transmission of electrical signals or data between them.

[0044] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "including" or "having" or the like, when used in this specification, specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] In one embodiment, as shown in FIG. 1, a resource board card of a test machine is provided, including a test pattern memory 110, a test pattern generator 120 and a timing module 130. The test pattern memory 110 is configured to store test pattern information of different functions. The test pattern generator 120 is connected to the test pattern memory 110 and the timing module 130, and is configured to generate corresponding pattern data according to the test pattern information stored in the test pattern memory 110, and send the pattern data to the timing module 130. The timing module 130 is connected to a device under test (DUT), and is configured to generate corresponding timing signals according to the pattern data, and send the timing signals to the DUT. The DUT can be a FLASH chip or other types of chips. Figure 1

[0046] In one embodiment, as shown in FIG. 1, a resource board card of a test machine is provided, including a test pattern memory 110, a test pattern generator 120 and a timing module 130. The test pattern memory 110 is configured to store test pattern information of different functions. The test pattern generator 120 is connected to the test pattern memory 110 and the timing module 130, and is configured to generate corresponding pattern data according to the test pattern information stored in the test pattern memory 110, and send the pattern data to the timing module 130. The timing module 130 is connected to a device under test (DUT), and is configured to generate corresponding timing signals according to the pattern data, and send the timing signals to the DUT. The DUT can be a FLASH chip or other types of chips.

[0046] In one embodiment, as shown in FIG. 1, a resource board card of a test machine is provided, including a test pattern memory 110, a test pattern generator 120 and a timing module 130. The test pattern memory 110 is configured to store test pattern information of different functions. The test pattern generator 120 is connected to the test pattern memory 110 and the timing module 130, and is configured to generate corresponding pattern data according to the test pattern information stored in the test pattern memory 110, and send the pattern data to the timing module 130. The timing module 130 is connected to a device under test (DUT), and is configured to generate corresponding timing signals according to the pattern data, and send the timing signals to the DUT. The DUT can be a FLASH chip or other types of chips.

[0046] In one embodiment, as shown in FIG. 1, a resource board card of a test machine is provided, including a test pattern memory 110, a test pattern generator 120 and a timing module 130. The test pattern memory 110 is configured to store test pattern information of different functions. The test pattern generator 120 is connected to the test pattern memory 110 and the timing module 130, and is configured to generate corresponding pattern data according to the test pattern information stored in the test pattern memory 110, and send the pattern data to the timing module 130. The timing module 130 is connected to a device under test (DUT), and is configured to generate corresponding timing signals according to the pattern data, and send the timing signals to the DUT. The DUT can be a FLASH chip or other types of chips.

[0047] Specifically, the test pattern information of power-on operation, reset operation, write operation, read operation and the like is stored in the test pattern memory 110, and the type of the target function is not unique, and can be set according to actual needs, for example, can include power-on operation, reset operation, write operation and the like. The test pattern generator 120 can be based on the state instruction carried in the test pattern information of the target function, or based on other state standard data stored outside the test pattern information. After the test pattern information of the current target function in the test pattern memory 110 is read and the pattern data generated by the test pattern generator 120 is sent to the timing module 130, the original test flow is exited, the test pattern information of the read operation is repeatedly called to generate pattern data and sent to the timing module 130, and the configuration state of the device under test DUT is detected until it is determined that the device under test DUT completes the operation corresponding to the current target function, and then returns to the original test flow to continue reading the test pattern information of the next target function from the test pattern memory 110 to test the device under test DUT. By deciding the time of outputting the next pattern data according to the feedback result of the device under test DUT, compared with the traditional scheme of setting a large waiting time to ensure that the DUT enters the target state and triggers the output of the next pattern data, the application can effectively reduce the waiting time and improve the test efficiency.

[0048] The test pattern generator 120 also determines the working state of the device under test DUT according to the comparison result data, and interrupts the test or performs power-off processing when it is determined that the device under test DUT has a pin abnormality according to the working state. Specifically, the test pattern information of different functions carries parameters for detecting whether the pins of the device under test DUT are normal. After the timing module 130 generates the corresponding timing signal and sends it to the device under test DUT each time, the test pattern generator 120 can detect the working state of the device under test DUT according to the comparison result data returned by the timing module 130. If the device under test DUT has a pin abnormality (such as a power pin state abnormality), the test is directly interrupted or power-off processing is performed.

[0049] In one embodiment, the test pattern information includes test pattern flow control instructions, test pattern control instructions and test pattern data; the test pattern generator 120 reads the next test pattern information from the test pattern memory 110 according to the test pattern flow control instructions and / or the configuration state of the device under test; and the test pattern generator 120 generates corresponding pattern data according to the test pattern control instructions and the test pattern data and sends it to the timing module 130. The test pattern flow control instructions determine the address of the test pattern memory 110 that the test pattern generator 120 reads next time, and can specifically include two types of sequential execution instructions and jump execution instructions. The two types of test pattern flow control instructions are introduced as follows.

[0050] Sequential execution instruction, i.e. execute one by one according to the order of the test pattern storage space. For the implementation of sequential execution, according to the execution condition, it is divided into NOP, STOP, PAUSE / CONTINUE, WAIT.

[0051] NOP, i.e. after executing the pattern of the current address, immediately execute the pattern of the next address.

[0052] STOP, i.e. after executing the pattern of the current address, stop the test.

[0053] PAUSE, i.e. after executing the pattern of the current address, pause the test, and after receiving CONTINUE, continue to execute the pattern of the next address.

[0054] WAIT, i.e. after executing the pattern of the current address, wait until the set condition is met, and then continue to execute the pattern of the next address. The condition here can be waiting time or other signals.

[0055] Jump execution instruction, i.e. the address of the pattern executed this time in the storage space is not continuous with the address of the pattern executed next time in the storage space. For the implementation of jump execution, according to the execution condition, it is divided into JUMPB, JUMPA / BACK, JUMPS, JUMPT.

[0056] JUMPB, i.e. after executing the pattern of the current address, jump to the address before the current address, and the number of repeated jumps can be configured. For example, as shown in Table 1.

[0057] Table 1

[0058]

[0059]

[0060] The test pattern information of each row in the test pattern memory 110 includes test pattern flow control instruction, test pattern control instruction and test pattern data. The "ADDR" column in Table 1 sets the storage address, the "microinstruction" column sets the test pattern flow control instruction, and the "parameter configuration" column sets the related parameters of the instruction, such as the related parameters of the JUMPB instruction, including the jump address and the number of repeated jumps. The execution order of Table 1 is: 0->1->2->3->1->2->3->4.

[0061] JUMPA / BACK, i.e. after executing the pattern at the current address, jump to the address after the current address and not continuous with the current address. Use the BACK flag to return to the address after the last JUMPA. Configure the number of times the jump needs to be repeated. If not configured, it is equivalent to configuring the number of times of jump as 1. Take Table 2 as an example.

[0062] Table 2

[0063] ADDR microinstruction parameter configuration 0 NOP / 1 JUMPA ADDR = 4; JUMPA JTIMES = 1; 2 NOP / 3 STOP 4 NOP / 5 BACK /

[0064] The execution order of Table 2 is: 0->1->4->5->1->4->5->2->3. Among them, the BACK flag must have a corresponding JUMPA instruction.

[0065] JUMPS, i.e. after executing the pattern at the current address, jump to the address set by the corresponding register. Configure the number of times the jump needs to be repeated. Take Table 3 as an example.

[0066] Table 3

[0067]

[0068]

[0069] The execution order of Table 3 is: 0->1->2->3->2->3->2->3->4. The difference between JUMPS and JUMPB instructions is that SET_ADDR and JUMPS JTIMES can be configured by the user, and the priority is higher than the setting value written in the pattern. Also, the value of SET_ADDR and JUMPS JTIMES can be changed in the pattern execution flow.

[0070] JUMPT, i.e. after executing the pattern at the current address, jump to the corresponding address and start the timer. Before the timer is completed, the execution of the pattern does not exceed the address where JUMPT is located. Take Table 4 as an example.

[0071] Table 4

[0072] ADDR microinstruction parameter configuration 0 NOP JUMPT EN = 1; 1 NOP / 2 NOP / 3 JUMPT ADDR = 1 4 NOP / 5 NOP /

[0073] The execution order of Table 4 is: 0->1->2->3->1->2->3->1->2->3->1->2->3->…->1->2->3->4. JUMPT corresponds to the timer, which keeps looping until the timer of JUMPT is reached, and then the original flow order is continued. When ADDR is 1 or 2 reaches the timer, it also needs to execute 3 before executing the subsequent pattern.

[0074] Further, the test pattern information of the target function further comprises a state instruction. After the test pattern generator 120 generates the corresponding pattern data according to the control instruction and the data of the test pattern corresponding to the current target function and sends the pattern data to the timing module 130, the test pattern generator 120 cyclically calls the test pattern information of the read operation in the test pattern memory 110 based on the state instruction and generates the pattern data and sends the pattern data to the timing module 130. After the test pattern generator 120 determines that the DUT to be tested completes the operation corresponding to the current target function, the test pattern generator 120 stops calling the test pattern information of the read operation in the test pattern memory 110, reads the test pattern information of the next target function from the test pattern memory 110 as the test pattern information of the new current target function according to the test pattern flow control instruction corresponding to the current target function, and generates the pattern data and sends the pattern data to the timing module 130.

[0075] Specifically, the state instruction comprises a state matching instruction (MATCH). The state matching instruction can match any condition to be matched. After the parameter configuration column in the test pattern information of the target function enables the MATCH, the test pattern generator 120 will always judge the condition matching state, and when the matching condition is reached, the current pattern (test pattern information) is suspended, the MATCH related pattern (test pattern information of the read operation) is executed, and after the execution of the MATCH related pattern, the pattern before the suspension is continued to be executed. That is, when the MATCH succeeds, the address to be read from the test pattern memory 110 at this time is latched, and the test pattern information of the MATCH execution is jumped to. After the MATCH is completed, the subsequent test pattern information is continued to be executed from the latched address in the test pattern memory 110.

[0076] The state matching instruction specifically includes a MATCH enablement and a MATCH condition, which can be located in the parameter configuration column of the same row or different rows of test pattern information in the test pattern memory 110; when the MATCH enablement is turned on and the MATCH condition is met, the test pattern generator 120 jumps to the test pattern information of the read operation in the test pattern memory and generates pattern data to be sent to the timing module. For example, in the test pattern memory 110, the parameter configuration column of the first row of test pattern information is configured with a MATCH enablement of 1 (1 represents turning on, and 0 represents turning off), and the parameter configuration column of the fourth row of test pattern information is configured with a MATCH condition. Then, the test pattern generator 120 generates corresponding pattern data according to the test pattern information and sends the pattern data to the timing module 130 from the first row to the fourth row (the fourth row is not executed), triggers the MATCH condition at the fourth row, jumps to generate pattern data according to the test pattern information of the read operation and sends the pattern data to the timing module 130, and then jumps back to the fourth row of test pattern information to continue to execute the fourth row of test pattern information and continue the original test process to test. According to the test pattern flow control instruction carried thereby, the address of the next test pattern information to be read is determined, and the original test process is returned to continue testing.

[0077] Of course, those skilled in the art can understand that after the parameter configuration column of the test pattern information of the target function enables the MATCH, the test pattern generator 120 will always judge the condition matching state, and when the matching condition is met, the next test pattern information is stopped from being read, the MATCH related pattern (test pattern information of the read operation) is executed, after the execution of the MATCH related pattern, the MATCH flow is exited, and the next test pattern information is read to continue execution. That is, when the MATCH is successful, the current row of test pattern information is executed, and the address of the next test pattern information to be read is latched, and the test pattern information of the MATCH execution is jumped to. After the MATCH is completed, the test pattern generator starts from the address latched from the test pattern memory 110 to continue to execute the subsequent test pattern information. It can be understood that in other embodiments, the state instruction can not be set in the test pattern information of the target function, but the MATCH enablement, the MATCH condition or other similar state standard data can be issued by the upper computer to the resource board card and stored in the test pattern generator 120 or other positions. The test pattern generator 120 triggers the call of the test pattern information of the read operation in the test pattern memory 110 according to the state standard data issued by the upper computer to detect whether the operation corresponding to the current target function of the device under test DUT is completed.

[0078] In one embodiment, after the test pattern generator 120 sends the corresponding pattern data to the timing module 130 according to the control instruction and the data of the test pattern corresponding to the current target function, the test pattern generator 120 further acquires the timing signal output by the timing module 130, and repeatedly sends the corresponding pattern data to the timing module 130 according to the control instruction and the data of the test pattern corresponding to the current target function until the timing signal output by the timing module 130 meets the requirement of the current target function, and then generates the pattern data based on the state instruction to call the test pattern information of the read operation in the test pattern memory 110 and sends the pattern data to the timing module 130.

[0079] Specifically, since there is a difference between the actual timing signal output to the device under test DUT and the theoretical signal, the feedback adjustment of the timing signal is introduced. After the timing module 130 outputs the corresponding timing signal to the device under test DUT according to the received pattern data, the test pattern generator 120 compares the actual output timing signal with the theoretical signal of the current target function. If the two are consistent or the difference is within the allowable range, it is considered that the timing signal output by the timing module 130 meets the requirement of the current target function; otherwise, it is considered that it does not meet the requirement. When the actual output timing signal does not meet the requirement of the current target function, the control instruction and the data of the test pattern corresponding to the current target function are repeatedly called to generate the corresponding pattern data and send the pattern data to the timing module 130 (which can be repeated all the time or a stop condition for repeated output can be set to stop the repetition). In this embodiment, the MATCH enable and the MATCH condition can also be set in the "parameter configuration" column of the test pattern information of the target function to achieve the repeated output of the timing signal according to the control instruction and the data of the test pattern corresponding to the current target function until the actual output timing signal meets the requirement of the current target function.

[0080] It should be noted that the feedback adjustment of the timing signal can be performed for all target functions or part of the target functions according to the actual situation. After the actual output timing signal corresponding to the current target function meets the requirement, the test pattern generator 120 calls the test pattern information of the read operation in the test pattern memory 110 based on the state instruction to detect whether the device under test DUT completes the operation corresponding to the current target function (which can be repeatedly called or a stop condition for the repeated calling can be set to exit the loop). After it is determined that the device under test DUT completes the operation corresponding to the current target function, the test pattern generator 120 determines the address of the test pattern information of the next target function according to the test pattern flow control instruction corresponding to the current target function to continue the test, thereby reducing the waiting time.

[0081] In one embodiment, the test pattern generator 120 judges whether a preset repeated output stop condition is reached when the acquired timing signal does not meet the requirement of the current target function; if not, the test pattern generator 120 repeatedly generates corresponding pattern data according to the control instruction of the test pattern corresponding to the current target function and the data of the test pattern and sends the pattern data to the timing module 130 until the timing signal output by the timing module 130 meets the requirement of the current target function; if yes, the test pattern generator 120 judges whether the type of the current target function is a preset specific type; the test pattern generator 120 interrupts the test or performs a power-down process when the type of the current target function is the preset specific type, and the test pattern generator 120 reads the test pattern information of the next target function from the test pattern storage 110 as the test pattern information of a new current target function according to the test pattern flow control instruction corresponding to the current target function and generates pattern data and sends the pattern data to the timing module 130 when the type of the current target function is not the preset specific type.

[0082] The repeated output stop condition can be a set time length or a set number of repetitions. For different test pattern information of functions, corresponding types can be set according to whether the test affects other tests. For important functions (for example, a reset function) that affect other tests, a label (for example, marked as 1) can be set as a preset specific type of function. For functions that do not affect each other (for example, function A, which cannot complete the test without affecting the test of the next function B), a label (for example, marked as 0) can be set as a non-pre-set specific type of function.

[0083] Taking the set time length as an example of the repeated output stop condition, the test pattern generator 120 starts timing (timer 1) when the control instruction of the test pattern corresponding to the current target function and the data of the test pattern are called for the first time. During the process of repeatedly generating corresponding pattern data according to the control instruction of the test pattern corresponding to the current target function and the data of the test pattern and sending the pattern data to the timing module 130, the test pattern generator 120 also detects whether the accumulated time length reaches the set time length. When the accumulated time length reaches the set time length, if the timing signal output by the timing module 130 still does not meet the requirement of the current target function, if the current target function is an important function of the preset specific type, the test is directly interrupted or a power-down process is performed, and if the current target function is not an important function of the preset specific type, the test of the current target function can be skipped, the test pattern generator 120 reads the test pattern information of the next target function according to the test pattern flow control instruction corresponding to the current target function, and continues the test as the test pattern information of a new current target function.

[0084] In one embodiment, the test pattern generator 120 determines whether a preset loop calling stop condition is reached when it is determined that the device under test does not complete the operation corresponding to the current target function according to the comparison result data; if not, the test pattern information of the read operation in the test pattern storage 110 is called again, and the pattern data is generated and sent to the timing module 130; if yes, the test is interrupted or power down processing is performed when the type of the current target function is a preset specific type, and the test pattern information of the soft reset operation in the test pattern storage 110 is called when the type of the current target function is not the preset specific type, and the pattern data is generated and sent to the timing module 130, so that the timing module 130 outputs a soft reset timing signal to the device under test DUT, and then the corresponding pattern data is generated and sent to the timing module 130 according to the control instruction of the test pattern corresponding to the current target function and the data of the test pattern; wherein, when the number of times of calling the test pattern information of the soft reset operation reaches a set number of times and the device under test DUT still does not complete the operation corresponding to the current target function, the test pattern information of the next target function is read from the test pattern storage 110, and the pattern data is generated and sent to the timing module 130 as the test pattern information of the new current target function.

[0085] Specifically, the loop calling stop condition can be a preset time length or a preset number of repetitions. Taking the case where the loop calling stop condition adopts the preset time length as an example, when MATCH is successful, the test pattern generator 120 starts timing (timer 2) when it calls the test pattern information of the read operation in the test pattern storage 110 for the first time based on the state instruction, and also detects whether the accumulated time length reaches the preset time length during the process of calling the test pattern information of the read operation in the test pattern storage 110. When the accumulated time length reaches the preset time length and the device under test DUT still does not complete the operation corresponding to the current target function, if the type of the current target function is a preset specific type of important function, the test is directly interrupted or power down processing is performed, and if the current target function is not the preset specific type of important function, the test pattern information of the soft reset operation in the test pattern storage 110 is called, the pattern data is generated and sent to the timing module 130, the timing module 130 outputs a soft reset timing signal to the device under test DUT for soft reset, and then the device under test DUT is tested for the current target function again, i.e., the timing (timer 1) is restarted, and the corresponding pattern data is generated and sent to the timing module 130 according to the control instruction of the test pattern corresponding to the current target function and the data of the test pattern repeatedly within the set time length, and the process is repeated until the device under test DUT completes the operation corresponding to the current target function or the number of times of calling the test pattern information of the soft reset operation reaches the set number of times.

[0086] The number of times can be set once, twice, or even more, depending on actual needs. Taking two times as an example, if the current target function is not a preset important function of a specific type, the test pattern information for the soft reset operation is called twice to perform a soft reset on the device under test (DUT). If the DUT still has not completed the operation corresponding to the current target function, the test of the current target function can be skipped. According to the test pattern flow control instruction corresponding to the current target function, the test pattern generator 120 reads the test pattern information of the next target function and uses it as the new test pattern information for the current target function for testing.

[0087] The specific structure of the test pattern generator 120 is not unique; in one embodiment, such as... Figure 2 As shown, the test pattern generator 120 includes a sequence controller 121, an address generator 122, a data generator 123, and a signal mapper 124. The sequence controller 121 is connected to the test pattern memory 110, the address generator 122, the data generator 123, and the signal mapper 124. The signal mapper 124 is connected to the address generator 122, the data generator 123, and the timing module 130. The sequence controller 121 sends corresponding signals according to the test pattern information. The address generator 122 is used to select the original address for processing according to the signal sent by the sequence controller 121 and output the processed address information to the signal mapper 124. The data generator 123 is used to select the original data for processing according to the signal sent by the sequence controller 121 and output the processed data information to the signal mapper 124. The signal mapper 124 is used to select the specified physically mapped address and data from the processed address information and processed data information according to the signal sent by the sequence controller 121 and output them to the timing module 130. Furthermore, the test pattern generator 120 also includes a data output enable controller 125 and a data comparison controller 126. The data output enable controller 125 is connected to the sequence controller 121 and the signal mapper 124, and the data comparison controller 126 is connected to the sequence controller 121 and the signal mapper 124. The data output enable controller 125 generates output enable data according to the signal sent by the sequence controller and sends it to the signal mapper 124. The data comparison controller 126 generates comparison enable data according to the signal sent by the sequence controller and sends it to the signal mapper 124. The signal mapper 124 transmits the physically mapped address and data, the output enable data, and the comparison enable data to the timing module 130.

[0088] Specifically, the test pattern information includes test pattern flow control instructions and status instructions, test pattern control instructions and test pattern data, and corresponding signals are generated based on the above instructions.

[0089] The sequence controller 121 generates an address jump signal based on the test pattern flow control instruction and the state instruction, determines the address for reading the test pattern memory next time, and generates the control signal and the data signal of the next stage module based on the test pattern control instruction and the test pattern data. The address generator 122 is used to generate the address output to the device under test DUT, including the output time. The data generator 123 is used to generate the data output to the device under test DUT, including the output time. The data output enable controller 125 is used to generate the data output enable to the device under test DUT, including the output time. The data comparison controller 126 is used to generate the expected value of the data comparison and the comparison time. The signal mapper module 124 is used to map the internal address signal and the data signal to the actual address pin and the data pin of the device under test DUT. The test pattern generation and execution flow is as follows:

[0090] After receiving the start generation instruction, the sequence controller 121 obtains the test pattern information of the first test period from the test pattern memory 110. The next reading address of the test pattern memory is generated according to the test pattern flow control instruction. The signals required by the address generator 122, the data generator 123, the data output enable controller 125, the data comparison controller 126, and the signal mapper 124 are generated according to the test pattern control instruction and the test pattern data. There are three rules for the next reading address of the test pattern memory 110: the first rule is to determine the address for reading the test pattern memory 110 based on the test pattern flow control instruction obtained from the test pattern memory 110 last time; the second rule is to determine the address for reading the test pattern memory 110 based on the configuration state of the device under test; and the third rule is to determine the address for reading the test pattern memory 110 based on the test pattern flow control instruction obtained from the test pattern memory 110 last time and the configuration state of the device under test.

[0091] The physical mapping address and data output by the signal mapper 124 are fixed bit length data. The signal mapper 124 controls each bit to select data and address processed by the address generator 122 and the data generator 123, or configuration data (including address and data) issued by the sequence controller 121, to perform physical mapping, and then to form fixed bit physical mapping address and data, according to the received signal. The sequence controller 121 also sets the time interval of the signals issued under different signals according to the time length of the data processed by the address generator 122, the data generator 123, the signal mapper 124, the data output enable controller 125 and the data comparison controller 126, so that the address generator 122, the data generator 123, the signal mapper 124, the data output enable controller 125 and the data comparison controller 126 all receive the output data of the previous module and the signals issued by the sequence controller 121 at the same time, and process the output data of the previous module based on the received signals.

[0092] The address generator 122 includes a raw address generation module, a scrambling module, a burst module and a check module connected in sequence. The raw address generation module is connected to the sequence controller 121, and the check module is connected to the signal mapper 124. The raw address generation module selects a specified bit as a raw address according to the signal issued by the sequence controller 121. The scrambling module scrambles the raw address to obtain a scrambled address according to the signal issued by the sequence controller 121. The burst module replaces the scrambled address to obtain a replaced address according to the signal issued by the sequence controller 121. The check module checks the replaced address according to the signal issued by the sequence controller 121, and outputs the check result and the replaced address to the signal mapper 124. The raw address source selection module, the scrambling module, the burst module and the check module all receive the output data of the previous module and the signal issued by the sequence controller 121 at the same time, and process the output data of the previous module based on the signal issued by the sequence controller 121.

[0093] It can be understood that the functions performed by the above modules in the address generator 122 are different, and therefore the signals issued by the sequence controller 121 to the modules are different, and each module performs the corresponding function according to the signals received by itself. In the embodiment, the original address generation module selects a value from the set value and the register value according to the selection logic address source instruction issued by the sequence controller 121, and performs an operation on the selected value based on the selection logic address operation rule sent by the sequence controller 121, to generate an original address. The logic address source and the logic address operation rule are selectable, which can increase the flexibility of address generation. The scrambling module scrambles the original address according to the scrambling enable and scrambling rule issued by the sequence controller 121 to obtain a scrambled address. By scrambling the logic address, the statistical characteristics of the logic address can be changed, and the noise can be reduced. The burst module replaces the scrambled address according to the burst enable and burst length issued by the sequence controller 121 to obtain a replaced address, which meets the test requirements of the device to be tested such as burst read and burst write. The check module checks (for example, parity check) the replaced address according to the selection logic address issued by the sequence controller 121, which meets the verification requirements of the device to be tested, and the check result and the replaced address are sent to the signal mapper 124.

[0094] Further, the data generator 123 includes an original data generation module, a data operation module, a flip module and a CRC check module connected in sequence, the original data generation module is connected to the sequence controller 121, and the CRC check module is connected to the signal mapper 124; the original data generation module selects a specified bit as original data according to the signal issued by the sequence controller 121; the data operation module performs an operation such as addition, subtraction, multiplication, division, exclusive or and the like on the original data according to the signal issued by the sequence controller to obtain operation data; the flip module flips the logical value of the specified position (specified bit / region / bus) of the operation data according to the signal (specified bit / address region / bus) issued by the sequence controller 121 to obtain flipped data. Among them, the specified bit is used to specify which bit to flip, the specified address region is used to specify which block of address domain to flip, and the specified bus is used to specify that the bus is flipped in its entirety. When the specified address region is flipped, the flip module is also connected to the burst module, and the corresponding address region in the operation data is flipped in combination with the replaced address output by the burst module. The CRC check module selects a CRC check rule (including not performing CRC operation) according to the signal issued by the sequence controller 121, and performs CRC operation on the flipped data to output the CRC check result to the signal mapper 124. The CRC check result includes the check result, and according to the check rule, the flipped data is also included or partially included.

[0095] Similarly, the functions performed by each of the above modules in the data generator 123 are different, so the signals issued by the sequence controller 121 to each module are also different, and each module performs the corresponding function according to the signal received by itself. The original data generation module, the data operation module, the flip module, and the CRC check module all simultaneously receive the output data of the previous module and the signal issued by the sequence controller 121, and perform corresponding processing on the output data of the previous module based on the signal issued by the sequence controller 121.

[0096] Specifically, the original address generation module, the scrambling module, the burst module, the check module, the original data generation module, the data operation module, the flip module, the CRC check module, and the signal mapper 124 are all directly connected to the sequence controller 121 and receive the signal issued by the sequence controller 121. When issuing signals to each module, the sequence controller 121 can also set the time interval for issuing different signals according to the length of time for each module to process data, so that each module simultaneously receives the output data of the previous module and the signal issued by the sequence controller 121, and performs corresponding processing on the output data of the previous module based on the signal issued by the sequence controller 121.

[0097] In addition, when the sequence controller 121 issues signals at time intervals, the above original address generation module, scrambling module, burst module, check module, original data generation module, data operation module, flip module, CRC check module, and signal mapper 124 can not be directly connected to the sequence controller 121, but can be connected in series according to the connection relationship of the modules in the address generator 122 and the data generator 123, and the sequence controller 121 can transfer the signals required by different modules in series and transmit them to each module at corresponding time intervals.

[0098] It can be understood that in other embodiments, when the sequence controller 121 issues signals to each module at the same time, the signal of each module can be transmitted to the corresponding module after being delayed through the corresponding path, or the signal of each module can be transmitted to the corresponding module after being delayed through the internal modules of the address generator 122 / data generator 123 in series, and the signal required by the next stage module is delayed for the time required for the processing of the current stage module, and then sent to the next stage module, so that different modules simultaneously receive the output data of the previous module and the corresponding signal issued by the sequence controller 121.

[0099] In one embodiment, the data output enable controller 125 selects output enable data from preset data according to a signal issued by the sequence controller 121 and sends the output enable data to the signal mapper 124; the data comparison controller 126 selects comparison enable data (including data comparison enable, expected data collected) from preset data according to a signal issued by the sequence controller 121 and sends the comparison enable data to the signal mapper 124; the signal mapper 124 outputs the output enable data, the comparison enable data, and the physical mapped address and data as calculated pattern data to the timing module 130.

[0100] Specifically, the signal mapper 124 selects, according to a signal sent by the sequence controller 121, an address sent by the sequence controller 121 or processed address information generated by the address generator 122 to map to an address pin of the actual device under test DUT, and selects data sent by the sequence controller 121 or processed data information generated by the data generator 123 to map to a data pin of the actual device under test DUT. The physical mapped address and its output time, the physical mapped data and its output time, the output enable and its output time, the comparison enable and its comparison time, and the comparison expected value output by the signal mapper 124 are aligned in time according to a test period.

[0101] The preset data stored by the data output enable controller 125 includes a PIN output enable preset table, each row of the PIN output enable preset table contains output enable data configuring the output state (output or not output) of all PINs, and the data output enable controller 125 selects output enable data of a corresponding row from the PIN output enable preset table according to a signal issued by the sequence controller 121 and sends the output enable data to the signal mapper 124. Further, the preset data stored by the data output enable controller 125 also includes custom PIN output enable data, and the data output enable controller 125 can also replace part of the PINs (one or more PINs) in the selected output enable data of the corresponding row with the custom PIN output enable data according to a signal issued by the sequence controller 121 and then send the output enable data to the signal mapper 124, to achieve custom adjustment of PIN test configuration parameters.

[0102] Furthermore, the preset data stored in the data comparison controller 126 includes a comparison enable preset table. Each row in the comparison enable preset table contains comparison enable data configured for the comparison state of all PINs (no comparison, comparison with a low expected value, comparison with a high expected value, comparison with a high expected value, and storing the sampled value as the comparison result). Based on the signal sent by the sequence controller 121, the data comparison controller 126 selects the corresponding row of comparison enable data from the comparison enable preset table and sends it to the signal mapper 124. Further, the preset data stored in the data comparison controller 126 also includes custom PIN comparison enable data. Based on the signal sent by the sequence controller 121, the data comparison controller 126 also replaces some PINs (one or more PINs) in the selected corresponding row of comparison enable data with custom PIN comparison enable data, and then sends it to the signal mapper 124, thereby realizing the customized adjustment of PIN test configuration parameters.

[0103] In one embodiment, such as Figure 2 As shown, the timing module 130 includes a waveform controller 132 and a timing controller 134. The waveform controller 132 is connected to the signal mapper 124 and the timing controller 134, and the timing controller 134 is connected to the sequence controller 121 and the device under test (DUT). The waveform controller 132 adjusts the waveforms of the received address signal and data signal according to waveform rules. The timing controller 134 outputs the address signal at the address signal output time, outputs the data signal at the data signal output time, outputs the output enable at the output enable output time, and obtains the comparison result / sampling result based on the expected comparison value at the comparison enable time, and transmits the comparison result / sampling result to the sequence controller 121.

[0104] In addition, the resource board also includes a PE chip, and the timing module 130 is connected to the device under test (DUT) via the PE chip. In this embodiment, the timing controller 134 is connected to the DUT via the PE chip. The PE chip performs level conversion based on the signal output by the timing controller 134 and the set comparison thresholds (including high comparison threshold and low comparison threshold), generates address line levels and data line levels, and sends them to the DUT. It performs high and low comparisons on the feedback signal from the DUT and transmits the comparison results to the timing controller 134. The timing controller 134 compares the sampled value of the comparison result with the expected value and transmits the comparison result to the sequence controller 121 for state matching.

[0105] In addition to feeding back the status of the device under test (DUT) to the sequence controller 121, the status of peripheral devices can also be fed back to the sequence controller 121, making the generation of test patterns more flexible and enabling the acquisition of test data from the DUT under various peripheral environments. (Continue to refer to...) Figure 2The resource board further comprises a peripheral control module 140, which is connected to the PE chip and the test pattern generator 120 (specifically connected to the sequence controller 121). The test pattern generator 120 further performs parameter configuration (for example, configuring high and low comparison thresholds) on the PE chip according to the test pattern information, and monitors whether the parameter configuration on the PE chip is successful. Specifically, the test pattern generator 120 obtains the high and low comparison thresholds according to the test pattern information, and outputs them to the peripheral control module 140. The peripheral control module 140 configures the high and low comparison thresholds on the PE chip, thereby realizing parameter configuration on the PE chip. After the PE chip is successfully configured, a configuration success signal is fed back to the sequence controller 121 in the test pattern generator 120 through the peripheral control module 140. The PE chip converts the received timing signal to a level according to the configured parameters, and then transmits it to the device under test DUT.

[0106] Further, the peripheral control module 140 is further connected to a peripheral device, and receives environmental state data of the device under test DUT sent by the peripheral device. The environmental state data is used to interrupt the test or perform power-down processing when it is determined that the set condition is not met.

[0107] The environmental state data can include test environment parameters such as temperature, humidity, current, voltage, etc. The environmental state data sent by the peripheral device can be determined in the peripheral control module 140 or the sequence controller 121 whether the set condition is met, for example, whether the corresponding temperature range, humidity range, current range, voltage range, etc. is met. When the environmental state data of the device under test DUT does not meet the set condition, the test is interrupted or power-down processing is performed.

[0108] In the embodiment, the peripheral control module 140 sends the comparison threshold (high comparison threshold and low comparison threshold) to the PE chip, which is used for PE chip parameter configuration. The PE chip parameter configuration is generally completed before the test pattern information of the target function starts to be generated. The test pattern information of the target function includes parameters for driving the PE chip to output or sampling the level signal of the output of the PE chip. The test pattern information is stored in the test pattern memory 110, which includes PE chip control parameters (such as comparison threshold), which are used to change the voltage output to the device under test DUT or change the comparison threshold of the PE chip during the test. When the test pattern generator reads the test pattern information including the PE chip control parameters, that is, the test pattern information is used to indicate the change, the peripheral control module 140 transmits to the PE chip, and the peripheral control module 140 reads the PE chip configuration success signal in real time. When the configuration success signal is obtained, it is transmitted to the test pattern generator. During the period when the peripheral control module 140 reads the PE chip configuration success signal in real time, the timing signal corresponding to the test pattern information of the target function will not be stopped from being transmitted to the device under test DUT, and the sampling of the signal of the device under test DUT will not be stopped. After the test pattern generator receives the PE chip configuration success signal transmitted by the peripheral control module 140, it starts to read the next test pattern information of the target function to generate the timing signal to the device under test DUT and sample the signal of the device under test DUT. Thus, the problem that the PE chip and the test chip cannot be configured simultaneously in the prior art is solved.

[0109] In one embodiment, a test machine is also provided, which includes a peripheral device and the resource board card described above. In order to better understand the resource board card described above, the following examples are described in combination with a test scene.

[0110] Test scene examples:

[0111] 1. Taking the device under test DUT as a flash chip and the target function as a reset operation as an example, the time range from starting the reset (outputting the test signal from the PE chip to the flash chip for reset) to being able to perform other operations increases with the increase of the storage space of the flash chip (resetting part or all of the storage space). In the traditional test method, when the test of the flash chip contains the reset operation, the test pattern information of the reset operation of the flash chip is sent to the test pattern memory 110. The sequence controller 121 reads the test pattern information of the reset operation to generate pattern data, which is output to the timing module. After the reset timing is generated to the flash chip by the timing module, the sequence controller 121 can only wait for the maximum value of the time range (previously set when writing the test pattern information, which can be determined according to different modes) before generating other test pattern information pattern.

[0112] In the present application, after the state feedback of the device under test DUT is introduced, the test pattern information of the read reset operation is read, the pattern data is generated, the reset timing signal is generated to the device under test DUT through the timing module, and then the test pattern of the repeated read flash chip state is executed, that is, the test pattern information of the read operation is obtained from the test pattern memory, the pattern data is generated, and the read timing signal is sent to the device under test DUT through the timing module. Specifically, when the sequence controller 121 reads the test pattern information of the reset operation, that is, the test pattern information used to reset the flash chip, the sequence controller 121 sends the pattern data of the reset operation to the timing module, and after the timing module generates the reset timing signal, the reset timing signal is finally sent to the flash chip through the PE chip level conversion. Then the sequence controller 121 continues to obtain the test pattern information of the read operation, which is used to read the state of the flash chip, and continuously sends the pattern data of the read flash chip to the timing module. After the timing module generates the read timing signal, the read timing signal is sent to the flash chip through the PE chip level conversion, so as to continuously obtain the current state of the flash chip. When the state of the flash chip is reset, the subsequent test is continued, that is, the sequence controller continues to read the test pattern information in the test pattern memory, and generates the pattern data to the device under test DUT through the timing module and the PE chip related processing. In addition, by recording the time when the reset of the flash chip is detected, it can also be used as a judgment whether the reset function of the flash chip is normal.

[0113] Further, a timeout condition can also be set. After the reset timing signal is generated and sent to the flash chip, if the reset of the flash chip is not detected within the set timeout time, the interrupt test or power-off processing is executed according to the type of the detected target function, or the test pattern information of the next target function is read from the test pattern memory according to the test pattern flow control instruction corresponding to the current target function, and the processing is more flexible.

[0114] 2、In the chip aging test, the environment temperature, humidity and the like of the device under test (DUT) are required. In the traditional test mode, the temperature and humidity of the environment are controlled first, and then the aging test is started manually after the environment reaches the requirements. During the test, the temperature and humidity of the environment are also required. In the present application, the peripheral control module 140 is connected to the PE chip, the signal voltage and current currently delivered to the device under test (DUT) are set, whether the PE parameter configuration is successful is monitored, and the environment state data collected by the peripheral device is obtained. After the introduction of the peripheral feedback, the sequence controller 121 can determine whether to continue the test according to the real-time environment. If the temperature and humidity of the environment change to be not in line with the requirements during the test, the test is interrupted according to the abnormal processing or the test machine is powered off. It should be noted that the aging test has more requirements for the temperature and humidity of the environment, and other tests also have certain requirements. For example, in the test of DDR, flash and other storage chips, the working temperature of the FPGA is monitored in real time, and the test is stopped / power off when the working temperature of the FPGA is too high.

[0115] The resource board card and the test machine have the following advantages:

[0116] 1. For the test pattern that needs to wait for the feedback of the device under test (DUT), the maximum waiting time does not need to be set before the subsequent test is executed, thereby improving the test efficiency.

[0117] 2. When the output time of the output signal of the device under test (DUT) fluctuates greatly, it is not necessary to sample all the time within the fluctuation time range, thereby improving the test efficiency and reducing the human error.

[0118] 3. The configuration state, pin working state and peripheral state of the device under test (DUT) are fed back to the sequence controller 121, more and more detailed test scenarios can be set, and the device under test (DUT) can be tested more comprehensively.

[0119] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0120] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent scope of the present application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A resource board card, characterized by, include: Test pattern memory is used to store test pattern information for different functions; A test pattern generator, connected to the test pattern memory and the timing module, is used to generate corresponding pattern data based on the test pattern information stored in the test pattern memory and send it to the timing module. The timing module is connected to the device under test and is used to generate corresponding timing signals based on the pattern data and send them to the device under test. The test pattern generator generates pattern data based on the test pattern information of the current target function and sends it to the timing module. Then, it calls the test pattern information of the read operation in the test pattern memory, generates pattern data based on the test pattern information of the read operation and sends it to the timing module. It also receives the comparison result data obtained after the timing module processes the feedback signal of the device under test performing the read operation. The test pattern generator further determines, based on the comparison result data, that after the device under test completes the operation corresponding to the current target function, it reads the test pattern information of the next target function from the test pattern memory and generates pattern data as the new test pattern information of the current target function, which is then sent to the timing module.

2. The resource board card of claim 1, wherein, The test pattern information includes test pattern flow control instructions, test pattern control instructions, and test pattern data; the test pattern generator reads the next test pattern information from the test pattern memory according to the test pattern flow control instructions and / or the configuration status of the device under test; The test pattern generator generates corresponding pattern data based on the control instructions and data of the test pattern and sends it to the timing module.

3. The resource board card of claim 2, wherein, The test pattern information for the target function also includes status instructions. After the test pattern generator generates corresponding pattern data and sends it to the timing module based on the control instructions and test pattern data of the test pattern corresponding to the current target function, it cyclically calls the test pattern information of the read operation in the test pattern memory based on the status instructions to generate pattern data and send it to the timing module. After determining that the device under test has completed the operation corresponding to the current target function, the test pattern generator stops calling the test pattern information of the read operation in the test pattern memory. According to the test pattern flow control instruction corresponding to the current target function, it reads the test pattern information of the next target function from the test pattern memory and generates pattern data as the new test pattern information of the current target function, which is then sent to the timing module.

4. The resource board card of claim 3, wherein, The test pattern generator further acquires the timing signal output by the timing module, and repeatedly generates corresponding pattern data according to the control instruction and the data of the test pattern corresponding to the current target function and sends the pattern data to the timing module until the timing signal output by the timing module meets the requirement of the current target function, and then generates pattern data based on the state instruction and the test pattern information of the read operation in the test pattern memory and sends the pattern data to the timing module.

5. The resource board card of claim 4, wherein, The test pattern generator further acquires the timing signal output by the timing module, and repeatedly generates corresponding pattern data according to the control instruction and the data of the test pattern corresponding to the current target function and sends the pattern data to the timing module until the timing signal output by the timing module meets the requirement of the current target function, and then generates pattern data based on the state instruction and the test pattern information of the read operation in the test pattern memory and sends the pattern data to the timing module. The test pattern generator further acquires the timing signal output by the timing module, and repeatedly generates corresponding pattern data according to the control instruction and the data of the test pattern corresponding to the current target function and sends the pattern data to the timing module until the timing signal output by the timing module meets the requirement of the current target function, and then generates pattern data based on the state instruction and the test pattern information of the read operation in the test pattern memory and sends the pattern data to the timing module.

6. The resource board card of claim 4 or 5, wherein, The test pattern generator further acquires the timing signal output by the timing module, and repeatedly generates corresponding pattern data according to the control instruction and the data of the test pattern corresponding to the current target function and sends the pattern data to the timing module until the timing signal output by the timing module meets the requirement of the current target function, and then generates pattern data based on the state instruction and the test pattern information of the read operation in the test pattern memory and sends the pattern data to the timing module.

7. The resource board card of claim 3, wherein, The test pattern flow control instruction comprises a sequential execution instruction and a jump execution instruction, and / or the state instruction comprises a state matching instruction.

8. The resource board card of claim 7, wherein, The state matching instruction includes a MATCH enable and a MATCH condition, which are located in parameter configuration columns in the same row or different rows of test pattern information in the test pattern memory; when the MATCH enable is turned on and the MATCH condition is satisfied, jump to a loop calling read operation of the test pattern information in the test pattern memory to generate pattern data and send the pattern data to the timing module.

9. The resource board card of claim 1, wherein, The test pattern generator further determines the working state of the device to be tested according to the comparison result data, and interrupts the test or performs a power-down process when it is determined that the device to be tested has a pin abnormality according to the working state.

10. The resource board card of claim 1, wherein, The test pattern generator includes a sequence controller, an address generator, a data generator and a signal mapper, the sequence controller is connected to the test pattern memory, the address generator, the data generator and the signal mapper, and the signal mapper is connected to the address generator, the data generator and the timing module. The sequence controller issues corresponding signals according to the test pattern information; the address generator is configured to select original addresses for processing according to the signals issued by the sequence controller, and output processed address information to the signal mapper; the data generator is configured to select original data for processing according to the signals issued by the sequence controller, and output processed data information to the signal mapper; and the signal mapper is configured to select specified physical mapped addresses and data from the processed address information and the processed data information according to the signals issued by the sequence controller, and output the physical mapped addresses and data to the timing module.

11. The resource board card of claim 10, wherein, The test pattern generator further includes a data output enable controller and a data comparison controller, the data output enable controller is connected to the sequence controller and the signal mapper, and the data comparison controller is connected to the sequence controller and the signal mapper; the data output enable controller generates output enable data and sends the output enable data to the signal mapper according to the signals issued by the sequence controller, and the data comparison controller generates comparison enable data and sends the comparison enable data to the signal mapper according to the signals issued by the sequence controller; and the signal mapper transmits the physical mapped addresses and data, the output enable data and the comparison enable data to the timing module.

12. The resource board card of claim 10, wherein, The address generator includes a original address generation module, a scrambling module, a burst module and a check module connected in sequence, the original address generation module is connected to the sequence controller, and the check module is connected to the signal mapper; The original address generation module selects specified bits as original addresses according to the signals issued by the sequence controller; the scrambling module scrambles the original addresses to obtain scrambled addresses according to the signals issued by the sequence controller; and the burst module replaces the scrambled addresses to obtain replaced addresses according to the signals issued by the sequence controller; The check module checks the replaced addresses according to the signals issued by the sequence controller, and outputs the check result and the replaced addresses to the signal mapper; and The signal mapper selects specified physical mapped addresses and data from the check result and the replaced addresses according to the signals issued by the sequence controller, and outputs the physical mapped addresses and data to the timing module. The original address source selection module, the scrambling module, the burst module and the check module all receive the output data of the previous module and the signal issued by the sequence controller, and perform corresponding processing on the output data of the previous module based on the signal issued by the sequence controller.

13. The resource board card of claim 12, wherein, The original address generation module selects a value from the set value and the register value according to the selection logic address source instruction issued by the sequence controller, and performs operation on the selected value based on the selection logic address operation rule sent by the column controller to generate the original address. The scrambling module scrambles the original address according to the scrambling enable and the scrambling rule issued by the sequence controller to obtain the scrambled address. The burst module replaces the scrambled address according to the burst enable and the burst length issued by the sequence controller to obtain the replaced address. The check module checks the replaced address according to the selection logic address issued by the sequence controller.

14. The resource board card of claim 10, wherein, The data generator comprises an original data generation module, a data operation module, a flip module and a CRC check module connected in sequence, the original data generation module is connected to the sequence controller, and the CRC check module is connected to the signal mapper. The original data generation module selects a specified bit as original data according to the signal issued by the sequence controller; the data operation module performs operation on the original data according to the signal issued by the sequence controller to obtain the operated data; and the flip module flips the logical value at a specified position of the operated data according to the signal issued by the sequence controller to obtain the flipped data. The CRC check module performs CRC operation on the flipped data according to the signal issued by the sequence controller, and outputs the CRC check result to the signal mapper. The original data generation module, the data operation module, the flip module and the CRC check module all receive the output data of the previous module and the signal issued by the sequence controller, and perform corresponding processing on the output data of the previous module based on the signal issued by the sequence controller.

15. The resource board card of claim 10, wherein, The timing module comprises a waveform controller and a timing controller, the waveform controller is connected to the signal mapper and the timing controller, and the timing controller is connected to the sequence controller and the device to be tested. The waveform controller adjusts the signal waveform according to the received address signal and data signal according to the waveform rule, the timing controller outputs the address signal according to the address signal output time, outputs the data according to the data signal output time, outputs the output enable according to the output enable output time, obtains the comparison result / sampling result according to the comparison expected value according to the comparison enable at the comparison time, and transmits the comparison result / sampling result to the sequence controller.

16. The resource board card of claim 1, wherein, Further comprising a peripheral control module and a PE chip, the timing module is connected to the device to be tested through the PE chip, and the peripheral control module is connected to the PE chip and the test pattern generator. The timing module is connected to the device to be tested through the PE chip, and the peripheral control module is connected to the PE chip and the test pattern generator. The test pattern generator also sends a comparison threshold to the PE chip through the peripheral control module according to the test pattern information, configures the PE chip, and the PE chip sends the timing signal received after level conversion to the device to be tested; the peripheral control module also reads the configuration success signal of the PE chip in real time, and transmits the configuration success signal to the test pattern generator after obtaining the configuration success signal; during reading the configuration success signal of the PE chip in real time, the peripheral control module does not stop outputting the timing signal corresponding to the test pattern information of the target function to the device to be tested, and does not stop sampling the signal of the device to be tested; And / or The peripheral control module is connected with a peripheral device, and the peripheral control module also receives the environmental state data of the device to be tested sent by the peripheral device, and the environmental state data is used to interrupt the test or do power-off processing when it is judged that the set condition is not met.

17. A testing machine characterized by, The resource board card comprises a peripheral device and the resource board card according to any one of claims 1 to 16.

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