Heterogeneous chip quick starting system and method

Abstract

The invention discloses a heterogeneous chip quick starting system and method, the system comprises a heterogeneous chip and a flash memory module, the heterogeneous chip is connected with the flash memory module, the heterogeneous chip comprises a first processor core module, a second processor core module and an on-chip bus, and the first processor core module and the second processor core module are respectively connected with the on-chip bus; when the heterogeneous chip is powered on and reset, the first processor core module and the second processor core module are powered on at the same time; the first processor core module accesses the flash memory module through the on-chip bus to obtain the first bootstrap program and load the modules in the module; and the second processor core module accesses the flash memory module through the on-chip bus so as to obtain the second bootstrap program and load the modules in the module to finish quick start. By initializing the plurality of processor core modules in parallel, the starting time of the whole system is greatly shortened, and the quick starting of the complex heterogeneous processor is realized.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a fast startup system and method for heterogeneous chips. Background Technology

[0002] General-purpose heterogeneous processors are widely used in various fields, such as personal computers, autonomous vehicles, and robotics. Different fields have different requirements for startup time. Some fields, such as personal computers, do not have particularly high requirements for startup time, and a startup time of ten to tens of seconds is acceptable. Other fields, such as autonomous vehicles and smart cockpits, have very high requirements for startup and response time, requiring less than 10 seconds, and even less than 3 seconds in some special scenarios.

[0003] The current mainstream heterogeneous processors basically use a separate boot core to power on and initialize the entire chip, and initialize them in sequence according to the boot dependencies of different modules of the chip.

[0004] Such a solution has a relatively fixed and simple startup sequence, but the startup time is relatively long. For some special products or scenarios that require fast startup, it is necessary to increase the frequency to achieve fast startup. However, the cost of increasing the frequency is increased design complexity, increased power consumption, and potential consumption of more area. Moreover, there are bottlenecks and upper limits to frequency increases, which can generally only achieve an improvement of about 10%. Summary of the Invention

[0005] This invention provides a heterogeneous chip fast startup system and method to achieve fast startup of heterogeneous chips.

[0006] According to a first aspect of the present invention, a heterogeneous chip fast boot system is provided, the system comprising a heterogeneous chip and a flash memory module, the heterogeneous chip being connected to the flash memory module, the heterogeneous chip comprising a first processor core module, a second processor core module and an on-chip bus, the first processor core module and the second processor core module being respectively connected to the on-chip bus;

[0007] When the heterogeneous chip is powered on and reset, the first processor core module and the second processor core module are powered on simultaneously.

[0008] The first processor core module accesses the flash memory module through the on-chip bus to obtain the first boot program and load the modules within the module;

[0009] The second processor core module accesses the flash memory module via the on-chip bus to obtain the second bootloader and load the modules within the module to complete the fast boot.

[0010] According to a second aspect of the present invention, a method for rapid startup of heterogeneous chips is provided, applied to a rapid startup system for heterogeneous chips as provided in any one of the embodiments of the present invention. The system includes a heterogeneous chip and a flash memory module, the heterogeneous chip being connected to the flash memory module. The heterogeneous chip includes a first processor core module, a second processor core module, and an on-chip bus, the first processor core module and the second processor core module being respectively connected to the on-chip bus. The method includes:

[0011] When the heterogeneous chip is powered on and reset, the first processor core module and the second processor core module are powered on simultaneously.

[0012] The first processor core module accesses the flash memory module via the on-chip bus to obtain the first boot program and load the modules within the module.

[0013] The second processor core module accesses the flash memory module via the on-chip bus to obtain the second bootloader and load the modules within the module, thus completing a fast boot.

[0014] The technical solution of this invention includes a system comprising a heterogeneous chip and a flash memory module. The heterogeneous chip is connected to the flash memory module. The heterogeneous chip includes a first processor core module, a second processor core module, and an on-chip bus. The first and second processor core modules are respectively connected to the on-chip bus. When the heterogeneous chip is powered on and reset, the first and second processor core modules are powered on simultaneously. The first processor core module accesses the flash memory module through the on-chip bus to obtain a first boot program and load the modules within its module. The second processor core module accesses the flash memory module through the on-chip bus to obtain a second boot program and load the modules within its module, thus completing a fast boot. By initializing multiple processor core modules in parallel, the boot time of the entire system is greatly shortened, enabling fast booting of complex heterogeneous processors.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1This is a schematic diagram of a heterogeneous chip fast startup system provided in Embodiment 1 of the present invention;

[0018] Figure 2 This is a schematic diagram of an example structure of a heterogeneous chip fast startup system provided in Embodiment 1 of the present invention;

[0019] Figure 3 This is a flowchart of a fast startup method for heterogeneous chips according to Embodiment 2 of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Example 1

[0023] Figure 1 This is a schematic diagram of a heterogeneous chip fast startup system provided in Embodiment 1 of the present invention. This embodiment is applicable to the fast startup of heterogeneous chips, such as... Figure 1 As shown, the system includes a heterogeneous chip 1 and a flash memory module 2. The heterogeneous chip 1 is connected to the flash memory module 2. The heterogeneous chip 1 includes a first processor core module 11, a second processor core module 12, and an on-chip bus 13. The first processor core module 11 and the second processor core module 12 are respectively connected to the on-chip bus 13.

[0024] When the heterogeneous chip 1 is powered on and reset, the first processor core module 11 and the second processor core module 12 are powered on simultaneously. The first processor core module 11 accesses the flash memory module 2 through the on-chip bus 13 to obtain the first boot program and load the modules within the module. The second processor core module 12 accesses the flash memory module 2 through the on-chip bus 13 to obtain the second boot program and load the modules within the module, thus completing the fast boot.

[0025] In this embodiment, heterogeneous chip 1 can be understood as a chip integrating two or more processor cores with different architectures and functions. These cores have different functions; for example, one is responsible for complex calculations, and the other is responsible for simple control, thus balancing performance and efficiency. The first processor core module 11 and the second processor core module 12 can be understood as two core processing units in heterogeneous chip 1. "Module" means that in addition to the core processor, it also includes its supporting auxiliary circuits (such as cache, interface circuits, etc.). The two have different architectures or functions, which is a concrete manifestation of "heterogeneity". The on-chip bus 13 can be understood as the "data highway" inside the chip, used to connect various modules within the chip (such as the two processor core modules, on-chip cache, etc.), allowing them to quickly transmit data and instructions. The flash memory module 2 can be understood as a storage device that can store data for a long time without losing data after power failure. In this text, it is used to store the boot program required for processor startup. The first boot program and the second boot program can be understood as the programs that run first after power-on. Their function is to initialize the hardware, detect the device status, and load subsequent more complex operating systems or applications. The first and second bootloaders are dedicated bootloaders corresponding to the two processor core modules, respectively.

[0026] Specifically, when the heterogeneous chip 1 is powered on and reset (restored to its initial state), the first processor core module 11 and the second processor core module 12 do not have a sequential order, but rather start up simultaneously, which is the basis for fast startup. The two processor core modules access the same flash memory module 2 through the internal channel 13 of the on-chip bus. The first processor core module 11 retrieves the first boot program from the flash memory, and the second processor core module 12 retrieves the second boot program. After obtaining their respective boot programs, the two modules simultaneously load the necessary modules (such as initializing their own cache and interfaces) within their respective modules, ultimately completing the startup process together. This avoids the waiting time experienced with single-core startup, achieving fast startup. Traditional methods require one processor core to power on, read the boot program, and then load the modules, a process that must be completed sequentially. In this application, both processor cores power on simultaneously, read the program simultaneously, and load the modules simultaneously, significantly reducing startup time, making it particularly suitable for devices with high startup speed requirements.

[0027] The technical solution of this invention includes a system comprising a heterogeneous chip and a flash memory module. The heterogeneous chip is connected to the flash memory module. The heterogeneous chip includes a first processor core module, a second processor core module, and an on-chip bus. The first and second processor core modules are respectively connected to the on-chip bus. When the heterogeneous chip is powered on and reset, the first and second processor core modules are powered on simultaneously. The first processor core module accesses the flash memory module through the on-chip bus to obtain a first boot program and load the modules within its module. The second processor core module accesses the flash memory module through the on-chip bus to obtain a second boot program and load the modules within its module, thus completing a fast boot. By initializing multiple processor core modules in parallel, the boot time of the entire system is greatly shortened, achieving fast boot of complex heterogeneous processors.

[0028] Furthermore, the first processor core module 11 includes a first processor core, a first memory, and at least one first other module.

[0029] After power-on, the first processor core reads the initialization code from the first memory and initializes it, and sends a first access request to the flash memory module 2 to the on-chip bus 13 to obtain the first boot program; the first processor core loads the first boot program and initializes each of the first other modules.

[0030] In this embodiment, the first processor core is the core computing unit of the first processor core module 11. It is the hardware core that actually executes instructions and processes data (similar to the CPU core of a computer), and is responsible for controlling the operating logic of the entire module. For example, it can be a boot core. The first memory is the local storage inside the first processor core module 11, usually a very fast memory (such as ROM), used to store the initialization code that the processor core needs first after power-on (similar to the basic boot code in the BIOS chip when a computer is turned on). The first other modules refer to the supporting functional modules in the first processor core module 11 other than the core and memory. The first access request can be understood as a signal used to request to read data from the flash memory module 2.

[0031] Specifically, after the first processor core module 11 is powered on, the first processor core first reads the pre-stored initialization code from the first memory (local fast storage) and executes this code to complete the most basic initialization of the processor core itself (such as setting registers, starting the clock, initializing the internal cache, etc.), enabling the processor core to have basic operating capabilities. After completing its basic initialization, the first processor core sends a first access request to the external flash memory module 2 through the on-chip bus 13 to obtain the first boot program dedicated to the first processor core (which is more complex than the initialization code in the first step and contains key logic for starting the subsequent system or application). After obtaining the first boot program from the flash memory module 2, the first processor core runs the program and initializes the various first other modules within the module through the instructions in the program.

[0032] Through the above steps, the boot process of the first processor core module 11 first completes the basic boot of the core itself through local memory, then obtains the external boot program through the on-chip bus 13, and finally uses the boot program to initialize other auxiliary modules within the module, ultimately bringing the entire module into a usable state. This process is carried out in parallel with the boot of the second processor core module 12, jointly achieving the rapid boot of the heterogeneous chip 1.

[0033] The first other modules include a clock reset control module, a storage module, and a first other internal sub-module. Correspondingly, the first boot program is loaded through the first processor core to initialize each of the first other modules, including:

[0034] The first processor core loads the first boot program to reset the clock reset control module; after the clock reset control module is reset, the first processor core initializes the storage device; the first processor core loads the boot program in the storage device to initialize each of the first other internal sub-modules.

[0035] In this embodiment, the clock reset control module can be understood as a module responsible for managing the clock signal and reset signal of the first processor core module 11. The clock signal is the time base for the operation of the processor and other modules, while the reset signal is used to restore the module to its initial state. The storage module refers to the other storage components within the first processor core module 11 besides the "first memory 112," used for temporarily storing data and boot programs to support more complex operational needs of the module. The first other internal sub-modules can be understood as more subdivided functional sub-components within the first processor core module 11.

[0036] Specifically, after the first processor core loads the first bootloader, it first performs a reset operation on the clock reset control module through program instructions to ensure that the clock reset control module itself is in its initial state, laying the foundation for generating a stable clock signal and controlling the reset of other modules. Since clock and reset are prerequisites for the operation of all hardware modules, they must be processed first. Once the clock reset control module has completed its reset and begins providing a stable clock signal, the first processor core then initializes the memory module. The memory module requires a stable clock signal to operate, so this must be done only after the clock reset control module is working properly to avoid initialization failure due to clock instability. After the memory module initialization is complete, the first processor core loads a more detailed bootloader from the memory module and then initializes the various other internal sub-modules according to these programs.

[0037] This phased initialization ensures that hardware modules start up in sequence and work together, avoiding startup failures caused by chaotic dependencies.

[0038] Furthermore, the second processor core module 12 includes a second processor core, a second memory, and at least one second other internal sub-module, including:

[0039] After power-on, the second processor core reads the initialization code from the second memory and initializes it, and sends a second access request to the flash memory module 2 to the on-chip bus 13 to obtain the second boot program; the second processor core loads the second boot program and initializes each of the second other internal sub-modules.

[0040] In this embodiment, the second processor core is the core computing unit of the second processor core module 12. It is the hardware core that actually executes instructions and processes data in this module, and is responsible for controlling the operating logic of the entire second module. It may have an architectural difference from the processor core in the first processor core module 11; for example, the second processor core may be a system core. The second memory is the local storage inside the second processor core module 12, usually a very fast memory (such as ROM), used to store the initialization code that the processor core needs first after power-on. The second other internal sub-modules refer to the supporting functional modules in the second processor core module 12 other than the core and memory. The second access request can be understood as a request signal sent by the second processor core to the on-chip bus 13 to access the flash memory module 2. Its purpose is to obtain the second boot program dedicated to the second processor core module 12, and it is an independent request that runs in parallel with the first access request of the first processor core.

[0041] Specifically, after the second processor core module 12 is powered on, the second processor core first reads the pre-stored initialization code from its own dedicated second memory and executes this code to complete the most basic hardware initialization of the second processor core, enabling it to have basic instruction execution capabilities. This step is performed simultaneously with the local initialization of the first processor core module 11 (because the two modules start in parallel after power-on), and is a key step in rapid startup. After completing its basic initialization, the second processor core sends a second access request to the external flash memory module 2 via the on-chip bus 13 to request to read its dedicated second boot program. After obtaining the second boot program from the flash memory module 2, the second processor core runs the program and initializes the various other internal sub-modules within the module according to the program instructions.

[0042] Through the above steps, this design demonstrates the advantages of heterogeneous chips with division of labor and parallel operation. The two modules can undertake different tasks according to their own characteristics, which not only improves the startup speed but also optimizes the overall functional adaptability of the chip.

[0043] Specifically, the on-chip bus 13 is used to arbitrate the first access request and the second access request to determine the access order.

[0044] Understandably, at this time, there may be a first access request from the first processor core and a second access request from the second processor core on the on-chip bus 13 at the same time. The chip usually coordinates the access order through the bus arbitration mechanism (such as priority allocation) of the on-chip bus 13 to ensure that both requests can efficiently obtain the required program and avoid conflicts.

[0045] The second other internal sub-module includes a memory module and other second internal sub-modules. Correspondingly, the step of loading the second boot program through the second processor core and initializing each of the second other internal sub-modules includes:

[0046] The second bootloader is loaded through the second processor core to initialize the memory module; after the memory module is initialized, each of the other second internal sub-modules is initialized.

[0047] In this embodiment, the memory module is the core storage component (typically referring to Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM)) within the second processor core module 12. It is used to temporarily store program instructions and data and serves as the working memory for the processor core during operation. Its capacity and speed directly affect the processor's operating efficiency and must be initialized first for normal use. The term "secondary other internal sub-modules" is a collective term for the more subdivided functional modules within the second processor core module 12.

[0048] Specifically, after the second processor core loads the second bootloader, it first executes the initialization instructions for the memory module. The memory module stores data and programs during processor core runtime. Subsequent initialization programs and configuration parameters for other sub-modules may also need to be stored in memory, and the operation of sub-modules depends on the data exchange space provided by memory. Therefore, memory must be initialized first to ensure normal read and write capabilities and avoid initialization failures or functional abnormalities due to memory unavailability. Once the memory module has completed initialization and is working normally, the second processor core then initializes other internal sub-modules.

[0049] Furthermore, the processor core performs parallel initialization on other internal sub-modules that have no dependencies, and performs sequential initialization on other internal sub-modules that have dependencies according to the dependencies.

[0050] In this embodiment, other internal submodules without dependencies refer to submodules that are independent of each other in terms of functionality and operating conditions. Other internal submodules with dependencies refer to submodules that have an associated startup order, such as a dependency between submodules where A must be started before B can be started.

[0051] Specifically, the processor core can first identify the dependencies between other internal submodules, perform parallel initialization of other internal submodules without dependencies, and perform sequential initialization of other internal submodules with dependencies.

[0052] Through the above steps, the optimization strategy for initializing other internal sub-modules is to distinguish dependencies and combine parallel and sequential methods. For sub-modules without dependencies, parallel processing is used to shorten the time and maximize the processing power of the processor core. For sub-modules with dependencies, sequential processing is used to ensure reliability and strictly follow the constraints of hardware design. Through this hybrid strategy, the processor core can avoid unnecessary waiting (improving startup speed) and ensure that all sub-modules can work normally (ensuring startup quality). This is the key optimization method for heterogeneous chip 1 to achieve fast and stable startup.

[0053] Optionally, the system further includes an external device, which is connected to the heterogeneous chip 1 via the on-chip bus 13.

[0054] In this embodiment, external devices refer to hardware devices connected to the outside of the heterogeneous chip 1. They are not modules inside the chip, but external components that interact with the chip through an interface. The on-chip bus 13 usually extends to the outside through the chip's external interfaces (such as GPIO, SPI, and USB) so that external devices can interact with the modules inside the chip through the bus.

[0055] This also includes initializing the external device through the first processor core or the second processor core.

[0056] Specifically, external devices connect to the system through the chip's external interface and ultimately establish a communication link with modules inside the heterogeneous chip 1 (such as the first / second processor core module 12) via the on-chip bus 13. Depending on the functionality of the external device and its compatibility with the processor core or a pre-defined division of labor, either the first or second processor core is selected to initialize the external device.

[0057] Initialization is completed by a processor core adapted to external device functions, which not only takes advantage of the performance of heterogeneous chip 1, but also ensures the collaborative work between external devices and the chip.

[0058] By way of example, the invention can be illustrated by a specific example. Figure 2 This is a schematic diagram of an example structure of a heterogeneous chip 1 fast startup system provided in Embodiment 1 of the present invention, as shown below. Figure 2As shown, the system includes a heterogeneous chip 1, a flash memory module 2, and a Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) 3. The heterogeneous chip 1 includes a first processor core module 11, a second processor core module 12, and an on-chip bus 13. The first processor core module 11 includes a first processor core (boot core) 111, a first memory 112, a clock reset control module 113, a storage device 114, and other internal sub-modules. The second processor core module 12 includes a second processor core (system core) 121, a second memory 122, a display module 123, an interface module 124, and a memory module 125. When the heterogeneous chip 1 is powered on and reset, the first processor core module 11 and the second processor core module 12 are powered on simultaneously. After power-on, the first processor core 111 reads the initialization code from the first memory 112 and initializes itself, and sends a first access request to the flash memory module 2 to the on-chip bus 13 to obtain a first boot program. The first processor core 111 loads the first boot program and resets the clock reset control module 113. After the clock reset control module 113 is reset, the first processor core 111 initializes the storage device 114. The first processor core loads the boot program in the storage device 114 and initializes each of the first other internal sub-modules. After power-on, the second processor core 121 reads the initialization code from the second memory 122 and initializes itself, and sends a second access request to the flash memory module 2 to the on-chip bus 13 to obtain a second boot program. The second processor core 121 loads the second boot program and initializes the memory module 125. After the memory module 125 is initialized, the display module 123 and the interface module 124 are initialized in parallel.

[0059] The heterogeneous chip fast startup system provided in this embodiment of the invention can execute the heterogeneous chip fast startup method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0060] Example 2

[0061] Figure 3 This is a flowchart of a heterogeneous chip fast boot method provided in Embodiment 2 of the present invention. This embodiment is applicable to the fast boot of heterogeneous chips. The method is applied to a heterogeneous chip fast boot system, which includes a heterogeneous chip and a flash memory module. The heterogeneous chip is connected to the flash memory module. The heterogeneous chip includes a first processor core module, a second processor core module, and an on-chip bus. The first processor core module and the second processor core module are respectively connected to the on-chip bus. The method includes:

[0062] S301. When the heterogeneous chip is powered on and reset, the first processor core module and the second processor core module are powered on simultaneously.

[0063] S302. The first processor core module accesses the flash memory module via the on-chip bus to obtain the first boot program and load the modules within the module.

[0064] S303: The second processor core module accesses the flash memory module via the on-chip bus to obtain the second boot program and load the modules within the module, thus completing the fast boot process.

[0065] The technical solution of this invention is applied to a heterogeneous chip fast boot system. The system includes a heterogeneous chip and a flash memory module. The heterogeneous chip is connected to the flash memory module. The heterogeneous chip includes a first processor core module, a second processor core module, and an on-chip bus. The first and second processor core modules are respectively connected to the on-chip bus. When the heterogeneous chip is powered on and reset, the first and second processor core modules are powered on simultaneously. The first processor core module accesses the flash memory module through the on-chip bus to obtain a first boot program and load the modules within the module. The second processor core module accesses the flash memory module through the on-chip bus to obtain a second boot program and load the modules within the module, completing the fast boot. By initializing multiple processor core modules in parallel, the boot time of the entire system is greatly shortened, achieving fast boot of complex heterogeneous processors.

Claims

1. A heterogeneous chip fast boot system, characterized in that, The system comprises a heterogeneous chip and a flash memory module, the heterogeneous chip is connected with the flash memory module, the heterogeneous chip comprises a first processor core module, a second processor core module and an on-chip bus, the first processor core module and the second processor core module are connected with the on-chip bus respectively; When the heterogeneous chip is powered on and reset, the first processor core module and the second processor core module are powered on at the same time; The first processor core module accesses the flash memory module through the on-chip bus to obtain a first boot program and load intra-module modules; The second processor core module accesses the flash memory module through the on-chip bus to obtain a second boot program and load intra-module modules, and complete fast startup.

2. The system of claim 1, wherein, The first processor core module comprises a first processor core, a first memory and at least one first other module; The first processor core reads initialization code from the first memory and performs initialization after power-on, and sends a first access request for the flash memory module to the on-chip bus to obtain a first boot program; The first processor core loads the first boot program to initialize each of the first other modules.

3. The system of claim 2, wherein, The first other module comprises a clock reset control module, a storage module and a first other internal sub-module, and correspondingly, the first boot program is loaded by the first processor core to initialize each of the first other modules, including: The first boot program is loaded by the first processor core to reset the clock reset control module; After the clock reset control module is reset, the first processor core initializes the storage device; The first boot program in the storage device is loaded by the first processor core to initialize each of the first other internal sub-modules.

4. The system of claim 1, wherein, The second processor core module comprises a second processor core, a second memory and at least one second other internal sub-module, including: The second processor core reads initialization code from the second memory and performs initialization after power-on, and sends a second access request for the flash memory module to the on-chip bus to obtain a second boot program; The second processor core loads the second boot program to initialize each of the second other internal sub-modules.

5. The system of claim 4, wherein, The second other internal sub-module comprises a memory module and a second other internal sub-module, and correspondingly, the second boot program is loaded by the second processor core to initialize each of the second other internal sub-modules, including: The second boot program is loaded by the second processor core to initialize the memory module; After the memory module is initialized, each of the second other internal sub-modules is initialized.

6. The system of any one of claims 3 or 5, wherein, The other internal sub-modules without dependency are initialized in parallel by the processor core, and the other internal sub-modules with dependency are sequentially initialized according to the dependency.

7. The system of any of claims 2-3, wherein, The on-chip bus is specifically used for arbitrating the first access request and the second access request to determine the access sequence.

8. The system of claim 1, wherein, The system further comprises an external device connected with the heterogeneous chip through the bus-in-chip.

9. The system of claim 8, wherein, Further comprising: initializing the external device through the first processor core or the second processor core.

10. A heterogeneous chip fast boot method, characterized in that, Applied to the heterogeneous chip fast start system provided in any one of claims 1-9, the system comprises a heterogeneous chip and a flash memory module, the heterogeneous chip is connected with the flash memory module, the heterogeneous chip comprises a first processor core module, a second processor core module and a bus-in-chip, the first processor core module and the second processor core module are connected with the bus-in-chip respectively, and the method comprises: When the heterogeneous chip is powered on and reset, the first processor core module and the second processor core module are powered on at the same time; The first processor core module accesses the flash memory module through the bus-in-chip to obtain a first boot program and load the modules within the module; The second processor core module accesses the flash memory module through the bus-in-chip to obtain a second boot program and load the modules within the module, and completes the fast start.

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