Interrupt system, method, apparatus, and medium

Abstract

This application discloses an interrupt system, method, device, and medium. The system includes a processor; an interrupt controller, with a first interrupt line and a data exchange interface between the interrupt controller and the processor, and a second interrupt line between the interrupt controller and peripherals; and an interrupt vector unit for storing the entry address of an interrupt service routine, connected to the interrupt controller. The first interrupt line and data exchange interface are provided between the processor and the interrupt controller. While sending an interrupt signal to the processor, the interrupt controller reads the entry address of the interrupt service routine from the interrupt vector unit and waits for the processor to read it. The processor reads the entry address of the interrupt service routine from the interrupt controller through the data exchange interface and executes the interrupt steps according to the interrupt signal and the entry address of the interrupt service routine. This application does not require consuming data bus bandwidth, thus improving the interrupt response speed.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to an interrupt system, method, device and medium. Background Technology

[0002] In modern computer technology, the interrupt mechanism is a core mechanism that allows the CPU to work efficiently with peripheral low-speed devices. It allows high-priority events to break the current CPU execution flow, ensuring that high-priority events are processed first, while preventing the CPU from wasting computing resources waiting for sudden events from peripheral devices. Therefore, as a core CPU mechanism, the response speed of interrupts largely determines the performance of the entire computer system.

[0003] In related technologies, the computer interrupt process is as follows: an interrupt controller (Programmable Interrupt Controller - PIC) is designed to receive interrupts. The interrupt controller PIC transmits the interrupt signal to the CPU. After receiving the interrupt signal, the CPU obtains the interrupt index from the PIC and then reads the interrupt service routine entry address from the interrupt vector table (IVT). This method consumes data bus bandwidth and is inefficient, resulting in a slow interrupt response speed. Summary of the Invention

[0004] This application aims to provide an interruption system, method, device, and medium that can improve the response speed of interruptions.

[0005] In a first aspect, embodiments of this application provide an interrupt system applied to an electronic device, the electronic device including one or more peripherals, the interrupt system including:

[0006] processor;

[0007] An interrupt controller is provided, wherein a first interrupt line and a data exchange interface are provided between the interrupt controller and the processor, and a second interrupt line is provided between the interrupt controller and the peripheral device;

[0008] An interrupt vector unit is used to store the entry address of an interrupt service routine, and the interrupt vector unit is connected to the interrupt controller.

[0009] Wherein, after receiving the interrupt signal sent by the peripheral device through the second interrupt line, the interrupt controller reads the interrupt service routine entry address from the interrupt vector unit, and then sends the interrupt signal to the processor through the first interrupt line. After receiving the interrupt signal, the processor reads the interrupt service routine entry address from the interrupt controller through the data exchange interface, and executes the interrupt steps according to the interrupt signal and the interrupt service routine entry address.

[0010] According to some embodiments of this application, the interrupt signal includes a first interrupt signal, which is a maskable interrupt signal, and the interrupt controller includes an interrupt arbitration logic unit, an interrupt flag register, and an interrupt enable register;

[0011] The interrupt flag register is connected to the second interrupt line, and the interrupt flag register and the interrupt enable register are respectively connected to the interrupt arbitration logic unit. The interrupt arbitration logic unit is connected to the processor through the first interrupt line.

[0012] The interrupt arbitration logic unit obtains the interrupt request of the first interrupt signal through the interrupt flag register, obtains the corresponding permission of the first interrupt signal through the interrupt enable register, arbitrates the first interrupt signal according to the permission, and sends the first interrupt signal that has passed the arbitration to the processor.

[0013] According to some embodiments of this application, the interrupt signal further includes a second interrupt signal, which is a non-maskable interrupt signal. A third interrupt line is also provided between the interrupt controller and the peripheral device. The interrupt arbitration logic unit is connected to the third interrupt line to receive the second interrupt signal.

[0014] The interrupt arbitration logic unit receives the second interrupt signal and then sends it directly to the processor through the first interrupt line.

[0015] According to some embodiments of this application, the interrupt vector unit includes a first interrupt vector table and a second interrupt vector table. Both the first interrupt vector table and the second interrupt vector table store the entry address of the interrupt service routine. The first interrupt vector table and the second interrupt vector table have different addressing spaces.

[0016] Secondly, embodiments of this application provide a control method for an interrupt system as described in the first aspect, comprising the following steps:

[0017] The interrupt controller receives interrupt signals sent by peripherals through the second interrupt line;

[0018] The interrupt controller reads the interrupt service routine entry address from the interrupt vector unit;

[0019] The interrupt controller sends the interrupt signal to the processor via the first interrupt line;

[0020] The processor reads the interrupt service routine entry address from the interrupt controller through the data exchange interface;

[0021] The processor executes the interrupt steps based on the interrupt signal and the interrupt service routine entry address.

[0022] According to some embodiments of this application, the interrupt vector unit includes a first interrupt vector table and a second interrupt vector table. Both the first and second interrupt vector tables store interrupt service routine entry addresses, and the first and second interrupt vector tables have different address spaces. The interrupt controller reads the interrupt service routine entry address from the interrupt vector unit, including:

[0023] The interrupt controller reads the first interrupt service routine entry address from the first interrupt vector table, and the interrupt controller reads the second interrupt service routine entry address from the second interrupt vector table;

[0024] The interrupt controller compares the consistency between the first interrupt service routine entry address and the second interrupt service routine entry address;

[0025] Where the first interrupt service routine entry address and the second interrupt service routine entry address are the same, the interrupt controller obtains the interrupt service routine entry address based on the first interrupt service routine entry address and the second interrupt service routine entry address for the processor to read.

[0026] If the first interrupt service routine entry address and the second interrupt service routine entry address are inconsistent, the interrupt controller outputs an interrupt exception signal to the processor.

[0027] According to some embodiments of this application, after the interrupt controller sends the interrupt signal to the processor via the first interrupt line, it further includes:

[0028] The processor sends a flag clearing command to the interrupt controller through a data interaction interface. The flag clearing command is used to clear the processed interrupt flags.

[0029] Thirdly, embodiments of this application provide an electronic device including the interrupt system described in the second aspect.

[0030] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the control method of the interrupt system as described in the second aspect.

[0031] The interrupt system, method, device, and medium of this application have at least the following beneficial effects:

[0032] In this embodiment, a separate first interrupt line is provided between the processor and the interrupt controller. An interrupt signal is inserted into the processor pipeline through this first interrupt line. While sending the interrupt signal to the processor, the interrupt controller reads the interrupt service routine entry address from the interrupt vector unit and waits for the processor to read it. Furthermore, a data exchange interface is added between the processor and the interrupt controller. The processor reads the interrupt service routine entry address from the interrupt controller through this data exchange interface and executes the interrupt steps based on the interrupt signal and the interrupt service routine entry address. This application does not require consuming data bus bandwidth, thus improving the interrupt response speed.

[0033] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0034] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0035] Figure 1 A schematic diagram of the interrupt system provided in this application;

[0036] Figure 2 A schematic diagram of the structure of the interrupt vector unit with redundant configuration provided in this application;

[0037] Figure 3 A flowchart illustrating an embodiment of the control method for the interrupt system provided in this application. Detailed Implementation

[0038] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0039] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0040] To address the problems of the prior art, embodiments of this application provide an interrupt system, method, device, and medium. The interrupt system provided in the embodiments of this application will be described first.

[0041] Figure 1 A schematic diagram of the structure of an interrupt system provided in an embodiment of this application is shown. An interrupt system is applied to an electronic device, which includes one or more peripherals. The interrupt system includes:

[0042] processor;

[0043] An interrupt controller is provided, with a first interrupt line and a data exchange interface between the interrupt controller and the processor, and a second interrupt line between the interrupt controller and the peripheral device;

[0044] The interrupt vector unit is used to store the entry address of the interrupt service routine. The interrupt vector unit is connected to the interrupt controller.

[0045] In this process, after receiving the interrupt signal sent by the peripheral device through the second interrupt line, the interrupt controller reads the interrupt service routine entry address from the interrupt vector unit, and then sends an interrupt signal to the processor through the first interrupt line. After receiving the interrupt signal, the processor reads the interrupt service routine entry address from the interrupt controller through the data exchange interface, and executes the interrupt steps according to the interrupt signal and the interrupt service routine entry address.

[0046] In this embodiment, a separate first interrupt line is provided between the processor and the interrupt controller. An interrupt signal is inserted into the processor pipeline through this first interrupt line. While sending the interrupt signal to the processor, the interrupt controller reads the interrupt service routine entry address from the interrupt vector unit and waits for the processor to read it. Furthermore, a data exchange interface is added between the processor and the interrupt controller. The processor reads the interrupt service routine entry address from the interrupt controller through this data exchange interface and executes the interrupt steps based on the interrupt signal and the interrupt service routine entry address. This application does not require consuming data bus bandwidth, thus improving the interrupt response speed.

[0047] In this embodiment, the processor refers to the CPU in a computer, and peripherals refer to hardware devices connected to the CPU and memory, such as power supplies, mice, keyboards, and monitors. The interrupt controller is responsible for receiving and arbitrating interrupt signals. It connects to the processor via a first interrupt line and to the peripherals via a second interrupt line. Both interrupt lines serve the same purpose: transmitting and solely transmitting interrupt signals. The second interrupt line transmits interrupt signals from peripherals to the interrupt controller, which then arbitrates them before sending them to the processor via the first interrupt line. The interrupt vector unit refers to the Interrupt Vector Table (IVT), which stores the entry addresses of interrupt service routines. After sending an interrupt signal to the processor, the interrupt controller reads the interrupt service routine entry address from the interrupt vector unit and stores it, awaiting the processor's retrieval. Upon receiving the interrupt signal, the processor reads the interrupt service routine entry address stored by the interrupt controller through a newly added data exchange interface. It then begins executing a series of interrupt steps, including saving the interrupt context, clearing the interrupt flag, and jumping to the interrupt service routine based on the entry address. Since the interrupt signal is transmitted between the processor and the interrupt controller via the first interrupt line, and the interrupt controller reads the interrupt service routine entry address from the interrupt vector table in advance, and then transmits the interrupt service routine entry address to the processor through the data exchange interface, this method does not require the use of data bus bandwidth and can improve the interrupt response speed.

[0048] In some implementations, the interrupt signal includes a first interrupt signal, which is a maskable interrupt signal, and the interrupt controller includes an interrupt arbitration logic unit, an interrupt flag register, and an interrupt enable register.

[0049] The interrupt flag register is connected to the second interrupt line. The interrupt flag register and the interrupt enable register are respectively connected to the interrupt arbitration logic unit, which is connected to the processor via the first interrupt line.

[0050] The interrupt arbitration logic unit obtains the interrupt request of the first interrupt signal through the interrupt flag register, obtains the corresponding permission of the first interrupt signal through the interrupt enable register, arbitrates the first interrupt signal according to the permission, and sends the first interrupt signal that has passed the arbitration to the processor.

[0051] In this embodiment, the interrupt arbitration logic unit obtains the interrupt request of the first interrupt signal through the interrupt flag register and the corresponding permission of the first interrupt signal through the interrupt enable register. Based on the permission, it arbitrates the first interrupt signal and sends the successfully arbitrated first interrupt signal to the processor. When multiple interrupt requests occur simultaneously, arbitration can determine which interrupt should be processed first, ensuring that the system can respond to the most important events in an orderly, efficient, and reliable manner.

[0052] It should be noted that the Interrupt Flag Register (PIC_IFR) has multiple interrupt flag bits. Each interrupt flag bit reflects whether a specific interrupt event has occurred. When one or more peripherals generate an interrupt, the corresponding interrupt flag bit in the Interrupt Flag Register is set, and the corresponding interrupt enable bit in the Interrupt Enable Register determines whether the corresponding interrupt flag bit participates in arbitration. Based on the arbitration result, the interrupt controller retrieves the interrupt service routine entry address from the interrupt vector table and transmits the interrupt signal to the processor.

[0053] For example, the interrupt flag bits in the interrupt flag register are represented by PIC_IFR[0], PIC_IFR[1], ..., PIC_IFR[n], respectively, which are used to reflect whether interrupt event 1, interrupt event 2, and interrupt event n have occurred. The priority is defined as: interrupt event 1 > interrupt event 2 > ... > interrupt event n. The following example illustrates the interrupt arbitration process:

[0054] If interrupt events 1, 3, and 5 occur simultaneously at a certain moment, PIC_IFR[0], PIC_IFR[2], and PIC_IFR[4] are set simultaneously. After the interrupt arbitration logic, since PIC_IFR[0] has the highest interrupt priority, the CPU prioritizes processing interrupt event 1, while interrupt events 3 and 5 are suspended and await processing. After the CPU processes interrupt event 1, to avoid interrupt event 1 being processed repeatedly, it resets PIC_IFR[0] to indicate that interrupt event 1 has been processed. If no new interrupt event occurs, the interrupt arbitration logic then performs interrupt arbitration on PIC_IFR[2] and PIC_IFR[4]. According to the defined priority, the CPU prioritizes processing interrupt event 3 and resets PIC_IFR[2], and finally processes interrupt event 5 and resets PIC_IFR[4].

[0055] In some implementations, the interrupt signal further includes a second interrupt signal, which is a non-maskable interrupt signal. A third interrupt line is also provided between the interrupt controller and the peripheral device. The interrupt arbitration logic unit is connected to the third interrupt line to receive the second interrupt signal.

[0056] In this case, the interrupt arbitration logic unit receives the second interrupt signal and sends it directly to the processor through the first interrupt line.

[0057] In this embodiment, the interrupt arbitration logic unit receives the non-maskable second interrupt signal through the third interrupt line, and after receiving the second interrupt signal, it directly sends it to the processor through the first interrupt line, which can further improve the speed of responding to specific interrupts and ensure the reliability of system operation.

[0058] It should be noted that if errors occur during system operation, such as power short circuits or memory check errors, these errors can severely impact system operation. Therefore, the CPU needs to handle them immediately. These types of error events are urgent and must be treated as non-maskable interrupts. Thus, the interrupt signal generated by this type of error is defined as a non-maskable second interrupt signal. This second interrupt signal does not pass through the interrupt flag register or arbitration; the interrupt arbitration logic unit receives it and sends it directly to the processor. This further improves the speed of response to specific interrupts and ensures the reliability of system operation.

[0059] In some implementations, the interrupt vector unit includes a first interrupt vector table and a second interrupt vector table. Both the first and second interrupt vector tables store the entry address of the interrupt service routine, and the first and second interrupt vector tables have different addressing spaces.

[0060] In this embodiment, setting the interrupt vector unit to two identical first interrupt vector tables and second interrupt vector tables can prevent the processor from obtaining the wrong interrupt service routine entry address, causing the program to enter an uncontrollable state and improving the reliability of system operation.

[0061] It should be noted that the Interrupt Vector Table (IVT) is a small segment of memory used to store the entry addresses of interrupt service routines. When responding to an interrupt, the interrupt controller reads the corresponding interrupt vector from the IVT and sends the address of the interrupt service routine to the processor. During the process of reading the interrupt service routine address, an incorrect address may be read due to external electromagnetic interference, voltage glitches, or other factors. If the processor continues to perform the interrupt steps according to the incorrect address, the program will enter an uncontrollable state.

[0062] To prevent the CPU from acquiring an incorrect interrupt service routine entry address, which could cause the program to enter an uncontrollable state, refer to... Figure 2As shown, this application sets up two interrupt vector tables, a first interrupt vector table and a second interrupt vector table, to store interrupt service routine addresses, namely IVT1 and IVT2, where IVT2 is a copy of IVT1. IVT1 and IVT2 occupy exactly the same memory size and have different address spaces. When the processor writes to an interrupt service routine address in IVT1, it maps the written data to the corresponding address in IVT2. When the interrupt controller reads the interrupt service routine address, it reads from both IVT1 and IVT2 simultaneously and compares whether the data read from IVT1 and IVT2 are consistent. If they are consistent, the data is valid, and the processor is allowed to receive the data from the interrupt controller; if they are inconsistent, it means that the interrupt service routine address read is incorrect, and an interrupt vector address error signal VECTERRADDR is output to the processor. After the processor detects that VECTERRADDR is pulled high, it jumps to the user-specified error handler or runs the default error handler in the BOOTROM to prevent the program from crashing.

[0063] It should be noted that the comparison of whether the data read from IVT1 and IVT2 are consistent can be determined by the interrupt controller itself, or by setting an additional hardware comparison circuit. In this embodiment, an additional hardware comparison circuit is used for the determination. When the data read from IVT1 and IVT2 are inconsistent, the hardware comparison circuit pulls up the interrupt vector address error signal VECTERRADDR to the CPU. After the processor detects that VECTERRADDR is high, it automatically enters the interrupt exception handler.

[0064] This application also relates to a control method for an interrupt system, comprising the following steps:

[0065] S101, The interrupt controller receives interrupt signals sent by peripherals through the second interrupt line;

[0066] S102. The interrupt controller reads the interrupt service routine entry address from the interrupt vector unit;

[0067] S103, The interrupt controller sends an interrupt signal to the processor through the first interrupt line;

[0068] S104. The processor reads the interrupt service routine entry address from the interrupt controller through the data exchange interface;

[0069] S105. The processor executes the interrupt steps based on the interrupt signal and the interrupt service routine entry address.

[0070] In this embodiment, the interrupt controller first receives the interrupt signal sent by the peripheral device through the second interrupt line. Then, the interrupt controller reads the interrupt service routine entry address from the interrupt vector unit. Next, the interrupt controller sends the interrupt signal to the processor through the first interrupt line. Then, the processor reads the interrupt service routine entry address from the interrupt controller through the data exchange interface. Finally, the processor executes the interrupt steps according to the interrupt service routine entry address. This application does not require the use of data bus bandwidth, thus improving the interrupt response speed.

[0071] The interrupt system in this application embodiment is controlled by the control method of the interrupt system in the above embodiment. Its specific processing is the same as that of the interrupt system in the above embodiment, and will not be described in detail here.

[0072] In some implementations, the interrupt vector unit includes a first interrupt vector table and a second interrupt vector table. Both the first and second interrupt vector tables store the entry address of an interrupt service routine, and the first and second interrupt vector tables have different address spaces. The interrupt controller reads the interrupt service routine entry address from the interrupt vector unit, which may include:

[0073] The interrupt controller reads the entry address of the first interrupt service routine from the first interrupt vector table, and the interrupt controller reads the entry address of the second interrupt service routine from the second interrupt vector table;

[0074] The interrupt controller compares the entry addresses of the first and second interrupt service routines for consistency.

[0075] In the case where the first interrupt service routine entry address and the second interrupt service routine entry address are the same, the interrupt controller obtains the interrupt service routine entry address based on the first interrupt service routine entry address and the second interrupt service routine entry address for the processor to read.

[0076] If the entry address of the first interrupt service routine and the entry address of the second interrupt service routine are inconsistent, the interrupt controller outputs an interrupt exception signal to the processor.

[0077] In this embodiment, the interrupt controller reads the first interrupt service routine entry address from the first interrupt vector table and the second interrupt service routine entry address from the second interrupt vector table. The interrupt controller compares the consistency of the first and second interrupt service routine entry addresses. If the first and second interrupt service routine entry addresses are consistent, the interrupt controller obtains the interrupt service routine entry address based on the first and second interrupt service routine entry addresses for the processor to read. If the first and second interrupt service routine entry addresses are inconsistent, the interrupt controller outputs an interrupt exception signal to the processor. This improves the reliability of system operation.

[0078] Specifically, to prevent the CPU from obtaining an incorrect interrupt service routine entry address and the program from entering an uncontrollable state, refer to... Figure 2 As shown, this application sets up two interrupt vector tables, a first interrupt vector table and a second interrupt vector table, to store interrupt service routine addresses, namely IVT1 and IVT2, where IVT2 is a copy of IVT1. IVT1 and IVT2 occupy exactly the same memory size and have different address spaces. When the processor writes to an interrupt service routine address in IVT1, it maps the written data to the corresponding address in IVT2. When the interrupt controller reads the interrupt service routine address, it reads from both IVT1 and IVT2 simultaneously and compares whether the data read from IVT1 and IVT2 are consistent. If they are consistent, the data is valid, and the processor is allowed to receive the data from the interrupt controller; if they are inconsistent, it means that the interrupt service routine address read is incorrect, and an interrupt vector address error signal VECTERRADDR is output to the processor. After the processor detects that VECTERRADDR is pulled high, it jumps to the user-specified error handler or runs the default error handler in the BOOTROM to prevent the program from crashing.

[0079] In this embodiment, the interrupt controller compares and judges the data read from IVT1 and IVT2. When the data read from IVT1 and IVT2 are inconsistent, the interrupt controller outputs an interrupt vector address error signal VECTERRADDR. After the processor detects that VECTERRADDR is high, it automatically enters the interrupt exception handling program.

[0080] In some implementations, after the interrupt controller sends an interrupt signal to the processor via a first interrupt line, it may further include:

[0081] The processor sends a flag clear command to the interrupt controller through the data interaction interface. The flag clear command is used to clear the flags of processed interrupts.

[0082] In this embodiment, after the interrupt controller sends the interrupt signal to the processor through the first interrupt line, the processor sends a flag clear command to the interrupt controller through the data interaction interface. After receiving the command, the interrupt controller can promptly clear the interrupt flags that have been processed by the processor, which can improve the reliability of the system.

[0083] The workflow of this application is explained in detail below with two specific examples:

[0084] Example 1: Assume the PIC interrupt enable register flag corresponding to interrupt event 1 is PIC_IER[0], the PIC interrupt flag register flag corresponding to interrupt event 1 is PIC_IFR[0], the PIC interrupt enable register flag corresponding to interrupt event 2 is PIC_IER[1], and the corresponding PIC interrupt flag register flag is PIC_IFR[1]. Assume that PIC_IER[0] and PIC_IER[1] are enabled before the interrupt event occurs, and the priority of interrupt event 1 is greater than that of interrupt event 2. At a certain moment, interrupt event 1 and interrupt event 2 occur simultaneously, and PIC_IFR[0] and PIC_IFR[1] are immediately set. The interrupt arbitration logic determines that interrupt event 1 is processed first and generates the read address and read control signal of IVT1 and IVT2. After the PIC reads the data from IVT1 and IVT2, it compares the consistency. If the data of IVT1 and IVT2 are consistent, the PIC saves the read data and waits for the CPU to read it. If the data are inconsistent, it pulls VECTERRADDR high for one system cycle. After the CPU detects that VECTERRADDR is high, it automatically enters the interrupt exception handler.

[0085] Example 2: Assume that when the CPU responds to an interrupt, it needs to save the values ​​of registers ACC, R0~R3, and the PC register. After receiving command 0x01 from the CPU, the PIC clears the relevant interrupt flag bits in the interrupt flag register. After receiving command 0x02, it sends the data read from the IVT to the CPU. Based on Example 1, after the CPU detects that the interrupt line is high, it clears the CPU pipeline and waits for the currently executing instruction to complete. Then, it executes the INTR instruction. The INTR instruction is executed in several steps, each consuming one system clock cycle.

[0086] Step S201: Write the value of ACC to RAM and send command 0x01 to PIC at the same time.

[0087] Step S202: Write the value of R0 to RAM and send command 0x02 to the PIC. The PIC receives command 0x01 from the CPU in step S201, prevents new interrupts from being passed to the CPU, and clears PIC_IER[0] and PIC_IFR[0] to prevent new interrupts from being lost while responding to the current interrupt.

[0088] Step S203: Write the value of R1 to RAM. The PIC sends the data read from the IVT by the command 0x02 to the CPU.

[0089] Step S204: Write the value of R2 to RAM, and the CPU receives the interrupt service routine entry address passed by the PIC.

[0090] Step S205: Write the value of R3 to RAM.

[0091] Step S206: Write the value of the PC register to RAM.

[0092] Step S207: After the INTR instruction is executed, the interrupt service routine entry address is assigned to the PC.

[0093] In summary, this application improves system real-time performance by inserting specific interrupt instructions into the processor pipeline and adding a data interaction interface between the interrupt controller and the processor. This is achieved by quickly completing tasks such as interrupt context saving and interrupt flag register clearing before entering an interrupt. Furthermore, by designing a redundant dual interrupt vector table, abnormal PC jumps caused by electromagnetic interference, voltage glitches, etc., during interrupt response can be avoided, thus improving system reliability.

[0094] This application also relates to an electronic device including the interrupt system of the above embodiments.

[0095] Furthermore, in conjunction with the interrupt system control method in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the interrupt system control methods in the above embodiments.

[0096] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0097] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0098] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0099] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0100] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An interrupt system, characterized by The application is applied to an electronic device comprising one or more peripherals, and the interrupt system comprises: a processor; an interrupt controller, which is connected with the processor via a first interrupt line and a data exchange interface, and is connected with the peripherals via a second interrupt line; an interrupt vector unit, which is used to store interrupt service program entry addresses and is connected with the interrupt controller; wherein, after the interrupt controller receives an interrupt signal sent by the peripherals via the second interrupt line, the interrupt controller reads an interrupt service program entry address from the interrupt vector unit, and then sends the interrupt signal to the processor via the first interrupt line; after the processor receives the interrupt signal, the processor reads an interrupt service program entry address from the interrupt controller via the data exchange interface, and executes an interrupt step according to the interrupt signal and the interrupt service program entry address; wherein, the interrupt vector unit comprises a first interrupt vector table and a second interrupt vector table, and the first interrupt vector table and the second interrupt vector table both store interrupt service program entry addresses, and the first interrupt vector table and the second interrupt vector table have different addressing spaces; the reading of the interrupt service program entry address from the interrupt vector unit comprises: the reading of a first interrupt service program entry address from the first interrupt vector table by the interrupt controller, and the reading of a second interrupt service program entry address from the second interrupt vector table by the interrupt controller; the comparison of the consistency of the first interrupt service program entry address and the second interrupt service program entry address by the interrupt controller; wherein, in the case that the first interrupt service program entry address and the second interrupt service program entry address are consistent, the interrupt controller obtains an interrupt service program entry address according to the first interrupt service program entry address and the second interrupt service program entry address for the processor to read; in the case that the first interrupt service program entry address and the second interrupt service program entry address are inconsistent, the interrupt controller outputs an interrupt exception signal to the processor.

2. The interrupt system of claim 1, wherein, The interrupt signal comprises a first interrupt signal, and the first interrupt signal is a maskable interrupt signal; the interrupt controller comprises an interrupt arbitration logic unit, an interrupt flag register and an interrupt enable register; the interrupt flag register is connected with the second interrupt line, and the interrupt flag register and the interrupt enable register are respectively connected with the interrupt arbitration logic unit; the interrupt arbitration logic unit is connected with the processor via the first interrupt line, wherein, the interrupt arbitration logic unit acquires an interrupt request of the first interrupt signal via the interrupt flag register, acquires a corresponding authority of the first interrupt signal via the interrupt enable register, arbitrates the first interrupt signal according to the authority, and sends the first interrupt signal that passes the arbitration to the processor.

3. The interrupt system of claim 2, wherein, The interrupt signal further comprises a second interrupt signal, the second interrupt signal being a non-maskable interrupt signal, and a third interrupt line is further provided between the interrupt controller and the peripheral device, and the interrupt arbitration logic unit is connected to the third interrupt line for receiving the second interrupt signal, wherein the interrupt arbitration logic unit directly sends the second interrupt signal to the processor through the first interrupt line after receiving the second interrupt signal.

4. A control method of the interrupt system according to any one of claims 1 to 3, characterized by, The method comprises the following steps: The interrupt controller receives the interrupt signal sent by the peripheral device through a second interrupt line; The interrupt controller reads the interrupt service program entry address from the interrupt vector unit; The interrupt controller sends the interrupt signal to the processor through a first interrupt line; The processor reads the interrupt service program entry address from the interrupt controller through a data exchange interface; The processor executes the interrupt step according to the interrupt signal and the interrupt service program entry address.

5. The control method of an interrupt system according to claim 4, characterized by, After the interrupt controller sends the interrupt signal to the processor through the first interrupt line, the method further comprises the following steps: The processor sends a flag bit clearing command to the interrupt controller through the data exchange interface, and the flag bit clearing command is used to clear the processed interrupt flag.

6. An electronic device, comprising: The interrupt system of any one of claims 1 to 3.

7. A computer readable storage medium characterized by, The computer readable storage medium stores computer program instructions, and the computer program instructions are executed by the processor to realize the control method of the interrupt system of any one of claims 4 to 5.

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