Low-kick-back low-imbalance dynamic comparator with cross-coupled pair transistors and operation method of low-kick-back low-imbalance dynamic comparator

Abstract

The invention discloses a low-kick-back low-detuning dynamic comparator with cross coupling pair transistors and an operation method, and belongs to the technical field of analog integrated circuits. The comparator comprises a pre-amplification stage and a regeneration stage, the pre-amplification stage is composed of a reset module I, an offset elimination module, a cross coupling module and a pre-amplification module, and the regeneration stage is composed of a reset module II, an enabling module and a latch comparison module. According to the operation method, a complete period is divided into four stages of resetting, offset elimination, sampling and comparison, wherein key nodes are initialized in the resetting stage; in the offset elimination stage, offset voltage of the input geminate transistors is stored through a capacitor. In the sampling stage, an input signal is coupled with a stored offset voltage, and introduction of additional offset is avoided; in the comparison stage, a cross coupling module is used for regulating and controlling the discharge rate, kickback noise is restrained, the comparison precision is improved, and finally signal latching is completed through a regenerative-stage positive feedback mechanism.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a low-kickback, low-offset dynamic comparator with cross-coupled transistors and its operation method. Background Technology

[0002] Compared to static comparators, dynamic comparators are simpler in structure and consume less power because the various parts of the comparator are not always active under the control of the clock signal. The Strong-arm comparator is a classic single-tailed dynamic comparator. In this structure, the latches that use positive feedback for output are directly stacked above the input pair. Abrupt changes at the output node are coupled to the input node through the gate-drain parasitic capacitance of the input pair, causing input voltage fluctuations, known as kickback noise. To mitigate this, dual-tailed comparators were proposed, with the structure shown below. Figure 1 As shown, the comparator's output and input nodes are separated by MN4 and MN7, preventing abrupt changes in the output node from affecting the input node. The operation of this structure involves the discharge of the X and Y nodes, which introduces a new kickback noise problem: the nodes discharge very quickly, also causing fluctuations in the input node voltage. Furthermore, the chip manufacturing process inevitably introduces transistor size mismatch, which manifests as offset voltage. While increasing the transistor size can reduce offset, this significantly increases area overhead. Summary of the Invention

[0003] To address the problems existing in traditional dual-tailed dynamic comparators, the present invention aims to provide a low-kickback, low-offset dynamic comparator with cross-coupled transistors and its operation method.

[0004] To achieve the above objectives, the present invention provides a low-kickback, low-offset dynamic comparator with cross-coupled transistors and a method for operating it, including a pre-amplification stage and a regeneration stage.

[0005] The pre-amplification stage includes: a reset module I, an offset cancellation module, a cross-coupling module, and a pre-amplification module; the reset module I is composed of MN6, MN7, MP1, and MP2; the offset cancellation module is composed of S3, S4, S5, S6, S7, and C1 and C2; the cross-coupling module is composed of MN3 and MN4; and the pre-amplification module is composed of S1, S2, and MN1, MN2, MN3, MN4, MN5, MP1, and MP2.

[0006] The regeneration stage includes: a reset module II, an enable module, and a latch comparison module; the reset module II is composed of MN10, MN11, MN12, and MN13; the enable module is composed of MP3; and the latch comparison module is composed of MN8, MN9, MP4, MP5, MP6, and MP7.

[0007] More specifically, in the reset module I, the sources of MN6 and MN7 are connected to GND; the gates of MN6 and MN7 are connected to the clock signal CLK1; the drain of MN6 is connected to the gate of MN1, and the drain of MN7 is connected to the gate of MN2; the gates of MP1 and MP2 are connected to the clock signal CLK2, and their sources are connected to VDD; the drain of MP1 is connected to the drain of MN1, and the drain of MP2 is connected to the drain of MN2.

[0008] More specifically, in the offset cancellation module, the first terminals of S3 and S4 are connected to the common-mode level VCM; the second terminal of S3 is connected to the first terminal of C1, and the second terminal of S4 is connected to the first terminal of C2; the first terminal of S5 is connected to the drain of MP1, and the first terminal of S6 is connected to the drain of MP2; the first terminal of S7 is connected to the source of MN1 and the drain of MN3, and the second terminal is connected to the source of MN2 and the drain of MN4; the second terminal of C1 is connected to the second terminal of S5 and the drain of MN6, and the second terminal of C2 is connected to the second terminal of S6 and the drain of MN7.

[0009] More specifically, in the cross-coupling module, the gate of MN3 is connected to the drain of MN2, and the gate of MN4 is connected to the drain of MN1; the sources of MN3 and MN4 are connected to the drain of MN5.

[0010] More specifically, in the pre-amplification module, the first terminal of S1 is connected to the first differential input signal INP, and the first terminal of S2 is connected to the second differential input signal INN; the second terminal of S1 is connected to the first terminal of C1, and the second terminal of S2 is connected to the first terminal of C2; the gate of MN1 is connected to the second terminal of C1, and the gate of MN2 is connected to the second terminal of C2; the source of MN1 is connected to the drain of MN3 and the first terminal of S7; the source of MN2 is connected to the drain of MN4 and the second terminal of S7; the gate of MN5 is connected to the clock signal CLK2, and the source is connected to GND.

[0011] More specifically, in the reset module II, the gates of MN10, MN11, MN12, and MN13 are connected to the clock signal CLK3, and their sources are connected to GND; the drain of MN10 is connected to the drain of MN8, the drain of MN11 is connected to the drain of MN9, the drain of MN12 is connected to the drain of MP4, and the drain of MN13 is connected to the drain of MP5.

[0012] More specifically, in the enable module, the gate of MP3 is connected to the clock signal CLK3, the source is connected to VDD, and the drain is connected to the source of MP4 and MP5.

[0013] More specifically, in the latch comparison module, the gate of MP6 is connected to the drain of MN1, and the gate of MP7 is connected to the drain of MN2; the source of MP6 is connected to the drain of MP4, and the source of MP7 is connected to the drain of MP5; the drain of MP6 is connected to the drain of MN8, and the drain of MP7 is connected to the drain of MN9; the gate of MN8 is connected to the gate of MP4 and the drain of MP7; and the gate of MN9 is connected to the gate of MP5 and the drain of MP6.

[0014] The present invention also provides a method for operating a low-kickback, low-offset dynamic comparator with cross-coupled transistors, comprising: A complete operating cycle of a comparator consists of the following four stages: reset, offset elimination, sampling, and comparison; During the reset phase of the comparator, MN5 is turned off, nodes X and Y are charged to VDD; the gates of MN1 and MN2, the sources of MP6 and MP7, and nodes OUTP and OUTN are discharged to GND. During the offset cancellation phase of the comparator, S3 and S4 are closed, and the first terminals of C1 and C2 are connected to the common-mode signal VCM; MN5 is turned on, MN6 and MN7 are turned off, and nodes X and Y begin to discharge; after the discharge is completed, the offset voltage is stored in capacitors C1 and C2; in the dual-tailed comparator, the main source of offset is the input pair transistors MN1 and MN2 in the pre-amplification stage, so offset cancellation operation only needs to be performed in the pre-amplification stage. During the sampling phase, MN5 is turned off, S1 and S2 are closed, the first terminal of C1 is connected to the first differential input signal INP, and the first terminal of C2 is connected to the second differential input signal INN; nodes X and Y are charged to VDD; S7 is closed to make the source voltages of MN1 and MN2 the same, thereby avoiding the introduction of additional offset voltage. During the comparison phase, MN5 is turned on. If INP > INN, the discharge current of MN1 exceeds the discharge current of MN2, thus keeping the voltage of node X lower than that of node Y. Since nodes X and Y are both input nodes of the regenerative stage, the charging current of MP6 exceeds the charging current of MP7, causing the voltage rise rate of node OUTP to be faster than that of node OUTN. After the voltage of node OUTP exceeds the threshold, the positive feedback mechanism of the latch will quickly pull node OUTP high to VDD and pull node OUTN down to GND, thus completing a full operating cycle.

[0015] Beneficial effects: The existence of cross-coupled modules has the following advantages: 1. During the comparison phase, the voltage drop at nodes X and Y increases the channel resistance of MN3 and MN4; this leads to a significant decrease in the discharge rate, thereby significantly suppressing kickback noise. 2. Because the discharge rate of node X is faster, the channel resistance of MN4 increases more than that of MN3, which further slows down the discharge rate of node Y; the difference in discharge rate increases the voltage difference between node X and node Y, thereby improving the comparison accuracy and speed. 3. When node X is fully discharged to GND, node Y immediately stops discharging, thereby reducing power consumption.

[0016] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is the circuit diagram of a traditional dual-tailed comparator; Figure 2 This is a circuit diagram of the comparator proposed in this invention; Figure 3 This is a simulation comparison of the kickback noise between the comparator proposed in this invention and a traditional dual-tailed comparator; Figure 4 This is a simulation diagram of the back-kick noise of the comparator proposed in this invention under different process angles; Figure 5 This is a simulation diagram comparing the offset voltage of the comparator proposed in this invention and a traditional dual-tailed comparator. Detailed Implementation

[0019] Specific embodiments of the invention will now be described in detail. Although the invention is described in conjunction with these specific embodiments, it should be understood that the invention is not intended to be limited to these specific embodiments. Rather, these embodiments are intended to cover alternative, modified, or equivalent embodiments that may be included within the spirit and scope of the invention as defined by the claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known processes have not been described in detail so as not to unnecessarily obscure the invention.

[0020] When used in conjunction with the terms "comprising," "method comprising," or similar language in this specification and appended claims, the singular forms "a," "some," and "the" include plural references unless the context clearly indicates otherwise. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0021] The present invention will now be described in further detail with reference to the full text.

[0022] A low-kickback, low-offset dynamic comparator with cross-coupled transistors, comprising a pre-amplification stage and a regeneration stage. The pre-amplification stage includes: Reset module I is used to reset the critical nodes of the pre-amplification stage to GND or VDD; Offset cancellation module, used to store offset voltage; Cross-coupling modules are used to suppress kickback noise, improve comparison accuracy and speed, and reduce power consumption; The pre-amplification module is used to amplify the small voltage difference of the differential signal; The regeneration stage includes: Reset module II is used to reset the critical nodes of the regenerator stage to GND; The enable module is used to control the operating status of the regenerator stage; The latch comparison module is used to perform comparison operations; The reset module I consists of MN6, MN7, MP1, and MP2; The imbalance elimination module consists of S3, S4, S5, S6, S7 and C1, C2; The cross-coupling module consists of MN3 and MN4; The pre-amplification module consists of S1, S2 and MN1, MN2, MN3, MN4, MN5, MP1, and MP2; The reset module II consists of MN10, MN11, MN12, and MN13; The enabling module is composed of MP3; The latch comparison module consists of MN8, MN9 and MP4, MP5, MP6 and MP7.

[0023] In the reset module I, the sources of MN6 and MN7 are connected to GND; the gates of MN6 and MN7 are connected to the clock signal CLK1; the drain of MN6 is connected to the gate of MN1, and the drain of MN7 is connected to the gate of MN2; the gates of MP1 and MP2 are connected to the clock signal CLK2, and their sources are connected to VDD; the drain of MP1 is connected to the drain of MN1, and the drain of MP2 is connected to the drain of MN2.

[0024] In the offset cancellation module, the first terminals of S3 and S4 are connected to the common-mode level VCM; the second terminal of S3 is connected to the first terminal of C1, and the second terminal of S4 is connected to the first terminal of C2; the first terminal of S5 is connected to the drain of MP1, and the first terminal of S6 is connected to the drain of MP2; the first terminal of S7 is connected to the source of MN1 and the drain of MN3, and the second terminal is connected to the source of MN2 and the drain of MN4; the second terminal of C1 is connected to the second terminal of S5 and the drain of MN6, and the second terminal of C2 is connected to the second terminal of S6 and the drain of MN7.

[0025] In the cross-coupling module, the gate of MN3 is connected to the drain of MN2, and the gate of MN4 is connected to the drain of MN1; the sources of MN3 and MN4 are connected to the drain of MN5.

[0026] In the pre-amplification module, the first terminal of S1 is connected to the first differential input signal INP, and the first terminal of S2 is connected to the second differential input signal INN; the second terminal of S1 is connected to the first terminal of C1, and the second terminal of S2 is connected to the first terminal of C2; the gate of MN1 is connected to the second terminal of C1, and the gate of MN2 is connected to the second terminal of C2; the source of MN1 is connected to the drain of MN3 and the first terminal of S7; the source of MN2 is connected to the drain of MN4 and the second terminal of S7; the gate of MN5 is connected to the clock signal CLK2, and the source is connected to GND.

[0027] In the reset module II, the gates of MN10, MN11, MN12, and MN13 are connected to the clock signal CLK3, and their sources are connected to GND; the drain of MN10 is connected to the drain of MN8, the drain of MN11 is connected to the drain of MN9, the drain of MN12 is connected to the drain of MP4, and the drain of MN13 is connected to the drain of MP5.

[0028] In the enable module, the gate of MP3 is connected to the clock signal CLK3, the source is connected to VDD, and the drain is connected to the source of MP4 and MP5.

[0029] In the latch comparison module, the gate of MP6 is connected to the drain of MN1, and the gate of MP7 is connected to the drain of MN2; the source of MP6 is connected to the drain of MP4, and the source of MP7 is connected to the drain of MP5; the drain of MP6 is connected to the drain of MN8, and the drain of MP7 is connected to the drain of MN9; the gate of MN8 is connected to the gate of MP4 and the drain of MP7; and the gate of MN9 is connected to the gate of MP5 and the drain of MP6.

[0030] A method for operating a low-kickback, low-offset dynamic comparator with cross-coupled transistors includes: A complete operating cycle of a comparator includes reset, offset cancellation, sampling, and comparison; During the reset phase of the comparator, MN5 is turned off, nodes X and Y are charged to VDD; the gates of MN1 and MN2, the sources of MP6 and MP7, and nodes OUTP and OUTN are discharged to GND. During the offset cancellation phase of the comparator, S3 and S4 are closed, and the gate voltages of the input transistor pair MN1 and MN2 are at the common-mode level VCM. MN5 is turned on, MN6 and MN7 are turned off, and nodes X and Y begin to discharge. After the discharge is complete, the offset voltage is stored in capacitors C1 and C2, and the gate voltage of MN1 is set to V1 and the gate voltage of MN2 is set to V2. In the dual-tailed comparator, the main source of offset is the input transistor pair MN1 and MN2 in the pre-amplification stage, so offset cancellation only needs to be performed in the pre-amplification stage. During the sampling phase of the comparator, MN5 is turned off, and nodes X and Y are charged to VDD; S7 is closed to make the source voltages of MN1 and MN2 the same, thereby avoiding the introduction of additional offset voltage; S1 and S2 are closed, at which time the gate voltage of the input pair transistor MN1 is V1+INP-VCM, and the gate voltage of MN2 is V2+INN-VCM. During the comparison phase, MN5 is turned on. If INP > INN, the discharge current of MN1 exceeds the discharge current of MN2, thus keeping the voltage of node X lower than that of node Y. Since X and Y are both input nodes of the regenerative stage, the charging current of MP6 exceeds the charging current of MP7, causing the voltage of node OUTP to rise faster than that of node OUTN. After OUTP exceeds the threshold, the positive feedback mechanism of the latch will quickly pull OUTP high to VDD and pull OUTN down to GND, thus completing a full operating cycle.

[0031] Reset Module I is an important component of the pre-amplification stage of a low-kickback, low-offset dynamic comparator with cross-coupled transistors. Its core function is to reset the critical nodes of the pre-amplification stage to a specific level (GND or VDD) during the reset phase of the comparator operation, thus preparing for the subsequent offset cancellation, sampling, and comparison phases.

[0032] Structurally, reset module I consists of transistors MN6, MN7, MP1, and MP2, and the connection method of each component is as follows: The sources of MN6 and MN7 are both connected to ground (GND).

[0033] The gate of MN5 is connected to the clock signal CLK1, and the gates of MN6 and MN7 are connected to the clock signal CLK2.

[0034] The drain of MN6 is connected to the gate of MN1, and the drain of MN7 is connected to the gate of MN2.

[0035] The gates of MP1 and MP2 are connected to the clock signal CLK2, and their sources are both connected to the power supply voltage (VDD).

[0036] The drain of MP1 is connected to the drain of MN1, and the drain of MP2 is connected to the drain of MN2.

[0037] During the reset phase, clock signals CLK1 and CLK2 control the operating state of each transistor in reset module I. At this time, MP1 and MP2 are turned on by the CLK2 signal, charging nodes X (drain of MN1) and Y (drain of MN2) connected to their drains to VDD; simultaneously, MN6 and MN7 are also turned on by the CLK1 signal, discharging the gates of MN1 and MN2 to GND. Through this operation, reset module I ensures that the pre-amplifier stage is in a defined state at the beginning of each operating cycle, avoiding interference from signal residue from the previous cycle and providing stable initial conditions for the accurate operation of the comparator.

[0038] The cross-coupling module (composed of MN3 and MN4) is the core innovation of this dynamic comparator in achieving "low kickback, low offset, and high performance," playing three key roles in the entire circuit: 1. Significantly suppresses kickback noise: In traditional dynamic comparators, sudden changes in the output node voltage during the comparison phase can couple to the input node through parasitic capacitance, causing input voltage fluctuations (kickback noise). In this invention, the gate of MN3 is connected to the drain of MN2 (node ​​Y), and the gate of MN4 is connected to the drain of MN1 (node ​​X), forming a cross-feedback structure.

[0039] When the voltages at nodes X and Y decrease during the comparison phase, the gate voltages of MN3 and MN4 decrease accordingly, leading to an increase in their channel resistance and significantly slowing down the discharge rate of MN1 and MN2 to nodes X and Y. This "discharge deceleration" effect directly weakens the intensity of voltage surges, suppressing kickback noise coupled to the input nodes through parasitic capacitance at its source.

[0040] 2. Improve comparison accuracy and speed: During the comparison phase, if the input signal INP > INN, the discharge current of MN1 is greater than that of MN2, and the voltage drop rate at node X is faster than that at node Y. At this time, the channel resistance increase of MN4 (gate connected to X) is greater than that of MN3 (gate connected to Y), further slowing down the discharge rate of node Y and "amplifying" the voltage difference between X and Y.

[0041] This active amplification of the voltage difference reduces the difficulty of decision-making in the subsequent regeneration stage, not only improving the comparison accuracy (especially for small input signals), but also accelerating the positive feedback response speed of the latch and shortening the overall comparison time.

[0042] 3. Reduce power consumption: The cross-coupled structure has an "adaptive cutoff" characteristic: when node X discharges to a voltage below the threshold voltage of MN4, MN4 is turned off, and the discharge process of node Y is terminated prematurely; while node X continues to discharge to GND.

[0043] Compared to the traditional design where both nodes need to be fully discharged to GND, the early cutoff of node Y reduces unnecessary charge consumption, thus reducing circuit power consumption while ensuring the comparison function.

[0044] Comparison and advantages of pre-amplification stage with traditional technology: Traditional techniques (taking a dual-tailed comparator as an example): The input transistors and output nodes are separated by transistors (such as MN4 and MN7). Although this avoids the direct impact of abrupt changes in the output node on the input node, the fast discharge speed of nodes X and Y makes them prone to kickback noise. There is no dedicated offset cancellation module. The offset mainly stems from the size mismatch of the input transistors, which requires increasing the transistor size to alleviate the problem, resulting in increased area overhead.

[0045] Pre-amplification stage of this invention: It includes a reset module I, an offset cancellation module, a cross-coupling module, and a pre-amplification module. The core innovation lies in the cross-coupling modules (MN3, MN4) and the offset cancellation modules (S3-S7, C1, C2), which address the shortcomings of traditional technologies from a structural and process perspective through a four-stage operation mechanism of "reset-offset cancellation-sampling-comparison".

[0046] Significantly suppresses kickback noise: In traditional technologies, rapid discharge at nodes X and Y causes voltage fluctuations at the input nodes (kickback noise). In this invention, as the voltages at nodes X and Y decrease during the comparison phase, the cross-coupling module increases the channel resistance of MN3 and MN4, significantly reducing the discharge rate and thus suppressing kickback noise (as shown in the simulation comparison in Figure 3).

[0047] Effectively reduces offset voltage: Traditional technologies rely on increasing transistor size to reduce offset, which is costly. This invention uses an offset cancellation module to store the offset voltage of the input pair transistors (MN1, MN2) in C1 and C2 during the offset cancellation stage. The offset is then canceled in subsequent stages, eliminating the need for additional size increases and significantly reducing the offset voltage (as shown in the simulation comparison in Figure 5).

[0048] Improve comparison accuracy and speed: In traditional technologies, the discharge rate difference between nodes X and Y is small, and the voltage difference increases slowly. In this invention, the cross-coupling module expands the discharge rate difference (e.g., when INP>INN, node X discharges faster, the channel resistance of MN4 increases more, and the discharge of node Y is delayed), increasing the voltage difference between X and Y, thereby improving accuracy and subsequent latching speed.

[0049] Reduce power consumption: In traditional technologies, both X and Y nodes are fully discharged to GND, resulting in high power consumption. In this invention, when node X is fully discharged, node Y stops discharging because MN4 is turned off, reducing unnecessary energy consumption.

[0050] Comparison and advantages of regenerative and traditional technologies.

[0051] Traditional techniques: The regenerative stage of the single-tailed comparator is directly stacked above the input transistor pair. The sudden change in the output node is coupled to the input node through the gate-drain parasitic capacitance, which aggravates the kickback noise. The reset mechanism is simple, but the reset of the critical node is incomplete, which can easily affect the comparator stability.

[0052] Regeneration stage of this invention: It includes a reset module II (MN10-MN13), an enable module (MP3), and a latch comparator module (MN8, MN9, MP4-MP7). Through independent reset module and enable control, combined with the output signal of the pre-amplification stage, more stable comparison and latching are achieved.

[0053] Enhance job stability: Traditional techniques often result in incomplete resets, leaving residual charge that affects comparison results. The reset module II of this invention, under the control of CLK3, thoroughly discharges critical nodes such as OUTP and OUTN to GND, ensuring a consistent starting point for each comparison and improving stability.

[0054] Reduce reliance on the pre-amplification stage: Traditional single-tail comparators need to process minute input signals and are susceptible to noise interference. In this invention, the regenerator stage receives the amplified X and Y node signals from the pre-amplifier stage, and MP6 and MP7 adjust the charging current according to the X and Y voltage difference, enabling OUTP and OUTN to be quickly distinguished and reducing the impact of noise.

[0055] High-efficiency latching and low latency: The latch comparison module shortens the latch time through a positive feedback mechanism (such as rapidly pulling OUTP up to VDD after it exceeds the threshold, while simultaneously pulling OUTN down to GND), and improves the overall comparison speed in conjunction with the voltage difference amplification of the pre-amplification stage.

[0056] Compared to traditional technologies, this invention provides a stable and amplified input signal to the regenerator stage by suppressing kickback noise, eliminating offset, and optimizing discharge characteristics through a pre-amplification stage. The regenerator stage, in turn, rapidly outputs the comparison result through complete reset and efficient latching. The synergistic effect of these two technologies reduces noise, offset, and power consumption while improving comparison accuracy, speed, and robustness (e.g., ...). Figure 4 As shown, the kickback noise varies little under different process angles.

[0057] In the pre-amplification stage of this invention, a new cross-coupling module (MN3, MN4) is added. Its gate is connected to nodes Y and X respectively (MN3's gate is connected to the drain of MN2, i.e., node Y; MN4's gate is connected to the drain of MN1, i.e., node X), and the source is connected to the drain of MN5. This structure forms a "voltage-resistance" dynamic feedback mechanism. When the voltages at nodes X and Y decrease, the channel resistances of MN3 and MN4 increase as the gate voltage decreases, directly slowing down the discharge rate and suppressing kickback noise from the source (as shown in the simulation in Figure 3, the kickback noise amplitude of this invention is much lower than that of traditional technology).

[0058] If INP>INN, node X discharges faster (lower voltage), causing the channel resistance of MN4 to increase more than that of MN3, further delaying the discharge of node Y, widening the voltage difference between X and Y, and significantly improving the comparison accuracy and subsequent latching speed.

[0059] When node X is fully discharged to GND, MN4 is turned off, and node Y stops discharging to avoid unnecessary power consumption (in traditional technology, node Y will continue to discharge to GND).

[0060] This module breaks through the traditional mindset of "isolation-type noise reduction" and forms a positive feedback mechanism of "discharge rate adaptive control" through cross-coupling. It combines noise suppression, accuracy improvement and power consumption reduction, achieving a "three birds with one stone" technical effect, which is an important innovation in the working principle of dynamic comparators.

[0061] This invention divides the complete cycle into four stages: "reset - offset elimination - sampling - comparison". Each stage precisely controls the module's operating state through clock signals (CLK1, CLK2, CLK3). Reset phase: The key nodes (X, Y, OUTP, OUTN, etc.) of the pre-amplification stage and regeneration stage are reset to VDD or GND respectively to ensure that the starting point of each comparison is consistent.

[0062] Offset elimination stage: The offset voltage is extracted and stored separately in preparation for subsequent cancellation.

[0063] Sampling stage: The input signal is coupled with the stored offset voltage to achieve "calibrated signal input".

[0064] Comparison phase: The cross-coupled module and the regenerator work together to complete signal amplification and latching.

[0065] This phased and refined control embeds "calibration" into the dynamic workflow, avoiding the inefficiency of "separation of calibration and comparison" in traditional technology. It enables the comparator to have low offset characteristics while operating at high speed, which is an important optimization for the timing design of dynamic comparators.

[0066] The pre-amplification stage of this invention incorporates a dedicated offset cancellation module (S3-S7, C1, C2) that achieves precise calibration through a "store-cancel" mechanism. Offset storage stage: During the "offset elimination stage", S3 and S4 are closed, the gate of the input pair transistors is connected to the common-mode level VCM, and during the discharge of nodes X and Y, the offset voltages of MN1 and MN2 (caused by size mismatch) are stored in capacitors C1 and C2.

[0067] Dynamic cancellation stage: During the "sampling stage", S1 and S2 are closed, and the input signals INP and INN are coupled to the gate through the capacitor, so that the gate voltage of MN1 is "V1+INP-VCM" and the gate voltage of MN2 is "V2+INN-VCM" (V1 and V2 are the stored offset voltages), realizing real-time offset cancellation (as shown in the simulation of Figure 5, the average offset voltage of the present invention is much lower than that of the traditional technology).

[0068] This module abandons the traditional approach of "hardware redundancy compensation" and uses capacitors to store offset voltage and dynamically cancel it out. It achieves effective elimination of offset voltage without increasing transistor size, balancing accuracy and area efficiency. This is a paradigm innovation in offset handling mechanisms.

[0069] The core of this invention lies in the fact that, through the dynamic control mechanism of the cross-coupling module, the precise calibration scheme of the offset elimination module, the four-stage refined operation process, and the collaborative optimization of the two-level modules, the pain points of traditional dynamic comparators, such as high kickback noise, high offset voltage, slow speed, and high power consumption, are systematically solved.

[0070] Example 1: like Figure 2 As shown, this embodiment provides a low-kickback, low-offset dynamic comparator with cross-coupled transistors, including a pre-amplification stage and a regeneration stage; The input of the preamplifier stage is connected to the differential input signal, and the output is connected to the input of the regenerator stage. During the comparison stage, the preamplifier stage amplifies the minute differences in the differential input signal to reduce the time it takes for the regenerator stage to obtain a stable output result. After receiving the amplified differential signal, the regenerator stage pulls the two differential signals high to VDD and low to GND respectively under the positive feedback of the latch, thereby completing one comparison.

[0071] The pre-amplification stage includes: reset module I, offset cancellation module, cross-coupling module, and pre-amplification module.

[0072] Reset module I consists of MN6, MN7, MP1, and MP2, and is used to reset the critical nodes of the pre-amplification stage to GND or VDD. The sources of MN6 and MN7 are connected to GND; the gates of MN6 and MN7 are connected to the clock signal CLK1; the drain of MN6 is connected to the gate of MN1, and the drain of MN7 is connected to the gate of MN2; the gates of MP1 and MP2 are connected to the clock signal CLK2, and their sources are connected to VDD; the drain of MP1 is connected to the drain of MN1, and the drain of MP2 is connected to the drain of MN2.

[0073] The offset cancellation module consists of S3, S4, S5, S6, S7 and C1, C2, used to store the offset voltage. The first terminals of S3 and S4 are connected to the common-mode level VCM; the second terminal of S3 is connected to the first terminal of C1, and the second terminal of S4 is connected to the first terminal of C2; the first terminal of S5 is connected to the drain of MP1, and the first terminal of S6 is connected to the drain of MP2; the first terminal of S7 is connected to the source of MN1 and the drain of MN3, and the second terminal is connected to the source of MN2 and the drain of MN4; the second terminal of C1 is connected to the second terminal of S5 and the drain of MN6, and the second terminal of C2 is connected to the second terminal of S6 and the drain of MN7.

[0074] The cross-coupling module consists of MN3 and MN4, which are used to suppress kickback noise, improve comparison accuracy and speed, and reduce power consumption. The gate of MN3 is connected to the drain of MN2, and the gate of MN4 is connected to the drain of MN1. The sources of MN3 and MN4 are connected to the drain of MN5.

[0075] The pre-amplification module consists of S1, S2, MN1, MN2, MN3, MN4, MN5, MP1, and MP2, and is used to amplify the small voltage difference of the differential signal. The first terminal of S1 is connected to the first differential input signal INP, and the first terminal of S2 is connected to the second differential input signal INN. The second terminal of S1 is connected to the first terminal of C1, and the second terminal of S2 is connected to the first terminal of C2. The gate of MN1 is connected to the second terminal of C1, and the gate of MN2 is connected to the second terminal of C2. The source of MN1 is connected to the drain of MN3 and the first terminal of S7. The source of MN2 is connected to the drain of MN4 and the second terminal of S7. The gate of MN5 is connected to the clock signal CLK2, and the source is connected to GND.

[0076] The regeneration stage includes: reset module II, enable module, and latch comparator module.

[0077] Reset module II consists of MN10, MN11, MN12, and MN13, and is used to reset the critical nodes of the regeneration stage to GND. The gates of MN10, MN11, MN12, and MN13 are connected to the clock signal CLK3, and the sources are connected to GND. The drain of MN10 is connected to the drain of MN8, the drain of MN11 is connected to the drain of MN9, the drain of MN12 is connected to the drain of MP4, and the drain of MN13 is connected to the drain of MP5.

[0078] The enable module consists of MP3, which is used to control the operating state of the regenerator; the gate of MP3 is connected to the clock signal CLK3, the source is connected to VDD, and the drain is connected to the source of MP4 and MP5.

[0079] The latch comparator module consists of MN8, MN9, MP4, MP5, MP6, and MP7, and is used to perform comparator operations. The gate of MP6 is connected to the drain of MN1, and the gate of MP7 is connected to the drain of MN2. The source of MP6 is connected to the drain of MP4, and the source of MP7 is connected to the drain of MP5. The drain of MP6 is connected to the drain of MN8, and the drain of MP7 is connected to the drain of MN9. The gate of MN8 is connected to the gate of MP4 and the drain of MP7. The gate of MN9 is connected to the gate of MP5 and the drain of MP6.

[0080] Example 2: Based on the low kickback low offset dynamic comparator with cross-coupled transistors provided in Embodiment 1, this embodiment provides a method for operating the low kickback low offset dynamic comparator with cross-coupled transistors.

[0081] A complete operating cycle of a comparator consists of the following four stages: reset, offset elimination, sampling, and comparison; During the reset phase of the comparator, MN5 is turned off, MP1 and MP2 are turned on, and nodes X and Y are charged to VDD; MN6, MN7, MN10, MN11, MN12, and MN13 are turned on, and the gates of MN1 and MN2, the sources of MP6 and MP7, and nodes OUTP and OUTN are discharged to GND. During the offset cancellation phase of the comparator, S3 and S4 are closed, and the first terminals of C1 and C2 are connected to the common-mode signal VCM; MN5 is turned on, MN6 and MN7 are turned off, S5 and S6 are closed, node X is connected to the gate of MN1, node Y is connected to the gate of MN2, and discharge begins; after the discharge is completed, the offset voltage is stored on capacitors C1 and C2, and the gate voltage of MN1 at this time is set to V1, and the gate voltage of MN2 is set to V2; the value of V1-V2 is the value of the offset voltage.

[0082] During the sampling phase, nodes X and Y are charged to VDD again; S7 is closed to make the source voltages of MN1 and MN2 the same, thereby avoiding the introduction of additional offset voltage; S1 and S2 are closed, at which time the gate voltage of the input pair transistor MN1 is V1+INP-VCM, and the gate voltage of MN2 is V2+INN-VCM.

[0083] During the comparison phase, MN5 is turned on, MP1 and MP2 are turned off, and nodes X and Y begin to discharge. Since node X is connected to the gate of MN4 and node Y is connected to the gate of MN3, the channel resistance of MN3 and MN4 gradually increases as the voltages of X and Y decrease, significantly slowing down the discharge rate of MN1 and MN2, thereby significantly suppressing kickback noise. If INP > INN, the discharge current of MN1 exceeds the discharge current of MN2, keeping the voltage of node X lower than the voltage of node Y. Therefore, the channel resistance of MN4 is larger than that of MN3, further slowing down the discharge rate of node Y. This increases the voltage difference between nodes X and Y, thereby improving the efficiency of subsequent latches. Operating speed and overall comparator accuracy; when node X discharges to a voltage lower than the threshold voltage of MN4, MN4 turns off, causing node Y to stop discharging, while node X continues to discharge to GND. The incomplete discharge of node Y reduces the power consumption of the comparator; since X and Y are both input nodes of the regenerative stage, the voltage of node X remains lower than the voltage of node Y, so the charging current of MP6 exceeds the charging current of MP7, causing the voltage rise rate of node OUTP to be faster than that of node OUTN; after the voltage of node OUTP exceeds the threshold, the positive feedback mechanism of the latch will quickly pull node OUTP high to VDD, while pulling node OUTN down to GND, thus completing a complete operating cycle.

[0084] Example 3: This embodiment verifies the effectiveness of the present invention through simulation experiments, as detailed below: like Figure 3 As shown, the input node of a traditional dual-tailed dynamic comparator is significantly affected by kickback noise during the comparison phase, while the present invention significantly suppresses kickback noise.

[0085] like Figure 4 As shown, the kickback noise of the present invention changes very little under five different process angles, which indicates that the present invention has good robustness.

[0086] like Figure 5 As shown, the results of Monte Carlo simulation with a sample size of 400 demonstrate that the present invention significantly reduces the offset voltage.

[0087] The present invention and its embodiments have been described above. This description is not restrictive, and the embodiments shown throughout are only one of the embodiments of the present invention. The actual structure is not limited to this. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present invention, they should all fall within the protection scope of the present invention.

Claims

1. A low kickback and low offset dynamic comparator with cross-coupled pair, comprising a pre-amplification stage and a regeneration stage, characterized in that: the pre-amplification stage comprises: a reset module I for resetting key nodes of the pre-amplification stage to GND or VDD; an offset cancellation module for storing an offset voltage; a cross-coupling module for suppressing kickback noise, improving comparison accuracy and speed, and reducing power consumption; a pre-amplification module for amplifying a small voltage difference of a differential signal; the regeneration stage comprises: a reset module II for resetting key nodes of the regeneration stage to GND; an enable module for controlling the working state of the regeneration stage; a latch comparison module for performing a comparison operation; the reset module I is composed of MN6, MN7, MP1, and MP2; the offset cancellation module is composed of S3, S4, S5, S6, S7, C1, and C2; the cross-coupling module is composed of MN3 and MN4; the pre-amplification module is composed of S1, S2, MN1, MN2, MN3, MN4, MN5, MP1, and MP2; the reset module II is composed of MN10, MN11, MN12, and MN13; the enable module is composed of MP3; the latch comparison module is composed of MN8, MN9, MP4, MP5, MP6, and MP7.

2. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, In the reset module I, the sources of MN6 and MN7 are connected to GND; the gates of MN6 and MN7 are connected to a clock signal CLK1; the drain of MN6 is connected to the gate of MN1, and the drain of MN7 is connected to the gate of MN2; the gates of MP1 and MP2 are connected to a clock signal CLK2, and the sources are connected to VDD; the drain of MP1 is connected to the drain of MN1, and the drain of MP2 is connected to the drain of MN2.

3. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, In the offset cancellation module, the first ends of S3 and S4 are connected to a common mode voltage VCM; the second end of S3 is connected to the first end of C1, and the second end of S4 is connected to the first end of C2; the first end of S5 is connected to the drain of MP1, and the first end of S6 is connected to the drain of MP2; the first end of S7 is connected to the source of MN1 and the drain of MN3, and the second end is connected to the source of MN2 and the drain of MN4; the second end of C1 is connected to the second end of S5 and the drain of MN6, and the second end of C2 is connected to the second end of S6 and the drain of MN7.

4. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, In the cross-coupling module, the gate of MN3 is connected to the drain of MN2, and the gate of MN4 is connected to the drain of MN1; the sources of MN3 and MN4 are connected to the drain of MN5.

5. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, In the pre-amplification module, the first end of S1 is connected to a first differential input signal INP, and the first end of S2 is connected to a second differential input signal INN; the second end of S1 is connected to the first end of C1, and the second end of S2 is connected to the first end of C2; the gate of MN1 is connected to the second end of C1, and the gate of MN2 is connected to the second end of C2; the source of MN1 is connected to the drain of MN3 and the first end of S7, and the source of MN2 is connected to the drain of MN4 and the second end of S7; the gate of MN5 is connected to a clock signal CLK2, and the source is connected to GND.

6. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, The reset module II, MN10, MN11, MN12, MN13 gate connects clock signal CLK3, source connects GND; MN10 drain connects MN8 drain, MN11 drain connects MN9 drain; MN12 drain connects MP4 drain, MN13 drain connects MP5 drain.

7. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, The enable module, MP3 gate connects clock signal CLK3, source connects VDD, drain connects MP4, MP5 source.

8. The low kick-back, low-offset dynamic comparator with cross-coupled pair transistors of claim 1, wherein, The latch comparison module, MP6 gate connects MN1 drain, MP7 gate connects MN2 drain; MP6 source connects MP4 drain, MP7 source connects MP5 drain; MP6 drain connects MN8 drain, MP7 drain connects MN9 drain; MN8 gate connects MP4 gate, MP7 drain; MN9 gate connects MP5 gate, MP6 drain.

9. The method of operating a low kick-back, low-offset dynamic comparator with cross-coupled pair transistors as recited in any of claims 1-8, wherein, Comprise: One complete running cycle of comparator includes reset, offset elimination, sampling, comparison; When the comparator is in the reset stage, MN5 is off, node X, Y is charged to VDD; MN1 and MN2 gate, MP6 and MP7 source, node OUTP, OUTN is discharged to GND; When the comparator is in the offset elimination stage, S3, S4 is closed, at this time, the input pair of MN1, MN2 gate voltage is common mode voltage VCM; MN5 is on, MN6, MN7 is off, node X, Y starts to discharge; After the discharge is completed, the offset voltage is stored on the capacitor C1, C2, and the MN1 gate voltage at this time is V1, and the MN2 gate voltage is V2; In the double tail comparator, the main source of offset is the input pair in the preamplifier stage, that is, MN1, MN2, so only the offset elimination operation is needed in the preamplifier stage; When the comparator is in the sampling stage, MN5 is off, node X, Y is charged to VDD; S7 is closed, so that the source voltage of MN1, MN2 is the same, so as to avoid introducing additional offset voltage; S1, S2 is closed, at this time, the input pair of MN1 gate voltage is V1+INP-VCM, MN2 gate voltage is V2+INN-VCM; When the comparator is in the comparison stage, MN5 is on, if INP>INN, then the discharge current of MN1 exceeds the discharge current of MN2, so that the X node voltage remains lower than Y node; Since X and Y are the input nodes of the regeneration stage at the same time, the charging current of MP6 exceeds the charging current of MP7, which causes the OUTP node voltage to rise faster than the OUTN node; After OUTP exceeds the threshold value, the positive feedback mechanism of the latch will quickly pull OUTP high to VDD, and at the same time, OUTN is pulled down to GND, thus completing a complete running cycle.

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