Processor and data processing method

Abstract

The invention discloses a processor and a data processing method, and relates to the technical field of data processing.The processor comprises a processor core, a first-level cache unit and a data rapid obtaining module; the processor core is used for obtaining an instruction for accessing the first-level cache unit and determining the number of times of accessing the first-level cache unit based on the access data volume; the instruction and the number of times are sent to the data rapid acquisition module; the data rapid acquisition module is used for receiving instructions and times sent by the processor core; generating a virtual cache block based on the number of times and an access initial address in the instruction; the virtual cache block comprises a plurality of cache blocks which are continuous with the target cache block corresponding to the access head address; and based on the instruction, synchronously accessing a plurality of cache blocks in the virtual cache block, so as to synchronously write the first target data into the plurality of cache blocks when the instruction is a storage instruction, or synchronously read the second target data from the plurality of cache blocks when the instruction is a loading instruction, and send the second target data to the processor core.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a processor and a data processing method. BACKGROUND

[0002] In a conventional scheme, for a processor core to continuously access a cache unit, data cannot be quickly returned from the cache or written to the cache. For example, the size of a cache line in the cache is generally 64 bytes, and if the processor core needs to read back 256 bytes of data from the cache, it needs to initiate four consecutive accesses to the cache, which is a great consumption of hardware resources and interface bandwidth of the processor core, and the data write / read time is also very long. SUMMARY

[0003] Therefore, embodiments of the present application provide a processor and a data processing method.

[0004] According to a first aspect of the present application, embodiments of the present application provide a processor, comprising: a processor core, a first-level cache unit, and a data fast acquisition module; The processor core is configured to obtain an instruction for accessing the first-level cache unit, the instruction comprising an instruction type, an access starting address, and an access data amount; determine a number of times of accessing the first-level cache unit based on the access data amount; determine a first number of valid periods of the instruction based on an access data bit width of the processor core and the access data amount; extend a valid duration of the instruction based on the first number of valid periods; send the instruction and the number of times to the data fast acquisition module; and when it is determined that the instruction is a storage instruction based on the instruction type, send first target data corresponding to the instruction to the data fast acquisition module within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of valid periods of the instruction based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of valid periods; and when it is determined that the instruction is a storage instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration; and generate a virtual cache block based on the number of times and the access starting address in the instruction; the virtual cache block comprising a plurality of cache blocks continuous with a target cache block corresponding to the access starting address; synchronously access the plurality of cache blocks in the virtual cache block based on the instruction, to synchronously write the first target data to the plurality of cache blocks when the instruction is a storage instruction, or synchronously read second target data from the plurality of cache blocks when the instruction is a load instruction, and send the second target data to the processor core.

[0005] Optionally, the processor core is further configured to receive the second target data sent by the data fast acquisition module within an extended valid duration when it is determined that the instruction is a store instruction based on the instruction type.

[0006] Optionally, the processor core is configured to determine the first number of cycles in which the instruction is valid based on a write data width of the processor core and the access data amount if it is determined that the instruction is a store instruction based on the instruction type, and determine the first number of cycles in which the instruction is valid based on a read data width of the processor core and the access data amount if it is determined that the instruction is a load instruction based on the instruction type.

[0007] Optionally, the data fast acquisition module comprises an access pattern analysis module, a core data write control module, a data cache module, a core data return control module, and a first cache unit access control module. The access pattern analysis module is configured to receive the instruction and the number of times sent by the processor core, send the instruction to the core data write control module and send a first control signal to the first cache unit access control module when it is determined that the instruction is a store instruction based on the instruction type, and send the instruction to the core data return control module and send a second control signal to the first cache unit access control module when it is determined that the instruction is a load instruction based on the instruction type, wherein the first control signal and the second control signal comprise the number of times and the access start address. The core data write control module is configured to determine the second number of cycles in which the instruction is valid based on the access data amount in the instruction and an access data width of the data fast acquisition module, extend the valid duration of the instruction based on the second number of cycles, receive the first target data sent by the processor core within the extended valid duration, and send the first target data to the data cache module for caching. The first cache unit access control module is configured to receive the first control signal or the second control signal, generate a virtual cache block based on the number of times and the access start address in the first control signal or the second control signal, wherein the virtual cache block comprises a plurality of cache blocks continuous to a target cache block corresponding to the access start address, and synchronously access the plurality of cache blocks in the virtual cache block based on the first control signal or the second control signal to synchronously write the first target data in the data cache module into the plurality of cache blocks or synchronously read the second target data from the plurality of cache blocks and send the second target data to the data cache module for caching. The core data return control module is configured to determine the second number of cycles in which the instruction is valid based on the access data amount in the instruction and an access data width of the data fast acquisition module, extend the valid duration of the instruction based on the second number of cycles, and send the second target data in the data cache module to the processor core within the extended valid duration.

[0008] Optionally, the core data write control module is configured to determine the second number of valid periods of the instruction based on the access data amount in the instruction and a write data bit width of the core data write control module.

[0009] Optionally, the core data return control module is configured to determine the second number of valid periods of the instruction based on the access data amount in the instruction and a read data bit width of the core data return control module.

[0010] Optionally, the processor further comprises a level-1 cache unit, a level-2 cache unit, an optimal dynamic prefetch module, and a global prefetch control module. The optimal dynamic prefetch module is configured to, when monitoring that the processor core is executing an application, generate a data prefetch enable signal, send the data prefetch enable signal to the global prefetch control module, and divide cache spaces of the level-1 cache unit, the level-2 cache unit, and the level-3 cache unit into a plurality of sub-cache spaces, the plurality of sub-cache spaces comprising a non-prefetch cache sub-space, a sequential prefetch cache sub-space, a step prefetch cache sub-space, and a self-analysis prefetch cache sub-space; when monitoring that data in the sequential prefetch cache sub-space is accessed by the processor core, determine a first address corresponding to prefetched data based on a sequential prefetch mode, and send the first address to the global prefetch control module; when monitoring that data in the step prefetch cache sub-space is accessed by the processor core, determine a second address corresponding to prefetched data based on a step prefetch mode, and send the second address to the global prefetch control module; and when monitoring that data in the self-analysis prefetch cache sub-space is accessed by the processor core, determine a third address corresponding to prefetched data based on a self-analysis prefetch mode, and send the third address to the global prefetch control module. The global prefetch control module is configured to, based on the data prefetch enable signal, prefetch data of the first address, the second address, and the third address to corresponding sequential prefetch cache sub-spaces, step prefetch cache sub-spaces, and self-analysis prefetch cache sub-spaces in parallel.

[0011] Optionally, the optimal dynamic prefetch module is configured to, when monitoring that the processor core is executing an application, acquire a current temperature of the processor and a hardware resource occupancy rate of the processor; and generate the data prefetch enable signal when the current temperature is less than a temperature threshold and the hardware resource occupancy rate is less than an occupancy rate threshold.

[0012] Optionally, the optimal dynamic prefetch module comprises a prefetch enable judgment module, a cache division control module, a sequential prefetch control module, a step prefetch control module, and a self-analysis prefetch control module. The prefetch enable judgment module is configured to, when monitoring that the processor core is executing an application, acquire a current temperature of the processor and a hardware resource occupancy rate of the processor; and generate the data prefetch enable signal and send the data prefetch enable signal to the global prefetch control module when the current temperature is less than a temperature threshold and the hardware resource occupancy rate is less than an occupancy rate threshold. The cache partition control module is configured to divide the cache spaces of the first-level cache unit, the second-level cache unit and the third-level cache unit into a plurality of sub-cache spaces respectively. The sequential prefetch control module is configured to, when monitoring that the data of the sequential prefetch cache sub-space is accessed by the processor core, determine a first address corresponding to the prefetch data based on the sequential prefetch mode, and send the first address to the overall prefetch control module. The step prefetch control module is configured to, when monitoring that the data of the step prefetch cache sub-space is accessed by the processor core, determine a second address corresponding to the prefetch data based on the step prefetch mode, and send the second address to the overall prefetch control module. The self-analysis prefetch control module is configured to, when monitoring that the data of the self-analysis prefetch cache sub-space is accessed by the processor core, determine a third address corresponding to the prefetch data based on the self-analysis prefetch mode, and send the third address to the overall prefetch control module.

[0013] Optionally, the optimal dynamic prefetch module further comprises a hit rate statistical analysis module. The hit rate statistical analysis module is configured to statistically analyze the hit rates of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step prefetch cache sub-space and the self-analysis prefetch cache sub-space when the processor executes the application program. The cache partition control module is further configured to adjust the cache spaces of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step prefetch cache sub-space and the self-analysis prefetch cache sub-space based on the hit rates.

[0014] According to the second aspect of the present application, the embodiments of the present application provide a data processing method applied to a processor, the processor comprising a processor core, a first-level cache unit and a data fast acquisition module, the method comprising: The processor core acquires an instruction for accessing the first-level cache unit, the instruction comprising an instruction type, an access first address and an access data amount; determines a number of times of accessing the first-level cache unit based on the access data amount; determines a first number of periods of the instruction based on an access data bit width of the processor core and the access data amount; prolongs a valid time length of the instruction based on the first number of periods; sends the instruction and the number of times to the data fast acquisition module; and when determining that the instruction is a storage instruction based on the instruction type, sends first target data corresponding to the instruction to the data fast acquisition module within the prolonged valid time length. The data fast acquisition module receives the instruction and the number of times sent by the processor core; determines the number of second periods in which the instruction is valid based on the access data amount in the instruction and the access data bit width of the data fast acquisition module; prolongs the valid duration of the instruction based on the number of second periods; and when it is determined based on the instruction type in the instruction that the instruction is a storage instruction, receives the first target data sent by the processor core within the prolonged valid duration; and generates a virtual cache block based on the number of times and the access start address in the instruction; the virtual cache block comprises a plurality of cache blocks continuous to the target cache block corresponding to the access start address; based on the instruction, synchronously accesses the plurality of cache blocks in the virtual cache block to synchronously write the first target data into the plurality of cache blocks when the instruction is a storage instruction, or synchronously read the second target data from the plurality of cache blocks when the instruction is a load instruction, and sends the second target data to the processor core.

[0015] Optionally, the processor core receives the second target data sent by the data fast acquisition module within the prolonged valid duration when it is determined based on the instruction type that the instruction is a storage instruction.

[0016] Optionally, the processor core determines the number of first periods in which the instruction is valid based on the write data bit width of the processor core and the access data amount when it is determined based on the instruction type that the instruction is a storage instruction; and determines the number of first periods in which the instruction is valid based on the read data bit width of the processor core and the access data amount when it is determined based on the instruction type that the instruction is a load instruction.

[0017] Optionally, the data fast acquisition module comprises an access mode analysis module, a core data write control module, a data cache module, a core data return control module, and a first-level cache unit access control module. The access mode analysis module receives the instruction and the number of times sent by the processor core; and when it is determined based on the instruction type in the instruction that the instruction is a storage instruction, sends the instruction to the core data write control module and sends a first control signal to the first-level cache unit access control module, the first control signal comprising the number of times and the access start address; and when it is determined based on the instruction type in the instruction that the instruction is a load instruction, sends the instruction to the core data return control module and sends a second control signal to the first-level cache unit access control module, the second control signal comprising the number of times and the access start address. The core data write control module determines the number of second periods in which the instruction is valid based on the access data amount in the instruction and the access data bit width of the data fast acquisition module; prolongs the valid duration of the instruction based on the number of second periods; receives the first target data sent by the processor core within the prolonged valid duration; and sends the first target data to the data cache module for caching. The first cache unit access control module receives the first control signal or the second control signal; generates a virtual cache block based on the number of times and the access head address in the first control signal or the second control signal; the virtual cache block includes a plurality of cache blocks continuous with the target cache block corresponding to the access head address; the plurality of cache blocks in the virtual cache block are synchronously accessed based on the first control signal or the second control signal, so as to synchronously write the first target data in the data cache module into the plurality of cache blocks, or synchronously read the second target data from the plurality of cache blocks and send to the data cache module for caching; The core data return control module determines the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the access data bit width of the data fast acquisition module; and prolongs the effective duration of the instruction based on the second number of cycles, and sends the second target data in the data cache module to the processor core in the prolonged effective duration.

[0018] Optionally, the core data write control module determines the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the write data bit width of the core data write control module.

[0019] Optionally, the core data return control module determines the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the read data bit width of the core data return control module.

[0020] Optionally, the processor further comprises a second cache unit, a third cache unit, an optimal dynamic prefetching module and an overall prefetching control module; the method further comprises: The optimal dynamic prefetching module generates a data prefetching enable signal when monitoring that the processor core executes an application, sends the data prefetching enable signal to the overall prefetching control module, and divides the cache spaces of the first cache unit, the second cache unit and the third cache unit into a plurality of sub-cache spaces respectively, the plurality of sub-cache spaces including a non-prefetching cache sub-space, a sequential prefetching cache sub-space, a step prefetching cache sub-space and a self-analysis prefetching cache sub-space; when monitoring that the data in the sequential prefetching cache sub-space is accessed by the processor core, determines a first address corresponding to the prefetching data based on a sequential prefetching mode and sends the first address to the overall prefetching control module; when monitoring that the data in the step prefetching cache sub-space is accessed by the processor core, determines a second address corresponding to the prefetching data based on a step prefetching mode and sends the second address to the overall prefetching control module; when monitoring that the data in the self-analysis prefetching cache sub-space is accessed by the processor core, determines a third address corresponding to the prefetching data based on a self-analysis prefetching mode and sends the third address to the overall prefetching control module; The overall prefetching control module parallelly prefetches the data of the first address, the second address and the third address to the corresponding sequential prefetching cache sub-space, step prefetching cache sub-space and self-analysis prefetching cache sub-space based on the data prefetching enable signal.

[0021] Optionally, the optimal dynamic prefetching module obtains the current temperature of the processor and the hardware resource occupation rate of the processor when the processor core is executing the application program; and generates a data prefetching enabling signal when the current temperature is less than a temperature threshold and the hardware resource occupation rate is less than an occupation rate threshold.

[0022] Optionally, the optimal dynamic prefetching module comprises a prefetching enabling judgment module, a cache partitioning control module, a sequential prefetching control module, a step prefetching control module, and a self-analysis prefetching control module. The prefetching enabling judgment module obtains the current temperature of the processor and the hardware resource occupation rate of the processor when the processor core is executing the application program; and generates a data prefetching enabling signal and sends it to the overall prefetching control module when the current temperature is less than a temperature threshold and the hardware resource occupation rate is less than an occupation rate threshold. The cache partitioning control module divides the cache space of the first-level cache unit, the second-level cache unit, and the third-level cache unit into a plurality of sub-cache spaces, respectively. The sequential prefetching control module determines a first address corresponding to the prefetching data based on the sequential prefetching mode when it monitors that the data in the sequential prefetching cache sub-space is accessed by the processor core, and sends the first address to the overall prefetching control module. The step prefetching control module determines a second address corresponding to the prefetching data based on the step prefetching mode when it monitors that the data in the step prefetching cache sub-space is accessed by the processor core, and sends the second address to the overall prefetching control module. The self-analysis prefetching control module determines a third address corresponding to the prefetching data based on the self-analysis prefetching mode when it monitors that the data in the self-analysis prefetching cache sub-space is accessed by the processor core, and sends the third address to the overall prefetching control module.

[0023] Optionally, the optimal dynamic prefetching module further comprises a hit rate statistical analysis module; and the method further comprises: The hit rate statistical analysis module statistically analyzes the access hit rates of the non-prefetching cache sub-space, the sequential prefetching cache sub-space, the step prefetching cache sub-space, and the self-analysis prefetching cache sub-space when the processor is executing the application program. The cache partitioning control module adjusts the cache space of the non-prefetching cache sub-space, the sequential prefetching cache sub-space, the step prefetching cache sub-space, and the self-analysis prefetching cache sub-space based on the access hit rates.

[0024] The processor and the data processing method provided by the embodiment of the application, the number of times of accessing the first cache unit is determined by the processor core based on the accessed data amount, and the number of times and the instruction are sent to the fast acquisition module; the virtual cache block is generated by the data fast acquisition module based on the number of times and the access first address in the instruction; the plurality of cache blocks in the virtual cache block are synchronously accessed based on the instruction, so that the first target data is synchronously written into the plurality of cache blocks when the instruction is a storage instruction, or the second target data is synchronously read from the plurality of cache blocks when the instruction is a loading instruction, and is sent to the processor core; in this way, for the continuous access of the first cache unit required by the processor core, the processor core can realize the continuous address data access of the first cache unit by initiating an access instruction once, and the time period of the continuous address data access of the first cache unit can be greatly shortened, so that the rate of the processor core accessing the data of the first cache unit is greatly improved, the delay of the data access is reduced, and the performance of the processor cache system is improved; for the processor of the RISC-V architecture, the demand of the high-performance data center level application scenario can be met.

[0025] The above description is only a summary of the technical solutions of the application. In order to more clearly understand the technical means of the application, the application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following specific embodiments of the application are described. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a structure schematic diagram of a processor in the embodiment of the application; Figure 2 It is a structure schematic diagram of a data fast acquisition module in the embodiment of the application; Figure 3 It is a structure schematic diagram of another processor in the embodiment of the application; Figure 4 It is a structure schematic diagram of a best dynamic prefetch module in the embodiment of the application; Figure 5 It is a flow schematic diagram of a data access method in the embodiment of the application. DETAILED DESCRIPTION

[0027] In order to make the purposes, technical solutions and advantages of the embodiments of the application more clear, the technical solutions in the embodiments of the application will be described clearly and completely in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0028] The embodiment of the application provides a processor, such as Figure 1As shown, comprising: The processor core 11, the first cache unit 12 and the data fast acquisition module 13.

[0029] The processor core 11 is configured to acquire an instruction for accessing the first cache unit 12, the instruction including an instruction type, an access starting address and an access data amount; determine a number of times of accessing the first cache unit 12 based on the access data amount; determine a first number of periods in which the instruction is valid based on an access data bit width of the processor core 11 and the access data amount; extend a valid time length of the instruction based on the first number of periods; send the instruction and the number of times to the data fast acquisition module 13; and when it is determined that the instruction is a store instruction based on the instruction type, send first target data corresponding to the instruction to the data fast acquisition module 13 within the extended valid time length.

[0030] The data fast acquisition module 13 is configured to receive the instruction and the number of times sent by the processor core 11; determine a second number of periods in which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module 13; extend the valid time length of the instruction based on the second number of periods; when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core 11 within the extended valid time length; and generate a virtual cache block based on the number of times and the access starting address in the instruction; the virtual cache block including a plurality of cache blocks continuous to a target cache block corresponding to the access starting address; synchronously access the plurality of cache blocks in the virtual cache block based on the instruction, so as to synchronously write the first target data into the plurality of cache blocks when the instruction is a store instruction, or synchronously read second target data from the plurality of cache blocks when the instruction is a load instruction, and send the second target data to the processor core 11.

[0031] In the embodiment, the processor can be a processor based on RISC-V architecture, and the processor can be a central processing unit (CPU). The processor can include a plurality of processor cores 11, as shown in Figure 1 Each processor core 11 corresponds to a respective first cache unit 12 and a respective data fast acquisition module 13. The first cache unit 12 can be, for example, an L1 cache unit (L1 Cache). The instruction type can include a load (Load) type and a store (Store) type.

[0032] In the embodiment, the main function of the data fast acquisition module 13 is to realize fast acquisition and fast writing of data of the first cache unit 12 for continuous access of the first cache unit 12 by the processor core 11.

[0033] In the embodiment, the processor core 11 can include a LSU (Load / Store Unit). The LSU can obtain an instruction for accessing the L1 cache unit 12, and detect a number of times of continuous writing / reading of the L1 Cache by the processor core 11, visit_count = visit_num / cacheline_size. visit_num is an amount of access data for continuous access to the L1 Cache counted by the LSU, and cacheline_size is a capacity of a Cacheline in the L1 Cache, which is generally 64 bytes. The LSU unit configures the visit_count and the instruction to the data fast acquisition module 13, so that the data fast acquisition module 13 initiates an access to the L1 Cache to obtain the amount of access data or write the amount of access data to the L1 Cache at a time. For example, the size of the cached data in the Cacheline is generally 64 bytes, and the RISC-V Core access instruction needs to continuously access 256 bytes of data, that is, 256 bytes of data in the L1 Cache needs to be loaded back to the LSU unit. In the conventional scheme, the LSU initiates 4 times (256 / 64) of the Load instruction to the L1 Cache, and the next Load instruction is initiated after the completion of the previous Load instruction. In the scheme of the present application, the number of times of continuous reading of the L1 Cache is detected by the LSU, and the number of times and the first instruction are sent to the data fast acquisition module 13, and the data fast acquisition module 13 executes one instruction to realize continuous access to 256 bytes of data.

[0034] In the embodiment, the processor core 11 can also determine a number of first periods of validity of the instruction based on an access data bit width and an access data amount of the processor core 11 when obtaining the instruction for accessing the L1 cache unit 12, and extend a validity duration of the instruction based on the number of first periods of validity.

[0035] In some embodiments, for a Store instruction, the access data bit width of the processor core 11 is a write data bit width of the processor core. For a Load instruction, the access data bit width of the processor core 11 is a read data bit width of the processor core. When determining the number of first periods of validity of the instruction based on the access data bit width and the access data amount of the processor core 11, the processor core 11 is configured to determine the number of first periods of validity of the instruction based on a write data bit width and the access data amount of the processor core 11 if the instruction is determined to be a Store instruction based on the type of the instruction, and determine the number of first periods of validity of the instruction based on a read data bit width and the access data amount of the processor core 11 if the instruction is determined to be a Load instruction based on the type of the instruction. In this way, the validity duration corresponding to the instruction can be accurately extended.

[0036] In the embodiment, if the instruction is a store instruction, the processor core 11 can continuously send the first target data corresponding to the instruction to the data fast acquisition module 13 in the prolonged valid time length.

[0037] In some embodiments, if the instruction is a load instruction, since the processor core 11 sends the instruction to the data fast acquisition module 13, the processor core 11 is further configured to, when it is determined that the instruction is a store instruction based on the instruction type, receive the second target data sent by the data fast acquisition module 13 in the prolonged valid time length.

[0038] For example, if the write data bit width of the LSU is 128 bits, and the total data to be stored is 256 Bytes, the number of first cycles in which the instruction is determined to be valid is 256*8 / 128=16, and then the LSU continuously pulls up the write data valid signal for 16 cycles (in the conventional scheme, 16 write operations are initiated, and each write operation detects the write data valid signal for one cycle, while in the embodiment of the application, only one write operation is initiated, and one write operation detects the write data valid signal for 16 cycles), so that the valid time length of the instruction can be delayed, and the first target data corresponding to the access data amount can be continuously sent to the data fast acquisition module 13 in the prolonged valid time length.

[0039] For example, if the read data bit width of the LSU is 128 bits, and the total data to be loaded is 256 Bytes, the number of first cycles in which the instruction is determined to be valid is 256*8 / 128=16, and then the LSU continuously pulls up the read data valid signal for 16 cycles (in the conventional scheme, 16 read operations are initiated, and each read operation detects the read data valid signal for one cycle, while in the embodiment of the application, only one read operation is initiated, and one read operation continuously detects the read data valid signal for 16 cycles), so that the valid time length of the instruction can be delayed, and the second target data returned by the data fast acquisition module 13 can be received in the prolonged valid time length.

[0040] In the embodiment, for the Store instruction, since the processor core 11 continuously sends the first target data corresponding to the access data amount to the data fast acquisition module 13, and the data fast acquisition module 13 needs to quickly write the first target data into the level one cache unit 12, when the data fast acquisition module 13 acquires the instruction and the number of times sent by the processor core 11, the number of second periods in which the instruction is valid can be determined based on the access data amount in the instruction and the access data bit width of the data fast acquisition module 13. For example, the write data bit width of the data fast acquisition module 13 is 128 bits, and the total data to be stored is 256 bytes, so the number of second periods in which the instruction is valid is determined to be 256*8 / 128=16. Then the data fast acquisition module 13 needs to continuously pull up the write data valid signal for 16 periods, and continuously receive the first target data sent by the processor core 11. And based on the number of times and the access first address in the instruction, a virtual cache block is generated. Based on the instruction, a plurality of cache blocks in the virtual cache block are synchronously accessed to synchronously write the first target data into the plurality of cache blocks.

[0041] For example, the data fast acquisition module 13 divides the range of the virtual Cacheline according to the access start address store_begin_addr and the number of times visit_count. For example, store_begin_addr corresponds to Cache_line_2, and visit_count=3. Cache_line_2, Cache_line_3 and Cache_line_4 are divided into a virtual Cacheline. The data bit width of the L1 Cache is expanded to three times (visit_count=3), and synchronous access to all physical Cachelines in the virtual Cacheline is simultaneously completed in the L1 Cache. For example, the Cacheline is 64 bytes, and the default data interface of the L1 Cache is 128 bits. According to the traditional scheme, four clock cycles (64*8 / 128) are required to complete the access to one Cacheline. In the embodiment of the present application, the data interface of the L1 Cache is temporarily expanded to 128*3 (visit_count=3) for synchronous access to three physical Cachelines.In clock cycle 1, the synchronous access to [127:0] of Cacheline2-Cacheline4 is completed, the first data in the first target data is written into the virtual Cacheline, the first write data of the virtual Cacheline is completed {Cacheline4[127:0], Cacheline3[127:0], Cacheline2[127:0]}, in clock cycle 2, the synchronous access to [255:128] of Cacheline2-Cacheline4 is completed, the second data in the first target data is written into the virtual Cacheline, the second write data of the virtual Cacheline is completed {Cacheline4[255:128], Cacheline3[255:128], Cacheline2[255:128]}; in clock cycle 3, the synchronous access to [383:256] of Cacheline2-Cacheline4 is completed, the third data in the first target data is written into the virtual Cacheline, the third write data of the virtual Cacheline is completed {Cacheline4[383:256], Cacheline3[383:256], Cacheline2[383:256]}; in clock cycle 4, the synchronous access to [511:384] of Cacheline2-Cacheline4 is completed, the fourth data in the first target data is written into the virtual Cacheline, the fourth write data of the virtual Cacheline is completed {Cacheline4[511:384], Cacheline3[511:384], Cacheline2[511:384]}; thus, the synchronous access to the physical Cacheline in the virtual Cacheline is completed in 4 clock cycles, while the conventional scheme needs 12 clock cycles, therefore, compared with the conventional scheme, the embodiment of the application improves the data Store efficiency by 2 times for the Store scene.

[0042] For the Load instruction, since the second target data corresponding to the access data amount obtained from the first cache unit 12 needs to be continuously returned to the processor core 11, after the data fast acquisition module 13 obtains the instruction and the number of times sent by the processor core 11, the number of second periods in which the instruction is valid can be determined based on the access data amount in the instruction and the access data bit width of the data fast acquisition module 13. For example, the read data bit width of the data fast acquisition module 13 is 128 bits, and the total data to be loaded is 256 bytes, so the number of second periods in which the instruction is valid is determined to be 256x8 / 128 = 16. Then the data fast acquisition module 13 needs to continuously pull up the read data valid signal for 16 periods, so as to continuously return the second target data to the processor core 11. And a virtual cache block can be generated based on the number of times and the access starting address in the instruction. Based on the instruction, multiple cache blocks in the virtual cache block are synchronously accessed to synchronously read the second target data from the multiple cache blocks.

[0043] In some embodiments, the processor core 11 is further configured to, when it is determined based on the instruction type that the instruction is a store instruction, receive the second target data sent by the data fast acquisition module 13 within the extended valid time length.

[0044] For example, the data fast acquisition module 13 divides the range of the virtual Cacheline according to the access first address load_begin_addr and the number of times visit_count. For example, load_begin_addr corresponds to Cache_line_3, and visit_count=4. Cache_line_3, Cache_line_4, Cache_line_5 and Cache_line_6 are divided into a virtual Cacheline. The data bit width of the L1 Cache is expanded to 4 times (visit_count=4), and synchronous access to all physical Cachelines in the virtual Cacheline is simultaneously completed in the L1 Cache. For example, the Cacheline is 64 bytes, and the default data interface of the L1 Cache is 128 bits. The traditional scheme needs 4 clock cycles (64*8 / 128) to complete the access to one Cacheline. In the embodiment of the present application, the data interface of the L1 Cache is temporarily expanded to 128*4 (visit_count=4), and the access to four physical Cachelines is synchronously completed.In clock cycle 1, the synchronous access to [63:0] of Cacheline3-Cacheline6 is completed, and the first read data of the virtual Cacheline is {Cacheline6[127:0], Cacheline5[127:0], Cacheline4[127:0], Cacheline3[127:0]}; in clock cycle 2, the synchronous access to [255:128] of Cacheline3-Cacheline6 is completed, and the second read data of the virtual Cacheline is {Cacheline6[255:128], Cacheline5[255:128], Cacheline4[255:128], Cacheline3[255:128]}; in clock cycle 3, the synchronous access to [383:256] of Cacheline3-Cacheline6 is completed, and the third read data of the virtual Cacheline is {Cacheline6[383:256], Cacheline5[383:256], Cacheline4[383:256], Cacheline3[383:256]}; in clock cycle 4, the synchronous access to [511:384] of Cacheline3-Cacheline6 is completed, and the fourth read data of the virtual Cacheline is {Cacheline6[511:384], Cacheline5[511:384], Cacheline4[511:384], Cacheline3[511:384]}. Thus, the synchronous access to the physical Cacheline in the virtual Cacheline is completed in 4 clock cycles, while the conventional scheme needs 16 clock cycles, and thus, compared with the conventional scheme, the present proposal improves the data Load efficiency by 3 times for the Load scenario.

[0045] The processor provided by the embodiment of the application determines the number of times of accessing the first cache unit based on the amount of accessed data by the processor core, and sends the number of times and the instruction to the fast data acquisition module; the fast data acquisition module generates a virtual cache block based on the number of times and the access start address in the instruction; and synchronously accesses a plurality of cache blocks in the virtual cache block based on the instruction, to synchronously write the first target data into the plurality of cache blocks when the instruction is a storage instruction, or synchronously read the second target data from the plurality of cache blocks when the instruction is a loading instruction, and send the second target data to the processor core; in this way, for the processor core to perform continuous access to the first cache unit, the processor core can realize continuous address data access to the first cache unit by initiating one access instruction, and can greatly shorten the time period of the continuous address data access to the first cache unit, thereby greatly improving the data access rate of the processor core to the first cache unit, reducing the data access delay, and improving the performance of the processor cache system; for the processor of the RISC-V architecture, the demand of the high-performance data center level application scenario can be met.

[0046] In an optional embodiment, as shown in Figure 2 The fast data acquisition module includes an access mode analysis module, a core data write control module, a data cache module, a core data return control module, and a first cache unit access control module.

[0047] The access mode analysis module is configured to receive the instruction and the number of times sent by the processor core, and when it is determined that the instruction is a storage instruction based on the instruction type in the instruction, send the instruction to the core data write control module, and send a first control signal to the first cache unit access control module, the first control signal including the number of times and the access start address; when it is determined that the instruction is a loading instruction based on the instruction type in the instruction, send the instruction to the core data return control module, and send a second control signal to the first cache unit access control module, the second control signal including the number of times and the access start address.

[0048] The core data write control module is configured to determine the number of effective second cycles of the instruction based on the amount of accessed data in the instruction and the access data bit width of the fast data acquisition module, extend the effective duration of the instruction based on the number of effective second cycles, receive the first target data sent by the processor core in the extended effective duration, and send the first target data to the data cache module for caching.

[0049] The first cache unit access control module is configured to receive the first control signal or the second control signal, generate a virtual cache block based on the number of times and the access head address in the first control signal or the second control signal, the virtual cache block comprising a plurality of cache blocks continuous with the target cache block corresponding to the access head address, and perform synchronous access on the plurality of cache blocks in the virtual cache block based on the first control signal or the second control signal to synchronously write the first target data in the data cache module into the plurality of cache blocks or synchronously read the second target data from the plurality of cache blocks and send the second target data to the data cache module for caching.

[0050] The core data return control module is configured to determine the number of second cycles in which the instruction is valid based on the access data amount in the instruction and the access data bit width of the data fast acquisition module, and extend the valid time length of the instruction based on the number of second cycles, and send the second target data in the data cache module to the processor core in the extended valid time length.

[0051] In some embodiments, the core data write control module is configured to determine the number of second cycles in which the instruction is valid based on the access data amount in the instruction and the write data bit width of the core data write control module. In this way, for the access data bit width of the data fast acquisition module, when the instruction is a Store instruction, the write data bit width of the core data write control module is selected, so that a more accurate number of second cycles can be obtained.

[0052] In some embodiments, the core data return control module is configured to determine the number of second cycles in which the instruction is valid based on the access data amount in the instruction and the read data bit width of the core data return control module. In this way, for the access data bit width of the data fast acquisition module, when the instruction is a Load instruction, the read data bit width of the core data return control module is selected, so that a more accurate number of second cycles can be obtained.

[0053] In specific implementation, the access mode analysis module is configured to receive the instruction and the number of times sent by the processor core, and analyze whether the instruction is a Load instruction or a Store instruction, and analyze the access head address of the Load / Store instruction.

[0054] The data cache module has two functions. For a Store instruction, the module is configured to cache the first target data and the access head address continuously received by the core data write control module. For a Load instruction, the module is configured to cache the second target data read from the first cache unit, so as to continuously write the second target data by the core data return control module to the processor core.

[0055] The first cache unit access control module is the most core module of the data fast acquisition module. The first cache unit access control module is responsible for generating a virtual Cacheline, realizing that all physical Cachelines in the virtual Cacheline synchronously complete data reading and writing to the data cache module after a Load operation, realizing that all physical Cachelines in the virtual Cacheline synchronously complete data updating and synchronously writing corresponding first target data in the data cache module to the physical Cacheline after a Store operation, and thus greatly accelerating the reading and updating of L1 Cache data.

[0056] In the embodiment, the data fast acquisition module includes the access mode analysis module, the core data write control module, the data cache module, the core data return control module, and the first cache unit access control module, so that the functions of the data fast acquisition module can be realized through multiple modules, and the processing efficiency of the data fast acquisition module is improved.

[0057] In an optional embodiment, as shown in Figure 3 The processor further includes a second cache unit 14, a third cache unit 15, an optimal dynamic prefetch module 16, and an overall prefetch control module 17.

[0058] The optimal dynamic prefetch module 16 is configured to generate a data prefetch enable signal when it is monitored that the processor core 11 is executing an application, send the data prefetch enable signal to the overall prefetch control module 17, and divide the cache spaces of the first cache unit 12, the second cache unit 14, and the third cache unit 15 into multiple sub-cache spaces, respectively. The multiple sub-cache spaces include a non-prefetch cache sub-space, a sequential prefetch cache sub-space, a step prefetch cache sub-space, and a self-analysis prefetch cache sub-space. When it is monitored that data in the sequential prefetch cache sub-space is accessed by the processor core 11, a first address corresponding to the prefetch data is determined based on a sequential prefetch mode, and the first address is sent to the overall prefetch control module 17. When it is monitored that data in the step prefetch cache sub-space is accessed by the processor core 11, a second address corresponding to the prefetch data is determined based on a step prefetch mode, and the second address is sent to the overall prefetch control module 17. When it is monitored that data in the self-analysis prefetch cache sub-space is accessed by the processor core 11, a third address corresponding to the prefetch data is determined based on a self-analysis prefetch mode, and the third address is sent to the overall prefetch control module 17.

[0059] The overall prefetch control module 17 is configured to prefetch data of the first address, the second address, and the third address to corresponding sequential prefetch cache sub-spaces, step prefetch cache sub-spaces, and self-analysis prefetch cache sub-spaces in parallel based on the data prefetch enable signal.

[0060] In the embodiment, as shown in Figure 3As shown, if the processor has multiple processor cores 11, the multiple processor cores 11 share the second-level cache unit 14 and the third-level cache unit 15. The first-level cache unit 12 can be an L1 Cache, the second-level cache unit 14 can be an L2 Cache, and the third-level cache unit 15 can be an L3 Cache. The first-level cache unit 12, the data fast acquisition module 13, the second-level cache unit 14, the third-level cache unit 15, the optimal dynamic prefetching module 16, and the overall prefetching control module 17 constitute a cache system of the processor.

[0061] In some embodiments, the optimal dynamic prefetching module 16 is configured to, when monitoring that the processor core 11 is executing an application, acquire a current temperature of the processor and a hardware resource occupancy rate of the processor; and generate a data prefetching enabling signal when the current temperature is less than a temperature threshold and the hardware resource occupancy rate is less than an occupancy rate threshold.

[0062] In some embodiments, as shown in Figure 4 The optimal dynamic prefetching module includes a prefetching enabling judgment module, a cache partitioning control module, a sequential prefetching control module, a step prefetching control module, and a self-analysis prefetching control module.

[0063] The prefetching enabling judgment module is configured to, when monitoring that the processor core is executing an application, acquire a current temperature of the processor and a hardware resource occupancy rate of the processor; and generate a data prefetching enabling signal and send the data prefetching enabling signal to the overall prefetching control module when the current temperature is less than a temperature threshold and the hardware resource occupancy rate is less than an occupancy rate threshold.

[0064] The cache partitioning control module is configured to divide cache spaces of the first-level cache unit, the second-level cache unit, and the third-level cache unit into multiple sub-cache spaces, respectively.

[0065] The sequential prefetching control module is configured to, when monitoring that data in a sequential prefetching cache sub-space is accessed by the processor core, determine a first address corresponding to the prefetching data based on a sequential prefetching mode, and send the first address to the overall prefetching control module.

[0066] The step prefetching control module is configured to, when monitoring that data in a step prefetching cache sub-space is accessed by the processor core, determine a second address corresponding to the prefetching data based on a step prefetching mode, and send the second address to the overall prefetching control module.

[0067] The self-analysis prefetching control module is configured to, when monitoring that data in a self-analysis prefetching cache sub-space is accessed by the processor core, determine a third address corresponding to the prefetching data based on a self-analysis prefetching mode, and send the third address to the overall prefetching control module.

[0068] In some embodiments, as shown in Figure 4 The optimal dynamic prefetching module further includes a hit rate statistical analysis module.

[0069] The hit rate statistical analysis module is configured to count the access hit rates of the processor when executing the application program to the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step prefetch cache sub-space and the self-analysis prefetch cache sub-space.

[0070] The cache partition control module is further configured to adjust the cache spaces of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step prefetch cache sub-space and the self-analysis prefetch cache sub-space based on the access hit rates.

[0071] In a specific implementation, the function of the prefetch enable judgment module is to adaptively judge whether to enable the prefetch function by hardware. The two main bases for the judgment are as follows: one is the current temperature of the processor, and the other is the hardware resource occupation rate of the processor (obtained by analyzing the resources of the processor or the system resources). If the current core temperature of the processor has exceeded a threshold value, for example, the set threshold temperature is 65 degrees, and if the current core temperature has exceeded 65 degrees, the prefetch function will not be enabled, because the prefetch function will cause a large amount of additional calculation and analysis and data movement, and these operations will further increase the temperature of the processor and thus cause a physical risk of burning the processor. Meanwhile, if the current hardware resource occupation rate of the processor has exceeded a threshold value, the prefetch function will also not be enabled, because the prefetch will further increase the occupation of the hardware resources, and thus the benefits brought by the prefetch may not be able to make up for the performance decline caused by the shortage of the hardware resources, and it will not be worth the candle. Therefore, in the embodiment of the present application, only when the current temperature of the processor and the hardware resource occupation rate are both lower than the threshold values, the prefetch function will be adaptively enabled by hardware.

[0072] The function of the cache partition control module is to divide the cache of the first-level cache unit / second-level cache unit / third-level cache unit in space, implement different prefetching strategies in different partition spaces, and dynamically and adaptively adjust the space partition in real time according to the result of the hit rate statistical analysis module, so as to meet the best prefetching strategy under different software programs running on the processor. In the embodiment, the cache is divided into a no-prefetch cache subspace, a sequential prefetch cache subspace, a step prefetch cache subspace, and a self-analysis prefetch cache subspace. Each cache subspace (cache block) implements a corresponding prefetching strategy, and the hit rate statistical analysis module then performs statistics on the hit rate of each cache block under the current software application, and further adjusts the range of the cache block. The adjustment strategy is: for a cache block with a high hit rate, the cache range is expanded, and for a cache block with a low hit rate, the cache range is reduced, but each cache block has a minimum space range, and even if the hit rate is low, the range will not be adjusted to 0. Because the software running on the processor changes in real time, different scenarios of the best prefetching strategy under different software programs often occur. Therefore, it is necessary to avoid the scenario that the best prefetching strategy of the next software program is B, but the cache space is already using prefetching strategy A and cannot perceive the hit rate of prefetching strategy B.

[0073] The adjustment steps of the cache space are as follows: First, calculate the average hit rate hit_average = (hit0+hit1+hit2+hit3) / 4; wherein the parameter hit0 represents the hit rate of the cache under the current software program under the no-prefetch strategy; the parameter hit1 represents the hit rate of the cache under the current software program under the sequential strategy; the parameter hit2 represents the hit rate of the cache under the current software program under the step strategy; and the parameter hit3 represents the hit rate of the cache under the current software program under the self-analysis strategy. If hit0> hit_average, then the adjusted proportion of the cache space of the no-prefetch strategy: param_0= param_0_default+(hit0 / ( hit0+hit1+hit2+hit3)×50%); If hit0< hit_average, then the adjusted proportion of the cache space of the no-prefetch strategy: param_0= param_0_default-( hit1+hit2+hit3 / ( hit0+hit1+hit2+hit3)×50%); If hit1> hit_average, the proportion of the Cache space occupied by the adjusted sequential prefetch strategy: param_1= param_1_default+ (hit1 / (hit0+hit1+hit2+hit3) x 50%); If hit1< hit_average, the proportion of the Cache space occupied by the adjusted sequential prefetch strategy: param_1= param_1_default- (hit0+hit2+hit3 / (hit0+hit1+hit2+hit3) x 50%); If hit2> hit_average, the proportion of the Cache space occupied by the adjusted step prefetch strategy: param_2= param_2_default+ (hit2 / (hit0+hit1+hit2+hit3) x 50%); If hit2< hit_average, the proportion of the Cache space occupied by the adjusted step prefetch strategy: param_2= param_2_default- (hit0+hit1+hit3 / (hit0+hit1+hit2+hit3) x 50%); If hit3> hit_average, the proportion of the Cache space occupied by the adjusted self-analysis prefetch strategy: param_3= param_3_default+ (hit3 / (hit0+hit1+hit2+hit3) x 50%); If hit3< hit_average, the proportion of the Cache space occupied by the adjusted self-analysis prefetch strategy: param_3= param_3_default- (hit0+hit1+hit2 / (hit0+hit1+hit2+hit3) x 50%).

[0074] Wherein, param_0_default represents the default proportion of the no prefetch strategy in the Cache, such as 25%; param_1_default represents the default proportion of the sequential prefetch strategy in the Cache, such as 25%; param_2_default represents the default proportion of the step prefetch strategy in the Cache, such as 25%; param_3_default represents the default proportion of the self-analysis prefetch strategy in the Cache, such as 25%.

[0075] The function of the sequential prefetch control module controls the corresponding divided Cache block, and sets the prefetch strategy in the corresponding Cache block to a sequential prefetch mode, that is, after a Cacheline in the current Cache block is accessed by software, the next Cacheline is prefetched from a periphery (a next-level Cache) back to the current Cache block before the software initiates next access.

[0076] The function of the step prefetch control module controls the corresponding divided Cache block, and sets the prefetch strategy in the corresponding Cache block to a step prefetch mode, that is, after a Cacheline in the current Cache block is accessed by software, every step Cachelines are prefetched from a periphery (a next-level Cache) back to the current Cache block before the software initiates next access. Step is a step length.

[0077] The function of the self-analysis prefetch control module controls the corresponding divided Cache block, and sets the prefetch strategy in the corresponding Cache block to a self-analysis prefetch mode. In the embodiment, self-analysis is performed by recording N times of software-issued access addresses, constructing a first-order equation, predicting an address when N+1 times of access is performed, and performing prefetch of a Cacheline in advance.

[0078] The starting addresses of the N times of access are denoted as addr_0, addr_1,..., addr_N-1.

[0079] The recorded addr_minus_0 = addr_1- addr0; addr_minus_1 = addr_2- addr1;..., addr_minus_N-2 = addr_N-1- addr_N-2.

[0080] The first-order prediction formula is as follows: addr_minus_predict = Param_addr_0 × addr_minus_P + Param_addr_1; where the initial value of Param_addr_0 is 1, and the initial value of Param_addr_1 is 0. The software first performs the 0th access; then performs the 1st access to obtain addr_minus_0, that is, addr_minus_P = addr_minus_0; before performing the 2nd access, the addr_minus_predict is calculated according to the above formula, that is, addr_minus_predict = Param_addr_0 × addr_minus_P + Param_addr_1, and the addr_minus_1 = addr_2- addr1 is obtained according to the actual address of the 2nd access of the real access, and the parameters Param_addr_0_mdy and Param_addr_1_mdy are modified according to the difference between addr_minus_predict and addr_minus_1, so that the modified Param_addr_0_mdy × addr_minus_0 + Param_addr_1_mdy = addr_minus_1.

[0081] Before the software issues the 3rd access, the new addr_minus_predict is obtained by using Param_addr_0_mdy × addr_minus_1 + Param_addr_1_mdy, and the addr_minus_2 = addr_3- addr2 is obtained according to the actual address of the 3rd access of the real access, and the parameters Param_addr_0_mdy and Param_addr_1_mdy are modified according to the difference between addr_minus_predict and addr_minus_2, so that the modified Param_addr_0_mdy × addr_minus_1 + Param_addr_1_mdy = addr_minus_2.

[0082] Similarly, before the software issues the (N+1)th access, the new addr_minus_predict is obtained by using Param_addr_0_mdy × addr_minus_N-1 + Param_addr_1_mdy.

[0083] The addr_minus_predict + addr_N-1 is used as the predicted address of the Nth access, and the pre-fetch of the peripheral Cache is performed according to the predicted address.

[0084] The function of the hit rate statistical analysis module is to count the software access hit rate of each Cache block under different prefetch strategies under the current software application. An important statistical point of this module is to perceive the changes of the upper layer software application of the processor and count the period. In this embodiment, when the software program changes, the enable register of this module is configured to start the hit rate counting. The counting period can be configured by default or modified by the register. Meanwhile, a software program can be enabled multiple times to count the hit rate period to more accurately predict the different memory characteristics requirements in the same software program running period and to meet the different memory characteristics requirements of different software programs.

[0085] The function of the overall prefetch control module is to realize the overall control of data prefetching in the cache system and realize the parallel prefetch data update of multiple Cache blocks. The working process is as follows: According to the sequential prefetch control module, the step prefetch control module, and the self-analysis prefetch control module, the address of the predicted Cacheline is obtained. The overall prefetch control module obtains the predicted Cacheline address of different Cache blocks and queries the second cache unit / third cache unit (L2 Cache / L3 Cache) in parallel. If the corresponding predicted Cacheline is queried in the L2 Cache, the overall prefetch control module loads it into the L1 Cache in advance. If the corresponding predicted Cacheline is not queried in the L2 Cache but is in the L3 Cache, the corresponding predicted Cacheline is loaded into the L2 Cache and the L1 Cache in advance.

[0086] If the corresponding predicted Cacheline is not queried in the L3 Cache, the overall prefetch control module obtains the predicted Cacheline from the DDR, and then loads the corresponding predicted Cacheline into the L3 Cache, the L2 Cache, and the L1 Cache in advance.

[0087] It is worth noting that the overall prefetch control module updates the peripheral Cacheline data to the corresponding Cache block of the corresponding prefetch control module to realize the parallel data update of different Cache blocks.

[0088] In the embodiment, the optimal data prefetching scheme for L1 Cache, L2 Cache and L3 Cache of hardware under different software applications is realized, the dynamic self-adaptive adjustment of the optimal prefetching strategy under different software applications and different running periods of application software is realized, the real-time performance and accuracy of the data prefetching strategy of the processor are greatly improved, the overall control of the data prefetching in the cache system is realized, the parallel prefetching data update of multiple Cache blocks is realized, the rate of the processor core accessing the cache data is greatly improved, the delay of the data access is reduced, and the overall performance of the processor cache system is improved.

[0089] The embodiment of the application further provides a data processing method applied to the processor in any of the above embodiments, the processor comprising a processor core, a first cache unit and a data fast acquisition module, as shown in Figure 5 The method comprises the following steps: S501, the processor core acquires an instruction for accessing the first cache unit, the instruction comprising an instruction type, an access starting address and an access data amount; the number of times of accessing the first cache unit is determined based on the access data amount; the first number of periods in which the instruction is valid is determined based on the access data bit width of the processor core and the access data amount; the effective duration of the instruction is extended based on the first number of periods; the instruction and the number of times are sent to the data fast acquisition module; and when it is determined that the instruction is a storage instruction based on the instruction type, the first target data corresponding to the instruction is sent to the data fast acquisition module within the extended effective duration.

[0090] S502, the data fast acquisition module receives the instruction and the number of times sent by the processor core; the second number of periods in which the instruction is valid is determined based on the access data amount in the instruction and the access data bit width of the data fast acquisition module; the effective duration of the instruction is extended based on the second number of periods; and when it is determined that the instruction is a storage instruction based on the instruction type in the instruction, the first target data sent by the processor core is received within the extended effective duration; a virtual cache block is generated based on the number of times and the access starting address in the instruction; the virtual cache block comprises a plurality of cache blocks continuous to the target cache block corresponding to the access starting address; the plurality of cache blocks in the virtual cache block are synchronously accessed based on the instruction, so that the first target data is synchronously written into the plurality of cache blocks when the instruction is a storage instruction, or the second target data is synchronously read from the plurality of cache blocks when the instruction is a loading instruction, and is sent to the processor core.

[0091] The specific implementation manner is described in the above embodiment of the processor, which will not be repeated here.

[0092] The data processing method provided by the embodiment of the application comprises the following steps: determining, by a processor core, the number of times of accessing a first cache unit based on an access data volume, and sending the number of times and an instruction to a fast data acquisition module; generating, by the fast data acquisition module, a virtual cache block based on the number of times and an access start address in the instruction; synchronously accessing a plurality of cache blocks in the virtual cache block based on the instruction, so as to synchronously write first target data into the plurality of cache blocks when the instruction is a storage instruction, or synchronously read second target data from the plurality of cache blocks when the instruction is a loading instruction, and send the second target data to the processor core; in this way, for the processor core to perform continuous access to the first cache unit, the processor core can realize continuous address data access to the first cache unit by initiating one access instruction, and can greatly shorten the time period of the continuous address data access to the first cache unit, thereby greatly improving the data rate of the processor core accessing the first cache unit, reducing the data access delay, and improving the performance of the processor cache system; for the processor of the RISC-V architecture, the demand of the high-performance data center level application scenario can be met.

[0093] In an optional embodiment, when the processor core determines that the instruction is a storage instruction based on the instruction type, the processor core receives the second target data sent by the fast data acquisition module within an extended effective time length.

[0094] In an optional embodiment, when the processor core determines that the instruction is a storage instruction based on the instruction type, the processor core determines the number of first cycles in which the instruction is effective based on the write data bit width of the processor core and the access data volume; and when the processor core determines that the instruction is a loading instruction based on the instruction type, the processor core determines the number of first cycles in which the instruction is effective based on the read data bit width of the processor core and the access data volume.

[0095] In an optional embodiment, the fast data acquisition module comprises an access mode analysis module, a core data write control module, a data cache module, a core data return control module, and a first cache unit access control module.

[0096] The access mode analysis module receives the instruction and the number of times sent by the processor core; and when it is determined that the instruction is a storage instruction based on the instruction type in the instruction, the access mode analysis module sends the instruction to the core data write control module, and sends a first control signal to the first cache unit access control module, the first control signal comprising the number of times and an access start address; and when it is determined that the instruction is a loading instruction based on the instruction type in the instruction, the access mode analysis module sends the instruction to the core data return control module, and sends a second control signal to the first cache unit access control module, the second control signal comprising the number of times and the access start address.

[0097] The core data write control module determines a second number of cycles in which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module, extends a valid time length of the instruction based on the second number of cycles, receives the first target data sent by the processor core in the extended valid time length, and sends the first target data to the data cache module for caching.

[0098] The first cache unit access control module receives the first control signal or the second control signal, generates a virtual cache block based on a number of times in the first control signal or the second control signal and an access first address, the virtual cache block including a plurality of cache blocks continuous to a target cache block corresponding to the access first address, and performs synchronous access on the plurality of cache blocks in the virtual cache block based on the first control signal or the second control signal to synchronously write the first target data in the data cache module into the plurality of cache blocks or synchronously read the second target data from the plurality of cache blocks and send the second target data to the data cache module for caching.

[0099] The core data return control module determines a second number of cycles in which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module, and sends the second target data in the data cache module to the processor core in the extended valid time length.

[0100] In an optional embodiment, the core data write control module determines a second number of cycles in which the instruction is valid based on the access data amount in the instruction and a write data bit width of the core data write control module.

[0101] In an optional embodiment, the core data return control module determines a second number of cycles in which the instruction is valid based on the access data amount in the instruction and a read data bit width of the core data return control module.

[0102] In an optional embodiment, the processor further includes a second cache unit, a third cache unit, an optimal dynamic prefetch module and an overall prefetch control module, and the method further includes: The optimal dynamic prefetch module generates a data prefetch enable signal when it is monitored that the processor core is executing an application, sends the data prefetch enable signal to the overall prefetch control module, and divides cache spaces of the first cache unit, the second cache unit and the third cache unit into a plurality of sub-cache spaces, respectively, wherein the plurality of sub-cache spaces include a non-prefetch cache sub-space, a sequential prefetch cache sub-space, a step prefetch cache sub-space and a self-analysis prefetch cache sub-space; when it is monitored that data of the sequential prefetch cache sub-space is accessed by the processor core, a first address corresponding to the prefetch data is determined based on a sequential prefetch mode, and the first address is sent to the overall prefetch control module; when it is monitored that data of the step prefetch cache sub-space is accessed by the processor core, a second address corresponding to the prefetch data is determined based on a step prefetch mode, and the second address is sent to the overall prefetch control module; when it is monitored that data of the self-analysis prefetch cache sub-space is accessed by the processor core, a third address corresponding to the prefetch data is determined based on a self-analysis prefetch mode, and the third address is sent to the overall prefetch control module.

[0103] The overall prefetch control module prefetches data of the first address, the second address and the third address to corresponding sequential prefetch cache sub-spaces, step prefetch cache sub-spaces and self-analysis prefetch cache sub-spaces in parallel based on the data prefetch enable signal.

[0104] In an optional embodiment, the optimal dynamic prefetch module acquires a current temperature of the processor and a hardware resource occupancy rate of the processor when it is monitored that the processor core is executing an application; and generates the data prefetch enable signal when the current temperature is less than a temperature threshold and the hardware resource occupancy rate is less than an occupancy rate threshold.

[0105] In an optional embodiment, the optimal dynamic prefetch module includes a prefetch enable judgment module, a cache division control module, a sequential prefetch control module, a step prefetch control module and a self-analysis prefetch control module.

[0106] The prefetch enable judgment module acquires a current temperature of the processor and a hardware resource occupancy rate of the processor when it is monitored that the processor core is executing an application; and generates the data prefetch enable signal and sends it to the overall prefetch control module when the current temperature is less than a temperature threshold and the hardware resource occupancy rate is less than an occupancy rate threshold.

[0107] The cache division control module divides cache spaces of the first cache unit, the second cache unit and the third cache unit into a plurality of sub-cache spaces, respectively.

[0108] The sequential prefetch control module determines a first address corresponding to the prefetch data based on a sequential prefetch mode when it is monitored that data of the sequential prefetch cache sub-space is accessed by the processor core, and sends the first address to the overall prefetch control module.

[0109] The step-prefetch control module, upon monitoring that data in the step-prefetch cache sub-space is accessed by the processor core, determines a second address corresponding to the prefetched data based on the step-prefetch mode, and sends the second address to the global prefetch control module.

[0110] The self-analysis prefetch control module, upon monitoring that data in the self-analysis prefetch cache sub-space is accessed by the processor core, determines a third address corresponding to the prefetched data based on the self-analysis prefetch mode, and sends the third address to the global prefetch control module.

[0111] In an optional embodiment, the optimal dynamic prefetch module further comprises a hit rate statistical analysis module; the method further comprises: The hit rate statistical analysis module statistically processes the access hit rates of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step-prefetch cache sub-space and the self-analysis prefetch cache sub-space when the processor executes the application program.

[0112] The cache partition control module adjusts the cache spaces of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step-prefetch cache sub-space and the self-analysis prefetch cache sub-space based on the access hit rates.

[0113] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0114] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0115] The computer system can include clients and servers. This relationship can be. The servers are typically large- scale computers that process requests and provide shared resources and data to the clients, which are computers in which a user requests a service. The clients and the servers can be in different physical locations, but they can also be co-located. The servers, which can also be cloud servers, can be servers of a distributed system, or servers combined with a blockchain.

[0116] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in series, or executed in different orders so long as the desired results of the disclosed techniques are achieved. The present disclosure is not limited in this regard.

[0117] In addition, the terms "first", "second", etc. are used herein only to describe various steps in a method, process, or mechanism, and are not meant to imply relative importance or a specific number of steps or components. Thus, a feature labeled with "first", "second", etc. can expressly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0118] The above description is merely illustrative of the application, and the scope of the application should not be limited thereto. Any variations and modifications of the application falling within the scope of the application disclosed herein can be easily made by those skilled in the art. Therefore, the scope of the application should be determined by the scope of the claims.

Claims

1. A processor, comprising: The processor comprises a processor core, a first cache unit and a data fast acquisition module. The processor core is configured to acquire an instruction for accessing the first cache unit, the instruction comprising an instruction type, an access start address and an access data amount; determine a number of times of accessing the first cache unit based on the access data amount; determine a first number of periods during which the instruction is valid based on an access data bit width of the processor core and the access data amount; extend a valid duration of the instruction based on the first number of periods; send the instruction and the number of times to the data fast acquisition module; and when it is determined that the instruction is a store instruction based on the instruction type, send first target data corresponding to the instruction to the data fast acquisition module within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. The data fast acquisition module is configured to receive the instruction and the number of times sent by the processor core; determine a second number of periods during which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; extend the valid duration of the instruction based on the second number of periods; and when it is determined that the instruction is a store instruction based on the instruction type in the instruction, receive the first target data sent by the processor core within the extended valid duration. ​ ​ ​ ​ 4. The processor of claim 1, wherein, ​ The access mode analysis module is configured to receive the instruction and the number of times sent by the processor core; and send the instruction to the core data write control module and send a first control signal to the first cache unit access control module when determining that the instruction is a store instruction based on the instruction type in the instruction, the first control signal including the number of times and the access starting address; send the instruction to the core data return control module and send a second control signal to the first cache unit access control module when determining that the instruction is a load instruction based on the instruction type in the instruction, the second control signal including the number of times and the access starting address; The core data write control module is configured to determine the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the access data bit width of the data fast acquisition module; Based on the second number of cycles, the effective duration of the instruction is extended, and the first target data sent by the processor core is received within the extended effective duration; And the first target data is sent to the data cache module for caching; The first cache unit access control module is configured to receive the first control signal or the second control signal; Based on the number of times and the access starting address in the first control signal or the second control signal, a virtual cache block is generated; the virtual cache block includes a plurality of cache blocks continuous with the target cache block corresponding to the access starting address; Based on the first control signal or the second control signal, a plurality of cache blocks in the virtual cache block are synchronously accessed to synchronously write the first target data in the data cache module to a plurality of the cache blocks, or synchronously read the second target data from a plurality of the cache blocks and send to the data cache module for caching; The core data return control module is configured to determine the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the access data bit width of the data fast acquisition module; Based on the second number of cycles, the effective duration of the instruction is extended, and the second target data in the data cache module is sent to the processor core within the extended effective duration.

5. The processor of claim 4, wherein The core data write control module is configured to determine the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the write data bit width of the core data write control module.

6. The processor of claim 4, wherein The core data return control module is configured to determine the second number of cycles in which the instruction is valid based on the access data amount in the instruction and the read data bit width of the core data return control module.

7. The processor of claim 1, wherein, Further comprising: a second cache unit, a third cache unit, an optimal dynamic prefetch module, and an overall prefetch control module. The optimal dynamic prefetching module is configured to generate a data prefetching enabling signal when it is monitored that the processor core is executing an application, send the data prefetching enabling signal to the overall prefetching control module, and divide cache spaces of the first-level cache unit, the second-level cache unit and the third-level cache unit into a plurality of sub-cache spaces respectively, wherein the plurality of sub-cache spaces include a non-prefetching cache sub-space, a sequential prefetching cache sub-space, a step prefetching cache sub-space and a self-analysis prefetching cache sub-space; when it is monitored that data of the sequential prefetching cache sub-space is accessed by the processor core, determine a first address corresponding to prefetching data based on a sequential prefetching mode, and send the first address to the overall prefetching control module; when it is monitored that data of the step prefetching cache sub-space is accessed by the processor core, determine a second address corresponding to prefetching data based on a step prefetching mode, and send the second address to the overall prefetching control module; when it is monitored that data of the self-analysis prefetching cache sub-space is accessed by the processor core, determine a third address corresponding to prefetching data based on a self-analysis prefetching mode, and send the third address to the overall prefetching control module; The overall prefetching control module is configured to prefetch data of the first address, the second address and the third address to corresponding sequential prefetching cache sub-spaces, step prefetching cache sub-spaces and self-analysis prefetching cache sub-spaces in parallel based on the data prefetching enabling signal.

8. The processor of claim 7, wherein The optimal dynamic prefetching module is configured to acquire a current temperature of the processor and a hardware resource occupation rate of the processor when it is monitored that the processor core is executing an application, and generate a data prefetching enabling signal when the current temperature is less than a temperature threshold and the hardware resource occupation rate is less than an occupation rate threshold.

9. The processor of claim 8, wherein, The optimal dynamic prefetching module includes a prefetching enabling judgment module, a cache division control module, a sequential prefetching control module, a step prefetching control module and a self-analysis prefetching control module. The prefetching enabling judgment module is configured to acquire a current temperature of the processor and a hardware resource occupation rate of the processor when it is monitored that the processor core is executing an application, and generate a data prefetching enabling signal when the current temperature is less than a temperature threshold and the hardware resource occupation rate is less than an occupation rate threshold, and send the data prefetching enabling signal to the overall prefetching control module. The cache division control module is configured to divide cache spaces of the first-level cache unit, the second-level cache unit and the third-level cache unit into a plurality of sub-cache spaces respectively. The sequential prefetching control module is configured to determine a first address corresponding to prefetching data based on a sequential prefetching mode when it is monitored that data of the sequential prefetching cache sub-space is accessed by the processor core, and send the first address to the overall prefetching control module. The step prefetching control module is configured to determine a second address corresponding to prefetching data based on a step prefetching mode when it is monitored that data of the step prefetching cache sub-space is accessed by the processor core, and send the second address to the overall prefetching control module. The self-analysis prefetch control module is configured to determine a third address corresponding to the prefetch data based on a self-analysis prefetch mode when it is monitored that the data in the self-analysis prefetch cache sub-space is accessed by the processor core, and send the third address to the overall prefetch control module.

10. The processor of claim 9, wherein, The optimal dynamic prefetch module further comprises a hit rate statistical analysis module. The hit rate statistical analysis module is configured to count access hit rates of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step prefetch cache sub-space and the self-analysis prefetch cache sub-space when the processor executes the application program. The cache partition control module is further configured to adjust cache spaces of the non-prefetch cache sub-space, the sequential prefetch cache sub-space, the step prefetch cache sub-space and the self-analysis prefetch cache sub-space based on the access hit rates.

11. A data processing method applied to a processor, the processor comprising a processor core, a level one cache unit and a data fast access module, the method comprising: The method comprises: The processor core acquires an instruction for accessing the first cache unit, the instruction comprising an instruction type, an access first address and an access data amount; determines a number of times for accessing the first cache unit based on the access data amount; determines a first number of periods in which the instruction is valid based on an access data bit width of the processor core and the access data amount; prolongs a valid time length of the instruction based on the first number of periods; and sends the instruction and the number of times to the data fast acquisition module; and when it is determined that the instruction is a storage instruction based on the instruction type, sends first target data corresponding to the instruction to the data fast acquisition module within the prolonged valid time length. The data fast acquisition module receives the instruction and the number of times sent by the processor core; determines a second number of periods in which the instruction is valid based on the access data amount in the instruction and an access data bit width of the data fast acquisition module; prolongs a valid time length of the instruction based on the second number of periods; and when it is determined that the instruction is a storage instruction based on the instruction type in the instruction, receives the first target data sent by the processor core within the prolonged valid time length; and generates a virtual cache block based on the number of times and the access first address in the instruction; the virtual cache block comprises a plurality of cache blocks continuous to a target cache block corresponding to the access first address; synchronously accesses the plurality of cache blocks in the virtual cache block based on the instruction, so as to synchronously write the first target data into the plurality of cache blocks when the instruction is a storage instruction, or synchronously read second target data from the plurality of cache blocks when the instruction is a load instruction, and send the second target data to the processor core.

12. The data processing method according to claim 11, wherein The processor core receives the second target data sent by the data fast acquisition module within the prolonged valid time length when it is determined that the instruction is a storage instruction based on the instruction type.

13. The data processing method according to claim 11, wherein The processor core determines a first number of cycles in which the instruction is valid based on a write data width of the processor core and the access data amount if the instruction is determined to be a store instruction based on the instruction type, and determines the first number of cycles in which the instruction is valid based on a read data width of the processor core and the access data amount if the instruction is determined to be a load instruction based on the instruction type. 14.The data processing method of claim 11, wherein the data fast acquisition module comprises an access pattern analysis module, a core data write control module, a data cache module, a core data return control module, and a first cache unit access control module. The access pattern analysis module receives the instruction and the number of times sent by the processor core, and sends the instruction to the core data write control module and sends a first control signal to the first cache unit access control module if the instruction is determined to be a store instruction based on an instruction type in the instruction, wherein the first control signal comprises the number of times and the access start address, and sends the instruction to the core data return control module and sends a second control signal to the first cache unit access control module if the instruction is determined to be a load instruction based on the instruction type in the instruction, wherein the second control signal comprises the number of times and the access start address. The core data write control module determines a second number of cycles in which the instruction is valid based on an access data amount in the instruction and an access data width of the data fast acquisition module. The effective duration of the instruction is extended based on the second number of cycles, and first target data sent by the processor core is received within the extended effective duration. The first target data is sent to the data cache module for caching. The first control signal or the second control signal is received by the first cache unit access control module. A virtual cache block is generated based on the number of times and the access start address in the first control signal or the second control signal, wherein the virtual cache block comprises a plurality of cache blocks continuous to a target cache block corresponding to the access start address. The plurality of cache blocks in the virtual cache block are synchronously accessed based on the first control signal or the second control signal, so that the first target data in the data cache module is synchronously written into the plurality of cache blocks, or second target data is synchronously read from the plurality of cache blocks and sent to the data cache module for caching. The core data return control module determines a second number of cycles in which the instruction is valid based on an access data amount in the instruction and an access data width of the data fast acquisition module. Second target data in the data cache module is sent to the processor core based on the second number of cycles. 15.The data processing method of claim 14, wherein The core data write control module determines the second number of periods in which the instruction is valid based on the access data amount in the instruction and a write data bit width of the core data write control module.

16. The data processing method of claim 14, wherein, The core data return control module determines the second number of periods in which the instruction is valid based on the access data amount in the instruction and a read data bit width of the core data return control module.

17. The data processing method of claim 11, wherein the processor further comprises a level two cache unit, a level three cache unit, an optimal dynamic prefetch module, and an overall prefetch control module; and wherein The method further comprises: The optimal dynamic prefetching module generates a data prefetching enable signal when it is monitored that the processor core is executing an application, and sends the data prefetching enable signal to the overall prefetching control module; and divides cache spaces of the first-level cache unit, the second-level cache unit and the third-level cache unit into a plurality of sub-cache spaces respectively, wherein the plurality of sub-cache spaces include a non-prefetching cache sub-space, a sequential prefetching cache sub-space, a step prefetching cache sub-space and a self-analysis prefetching cache sub-space; determines a first address corresponding to prefetching data based on a sequential prefetching mode when it is monitored that data in the sequential prefetching cache sub-space is accessed by the processor core, and sends the first address to the overall prefetching control module; determines a second address corresponding to prefetching data based on a step prefetching mode when it is monitored that data in the step prefetching cache sub-space is accessed by the processor core, and sends the second address to the overall prefetching control module; and determines a third address corresponding to prefetching data based on a self-analysis prefetching mode when it is monitored that data in the self-analysis prefetching cache sub-space is accessed by the processor core, and sends the third address to the overall prefetching control module. The overall prefetching control module prefetches data of the first address, the second address and the third address to corresponding sequential prefetching cache sub-spaces, step prefetching cache sub-spaces and self-analysis prefetching cache sub-spaces in parallel based on the data prefetching enable signal.

18. The data processing method of claim 17, wherein, The optimal dynamic prefetching module acquires a current temperature of the processor and a hardware resource occupation rate of the processor when it is monitored that the processor core is executing an application, and generates a data prefetching enable signal when the current temperature is less than a temperature threshold and the hardware resource occupation rate is less than an occupation rate threshold.

19. The data processing method of claim 18, wherein the optimal dynamic prefetching module comprises a prefetching enable judging module, a cache division control module, a sequential prefetching control module, a step prefetching control module and a self-analysis prefetching control module, and wherein: The prefetching enable judging module acquires a current temperature of the processor and a hardware resource occupation rate of the processor when it is monitored that the processor core is executing an application, and generates a data prefetching enable signal when the current temperature is less than a temperature threshold and the hardware resource occupation rate is less than an occupation rate threshold, and sends the data prefetching enable signal to the overall prefetching control module; The cache division control module divides cache spaces of the first-level cache unit, the second-level cache unit and the third-level cache unit into a plurality of sub-cache spaces respectively; and The sequential prefetching control module determines a first address corresponding to prefetching data based on a sequential prefetching mode when it is monitored that data in the sequential prefetching cache sub-space is accessed by the processor core, and sends the first address to the overall prefetching control module; the step prefetching control module determines a second address corresponding to prefetching data based on a step prefetching mode when it is monitored that data in the step prefetching cache sub-space is accessed by the processor core, and sends the second address to the overall prefetching control module; and the self-analysis prefetching control module determines a third address corresponding to prefetching data based on a self-analysis prefetching mode when it is monitored that data in the self-analysis prefetching cache sub-space is accessed by the processor core, and sends the third address to the overall prefetching control module. The sequential prefetch control module determines a first address corresponding to the prefetch data based on a sequential prefetch mode when monitoring that the data of the sequential prefetch cache subspace is accessed by the processor core, and sends the first address to the overall prefetch control module; The step prefetch control module determines a second address corresponding to the prefetch data based on a step prefetch mode when monitoring that the data of the step prefetch cache subspace is accessed by the processor core, and sends the second address to the overall prefetch control module; The self-analysis prefetch control module determines a third address corresponding to the prefetch data based on a self-analysis prefetch mode when monitoring that the data of the self-analysis prefetch cache subspace is accessed by the processor core, and sends the third address to the overall prefetch control module.

20. The data processing method of claim 19, the optimal dynamic prefetching module further comprising: The hit rate statistical analysis module; characterized in that, the method further comprises: The hit rate statistical analysis module counts the access hit rate of the processor when executing the application program to access the non-prefetch cache subspace, the sequential prefetch cache subspace, the step prefetch cache subspace and the self-analysis prefetch cache subspace; The cache partition control module adjusts the cache space of the non-prefetch cache subspace, the sequential prefetch cache subspace, the step prefetch cache subspace and the self-analysis prefetch cache subspace based on the access hit rate.

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