Signal generation device, circuit to be tested and signal generation method
By integrating a configuration module and a counter inside the circuit under test to generate test function signals, the problems of increased chip pads and timing convergence caused by ATE signal dependence are solved, achieving cost savings and timing optimization.
Patent Information
- Application Number
- CN202511432189.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-01-23
AI Technical Summary
In the prior art, because the ATE needs to provide multiple test function signals, the use of chip pads increases and is not conducive to the timing convergence of ATPG.
The configuration module, counter, and finite state machine are integrated inside the circuit under test. The test function signal is generated by the counter enable signal, reducing the dependence on ATE.
It enables the automatic generation of test function signals within the circuit under test, reducing the use of chip pads and testing costs, while also facilitating the timing convergence of ATPG.
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Figure CN121385589A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip testing technology, and in particular to a signal generation device, circuit under test, and signal generation method suitable for chip testability design. Background Technology
[0002] When performing Design for Test (DFT) on a chip (circuit under test), it is necessary to define test function signals for Automatic Test Pattern Generation (ATPG). These test function signals may include a scan enable signal (scan_en signal) and an embedded deterministic testing (EDT) update signal (edt_update signal).
[0003] However, the scan_en and edt_update signals are typically input to the chip by an automated test equipment (ATE). As chip size increases, the demand for ATPG test signals grows, leading to a higher requirement for the number of ATE channels and consequently, the increased use of chip pads. Furthermore, from a chip physical implementation perspective, test function signals must meet timing requirements, which is detrimental to ATPG timing convergence. Summary of the Invention
[0004] In view of this, the present disclosure provides a signal generation device, a circuit under test, and a signal generation method.
[0005] According to a first aspect of this disclosure, a signal generation device is provided, integrated into a circuit under test. The signal generation device includes: a configuration module; a counter whose initial value is configured by the configuration module; and a finite state machine. When the finite state machine is in a test state, the finite state machine sends a counter enable signal to the counter, wherein the counter is enabled in response to the counter enable signal, and generates a state transition signal for causing a test state transition of the finite state machine when the counter count value reaches the initial value. The finite state machine performs a test state transition according to the state transition signal and generates a test function signal corresponding to the test state to which it transitions.
[0006] In one possible implementation, the test states include a load / unload state, a shift state, and a capture state, and the test function signals include a scan enable signal; during the period from when the finite state machine transitions to the load / unload state to when it transitions to the capture state, the finite state machine generates a high-level scan enable signal; during the period from when the finite state machine transitions to the capture state to when it transitions to the load / unload state, the finite state machine generates a low-level scan enable signal.
[0007] In one possible implementation, the counter includes a load-unload counter, and the configuration module configures the initial value of the load-unload counter to a first cycle number; when the finite state machine transitions to the load-unload state, the finite state machine sends a counter enable signal to the load-unload counter, and at the same time, the finite state machine starts generating a high-level scan enable signal.
[0008] In one possible implementation, the counter further includes a shift counter, the configuration module configuring the initial value of the shift counter to a second number of cycles; in response to the load / unload counter's count value being equal to the first number of cycles, the load / unload counter generates a first state transition signal to cause the finite state machine to transition from the load / unload state to the shift state; the finite state machine transitions from the load / unload state to the shift state according to the first state transition signal; in response to transitioning to the shift state, the finite state machine sends a counter enable signal to the shift counter, while simultaneously continuing to generate a high-level scan enable signal.
[0009] In one possible implementation, the test state further includes a shift-end state, the counter further includes a capture counter and a test vector counter, the configuration module configures the initial value of the capture counter to a third cycle number, and configures the initial value of the test vector counter to a fourth value; in response to the count value of the shift counter being equal to the second cycle number, the shift counter generates a second state transition signal for causing the finite state machine to jump from the shift state to the shift-end state; the finite state machine jumps from the shift state to the shift-end state according to the second state transition signal.
[0010] In one possible implementation, in response to a transition to the shift-end state, if the count value of the test vector counter is less than the fourth value and the scan chain test for the circuit under test has not yet been completed, the shift counter generates a third state transition signal to cause the finite state machine to transition from the shift-end state to the capture state; the finite state machine transitions from the shift-end state to the capture state according to the third state transition signal; in response to the transition to the capture state, the finite state machine sends a counter enable signal to the capture counter, and simultaneously, the finite state machine begins generating a low-level scan enable signal.
[0011] In one possible implementation, in response to the capture counter's count value being equal to the third cycle number, the capture counter generates a fourth state transition signal to cause the finite state machine to transition from the capture state to the load / unload state; the finite state machine transitions from the capture state to the load / unload state according to the fourth state transition signal; in response to transitioning to the load / unload state, the finite state machine sends a counter enable signal to the load / unload counter, and simultaneously, the finite state machine begins generating a high-level scan enable signal.
[0012] In one possible implementation, in response to a transition to the shift-end state, if the count value of the test vector counter is less than the fourth value and a scan chain test for the circuit under test has been completed, the shift counter generates a fifth state transition signal to cause the finite state machine to transition from the shift-end state to the load-unload state; the finite state machine transitions from the shift-end state to the load-unload state according to the fifth state transition signal; in response to transitioning to the load-unload state, the finite state machine sends a counter enable signal to the load-unload counter, while the finite state machine continues to generate a high-level scan enable signal.
[0013] In one possible implementation, the test state further includes a test reset state; in response to transitioning to the shift end state, if the count value of the test vector counter is equal to the fourth value, the shift counter generates a sixth state transition signal to cause the finite state machine to transition from the shift end state to the test reset state; the finite state machine transitions from the shift end state to the test reset state according to the sixth state transition signal; and during the period when the finite state machine is in the test reset state, if a test start signal is received, the finite state machine transitions from the test reset state to the load / unload state.
[0014] In one possible implementation, the test states include a load / unload state, a shift state, and a capture state, and the test function signals include an embedded deterministic test update signal; during a preset time period when the finite state machine is in the load / unload state, the finite state machine generates a high-level embedded deterministic test update signal; during the remaining time periods when the finite state machine is in the load / unload state, and during the shift state and the capture state, the finite state machine generates a low-level embedded deterministic test update signal.
[0015] In one possible implementation, the counter further includes an embedded deterministic test update counter, wherein the configuration module configures the initial value of the embedded deterministic test update counter to the fifth cycle number; the finite state machine in the load / unload state sends a counter enable signal to the embedded deterministic test update counter, and simultaneously, the finite state machine starts generating a high-level embedded deterministic test update signal; in response to the count value of the embedded deterministic test update counter being equal to the fifth cycle number, the finite state machine starts generating a low-level embedded deterministic test update signal.
[0016] According to a second aspect of this disclosure, a circuit under test is provided, which includes the signal generation apparatus described above.
[0017] According to a third aspect of this disclosure, a signal generation method is provided, comprising: a configuration step of configuring an initial value for a counter; a sending step of sending a counter enable signal to the counter when the finite state machine is in a test state; and a processing step of enabling the counter in response to the counter enable signal, generating a state transition signal for causing a test state transition of the finite state machine when the count value of the counter reaches the initial value, causing the finite state machine to transition to a test state according to the state transition signal, and generating a test function signal corresponding to the test state to which the transition occurs.
[0018] The signal generation apparatus, circuit under test (DUT), and signal generation method disclosed herein integrate a configuration module, a counter, and a finite state machine (FSM) within the DUT. When the FSM is in a test state, it sends a counter enable signal to the counter, which has been configured with an initial value by the configuration module. Responding to this enable signal, the enabled counter generates a state transition signal when its count reaches the initial value. The FSM then performs a test state transition based on this transition signal and generates a test function signal corresponding to the transitioned test state for use in the design for testability of the DUT. Therefore, test function signals can be automatically generated within the DUT without requiring the ATE (Automatic Test Equipment) to provide them. This reduces the number of test function ports on the ATE, saving on the use of DUT PADs and effectively lowering the testing cost. Furthermore, it facilitates timing convergence of the ATPG (Automatic Test Tool).
[0019] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0020] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0021] Figure 1 A block diagram of a signal generation apparatus 100 according to an embodiment of the present disclosure is shown.
[0022] Figure 2 A block diagram of a counter 130 according to an embodiment of the present disclosure is shown.
[0023] Figure 3 A schematic diagram showing the signals configured by the configuration module 110 according to an embodiment of the present disclosure is provided.
[0024] Figure 4 A schematic diagram showing the state transition process of a finite state machine 150 according to an embodiment of the present disclosure is provided.
[0025] Figure 5 A timing diagram showing the generation of test function signals according to an embodiment of the present disclosure is provided.
[0026] Figure 6 A flowchart of a signal generation method according to an embodiment of the present disclosure is shown.
[0027] Figure 7 A block diagram of a circuit under test 600 according to an embodiment of the present disclosure is shown. Detailed Implementation
[0028] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0029] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0030] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0031] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0032] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0033] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0034] As mentioned above, in the prior art, the ATE needs to provide the scan_en signal and edt_update signal to the circuit under test. This requires the ATE to set up corresponding test function ports to provide these two test function signals to the circuit under test, which increases the use of PAD in the circuit under test and is not conducive to the timing convergence of ATPG.
[0035] To this end, this disclosure provides a signal generation device, a circuit under test (DUT), and a signal generation method for test function signals. A configuration module, a counter, and a finite state machine are integrated within the DUT. When the finite state machine is in a test state, it sends a counter enable signal to a counter configured with an initial value. The counter, enabled in response to the enable signal, generates a state transition signal when its count value reaches the initial value. The finite state machine then transitions from its current test state to the next test state based on the state transition signal and generates a test function signal corresponding to the next test state for use in the testability design of the DUT.
[0036] Therefore, it can automatically generate test function signals inside the circuit under test without providing test function signals to the circuit under test from the outside, and it does not require providing additional clock signals to the circuit under test from the outside. In addition, it does not require reconfiguring the scan_en signal every time a test vector is run during the operation of the test vector.
[0037] The following combination Figures 1-6 The present disclosure will now describe in detail the signal generation apparatus and signal generation method.
[0038] Figure 1 A block diagram of a signal generation apparatus 100 according to an embodiment of the present disclosure is shown. Figure 1 As shown, the signal generation device 100 may include a configuration module 110, a counter 130, and a finite state machine 150, and the signal generation device 100 may be integrated into the circuit under test.
[0039] In this embodiment, a configuration module 110, a counter 130, and a finite state machine 150 can be directly added to the circuit under test. Thus, the test function signals scan_en and edt_update required for the testability design of the circuit under test can be automatically generated inside the circuit under test through the configuration module 110, the counter 130, and the finite state machine 150.
[0040] It should be understood that the scan_en signal is the scan enable signal, a global enable signal for the scan chain, used to switch the circuit's operating mode. When the scan_en signal is high, such as 1, the circuit is in test shift mode, and all scan flip-flops (Scan DFFs) are connected as a shift register chain, supporting serial shift-in (scan_in) / scan-out (scan_out) of test data. When the scan_en signal is low, such as 0, the circuit is in test capture mode, the circuit resumes normal logic function, the scan chain is disconnected, and the flip-flops operate according to the design logic.
[0041] During the shift phase, the scan_en signal is high (e.g., 1), and the test vector is shifted into the scan chain via the ATE (Automatic Test Array). During the capture phase, the scan_en signal is low (e.g., 0), triggering the combinational logic output value to be latched into the scan flip-flop. Therefore, the value of the scan_en signal is switched during the shift and capture phases to achieve the shifting and capture of test data. During the shift phase, both data shift-in and shift-out operations can be performed simultaneously.
[0042] The edt_update signal is an update signal for Embedded Deterministic Test (EDT) logic, used to control data update operations within the EDT. During the load / unload phase, the edt_update signal can be loaded and unloaded simultaneously; that is, the values of triggers in the EDT can be updated, the decompressor can be updated to prepare for data input operations, and the compactor can be updated to prepare for data output operations.
[0043] Therefore, the `scan_en` signal is mainly used to control the enable of the scan chain, determining whether the circuit under test (DUT) enters the test shift mode; the `edt_update` signal is mainly used to control the data update in the EDT logic, ensuring that test data can be correctly transmitted between the EDT and the scan chain. It is evident that the `scan_en` and `edt_update` signals work together in the DFT testing of the DUT, jointly ensuring that test data can be correctly loaded, captured, and output, thereby achieving effective testing of the internal logic of the DUT.
[0044] The configuration module 110 is used to configure the initial value of the counter 130. In this embodiment, the configuration module 110 can use the IJTAG protocol to pre-configure the initial value of the counter 130 into the Test Data Register (TDR) based on the information of the test vector or the scan structure information of the circuit under test. It should be understood that the IJTAG protocol is an extended network protocol of the JTAG protocol, and the specific content of the IJTAG protocol will not be described in detail.
[0045] In one possible implementation, the initial value configured by the configuration module 110 can be stored in a register such as TDR. When the counter 130 needs to use the initial value, the counter 130 can read the stored initial value from the register.
[0046] In one possible implementation, the initial value of the signal to be configured depends on the test vector, because the function of the ATPG test vector is to test the circuit under test. Therefore, the configuration module 110 can configure the initial value of the counter 130 according to the structure of the circuit under test.
[0047] In this embodiment, the configuration module 110 can configure an initial value that meets the requirements of the size of the circuit under test and the length of the required test vectors, based on the size of the circuit under test and the length of the required test vectors. If the circuit under test is large and the required test vectors are complex or numerous, the configuration module 110 can configure a larger initial value for the counter 130; if the circuit under test is small and the required test vectors are simple or few, the configuration module 110 can configure a smaller initial value for the counter 130.
[0048] For example, if the circuit under test requires 100 test vectors, the configuration module 110 configures the initial value of the test vector counter included in the counter 130 to 100. If the scan chain of the circuit under test is particularly long or has 1000 cycles, the configuration module 110 configures the initial value of the test vector counter included in the counter 130 to 1000. The configuration module 110 can customize the initial value of the capture counter included in the counter 130. If it is feasible to capture the test vectors in 10 cycles or 20 cycles, the configuration module 110 can configure the initial value of the capture counter included in the counter 130 to 10 or 20 clock cycles.
[0049] It should be understood that this embodiment does not limit the specific method by which the configuration module 110 configures the initial value of the counter 130. In addition to configuring the initial value of the counter 130 in the manner described above, the configuration module 110 can also use other methods to configure the initial value of the counter 130. For example, it can also configure the initial value of the counter 130 according to any suitable requirements related to the DFT test of the circuit under test.
[0050] In one possible implementation, the configuration module 110 can also be used to configure whether the circuit under test (DUT) enters the test shift mode. For example, when testing the DUT, the configuration module 110 can configure the test shift mode signal value to a first value, such as pulling the test shift mode signal high. After the configuration module 110 configures the DUT to enter the test shift mode, the configuration module 110 can configure the initial value of the counter 130 in the manner described above.
[0051] After the configuration module 110 configures the initial value of the counter 130, when the finite state machine 150 is in the corresponding test state, the finite state machine 150 can send a counter enable signal to the counter 130.
[0052] In this embodiment, when the finite state machine 150 is in different test states, the finite state machine 150 can send a corresponding counter enable signal to the corresponding counter 130 to enable the counter 130. That is, when the finite state machine 150 jumps from the current test state to the next test state, the finite state machine 150 can send a counter enable signal matching the next test state to the counter 130 to enable the counter 130 corresponding to the counter enable signal, so that the enabled counter 130 can count as the clock runs during the next test state.
[0053] For example, in response to the counter enable signal, counter 130 is enabled to trigger counter 130 to start working. Counter 130 reads the initial value configured by configuration module 110 from the register. The initial count value of counter 130 is 0. Starting from when finite state machine 150 jumps to the next test state, the count value of counter 130 is incremented by 1 every clock cycle. During this period, counter 130 determines in real time whether its count value has reached the initial value stored in the register. If it determines that the current count value has reached the initial value, counter 130 generates a state transition signal to cause finite state machine 150 to jump from the current test state.
[0054] The finite state machine 150 performs test state transitions based on the state transition signals generated by the counter 130, and generates test function signals corresponding to the test states to which they are transitioned. These test function signals are used for the testability design of the circuit under test.
[0055] In this embodiment, the finite state machine 150 jumps from the current test state to the next test state according to the state transition signal generated by the counter 130, and generates a test function signal corresponding to the next test state. The test function signal includes the scan_en signal and the edt_update signal.
[0056] In one possible implementation, such as Figure 4 and Figure 5 As shown, the test states include load_unload state, shift state, and capture state. From the time the finite state machine 150 jumps to the load_unload state, through the shift state, and then to the capture state, the finite state machine 150 generates a high-level scan_en signal. From the time the finite state machine 150 jumps to the capture state, until the time the finite state machine 150 jumps to the load_unload state, the finite state machine 150 generates a low-level scan_en signal.
[0057] In one possible implementation, continue as follows Figure 4 and Figure 5 As shown, during a preset time period when the finite state machine 150 is in the load_unload state, the finite state machine 150 generates a high-level edt_update signal; during the remaining time periods when the finite state machine 150 is in the load_unload state, and during the periods when the finite state machine 150 is in the shift state and the capture state, the finite state machine 150 generates a low-level edt_update signal.
[0058] Therefore, under the coordinated processing of finite state machine 150 and counter 130, as the clock runs, the two functional test signals, scan_en and edt_update, are automatically generated inside the circuit under test.
[0059] According to this embodiment, a configuration module, a counter, and a finite state machine are added to the circuit under test (DUT). When the finite state machine is in the test state, it sends a counter enable signal to the counter configured with an initial value. In response to the enable signal, the enabled counter generates a state transition signal when its count value reaches the initial value. The finite state machine performs a test state transition based on the state transition signal and generates a test function signal corresponding to the test state to which it transitions for the testability design of the DUT. Thus, test function signals can be automatically generated within the DUT without needing to be provided by the ATE (Automatic Test Equipment). In this way, the ATE only needs to provide data signals and clock signals, thereby reducing the number of test function ports from external sources such as the ATE, saving the use of PADs in the DUT, and also facilitating the timing convergence of the ATPG (Automatic Test Tool).
[0060] In one possible implementation, such as Figure 2 As shown, counter 130 may include five counters: test vector counter (pattern number counter) 131, load_unload counter (load_unload counter) 132, embedded deterministic test update counter (edt_update counter) 133, shift counter (shift counter) 134, and capture counter (capture counter) 135.
[0061] It should be understood that the test vector counter 131 is used to count the number of test vectors as the clock runs, the load / unload counter 132 is used to count the number of load / unload cycles as the clock runs, the embedded deterministic test update counter 133 is used to count the number of embedded deterministic test update cycles as the clock runs, the shift counter 134 is used to count the number of shift cycles as the clock runs, and the capture counter 135 is used to count the number of capture cycles as the clock runs.
[0062] The configuration module 110 can configure the initial values of these five counters in the manner described above. For example, the configuration module 110 can configure the initial value of the test vector counter 131 to 50, the initial value of the load / unload counter 132 to 10 clock cycles, the initial value of the embedded deterministic test update counter 133 to 2 clock cycles, the initial value of the shift counter 134 to 1000 clock cycles, and the initial value of the capture counter 135 to 20 clock cycles.
[0063] In one possible implementation, such as Figure 3 As shown, the signals that the configuration module 110 needs to configure include the lpct_mode signal, test_start signal, load_unload_count signal, edt_update_count signal, shift_count signal, capture_count signal, chain_pattern_count signal, and scan_pattern_count signal.
[0064] It should be understood that the `lpct_mode` signal is the flag signal for entering LPCT mode (low pin count mode). The `test_start` signal is the test start trigger signal; when the `test_start` signal is high (e.g., 1), the test vector (load pattern) begins to load. The `load_unload_count` signal is the number of load / unload cycles in the scan chain, which is the count of each small stage in the test vector cycle. The `edt_update_count` signal is the number of cycles in which the `edt_update` signal in the EDT module of the circuit under test is kept high.
[0065] The `shift_count` signal represents the length of the scan chain, i.e., how many clock cycles were shifted when scan chain shifts occurred. The `capture_count` signal represents the number of capture cycles of the scan chain, i.e., how many clock cycles the scan chain captured. The `chain_pattern_count` signal represents the number of cycles of the scan chain test pattern for the circuit under test. The `scan_pattern_count` signal represents the number of cycles of the scan test pattern for the circuit under test.
[0066] In DFT testing, the configuration module 110 can comprehensively configure the load_unload_count, edt_update_count, shift_count, capture_count, chain_pattern_count, and scan_pattern_count signals according to test requirements, scan chain length, and test efficiency.
[0067] In this embodiment, the configuration module 110 can configure the chain_pattern_count signal or the scan_pattern_count signal to use the configured value of the chain_pattern_count signal or the scan_pattern_count signal as the initial value, i.e., the fourth value, of the test vector counter 111. The configuration module 110 can also configure the load_unload_count signal to use the configured value of the load_unload_count signal as the initial value, i.e., the first cycle number, of the load / unload counter 132.
[0068] Configuration module 110 can configure the edt_update_count signal to use its configured value as the initial value of the embedded deterministic test update counter 133, i.e., the fifth cycle number. Configuration module 110 can also configure the shift_count signal to use its configured value as the initial value of the shift counter 134, i.e., the second cycle number. Configuration module 110 can further configure the capture_count signal to use its configured value as the initial value of the capture counter 135, i.e., the third cycle number.
[0069] In one possible implementation, the counter 130 includes a load / unload counter 132, and the configuration module 110 configures the initial value of the load / unload counter 132 as a first cycle number; when the finite state machine 150 jumps to the load / unload state, the finite state machine 150 sends a counter enable signal to the load / unload counter 132, and at the same time, the finite state machine 150 starts generating a high-level scan_en signal.
[0070] like Figure 4 As shown, the finite state machine 150 has five states: test_reset, load_unload, shift, shift_end, and capture. The testing process of the test vector can be determined based on the state of the finite state machine 150. Figure 5 As shown, when finite state machine 150 is in the load_unload state, finite state machine 150 starts to set the scan_en signal to 1. Simultaneously, as... Figure 4 As shown, the finite state machine 150 sends a counter enable signal to the load / unload counter 132 to enable the load / unload counter 132.
[0071] In one possible implementation, the counter 130 further includes a shift counter 134, the configuration module 110 configuring the initial value of the shift counter 134 to a second cycle number; in response to the load / unload counter 132's count value being equal to the first cycle number, the load / unload counter 132 generates a first state transition signal for causing the finite state machine 150 to transition from the load / unload state to the shift state; the finite state machine 150 transitions from the load / unload state to the shift state according to the first state transition signal; in response to transitioning to the shift state, the finite state machine 150 sends a counter enable signal to the shift counter 134, while simultaneously continuing to generate a high-level scan_en signal.
[0072] In this embodiment, if the lpct_mode signal is configured to 1 by configuration module 110, the test_start signal is configured to 1 by configuration module 110, the load_unload_count signal is configured to 10 clock cycles by configuration module 110, the edt_update_count signal is configured to 2 clock cycles by configuration module 110, the shift_count signal is configured to 1000 clock cycles by configuration module 110, the capture_count signal is configured to 20 clock cycles by configuration module 110, and the chain_pattern_count signal or scan_pattern_count signal is configured to 50, then... Figure 4 As shown, with each clock cycle, the load / unload counter 132 increments by 1. When the load / unload counter 132 equals 10, a load_unload_done signal is generated (load_unload_done signal = 1'b1), and the finite state machine 150 enters the shift state, as follows. Figure 5 As shown, finite state machine 150 maintains the scan_en signal = 1. Meanwhile, as... Figure 4 As shown, the finite state machine 150 sends a counter enable signal to the shift counter 134 to enable the shift counter 134.
[0073] In one possible implementation, the test state further includes a shift-end state, the counter 130 further includes a capture counter 135 and a test vector counter 131, the configuration module 110 configures the initial value of the capture counter 135 to a third cycle number, and configures the initial value of the test vector counter 131 to a fourth value; in response to the count value of the shift counter 134 being equal to the second cycle number, the shift counter 134 generates a second state transition signal for causing the finite state machine 150 to jump from the shift state to the shift-end state; the finite state machine 150 jumps from the shift state to the shift-end state according to the second state transition signal.
[0074] Continuing with the example above, such as Figure 4 As shown, shift counter 134 starts working. With each clock cycle, the count value of shift counter 134 is incremented by 1. When the count value of shift counter 134 equals 1000, the shift_done signal is generated (shift_done signal = 1'b1), and finite state machine 150 enters the shift_end state.
[0075] In one possible implementation, in response to a transition to the shift-end state, if the count value of the test vector counter 131 is less than the fourth value and the scan chain test for the circuit under test has not yet been completed, the shift counter 134 generates a third state transition signal to cause the finite state machine 150 to transition from the shift-end state to the capture state; the finite state machine 150 transitions from the shift-end state to the capture state according to the third state transition signal; in response to the transition to the capture state, the finite state machine 150 sends a counter enable signal to the capture counter 135, and simultaneously, the finite state machine 150 begins generating a low-level scan_en signal.
[0076] Continuing with the example above, such as Figure 4 As shown, when the finite state machine 150 is in the shift_end state, the shift counter 134 determines whether all test vectors have been tested, that is, whether the value of the test vector counter 131 is 50. If the determination is negative (pattern_done signal = 1'b0), and the scan chain test has not yet been completed (chain_test signal = 1'b0), then it enters the capture state, as shown. Figure 5 As shown, finite state machine 150 sets the scan_en signal to 0. Simultaneously, as... Figure 4 As shown, the finite state machine 150 sends a counter enable signal to the capture counter 135 to enable the capture counter 135.
[0077] In one possible implementation, in response to the capture counter 135's count value being equal to the third cycle number, the capture counter 135 generates a fourth state transition signal for causing the finite state machine 150 to transition from the capture state to the load / unload state; the finite state machine 150 transitions from the capture state to the load / unload state according to the fourth state transition signal; in response to transitioning to the load / unload state, the finite state machine 150 sends a counter enable signal to the load / unload counter 132, and simultaneously, the finite state machine 150 begins generating a high-level scan_en signal.
[0078] Continuing with the example above, such as Figure 4 As shown, the capture counter 135 starts working, and its count value increments by 1 with each clock cycle. When the count value of the capture counter 135 equals 20, a capture_done signal is generated (capture_done signal = 1'b1), and the finite state machine 150 enters the load_unload state, as follows. Figure 5 As shown, finite state machine 150 sets the scan_en signal to 1. Simultaneously, as... Figure 4As shown, the finite state machine 150 sends a counter enable signal to the load / unload counter 132 to enable the load / unload counter 132 and continue according to... Figure 4 The state transition diagram shown illustrates the state transitions.
[0079] In one possible implementation, in response to a transition to the shift-end state, if the count value of the test vector counter 131 is less than the fourth value and a scan chain test for the circuit under test has been completed, the shift counter 134 generates a fifth state transition signal to cause the finite state machine 150 to transition from the shift-end state to the load-unload state; the finite state machine 150 transitions from the shift-end state to the load-unload state according to the fifth state transition signal; in response to transitioning to the load-unload state, the finite state machine 150 sends a counter enable signal to the load-unload counter 132, while the finite state machine 150 continues to generate a high-level scan_en signal.
[0080] Continuing with the example above, such as Figure 4 As shown, when finite state machine 150 is in the shift_end state (shift_done signal = 1'b1), shift counter 134 determines whether all test vectors have been tested, that is, whether the value of test vector counter 131 is 50. If the determination is negative (pattern_done signal = 1'b0), and the scan chain test has been completed (chain_test signal = 1'b1), then finite state machine 150 returns to the load_unload state and continues testing the scan chain. That is, finite state machine 150 continues to enter the load_unload state, as... Figure 5 As shown, finite state machine 150 sets the scan_en signal to 1. Simultaneously, as... Figure 4 As shown, the finite state machine 150 sends a counter enable signal to the load / unload counter 132 to enable the load / unload counter 132 and continue according to... Figure 4 The state transition diagram shown illustrates the state transitions.
[0081] In one possible implementation, the test state further includes a test reset state; in response to transitioning to the shift end state, if the count value of the test vector counter 131 is equal to the fourth value, the shift counter 131 generates a sixth state transition signal to cause the finite state machine 150 to transition from the shift end state to the test reset state; the finite state machine 150 transitions from the shift end state to the test reset state according to the sixth state transition signal; and while the finite state machine 150 is in the test reset state, if a test start signal is received, the finite state machine 150 transitions from the test reset state to the load / unload state.
[0082] Continuing with the example above, such as Figure 4 As shown, when finite state machine 150 is in the shift_end state (shift_done signal = 1'b1), shift counter 134 determines whether all test vectors have been tested, that is, whether the value of test vector counter 131 is 50. If the determination is yes (pattern_done signal = 1'b1), it returns to the test_reset state. During the test_reset state of finite state machine 150, if the test start signal is 1 (test_start signal = 1'b1), finite state machine 150 jumps from the test_reset state to the load_unload state.
[0083] In one possible implementation, the counter 130 further includes an embedded deterministic test update counter 133, wherein the configuration module 110 configures the initial value of the embedded deterministic test update counter 133 to the fifth cycle number; the finite state machine 150, in the load / unload state, sends a counter enable signal to the embedded deterministic test update counter 133, and simultaneously, the finite state machine 150 starts generating a high-level edt_update signal; in response to the count value of the embedded deterministic test update counter 133 being equal to the fifth cycle number, the finite state machine 150 starts generating a low-level edt_update signal.
[0084] Continuing with the example above, such as Figure 5As shown, when finite state machine 150 is in the load_unload state, at a certain point, the embedded deterministic test update counter 133 is enabled, and the embedded deterministic test update counter 133 starts working. Simultaneously, finite state machine 150 sets the edt_update signal to 1. With each clock cycle, the count value of the embedded deterministic test update counter 133 is incremented by 1. When the count value of the embedded deterministic test update counter 133 equals 2, the edt_update_done signal is generated (edt_update_done signal = 1'b1), and finite state machine 150 sets the edt_update signal to 0.
[0085] According to this embodiment, after configuring the initial values of counters 131 to 135, the corresponding counters start counting as the clock runs. After the count value of the corresponding counter reaches the configured initial value, the corresponding state transition condition is met, thereby performing the state transition of the state machine until the test vector of the circuit under test is completed. During this period, the scan_en signal and edt_update signal are automatically generated.
[0086] Therefore, by integrating the configuration module 110, the counter 130, and the finite state machine 150 into the circuit under test, the two functional test signals scan_en and edt_update can be automatically generated inside the circuit under test without the ATE providing these two functional test signals to the circuit under test.
[0087] Figure 6 A flowchart illustrating a signal generation method according to an embodiment of the present disclosure is shown. Figure 6 As shown, the signal generation method may include the following steps:
[0088] In step S510, the initial value of counter 130 is configured by configuration module 110. Then, step S520 is executed.
[0089] In step S520, when the finite state machine 150 is in the corresponding test state, a counter enable signal is sent to the counter 130 through the finite state machine 150. Then, step S530 is executed.
[0090] In step S530, counter 130 is enabled in response to the counter enable signal from finite state machine 150. Then, step S540 is executed.
[0091] In step S540, it is determined whether the count value of counter 130 has reached the configured initial value. If the determination is yes, step S550 is executed; otherwise, step S570 is executed.
[0092] In step S550, a state transition signal is generated by counter 130 to cause a change in the test state of finite state machine 150. Then, step S560 is executed.
[0093] In step S560, the finite state machine 150 is caused to switch test states according to the state transition signal generated by the counter 130, and a test function signal corresponding to the test state to which it is switched is generated. The test function signal is used for the testability design of the circuit under test.
[0094] In step S570, the finite state machine 150 is maintained in the test state.
[0095] For a detailed description of steps S510-570, please refer to the previous section on... Figure 1 The relevant descriptions will not be repeated here.
[0096] According to this embodiment, test function signals can be automatically generated inside the circuit under test (TUT) without the need for the ATE to provide test function signals. This reduces the number of test function ports of the ATE, thereby saving the use of the TUT PAD and effectively reducing the testing cost of the TUT. In addition, it is also beneficial to the timing convergence of ATPG.
[0097] In some embodiments, the steps or steps included in the method provided in this disclosure can be executed by the modules described in the above device embodiments. The specific implementation can be referred to the description of the above device embodiments, and for the sake of brevity, it will not be repeated here.
[0098] Figure 7 A block diagram of a circuit under test according to an embodiment of the present disclosure is shown. For example... Figure 7 As shown, the circuit under test 600 integrates a signal generation device 100, that is, the circuit under test 600 has an added configuration module 110, a counter 130 and a finite state machine 150.
[0099] Therefore, the circuit under test 600 can automatically generate test function signals within itself through the added configuration module 110, counter 130 and finite state machine 150, without having to provide test function signals through ATE. This reduces the number of test function ports of ATE, thereby saving the use of PADs in the circuit under test and effectively reducing the testing cost of the circuit under test. In addition, it is also beneficial to the timing convergence of ATPG.
[0100] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A signal generation device, characterized in that, The signal generation device is integrated into the circuit under test, and the signal generation device includes: Configuration module; The counter, whose initial value is configured by the configuration module; and A finite state machine, when in test state, sends a counter enable signal to the counter. The counter is enabled in response to the counter enable signal, and generates a state transition signal to cause the test state of the finite state machine to transition when the counter value reaches the initial value. The finite state machine performs test state transitions according to the state transition signal and generates a test function signal corresponding to the test state to which it transitions.
2. The signal generation device according to claim 1, characterized in that, The test states include loading / unloading state, shifting state, and capture state; the test function signals include a scan enable signal. From the time the finite state machine transitions to the load / unload state until the time the finite state machine transitions to the capture state, the finite state machine generates a high-level scan enable signal; From the time the finite state machine transitions to the capture state until the time the finite state machine transitions to the load / unload state, the finite state machine generates a low-level scan enable signal.
3. The signal generation device according to claim 2, characterized in that, The counter includes a load / unload counter, and the configuration module configures the initial value of the load / unload counter to the first cycle number. When the finite state machine transitions to the load / unload state, it sends a counter enable signal to the load / unload counter, and at the same time, it starts generating a high-level scan enable signal.
4. The signal generation device according to claim 3, characterized in that, The counter also includes a shift counter, and the configuration module configures the initial value of the shift counter to the second cycle number; In response to the load-unload counter's count value being equal to the first number of cycles, the load-unload counter generates a first state transition signal for causing the finite state machine to transition from the load-unload state to the shift state; The finite state machine transitions from the loading / unloading state to the shifting state according to the first state transition signal; In response to the transition to the shift state, the finite state machine sends a counter enable signal to the shift counter, while the finite state machine continues to generate a high-level scan enable signal.
5. The signal generation device according to claim 4, characterized in that, The test state also includes a shift end state, the counter also includes a capture counter and a test vector counter, and the configuration module configures the initial value of the capture counter to the third cycle number and the initial value of the test vector counter to the fourth value. In response to the shift counter's count value being equal to the second number of cycles, the shift counter generates a second state transition signal to cause the finite state machine to transition from the shift state to the shift-end state; The finite state machine jumps from the shift state to the shift end state according to the second state jump signal.
6. The signal generation apparatus according to claim 5, characterized in that, In response to the transition to the shift-end state, if the count value of the test vector counter is less than the fourth value and the scan chain test for the circuit under test has not been completed, the shift counter generates a third state transition signal to cause the finite state machine to transition from the shift-end state to the capture state. The finite state machine jumps from the shift end state to the capture state according to the third state transition signal; In response to the transition to the capture state, the finite state machine sends a counter enable signal to the capture counter, and at the same time, the finite state machine starts generating a low-level scan enable signal.
7. The signal generating apparatus according to claim 6, characterized in that, In response to the capture counter's count value being equal to the third cycle number, the capture counter generates a fourth state transition signal to cause the finite state machine to transition from the capture state to the load / unload state; The finite state machine jumps from the capture state to the load / unload state according to the fourth state transition signal; In response to the transition to the load / unload state, the finite state machine sends a counter enable signal to the load / unload counter, and at the same time, the finite state machine starts generating a high-level scan enable signal.
8. The signal generation apparatus according to claim 5, characterized in that, In response to the transition to the shift end state, if the count value of the test vector counter is less than the fourth value and the scan chain test for the circuit under test has been completed, the shift counter generates a fifth state transition signal to cause the finite state machine to transition from the shift end state to the load unload state. The finite state machine jumps from the shift end state to the loading / unloading state according to the fifth state jump signal; In response to the transition to the load / unload state, the finite state machine sends a counter enable signal to the load / unload counter, while the finite state machine continues to generate a high-level scan enable signal.
9. The signal generation apparatus according to claim 5, characterized in that, The test status also includes the test reset status; In response to the transition to the shift end state, if the count value of the test vector counter is equal to the fourth value, the shift counter generates a sixth state transition signal to cause the finite state machine to transition from the shift end state to the test reset state. The finite state machine jumps from the shift end state to the test reset state according to the sixth state jump signal; If a test start signal is received while the finite state machine is in the test reset state, the finite state machine jumps from the test reset state to the load / unload state.
10. The signal generation apparatus according to claim 1, characterized in that, The test states include loading / unloading state, shifting state, and capturing state; the test function signals include embedded deterministic test update signals. During a preset time period when the finite state machine is in the loading / unloading state, the finite state machine generates a high-level embedded deterministic test update signal; During the remaining time period when the finite state machine is in the load / unload state, and during the time period when the finite state machine is in the shift state and the capture state, the finite state machine generates a low-level embedded deterministic test update signal.
11. The signal generating apparatus according to claim 10, characterized in that, The counter also includes an embedded deterministic test update counter, and the configuration module configures the initial value of the embedded deterministic test update counter to the fifth cycle number; The finite state machine in the loading / unloading state sends a counter enable signal to the embedded deterministic test update counter, and at the same time, the finite state machine starts generating a high-level embedded deterministic test update signal. In response to the embedded deterministic test update counter's count value being equal to the fifth cycle number, the finite state machine begins generating a low-level embedded deterministic test update signal.
12. A circuit under test, characterized in that, The signal generating apparatus includes any one of claims 1 to 11.
13. A signal generation method, characterized in that, The signal generation method, applied to the circuit under test, includes: The configuration steps involve configuring the initial value of the counter; In the sending step, when the finite state machine is in the test state, a counter enable signal is sent to the counter; The processing steps include enabling the counter in response to the counter enable signal, generating a state transition signal for causing the test state of the finite state machine to transition when the counter count value reaches the initial value, causing the finite state machine to transition to the test state according to the state transition signal, and generating a test function signal corresponding to the test state to which it has transitioned.