DPU-based index analysis calculation and release acceleration system

Abstract

The invention relates to the technical field of financial data processing, in particular to a DPU-based index analytic calculation and release acceleration system, which comprises a flow controller, a finite state machine (FSM), a hierarchical storage module, a parallel ALU calculation channel, a coding transmission module and an upper computer interaction module, the hierarchical storage module comprises a local storage unit and a global storage unit, and the encoding transmission module covers an encoder, an output buffer area, a DMA transmission unit and a network card. The system carries out four-stage propulsion processing, an FSM analyzes control words and distributes channels, a hierarchical storage module efficiently manages data, a parallel ALU calculation channel completes index correlation calculation, an encoder carries out preprocessing and then packages the data and sends the data through DMA, the system is provided with a software and hardware collaborative optimization module to support dynamic parameter updating, and whole-process hardware acceleration is achieved. The method has the characteristics of high certainty, high throughput and flexible configuration, and is suitable for financial scenes with strict requirements on real-time performance and certainty.

Description

Technical Field

[0001] This invention relates to the field of financial data processing technology, and in particular to an index parsing, calculation and publishing acceleration system based on DPU. Background Technology

[0002] FPGA, short for Field Programmable Gate Array, is a type of programmable device. It is a semi-custom circuit developed based on traditional logic circuits and gate arrays such as PAL (Programmable Logic Array), GAL (General Purpose Array Logic), and CPLD (Complex Programmable Logic Device). It not only solves the shortcomings of semi-custom circuits but also overcomes the limitation of the limited number of gate circuits in the original programmable devices. Its unique advantages in computing and storage, algorithm acceleration, and low-latency transmission have profound technical application value in the financial field.

[0003] Existing financial index calculation systems primarily rely on general-purpose CPUs or distributed clusters, exhibiting significant shortcomings in real-time performance, data processing efficiency, resource utilization, and system scalability. Traditional CPUs' serial processing mode struggles to handle the throughput demands of massive financial data scenarios, while distributed systems, although improving computing power, suffer from unstable response times due to network communication latency, failing to meet the stringent deterministic requirements of financial operations. At the data processing level, traditional memory access mechanisms are inefficient for processing non-continuous data; due to the need for multiple memory accesses, actual bandwidth utilization is often less than 50%, creating severe performance bottlenecks. The design of general-purpose computing units is not optimized for the characteristics of financial data, resulting in significant computational waste in specific scenarios such as sudden traffic spikes and high-precision decimal calculations. Existing solutions are also limited in scalability; software implementations heavily rely on specific processor instruction sets, while hardware solutions such as FPGAs lack dynamic reconfiguration capabilities, both failing to adapt to the rapidly changing business rules of the financial market.

[0004] Therefore, a new technical solution is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a DPU-based index parsing, calculation and publishing acceleration system to solve the technical problems of high latency, low memory access efficiency, insufficient computing power utilization, large protocol encapsulation overhead and insufficient scalability in traditional financial index calculation systems, and to meet the stringent requirements of real-time performance and determinism in financial scenarios.

[0006] The above objectives are achieved through the following technical solutions: A DPU-based exponential parsing, calculation, and publishing acceleration system includes a flow controller, a finite state machine (FSM), a hierarchical storage module, 16 parallel ALU computing channels, an encoding and transmission module, and a host computer interaction module. The flow controller communicates with the host computer via a PCIe interface. The hierarchical storage module includes local RAM (BRAM) and global REG (REG) storage units. The encoding and transmission module includes an encoder, an output buffer, a DMA (DMA) transmission unit, and a network interface card (NIC). These modules work together to accelerate the entire process of exponential data parsing, calculation, encapsulation, and publishing using hardware acceleration. The system as a whole processes data sequentially in four stages: control word extraction and channel allocation, hierarchical storage update, parallel computing execution, and data encapsulation and transmission.

[0007] Furthermore, the flow controller is configured with a template address register group T0-T4 and a sequence field address register. The template address register group T0-T4 stores RAM entry addresses corresponding to multiple different templates, and the sequence field address register stores entry addresses of multiple nested sequence loops. The two types of registers jointly determine the starting address of the exponential data segment, enabling complete reception of unaligned data under full bandwidth.

[0008] Furthermore, the finite state machine (FSM) includes six working states: fetch, decode, receive, preprocess, field operation, and output. The state transition adopts a dual judgment mechanism based on byte counter and protocol field verification. Moreover, the logic of the FSM is coupled with the handshake signal of the AXI-Stream protocol, and the processing progress is only advanced when the TVALID and TREADY signals are both valid. The FSM extracts a 32-bit control word from RAM, parses out a 4-bit ALU channel selection code, and locks the target ALU calculation channel through ALUS Sel Reg.

[0009] Furthermore, the local storage unit (BRAM) corresponds one-to-one with the ALU calculation channel. Each ALU calculation channel only accesses the index data specified by the host computer. The local storage unit (BRAM) uses a two-level addressing method of high-three initial addressing + low-three secondary addressing to store discrete index data, supporting parallel read and write of dual ALU channels. The global storage unit (REG) centrally manages the common data of all indices. The common data includes index value, change value, and change rate. The global storage unit (REG) is configured with an arbitrator to handle write conflicts of multiple ALU channels. The host computer monitors the storage status of the hierarchical storage module in real time through the PCIe configuration space 0x0C.

[0010] Furthermore, the 16 ALU computing channels operate synchronously in parallel. Each ALU computing channel is equipped with a dedicated computing unit. The dedicated computing unit integrates a high-performance fixed-point arithmetic unit and calls dedicated multipliers and dividers IP to perform high-bit-width multiplication and division. The calculation process of each ALU computing channel is executed in three cycles. The first cycle performs arithmetic operations, the second cycle temporarily stores the calculation results, and the last cycle updates the global storage unit REG according to the control word flag.

[0011] Furthermore, the ALU calculation channel adopts a two-cycle separation processing mode for exponent / mantissa of decimal data. The system is configured with an abnormal state reporting register 0x10. The ALU calculation channel reports the abnormal state during the calculation process to the host computer through register 0x10. The finite state machine (FSM) decodes the control signals to the corresponding modules of each ALU calculation channel and updates the relevant flag registers of the sorting lane running sign and the external global sign.

[0012] Furthermore, the ALU calculation channel uses hardware circuitry to solidify the relevant calculation formulas for the index. The index value is calculated using a real-time weighted method, and the core formula is: Index value = (Σ(Product price × Calculated share capital × Calculated exchange rate × Sample identifier × Weighted identifier) ​​ / Base period) × Base period parameter + Additional index; The formula for calculating cumulative transaction volume is: Σ(product transaction volume × transaction identifier); The formula for calculating the cumulative transaction amount is: Σ(product transaction amount × transaction identifier × exchange rate).

[0013] Furthermore, the encoder performs differential preprocessing operations on Int32, Int64, uInt32, uInt64, decimal, string, and byte vector data types. It extends the sign bit of numeric data to 64 bits, extends the sign bit of the exponent and mantissa of decimal data and stores them in two 64-bit registers, and adds a 2-byte prefix to strings. The encoder uses parallel bit concatenation technology to automatically complete the big-endian conversion and field offset alignment of 64-bit data fields.

[0014] Furthermore, the output buffer is an 8-depth buffer, each corresponding to a different QoS priority. The host computer sets the QoS priority mapping rules through PCIe configuration register 0x14. The DMA transmission unit adds a 16-bit CRC checksum to the encapsulated UDP packet and writes it directly into the network card's transmission queue. The system is configured with a status register 0x18. After the DMA transmission unit completes the transmission, it triggers the transmission completion flag bit of register 0x18.

[0015] Furthermore, the host computer interaction module is equipped with a hardware timer and a hardware-software co-optimization module. The minimum time granularity of the hardware timer can be configured to 1μs. The host computer controls the timing and working status of the hardware timer through registers 0x14 / 0x18. The hardware-software co-optimization module realizes floating-point to fixed-point conversion and parameter bit-level concatenation through the host preprocessing script, and supports dynamic online updates of index constituent stocks and weight parameters through the PCIe interface.

[0016] The present invention provides an exponential parsing calculation and publishing acceleration system based on DPU. Through multi-module collaborative full-process hardware acceleration under the DPU architecture, combined with 16-channel parallel computing, hierarchical storage management and hardware-level data encapsulation and transmission, it realizes microsecond-level processing of exponential parsing calculation and publishing, greatly improves memory access and computing power utilization, eliminates the additional overhead of protocol encapsulation, supports dynamic parameter updates, adapts to rapid changes in market rules, and significantly improves performance compared with traditional solutions. Attached Figure Description

[0017] Figure 1 This is an architecture diagram of a DPU-based exponential parsing calculation and publishing acceleration system described in this invention. The diagram illustrates the four processing stages of the system and the connections and data flow of each module, register, and storage unit. It includes core components such as template address registers T0-T4.Addr Regs, sequence flag register Seq.FlagReg, ALU selection register ALUS SelReg, global register GlobalReg, various function registers ICJJE.Reg, ICJL.Reg, IMAX.Reg, IMIN.Reg, IZDF.Reg, IZD.Reg, template register Template.Reg, local storage units ZQJB1_Bram and ZQJBN_Bram, finite state machine FSM, 16 ALU calculation channels, timerCount, PCIe interface, QSFP, and ETH. Each component achieves high-speed data and control signal transmission through a dedicated bus, completing the entire process from exponential data input to calculation and output. The system is divided into four stages, Stage 1 to Stage 4, each sequentially connecting and cooperating with various registers, storage units, and calculation units to complete corresponding data processing tasks. The host computer interacts with the system via PCIe for bidirectional instruction issuance, parameter configuration, and status monitoring. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, this solution provides a DPU-based exponential parsing, calculation, and publishing acceleration system, including a flow controller, a finite state machine (FSM), a hierarchical storage module, 16 parallel ALU calculation channels, an encoding and transmission module, and a host computer interaction module. The flow controller communicates with the host computer via a PCIe interface. The hierarchical storage module includes local RAM (BRAM) and global REG (REG) storage units. The encoding and transmission module includes an encoder, an output buffer, a DMA (DMA transfer) unit, and a network interface card (NIC). These modules work together to complete the entire hardware acceleration process for exponential data parsing, calculation, encapsulation, and publishing. Figure 1 As shown, the system is divided into four core processing stages: control word extraction and channel allocation, hierarchical storage update, parallel computing execution, and data encapsulation and transmission. Each stage is coordinated and scheduled through a finite state machine (FSM) and various registers. The host computer configures system parameters, monitors status, and issues instructions through the PCIe bus.

[0020] S1. Control Word Extraction and Channel Allocation Stage The flow controller receives template configuration parameters from the host computer via the PCIe interface and initializes the template address register group T0-T4 and the sequence field address register (Seq. Flag Regs). The template address register group T0-T4 stores RAM entry addresses corresponding to multiple different templates, enabling complete reception of unaligned data at full bandwidth through multi-template adaptation. The sequence field address register stores entry addresses of multiple nested sequence loops. The two types of registers together determine the starting address of the exponential data segment, in which the decoder sequentially acquires control words.

[0021] The Finite State Machine (FSM) executes its process in six states: fetch, decode, receive, preprocess, field operation, and output. In the fetch state, a 32-bit control word is retrieved from RAM based on the current pipeline position. In the decode state, after parsing the target ALU channel number, the target computation channel is locked using a 4-bit ALUS Sel Reg, and the control word is stored in the dedicated pipeline control word register for that channel. In the receive state, discontinuous data blocks are reassembled based on the base address offset in the template address register. In the preprocessing state, sign bit extension is performed on data with a width less than 64 bits. In the field operation state, bit concatenation / masking operations are completed. In the output state, valid data is written to the input buffer of the target channel.

[0022] The state transition of the Finite State Machine (FSM) adopts a dual judgment mechanism based on byte counter and protocol field verification. When parsing the ARCH protocol header, the process only proceeds to the next stage after the byte counter reaches a preset threshold and the key protocol fields pass verification. This effectively prevents parsing errors caused by incomplete data or abnormal format. At the same time, the state machine logic is tightly coupled with the handshake signals of the AXI-Stream protocol. The processing progresses only when the TVALID and TREADY signals are both valid, ensuring the determinism of data transmission and eliminating the risk of data loss and link congestion.

[0023] S2, Tiered Storage Update Phase While selecting the data sequence channel, the local storage unit BRAM and the global storage unit REG are updated simultaneously to achieve separate storage and efficient management of dedicated data and public data.

[0024] The local memory unit BRAM corresponds one-to-one with the ALU computing path. Each ALU only accesses the exponent data specified by the host computer, and uses the high three bits of the exponent as the initial address and the low three bits as the secondary address. This secondary addressing architecture can improve the storage density and access efficiency of discontinuous exponent data under limited hardware resources, avoiding the memory access bottleneck of traditional storage architecture. At the same time, the local memory unit BRAM supports parallel read and write of dual ALU channels, further improving memory access throughput.

[0025] The global storage unit REG centrally manages the public data of all indices, including index values, change values, and percentage changes. It handles multi-channel write conflicts through an arbitrator to ensure data consistency when multiple ALU channels are written in parallel. The host computer can monitor the storage status in real time through the PCIe configuration space 0x0C to achieve visualized control of the tiered storage modules.

[0026] This tiered storage design ensures the independence of data access in the computing channels, improves the sharing efficiency of public data, balances storage resource consumption and access speed, and breaks through the bottleneck of traditional storage architecture in processing non-continuous data.

[0027] S3, Parallel Computing Execution Phase Sixteen ALU computing channels work synchronously and in parallel to complete the full calculation of the predetermined exponent, realizing hardware-level concurrent processing of multiple exponent updates and significantly improving computing throughput. In each loop, a control word is sent to the selected computing channel to trigger the calculation flow of the corresponding field in the data stream. The pipeline control word in the channel stores the currently retrieved control word until the exponent calculation is completed. Local storage units and global storage units serve as addresses of preset value RAM to store the current stage exponent value to support subsequent continuous calculations, realizing continuous iterative calculation of exponent data.

[0028] Each ALU computing channel contains a dedicated computing unit, and the computing is executed in three cycles: the first cycle performs arithmetic operations, the second cycle temporarily stores the results, and the last cycle updates the global storage according to the control word flag; the computing core integrates a high-performance fixed-point arithmetic unit, which performs high-bit-width multiplication and division by calling dedicated multiplier and divider IPs, replacing traditional software floating-point operations, and significantly reducing combinational logic latency while ensuring computing accuracy.

[0029] The finite state machine (FSM) decodes the control signals to the corresponding modules and updates the relevant flag registers, including the lane operation signs and external global flags. During the calculation process, the decimal data is processed in two cycles: exponent and mantissa, which is suitable for the high-precision calculation requirements of financial data. Abnormal states are reported through register 0x10, and the host computer can obtain calculation abnormal information in real time through this register.

[0030] The index value calculation of this system adopts a real-time weighted method. The core formula is: Index value = (Σ(Product price × Calculated share capital × Calculated exchange rate × Sample identifier × Weighted identifier) ​​ / Base period) × Base period parameter + Additional index; The cumulative trading volume calculation formula is: Σ(Product trading volume × Trading identifier); The cumulative trading amount calculation formula is: Σ(Product trading amount × Trading identifier × Calculated exchange rate); The price change calculation formula is: Current calculated value - Previous trading day's closing value; The price change percentage calculation formula is: (Current calculated value - Previous trading day's closing value) / Previous trading day's closing value × 100%. All formulas are implemented through hardware circuitry to ensure the efficiency and determinism of the calculation.

[0031] S4, Data Encapsulation and Transmission Stage The fields of the index publishing stream are fixed-length data bytes. The encoder obtains the field data from the template address register for encapsulation. The encoder continuously receives all results from the computing unit in each cycle. The timer executes timing according to the requirements of the host computer. The received data is temporarily stored in the register until the timing is completed. For special fields such as decimal type fields and byte vector type fields, the two slices contained therein can be set and determined by the host computer, which improves the configuration flexibility of the system.

[0032] The encoder performs differentiated preprocessing operations for different data types such as Int32, Int64, uInt32, uInt64, decimal, string, and byte vector. Specifically, Int32, Int64, uInt32, and uInt64 data types are sign-extended to 64 bits; decimal data types have their exponent and mantissa sign bits extended and stored in two 64-bit registers; string and byte vector data types are processed according to corresponding rules. This differentiated preprocessing scheme ensures the uniformity and compatibility of data formats, meeting the requirements of subsequent encapsulation and transmission.

[0033] To address the big-endian requirements of financial market data protocols, the encoder employs parallel bit-by-bit concatenation technology. Within each clock cycle of the AXI-Stream bus, it automatically performs byte order conversion and field offset alignment for 64-bit data fields, eliminating the CPU memory copying and protocol encapsulation overhead common in traditional software solutions. The encoder encapsulates data according to predefined field descriptors in the template address register: numeric data is converted to big-endian 64-bit format; string data is prefixed with a 2-byte length; and decimal data is split into exponent and mantissa fields.

[0034] During the encapsulation process, an output buffer with 8 depths is maintained, each corresponding to a different QoS level. The host computer sets priority mapping rules through PCIe configuration register 0x14 to ensure the transmission priority of key index data and ensure low-latency release of core financial data. The final generated UDP packet is added with a 16-bit CRC checksum and directly written to the network card's transmission queue through the DMA channel. At the same time, the transmission completion flag bit of the 0x18 status register is triggered, realizing high-speed hardware-level transmission and eliminating software scheduling delays. The entire transmission process is controlled by a hardware timer issued by the host computer, with a minimum time granularity configurable to 1μs. The encapsulated data stream is sent out via the UDP protocol and handed over to the host computer for data display and disk storage.

[0035] This system also includes a hardware and software co-optimization mechanism: by using a host-side preprocessing script to perform floating-point to fixed-point conversion and parameter bit-level concatenation, non-real-time loads are removed from the hardware, reducing FPGA logic resource consumption; it supports dynamic online updates of index constituent stocks and weight parameters through the PCIe interface, giving the system the ability to quickly adapt to changes in market rules and improving the system's scalability and usability.

[0036] During system deployment, the host unit is responsible for FPGA program loading, file and module configuration, module monitoring and information reading. It interacts with the DPU hardware at high speed through the PCIe bus, realizing full-process hardware acceleration from protocol parsing, parameter calculation to packaging and release. The end-to-end processing latency is as low as 6.29μs, including 4.49μs for protocol parsing, 1.61μs for exponent calculation, and 0.19μs for exponent release.

[0037] As a specific embodiment of this system, the DPU-based exponent analysis, calculation, and publishing acceleration system of this invention uses the DPU as the hardware core and integrates a flow controller, a finite state machine (FSM), a hierarchical storage module, 16 parallel ALU computing channels, an encoding and transmission module, and a host computer interaction module. Each module achieves high-speed interaction of data and control signals through a dedicated hardware bus and register group. During system deployment, the host and DPU hardware establish a communication connection through the PCIe bus. The host completes tasks such as FPGA program loading, system module initialization and configuration, operation status monitoring, and data reading. The DPU hardware is responsible for the full-process hardware acceleration processing of exponent data from protocol parsing, control word extraction, hierarchical storage, parallel computing to data encapsulation and UDP publishing. The overall execution process strictly follows the four stages of control word extraction and channel allocation, hierarchical storage update, parallel computing execution, and data encapsulation and transmission.

[0038] I. System Initialization Configuration The host computer sends template configuration parameters to the flow controller via the PCIe interface. After receiving the parameters, the flow controller completes the initialization of the template address register group T0-T4 and the sequence field address register. The template address register group T0-T4 is written with the RAM entry addresses corresponding to multiple different templates, and the sequence field address register is written with the entry addresses of multiple nested sequence loops. The initial values ​​of the two types of registers jointly determine the starting addressing position of the exponential data segment. At the same time, the host computer completes the initial configuration of various function registers through the PCIe configuration space, including setting QoS priority mapping rules through register 0x14, configuring the minimum time granularity of the hardware timer to 1μs, completing the initial configuration of ALU channel selection through ALUS Sel Reg, and enabling functions such as storage status monitoring of register 0x0C, abnormal status reporting of register 0x10, and transmission status triggering of register 0x18. After completing the full system initialization, each module enters the ready state and waits for the input of the exponential data stream.

[0039] II. Execution of the Entire Index Data Processing Process 1. Control Word Extraction and Channel Allocation Stage: After the exponential data stream enters the system via the ETH, the flow controller addresses the data according to the initialized template address register group T0-T4 and the sequence field address register. The finite state machine (FSM) initiates the parsing process in six states: fetch, decode, receive, preprocess, field operation, and output. In the fetch state, the FSM accurately extracts the 32-bit control word from RAM according to the current pipeline position. In the decode state, the control word is parsed to obtain the 4-bit ALU channel selection code, which is then processed via ALUS Sel. The system locks the target ALU calculation channel and stores the control word in the dedicated pipelined control word register for that channel. In the receive state, non-contiguous data blocks are reassembled according to the base address offset in the template address register to achieve continuous processing of non-contiguous data. In the preprocessing state, all exponent data with a bit width of less than 64 bits are sign-extended to ensure data bit width consistency. In the field operation state, bit concatenation / masking operations are performed on the data to filter out valid calculation data. In the output state, the processed valid data is written to the input buffer of the target ALU calculation channel, completing the extraction of the single-channel control word and channel allocation. This process is executed cyclically to achieve continuous parsing and channel allocation of all control words in the exponent data stream.

[0040] 2. Tiered Storage Update Phase: While the FSM completes the allocation of target ALU computing channels, the system simultaneously initiates the update of the local storage unit (BRAM) and the global storage unit (REG). The local storage unit (BRAM) corresponds one-to-one with each ALU computing path. Each ALU computing channel only accesses the index data pre-specified by the host computer, using the high three bits of the index data as the initial address and the low three bits as the secondary address. This secondary addressing method enables the storage of discrete index data. Simultaneously, the BRAM supports parallel read / write operations for dual ALU channels, improving memory access efficiency. The global storage unit (REG) centrally stores common data for all indices, including index values, change values, and percentage changes. When multiple ALU computing channels simultaneously write data to the REG, an arbitrator schedules the write requests in an orderly manner, handling multi-channel write conflicts and ensuring data consistency. Throughout the storage update process, the host computer can read the storage addresses, data write status, and remaining storage space of the BRAM and REG in real time through the PCIe configuration space 0x0C, enabling full monitoring of the tiered storage module.

[0041] 3. Parallel Computing Execution Phase: After receiving valid data from the input buffer, the 16 ALU computing channels synchronously initiate the parallel computing process, realizing hardware-level concurrent computation of multiple exponents. In each loop, the target ALU computing channel receives the control word from the FSM and triggers the computation flow of the corresponding field in the data stream according to the control word. The pipeline control word register within the channel continuously stores the currently retrieved control word until the computation flow of that exponent is completely completed. During the computation, the local memory unit BRAM and the global memory unit REG serve as the addresses of the preset value RAM, providing data support for the computation process. At the same time, the exponent values ​​of the current computation stage are stored in real time, providing a data foundation for subsequent continuous computation. The dedicated computing unit of each ALU computing channel executes the computation in three cycles. The first cycle performs arithmetic operations according to the fixed hardware circuit. The system calculates data such as index value, change value, cumulative trading volume, and cumulative trading amount. In the next cycle, the arithmetic operation results are temporarily stored in a dedicated register. In the final cycle, the temporarily stored calculation results are updated to the global storage unit REG according to the flag information in the control word. During the calculation process, for decimal index data, a two-cycle processing mode with separate exponent and mantissa is adopted to complete the high-precision calculation of decimal data separately. If abnormal states such as abnormal data format, calculation overflow, or memory access error occur during the calculation process, the system will report the abnormal information to the host computer in real time through register 0x10. While coordinating the parallel calculation of all ALU calculation channels, the FSM decodes the control signals to the corresponding units of each module and updates the relevant flag registers such as the sorting lane running flag and external global flag in real time, realizing full control of the parallel calculation process.

[0042] 4. Data Encapsulation and Transmission Stage: The calculation results of each ALU calculation channel are synchronously transmitted to the encoder of the encoding and transmission module. The encoder obtains fixed-length field data from the template address register and starts the data encapsulation process. The encoder continuously receives the calculation results from all ALU calculation units every clock cycle. The hardware timer executes timing according to the rules pre-configured by the host computer. The received calculation results are temporarily stored in a dedicated register until the timer completes timing and then starts the encapsulation operation. For different data types such as Int32, Int64, uInt32, uInt64, decimal, string, and byte vector, the encoder performs differentiated preprocessing. The sign bit of Int32, Int64, uInt32, and uInt64 numeric data is extended to 64 bits. The sign bit of the exponent and mantissa of the decimal data is extended and stored in two 64-bit registers. A 2-byte prefix is ​​added to the string. The byte vector is pre-processed according to the rules. The algorithm is designed for rule-based processing. After preprocessing, the encoder uses parallel bit-joining technology to automatically complete the big-endian conversion and field offset alignment of the 64-bit data field within each clock cycle of the AXI-Stream bus. Then, it completes data encapsulation according to the predefined field descriptors in the template address register. The encapsulated data is sent to an 8-depth output buffer, which sorts the data according to a preset QoS priority to ensure the priority transmission of critical index data. Finally, the data retrieved from the output buffer is encapsulated into a UDP packet. After adding a 16-bit CRC checksum to the packet, it is directly written to the network card's transmission queue through the DMA channel. At the same time, the transmission completion flag bit of the 0x18 status register is triggered. The encapsulated data stream is sent to the host computer via the UDP protocol, where the host computer completes the subsequent data display and disk writing. The entire transmission process is precisely controlled by a hardware timer with a minimum time granularity of 1μs, ensuring the real-time and deterministic nature of the transmission.

[0043] III. System Performance Testing and Verification To verify the performance advantages of the system of this invention, the traditional software index calculation and publishing system and the DPU-based index parsing, calculation and publishing acceleration system of this invention were deployed on two identical physical servers. Both servers were equipped with a standard market data gateway from an exchange, which sent identical index data streams to both systems to ensure the consistency of the test environment. During the test, the processing cycle and latency of the two systems in the three core modules of protocol parsing, index calculation and index publishing, as well as the overall processing cycle and latency of the entire link, were statistically analyzed to compare and verify the performance improvement effect of the system of this invention.

[0044] During the test, the processing cycle of each module of the system was counted in clock cycles, and the processing latency was calculated based on the number of clock cycles and the system clock frequency. The specific test results are shown in Tables 1 and 2 below: Table 1 Processing cycle and latency of each module in the system of the present invention Module Protocol parsing Index Calculation Index Release Overall Link cycle 449 cycles 161 cycles 19 cycles 629 cycles Delay 4.49μs 1.61μs 0.19μs 6.29μs Table 2 Comparison of processing latency between traditional software systems and the system of this invention. Protocol parsing Index Calculation Index Release Overall Link Software index calculation 798.69μs 334.59μs 295.49μs 1428.77μs Hardware Index Calculation 4.49μs 1.61μs 0.19μs 6.29μs The test results show that the DPU-based index parsing, calculation, and publishing acceleration system of this invention achieves microsecond-level index data processing under the premise of timely data arrival. The processing latency of the three core modules—protocol parsing, index calculation, and index publishing—all reach the microsecond level, with an end-to-end processing latency as low as 6.29 μs. Compared with traditional software index calculation and publishing systems, the protocol parsing latency of this invention is reduced by 794.2 μs, the index calculation latency by 332.98 μs, the index publishing latency by 295.3 μs, and the end-to-end processing latency by 1422.48 μs. The overall performance is improved by approximately 250 times compared with traditional software solutions.

[0045] After eliminating the millisecond-level latency caused by network uncertainties during upstream data transmission, the hardware acceleration architecture of this invention achieves a hundredfold improvement in computing performance. Compared with traditional index calculation systems, it has higher computing speed and lower processing latency, enabling efficient handling of massive index data streams and complex index calculation tasks. Especially in multi-index parallel processing, it significantly reduces the latency impact of index stream data on downstream systems. At the same time, the system supports dynamic online updates of index constituent stocks and weight parameters through the PCIe interface, adapting to changes in financial market rules without restarting the system. Combined with a hardware and software co-optimization mechanism, it achieves efficient utilization of system resources and flexible configuration adjustment while ensuring high computing performance.

[0046] In summary, the DPU-based index parsing, calculation, and publishing acceleration system of this invention achieves end-to-end hardware acceleration for financial index parsing, calculation, and publishing through an innovative combination of technologies such as dedicated pipeline control, hierarchical storage management, 16-channel parallel computing, and hardware-level data encapsulation and transmission. It solves the technical problems of traditional systems, such as poor real-time performance, low memory access efficiency, wasted computing power, and insufficient scalability. The end-to-end processing latency is as low as 6.29μs, and the performance is approximately 250 times higher than traditional software solutions. It features high determinism, high throughput, low latency, and flexible configuration, making it perfectly adaptable to financial business scenarios with stringent real-time and deterministic requirements, such as high-frequency trading and real-time quantitative analysis.

[0047] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A DPU-based exponential resolution computation and publication acceleration system, characterized by, The system includes a flow controller, a finite state machine (FSM), a hierarchical storage module, 16 parallel ALU computing channels, an encoding and transmission module, and a host computer interaction module. The flow controller communicates with the host computer via a PCIe interface. The hierarchical storage module includes local RAM (BRAM) and global REG (REG) storage units. The encoding and transmission module includes an encoder, an output buffer, a DMA (DMA) transmission unit, and a network interface card (NIC). These modules work together to accelerate the entire process of parsing, calculating, encapsulating, and publishing exponential data. The system as a whole processes data sequentially in four stages: control word extraction and channel allocation, hierarchical storage update, parallel computing execution, and data encapsulation and transmission.

2. The DPU-based exponential analysis calculation and publishing acceleration system according to claim 1, characterized in that, The flow controller is configured with template address register group T0-T4 and sequence field address register. The template address register group T0-T4 stores RAM entry addresses corresponding to multiple different templates, and the sequence field address register stores entry addresses of multiple nested sequence loops. The two types of registers jointly determine the starting address of the exponential data segment, realizing the complete reception of unaligned data under full bandwidth.

3. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 1, characterized in that, The finite state machine (FSM) includes six working states: fetch, decode, receive, preprocess, field operation, and output. The state transition adopts a dual judgment mechanism based on byte counter and protocol field verification. The logic of the FSM is coupled with the handshake signal of the AXI-Stream protocol, and the processing progress is only advanced when the TVALID and TREADY signals are both valid. The FSM extracts a 32-bit control word from RAM, parses out a 4-bit ALU channel selection code, and locks the target ALU calculation channel through ALUS Sel Reg.

4. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 1, characterized in that, The local storage unit (BRAM) corresponds one-to-one with the ALU calculation channel. Each ALU calculation channel only accesses the index data specified by the host computer. The local storage unit (BRAM) uses a two-level addressing method with high-three initial addressing and low-three secondary addressing to store discrete index data, supporting parallel read and write of dual ALU channels. The global storage unit (REG) centrally manages the common data of all indices. The common data includes index value, change value, and change rate. The global storage unit (REG) is configured with an arbitrator to handle write conflicts of multiple ALU channels. The host computer monitors the storage status of the hierarchical storage module in real time through the PCIe configuration space 0x0C.

5. A DPU-based exponential parsing calculation and publishing acceleration system according to claim 1 or 4, characterized in that, The 16 ALU computing channels operate synchronously in parallel. Each ALU computing channel is equipped with a dedicated computing unit. The dedicated computing unit integrates a high-performance fixed-point arithmetic unit and calls dedicated multipliers and dividers IP to perform high-bit-width multiplication and division. The computing process of each ALU computing channel is executed in three cycles. The first cycle performs arithmetic operations, the second cycle temporarily stores the calculation results, and the last cycle updates the global storage unit REG according to the control word flag.

6. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 5, characterized in that, The ALU calculation channel adopts a two-cycle separation processing mode for exponent / mantissa of decimal data. The system is configured with an abnormal state reporting register 0x10. The ALU calculation channel reports the abnormal state during the calculation process to the host computer through register 0x10. The finite state machine (FSM) decodes the control signals to the corresponding modules of each ALU calculation channel and updates the relevant flag registers of the sorting lane running sign and the external global sign.

7. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 5, characterized in that, The ALU calculation channel uses hardware circuitry to solidify the relevant calculation formulas for the index. The index value is calculated using a real-time weighted method. The core formula is: Index value = (Σ(Product price × Calculated share capital × Calculated exchange rate × Sample identifier × Weighted identifier) ​​ / Base period) × Base period parameter + Additional index; The formula for calculating cumulative transaction volume is: Σ(product transaction volume × transaction identifier); The formula for calculating the cumulative transaction amount is: Σ(product transaction amount × transaction identifier × exchange rate).

8. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 1, characterized in that, The encoder performs differential preprocessing operations on Int32, Int64, uInt32, uInt64, decimal, string, and byte vector data types. It extends the sign bit of numeric data to 64 bits, extends the sign bit of the exponent and mantissa of decimal data and stores them in two 64-bit registers, and adds a 2-byte prefix to strings. The encoder uses parallel bit concatenation technology to automatically complete the big-endian conversion and field offset alignment of 64-bit data fields.

9. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 1, characterized in that, The output buffer is an 8-depth buffer, each corresponding to a different QoS priority. The host computer sets the QoS priority mapping rules through PCIe configuration register 0x14. The DMA transmission unit adds a 16-bit CRC checksum to the encapsulated UDP packet and writes it directly into the network card's transmission queue. The system is configured with a status register 0x18. After the DMA transmission unit completes transmission, it triggers the transmission completion flag bit of register 0x18.

10. The DPU-based exponential parsing calculation and publishing acceleration system according to claim 1, characterized in that, The host computer interaction module is equipped with a hardware timer and a hardware-software co-optimization module. The minimum time granularity of the hardware timer can be configured to 1μs. The host computer controls the timing and working status of the hardware timer through registers 0x14 / 0x18. The hardware-software co-optimization module realizes floating-point to fixed-point conversion and parameter bit-level concatenation through host preprocessing scripts, and supports dynamic online updates of index constituent stocks and weight parameters through the PCIe interface.

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