Chip interface debugging method and device, storage medium and program product

Abstract

The invention relates to the technical field of computers, and provides a chip interface debugging method and device, a storage medium and a program product. The chip interface comprises a serializer and a deserializer, the serializer is connected with the deserializer through a plurality of channels, and the method comprises the following steps: determining a plurality of first parameter groups of an equalizer in the serializer and an error rate threshold value of each channel; debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer according to a debugging result and an error rate threshold; wherein when the chip interface is debugged at any time according to any first parameter group, the serializer outputs a test code pattern to the at least one channel, the deserializer determines the error rate of the channel according to the actual code pattern and the test code pattern received from each channel, and the obtained debugging result comprises the error rate of the at least one channel. According to the method, the hardware cost and the labor cost can be reduced, the debugging efficiency is improved, and the adaptability of the chip interface debugging method to different application scenes is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a chip interface debugging method, apparatus, storage medium, and program product. Background Technology

[0002] A serializer / deserializer (SerDes) is a chip interface used for high-speed data transmission. A SerDes consists of a serializer and a deserializer, connected via a transmission channel. The serializer converts parallel data into serial data for output to the transmission channel, while the deserializer converts serial data input to the transmission channel back into parallel data.

[0003] Currently, SerDes primarily relies on manual debugging. This requires manually setting the parameter set used by the serializer and verifying the bit error rate (BER) using a bit error rate tester (BERT). If the BER is too high, the parameter set used by the serializer needs to be manually adjusted. This process may need to be repeated multiple times until the BER meets the requirements, increasing hardware and labor costs and reducing debugging efficiency. Furthermore, debugging only covers one transmission channel between the serializer and deserializer, and the final parameter set is only applicable to single-channel transmission scenarios, offering poor adaptability to multi-channel transmission scenarios. Summary of the Invention

[0004] In view of this, this disclosure proposes a chip interface debugging method, apparatus, storage medium, and program product. The chip interface debugging method of this disclosure can reduce hardware and labor costs, improve debugging efficiency, and enhance the adaptability of the chip interface debugging method to different application scenarios.

[0005] According to one aspect of this disclosure, a chip interface debugging method is provided. The chip interface includes a serializer and a deserializer. The serializer is connected to the deserializer through multiple channels. The method includes: determining multiple first parameter groups of an equalizer in the serializer and a bit error rate threshold for each channel based on interface attribute information of the chip interface; debugging the chip interface according to the multiple first parameter groups; and selecting at least one target parameter group for the serializer based on the debugging result and the bit error rate threshold. Specifically, when the chip interface is debugged once according to any one of the first parameter groups, the first parameter group is written into the serializer, the serializer outputs a test pattern to at least one channel, the deserializer determines the bit error rate of each channel based on the actual pattern received from each channel and the test pattern of that channel, and the obtained debugging result includes the bit error rate of the at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group.

[0006] In one possible implementation, the process of debugging the chip interface according to the plurality of first parameter groups includes a first debugging stage and a second debugging stage. Debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer based on the debugging results and the bit error rate threshold, includes: in the first debugging stage, debugging the chip interface according to the plurality of first parameter groups, each first parameter group corresponding to one debugging session and one debugging result; selecting at least one second parameter group for the serializer from the plurality of first parameter groups based on the debugging results of the first debugging stage and the bit error rate threshold; in the second debugging stage, debugging the chip interface according to the at least one second parameter group, each second parameter group corresponding to X debugging sessions and X debugging results, where X is an integer greater than 1; and selecting at least one target parameter group for the serializer from the at least one second parameter group based on the debugging results of the second debugging stage and the bit error rate threshold.

[0007] In one possible implementation, selecting at least one second parameter group for the serializer from the plurality of first parameter groups based on the debugging results of the first debugging phase and the bit error rate threshold includes: determining whether the debugging results corresponding to each first parameter group meet a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; when the debugging results corresponding to any first parameter group meet the first preset condition, selecting that first parameter group as the second parameter group.

[0008] In one possible implementation, selecting at least one target parameter group for the serializer from the at least one second parameter group based on the debugging results of the second debugging phase and the bit error rate threshold includes: determining whether the X debugging results corresponding to each second parameter group satisfy a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; counting the total number of debugging results corresponding to the second parameter group that satisfy the first preset condition to obtain a first statistical value corresponding to the second parameter group; and selecting the second parameter group as the target parameter group when the first statistical value corresponding to any second parameter group is greater than Y, wherein Y is a positive integer less than or equal to X.

[0009] In one possible implementation, selecting at least one target parameter group for the serializer from the at least one second parameter group based on the debugging results of the second debugging phase and the bit error rate threshold includes: determining whether the X debugging results corresponding to each second parameter group satisfy a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; counting the total number of debugging results corresponding to the second parameter group that satisfy the first preset condition to obtain a first statistical value corresponding to the second parameter group; when the first statistical value corresponding to any second parameter group is greater than Y, taking the first statistical value as a second statistical value, where Y is a positive integer less than or equal to X; sorting the obtained second statistical values ​​according to their numerical values, and selecting at least one second parameter group corresponding to the at least one second statistical value with the largest numerical value as at least one target parameter group.

[0010] In one possible implementation, the step of debugging the chip interface according to the plurality of first parameter groups and selecting at least one target parameter group for the serializer according to the debugging results and the bit error rate threshold includes: for each first parameter group, debugging the chip interface once according to the first parameter group; determining whether the debugging result obtained from the debugging meets a first preset condition, the first preset condition being that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold; if the debugging result obtained from the debugging meets the first preset condition, continuing to debug the chip interface X times according to the first parameter group to obtain X debugging results, where X is an integer greater than 1; determining whether each of the X debugging results meets the first preset condition, counting the total number of debugging results that meet the first preset condition among the X debugging results to obtain a third statistical value corresponding to the first parameter group; when the third statistical value corresponding to any first parameter group is greater than Y, using the third statistical value as a fourth statistical value, where Y is a positive integer less than or equal to X; sorting the obtained fourth statistical values ​​according to their numerical values, and selecting at least one first parameter group corresponding to at least one fourth statistical value with the largest numerical value as at least one target parameter group.

[0011] In one possible implementation, the interface attribute information includes the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode. The first parameter group includes multiple parameters. Determining multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel based on the interface attribute information of the chip interface includes: determining the value range of each parameter based on the chip identifier of the chip to which the chip interface belongs and the expected transmission rate; obtaining the multiple first parameter groups based on the value ranges of the multiple parameters, wherein at least one parameter in any two first parameter groups has a different parameter value; and determining the bit error rate threshold of each channel based on the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode.

[0012] In one possible implementation, any debugging of the chip interface includes: writing the parameter set to be used into the serializer, the serializer simultaneously outputting a test pattern to the at least one channel; resetting the deserializer and setting the parameter values ​​of the deserializer; starting the debugging of the deserializer and obtaining the status information of the at least one channel; when the status information indicates that the at least one channel is in a stable state, resetting the counting result of the deserializer; the deserializer obtaining the counting result of each channel based on the actual pattern received by each channel and the test pattern, and determining the bit error rate of the channel based on the counting result of each channel.

[0013] In one possible implementation, during any debugging of the chip interface, the serializer simultaneously outputs test patterns to multiple channels.

[0014] According to another aspect of this disclosure, a chip interface debugging apparatus is provided. The chip interface includes a serializer and a deserializer. The serializer is connected to the deserializer through multiple channels. The apparatus includes: a preprocessing module, used to determine multiple first parameter groups of the equalizer in the serializer and a bit error rate threshold for each channel based on the interface attribute information of the chip interface; and a debugging and selection module, used to debug the chip interface according to the multiple first parameter groups, and select at least one target parameter group for the serializer based on the debugging result and the bit error rate threshold. Specifically, when the chip interface is debugged once according to any one of the first parameter groups, the first parameter group is written into the serializer, the serializer outputs a test pattern to at least one channel, the deserializer determines the bit error rate of each channel based on the actual pattern received from each channel and the test pattern of that channel, and the obtained debugging result includes the bit error rate of the at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group.

[0015] In one possible implementation, the process of debugging the chip interface according to the plurality of first parameter groups includes a first debugging stage and a second debugging stage. The debugging and selection module includes a first debugging unit and a second debugging unit. The first debugging unit is used to: in the first debugging stage, debug the chip interface according to the plurality of first parameter groups, each first parameter group corresponding to one debugging session and one debugging result; and select at least one second parameter group for the serializer from the plurality of first parameter groups based on the debugging result of the first debugging stage and the bit error rate threshold. The second debugging unit is used to: in the second debugging stage, debug the chip interface according to the at least one second parameter group, each second parameter group corresponding to X debugging sessions and X debugging results, where X is an integer greater than 1; and select at least one target parameter group for the serializer from the at least one second parameter group based on the debugging result of the second debugging stage and the bit error rate threshold.

[0016] In one possible implementation, the first debugging unit is specifically used to determine whether the debugging result corresponding to each first parameter group meets a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold; when the debugging result corresponding to any first parameter group meets the first preset condition, the first parameter group is selected as the second parameter group.

[0017] In one possible implementation, the second debugging unit is specifically used to: determine whether the X debugging results corresponding to each second parameter group meet a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; count the total number of debugging results corresponding to the second parameter group that meet the first preset condition to obtain a first statistical value corresponding to the second parameter group; when the first statistical value corresponding to any second parameter group is greater than Y, select the second parameter group as the target parameter group, where Y is a positive integer less than or equal to X.

[0018] In one possible implementation, the second debugging unit is specifically used to: determine whether the X debugging results corresponding to each second parameter group meet a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; count the total number of debugging results corresponding to the second parameter group that meet the first preset condition to obtain a first statistical value corresponding to the second parameter group; when the first statistical value corresponding to any second parameter group is greater than Y, use the first statistical value as a second statistical value, where Y is a positive integer less than or equal to X; sort the obtained second statistical values ​​according to their numerical values, and select at least one second parameter group corresponding to at least one second statistical value with the largest numerical value as at least one target parameter group.

[0019] In one possible implementation, the debugging and selection module is specifically used to: for each first parameter group, perform one debugging operation on the chip interface based on the first parameter group; determine whether the debugging result obtained from this debugging operation meets a first preset condition, the first preset condition being that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold; when the debugging result obtained from this debugging operation meets the first preset condition, continue to perform X debugging operations on the chip interface based on the first parameter group to obtain X debugging results, where X is an integer greater than 1; determine whether each of the X debugging results meets the first preset condition, count the total number of debugging results that meet the first preset condition among the X debugging results, and obtain a third statistical value corresponding to the first parameter group; when the third statistical value corresponding to any first parameter group is greater than Y, use the third statistical value as a fourth statistical value, where Y is a positive integer less than or equal to X; sort the obtained fourth statistical values ​​according to their numerical values, and select at least one first parameter group corresponding to at least one fourth statistical value with the largest numerical value as at least one target parameter group.

[0020] In one possible implementation, the interface attribute information includes the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode. The first parameter group includes multiple parameters. The preprocessing module is specifically used to: determine the value range of each parameter based on the chip identifier of the chip to which the chip interface belongs and the expected transmission rate; obtain the multiple first parameter groups based on the value ranges of the multiple parameters, wherein at least one parameter in any two first parameter groups has a different parameter value; and determine the bit error rate threshold for each channel based on the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode.

[0021] In one possible implementation, any debugging of the chip interface includes: writing the parameter set to be used into the serializer, the serializer simultaneously outputting a test pattern to the at least one channel; resetting the deserializer and setting the parameter values ​​of the deserializer; starting the debugging of the deserializer and obtaining the status information of the at least one channel; when the status information indicates that the at least one channel is in a stable state, resetting the counting result of the deserializer; the deserializer obtaining the counting result of each channel based on the actual pattern received by each channel and the test pattern, and determining the bit error rate of the channel based on the counting result of each channel.

[0022] In one possible implementation, during any debugging of the chip interface, the serializer simultaneously outputs test patterns to multiple channels.

[0023] According to another aspect of this disclosure, a chip interface debugging apparatus is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0024] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0025] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0026] The chip interface debugging method according to embodiments of this disclosure can be used to debug chip interfaces, including serializers and deserializers. The serializer is connected to the deserializer through multiple channels. First, based on the interface attribute information of the chip interface, multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel are determined. The chip interface is then debugged according to the multiple first parameter groups. Specifically, when debugging the chip interface according to any one of the first parameter groups, the first parameter group is written to the serializer, and the serializer outputs a test pattern to at least one channel. The deserializer determines the bit error rate of each channel based on the actual pattern received from each channel and the test pattern of that channel. The resulting debugging result includes the bit error rate of at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group. Based on the debugging result and the bit error rate threshold, at least one target parameter group is selected for the serializer. Since high-end instruments such as oscilloscopes and bit error rate testers are not required, hardware costs are reduced. The software automatically selects the target parameter group, eliminating the need for manual adjustment of the parameter group or repeated iterations, achieving closed-loop automated debugging, reducing labor costs, and improving debugging efficiency. During each debugging session, if the serializer is selected to output a test pattern to a single channel, the chosen set of at least one target parameter can be applied to simple single-channel transmission scenarios. If the serializer outputs test patterns to multiple channels, the debugging can cover multiple channels between the serializer and deserializer, ensuring that crosstalk between channels is reflected in the debugging results. Therefore, the chosen set of at least one target parameter can be applied to complex multi-channel transmission scenarios. In summary, the chip interface debugging method of this disclosure can reduce hardware and labor costs, improve debugging efficiency, and enhance the adaptability of the chip interface debugging method to different application scenarios.

[0027] Furthermore, the chip interface debugging method proposed in this disclosure does not require obtaining signals through the PCB interface, and can also be used to debug the SerDes packaged inside the chip.

[0028] Furthermore, the chip interface debugging method proposed in this disclosure improves the accuracy of debugging results through phased debugging, thereby improving the accuracy of parameter group selection.

[0029] Furthermore, the chip interface debugging method proposed in this disclosure performs multiple debugging sessions on the same parameter group during debugging, which is also suitable for long-term signal transmission scenarios.

[0030] Furthermore, the chip interface debugging method proposed in this disclosure sets a bit error rate threshold for each transmission channel according to the expected transmission rate, thereby improving the accuracy of parameter group selection.

[0031] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0032] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0033] Figure 1 A schematic diagram of the structure of SerDes is shown.

[0034] Figure 2 This illustrates an exemplary application scenario of the chip interface debugging method according to embodiments of the present disclosure.

[0035] Figure 3 A schematic diagram illustrating the flow of a chip interface debugging method according to an embodiment of the present disclosure is shown.

[0036] Figure 4 This diagram illustrates a method for debugging a chip interface and selecting a target parameter group based on the debugging results, according to an embodiment of the present disclosure.

[0037] Figure 5 This diagram illustrates a process for debugging a chip interface according to an embodiment of the present disclosure.

[0038] Figure 6 This diagram illustrates the process of debugging the chip interface during the first debugging phase according to an embodiment of the present disclosure.

[0039] Figure 7 This diagram illustrates the process of debugging the chip interface during the second debugging phase according to an embodiment of the present disclosure.

[0040] Figure 8 A schematic diagram showing the structure of a chip interface debugging apparatus according to an embodiment of the present disclosure is provided.

[0041] Figure 9A block diagram of a chip interface debugging apparatus 1900 according to an embodiment of the present disclosure is shown. Detailed Implementation

[0042] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0043] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0044] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0045] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0046] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0047] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0048] The following section introduces an exemplary structure and working principle of SerDes.

[0049] Figure 1 A schematic diagram of the structure of SerDes is shown.

[0050] like Figure 1As shown, SerDes includes a serializer and a deserializer. The serializer, acting as the transmitter, includes a Feed Forward Equalizer (FFE). The deserializer, acting as the receiver, includes a Continuous Time Linear Equalizer (CTLE) and a Decision Feedback Equalizer (DFE).

[0051] The pre-equalizer is used to pre-emphasize the high-frequency components of the signal, compensating in advance for high-frequency attenuation caused by subsequent transmission signals. It also pre-compensates for known inter-symbol interference, reducing the processing load on the equalizer at the deserializer.

[0052] The signal processing effect of a pre-equalizer is affected by a variety of parameters. Taking a pre-equalizer using a Finite Impulse Response (FIR) filter structure as an example, the parameter set of the pre-equalizer can be [preN, ..., pre1, main, post1, post2, ..., postM], where N and M are positive integers. [preN, ..., pre1] is used to compensate for interference from preceding bits on the current bit. For example, pre1, also called pre-cursor 1, is used to compensate for interference from the previous bit and is usually negative or zero. The parameter main represents the weight of the current bit and is usually positive with the largest absolute value to ensure the signal has sufficient energy. [post1, post2, ..., postM] is used to compensate for interference from following bits on the current bit. For example, post1, also called post-cursor 1, is used to compensate for interference from the bit following the current bit and is usually negative. post2, also called post-cursor 2, is used to compensate for interference from the second bit following the current bit and is usually smaller. The values ​​of N and M, and the specific values ​​of [preN, ..., pre1, main, post1, post2, ..., postM] can be set according to the actual application scenario requirements of SerDes.

[0053] Continuous-time linear equalizers are used to enhance signals at high frequencies in the analog domain, compensate for high-frequency losses in the channel, and improve the amplitude and clarity of the signal through adjustable frequency response.

[0054] Decision feedback equalizers are used to eliminate inter-symbol interference, especially interference from the later bit to the current bit.

[0055] The existing approach to debugging SerDes is as follows: A transmission channel is selected, and the serializer's parameter set is configured based on this channel. The serializer's parameter set includes the pre-equalizer's parameter set. The serializer outputs the signal to the pre-equalizer for pre-emphasis and other processing. The pre-equalizer outputs the signal through the selected transmission channel to the continuous-time linear equalizer at the deserializer. The continuous-time linear equalizer performs high-frequency enhancement and other processing on the signal before outputting it to the decision feedback equalizer. The decision feedback equalizer further eliminates inter-symbol interference and then compares the output signal with the initial signal to calculate the bit error rate (BER).

[0056] Currently, SerDes debugging is still primarily manual. It requires manually setting the serializer's parameter set according to the pre-selected transmission channel, transmitting the signal through the selected channel, observing the signal's eye diagram with an oscilloscope, and repeatedly adjusting the parameter values ​​in the serializer's parameter set to maximize the eye height / eye width. Then, a Bit Error Rate Tester (BERT) is used to verify the bit error rate (BER) of the signal finally processed by the deserializer. Since the BER may not meet the requirements, the above process may need to be repeated multiple times until the BER meets the requirements.

[0057] The disadvantages of the existing SerDes debugging method are as follows:

[0058] 1. Manual debugging increases labor costs and reduces debugging efficiency.

[0059] 2. Oscilloscopes and bit error rate testers are both high-end instruments, which increases hardware costs.

[0060] 3. Oscilloscopes can only display the eye diagram of the signal under the current parameters. They cannot compare the eye diagrams before and after parameter group adjustments, nor can they automatically compare the advantages and disadvantages of different parameter groups. Manual comparison by engineers is required. In this situation, how to adjust the serializer parameter group to improve signal quality depends entirely on the engineer's experience, which is prone to misjudgment, resulting in worse effects after parameter group adjustments and reduced debugging efficiency.

[0061] 4. Multiple transmission channels exist between the serializer and deserializer. In real-world scenarios, the signal transmission environment is highly complex, and multiple channels may operate simultaneously, causing crosstalk. Clock deviations in each transmission channel also affect signal transmission. The above debugging method utilizes only a single transmission channel and does not consider the impact of crosstalk and clock deviations. Therefore, the obtained eye diagrams and bit error rates will differ from those in actual scenarios. Furthermore, variations in chip manufacturing processes, voltage, and temperature (PVT) can affect signal quality, and these effects are difficult to detect in the short term. The parameter sets obtained through each adjustment in the above debugging method are applied for relatively short periods, resulting in poor adaptability to long-term signal transmission scenarios.

[0062] 5. Oscilloscopes acquire signals from chips through the printed circuit board (PCB) interface. In some applications, such as die-to-die (D2D) interconnection, multiple dies can be packaged in the same chip, and the dies can communicate directly at high speed. In this case, the serializer and deserializer are packaged inside the chip, and the signals transmitted between the serializer and deserializer are not output to the PCB interface. Under these circumstances, it is impossible to use an oscilloscope to obtain eye diagrams.

[0063] In view of this, this disclosure proposes a chip interface debugging method, apparatus, storage medium, and program product. The chip interface debugging method of this disclosure can reduce hardware and labor costs, improve debugging efficiency, and enhance the adaptability of the chip interface debugging method to different application scenarios.

[0064] Furthermore, the chip interface debugging method proposed in this disclosure does not require obtaining signals through the PCB interface, and can also be used to debug the SerDes packaged inside the chip.

[0065] Furthermore, the chip interface debugging method proposed in this disclosure improves the accuracy of debugging results through phased debugging, thereby improving the accuracy of parameter group selection.

[0066] Furthermore, the chip interface debugging method proposed in this disclosure performs multiple debugging sessions on the same parameter group during debugging, which is also suitable for long-term signal transmission scenarios.

[0067] Furthermore, the chip interface debugging method proposed in this disclosure sets a bit error rate threshold for each transmission channel according to the expected transmission rate, thereby improving the accuracy of parameter group selection.

[0068] Figure 2 This illustrates an exemplary application scenario of the chip interface debugging method according to embodiments of the present disclosure.

[0069] like Figure 2 As shown, the chip interface debugging method can be applied to a central controller. The central controller connects to the serializer and deserializer of the SerDes. The SerDes can be 112G PAM4, 106G PAM4, 100G PAM4, 56G PAM4, 56G NRZ, etc., and this disclosure does not limit the specific type of SerDes. The central controller can communicate with the serializer and deserializer through protocols such as Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), and Joint Test Action Group (JTAG), for example, issuing commands / data to the serializer and deserializer, and receiving data from the serializer and deserializer.

[0070] The serializer includes a test pattern generation module and a pre-equalizer. The test pattern generation module generates test patterns, which can be pseudo-random binary sequences (PRBS) or other custom patterns (such as all 0s, all 1s, alternating sequences, etc.). Commonly used PRBSs include PRBS7, PRBS15, PRBS23, and PRBS31. This disclosure does not limit the specific form of the test pattern. The function of the pre-equalizer can be found in [reference needed]. Figure 1 The relevant descriptions are omitted here. The parameters of the test code and pre-equalizer can be configured via commands issued by the central processing unit. An example of the pre-equalizer parameter groups can be found in [link to relevant documentation]. Figure 1 In practical applications, the parameter set of the pre-equalizer may include more or fewer parameters. This disclosure does not limit the specific parameters included in the parameter set of the pre-equalizer.

[0071] The deserializer includes a continuous-time linear equalizer, a decision feedback equalizer, and a code pattern checking module. The functions of the continuous-time linear equalizer and the decision feedback equalizer can be found in [link to documentation]. Figure 1 The relevant descriptions are not repeated here. The debugging of the deserializer can be initiated by a command issued by the central controller. The test pattern checking module is used to determine the debugging results, including the bit error rate. The debugging results of the deserializer can be uploaded to the central controller. Specifically, the test pattern checking module compares the received actual pattern with the test pattern, counts the number of inconsistent bits, and then calculates the total number of transmitted bits using the transmission rate and transmission time. The number of inconsistent bits divided by the total number of bits is the bit error rate. This disclosure does not limit the specific method by which the test pattern checking module calculates the bit error rate. In this way, a mapping relationship between the parameter set and the bit error rate can be established.

[0072] The debugging results may also include eye diagrams and inter-symbol interference (ISI). The test pattern checking module can incorporate existing hardware components to obtain eye diagrams and ISI. This disclosure does not limit the specific method by which the test pattern checking module obtains eye diagrams and ISI. The bit error rate, eye diagrams, and ISI obtained by the test pattern checking module can be stored in a file and reported to the user when needed.

[0073] The central controller executes a chip interface method to determine multiple candidate first parameter groups for the serializer's pre-equalizer. Each first parameter group includes various parameters of the serializer's pre-equalizer, and at least one parameter in any two first parameter groups has a different value. The serializer and deserializer are debugged using each first parameter group, and based on the debugging results, at least one target parameter group with a low bit error rate is selected. The selected target parameter group can be reported to the user, who can then further select the corresponding parameter group for each transmission channel. Notably, any two transmission channels can ultimately select the same parameter group or different parameter groups.

[0074] Figure 3 A schematic diagram illustrating the flow of a chip interface debugging method according to an embodiment of the present disclosure is shown.

[0075] like Figure 3 As shown, in one possible implementation, the chip interface includes a serializer and a deserializer, the serializer being connected to the deserializer through multiple channels, and the method includes:

[0076] Step S31: Based on the interface attribute information of the chip interface, determine multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel.

[0077] Step S32: Debug the chip interface according to multiple first parameter groups, and select at least one target parameter group for the serializer according to the debugging results and the bit error rate threshold.

[0078] Specifically, when the chip interface is debugged once according to any first parameter group, the first parameter group is written into the serializer, the serializer outputs a test code pattern to at least one channel, the deserializer determines the bit error rate of the channel based on the actual code pattern received from each channel and the test code pattern of that channel, and the obtained debugging result includes the bit error rate of at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group.

[0079] For example, the chip interface debugging method is used to select parameter groups for the equalizer (pre-equalizer) in the serializer. The types of parameters used by the pre-equalizer have been introduced above and will not be repeated here.

[0080] In step S31, multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel can be determined based on the interface attribute information of the chip interface.

[0081] Interface attribute information can indicate the location of the chip to which the chip interface belongs in the electronic device, the expected transmission rate of each channel, etc. Based on the interface attribute information, the value range of each parameter can be determined. By traversing the value range of each parameter, multiple first parameter groups can be obtained.

[0082] For example, assuming there are two parameters, parameter 1 has a value range of [1,2] and parameter 2 has a value range of [2,3], then four sets of first parameters can be determined, as shown in Table 1.

[0083] Table 1

[0084]

[0085] The correlation between the bit error rate threshold and interface attribute information can be preset, and this embodiment does not limit the correlation between the bit error rate threshold and interface attribute information. During step S31, the bit error rate threshold corresponding to the interface attribute information can be found based on the preset correlation. The bit error rate thresholds for each channel can be the same or different.

[0086] In step S32, the serializer and deserializer can be debugged according to multiple first parameter groups, with each first parameter group corresponding to at least one debugging session. At least one of the multiple channels can be selected to participate in the debugging process based on application requirements. When any debugging session is performed on the chip interface according to any first parameter group, that first parameter group is written to the serializer, and the serializer outputs a test code pattern to at least one channel participating in the debugging process, while channels not participating in the debugging process remain idle.

[0087] When the test pattern is transmitted on the channel, it may experience bit errors due to factors such as crosstalk, loss, PVT variations, and clock skew, causing the actual pattern received by the deserializer from the channel to differ from the test pattern. The deserializer can determine the bit error rate (BER) of each channel based on the actual BER received and the test pattern. The method by which the deserializer determines the BER has been described above and will not be repeated here. The result of each debugging session includes the BER of at least one channel involved in the debugging. The result of each debugging session is used to determine whether the first parameter set used for debugging is selected as the target parameter set.

[0088] Based on the debugging results and the bit error rate threshold, at least one target parameter group can be selected for the serializer from multiple first parameter groups. This disclosure does not limit the specific selection method of the parameter groups. For example, certain conditions can be preset, such as the first preset condition described below. Based on the debugging results and the bit error rate threshold, it is determined whether the debugging result corresponding to each first parameter group meets the preset conditions. If the preset conditions are met, the bit error rate can be considered low. The target parameter group can be selected from the first parameter groups whose corresponding debugging results meet the preset conditions. Exemplary selection methods for the target parameter group are given below.

[0089] The chip interface debugging method according to embodiments of this disclosure can be used to debug chip interfaces, including serializers and deserializers. The serializer is connected to the deserializer through multiple channels. First, based on the interface attribute information of the chip interface, multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel are determined. The chip interface is then debugged according to the multiple first parameter groups. Specifically, when debugging the chip interface according to any one of the first parameter groups, the first parameter group is written to the serializer, and the serializer outputs a test pattern to at least one channel. The deserializer determines the bit error rate of each channel based on the actual pattern received from each channel and the test pattern of that channel. The resulting debugging result includes the bit error rate of at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group. Based on the debugging result and the bit error rate threshold, at least one target parameter group is selected for the serializer. Since high-end instruments such as oscilloscopes and bit error rate testers are not required, hardware costs are reduced. The software automatically selects the target parameter group, eliminating the need for manual adjustment of the parameter group or repeated iterations, achieving closed-loop automated debugging, reducing labor costs, and improving debugging efficiency. During each debugging session, if the serializer is selected to output a test pattern to a single channel, the chosen set of at least one target parameter can be applied to simple single-channel transmission scenarios. If the serializer outputs test patterns to multiple channels, the debugging can cover multiple channels between the serializer and deserializer, ensuring that crosstalk between channels is reflected in the debugging results. Therefore, the chosen set of at least one target parameter can be applied to complex multi-channel transmission scenarios. In summary, the chip interface debugging method of this disclosure can reduce hardware and labor costs, improve debugging efficiency, and enhance the adaptability of the chip interface debugging method to different application scenarios.

[0090] In one possible implementation, during any debugging of the chip interface, the serializer simultaneously outputs test patterns to multiple channels. This ensures that crosstalk exists between channels during chip interface debugging, making the debugging process consistent with the actual data transmission scenario of the chip interface.

[0091] The following describes an example of the content of the interface attribute information, and an example of how to determine multiple first parameter groups and the bit error rate threshold for each channel based on the interface attribute information.

[0092] In one possible implementation, the interface attribute information includes the chip identifier of the chip to which the chip interface belongs, the interface identifier within the chip, the desired transmission rate, and the signal modulation mode. The first parameter group includes multiple parameters.

[0093] Step S31 includes:

[0094] Determine the value range of each parameter based on the chip identifier of the chip to which the chip interface belongs and the expected transmission rate;

[0095] Based on the range of values ​​of various parameters, multiple first parameter groups are obtained, and the parameter values ​​of at least one parameter in any two first parameter groups are different;

[0096] The bit error rate threshold for each channel is determined based on the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode.

[0097] For example, interface attribute information includes the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode.

[0098] The serializer and deserializer can be located on different chips or on the same chip. When the serializer and deserializer are located on different chips, the chip identifier of the chip to which the chip interface belongs can include the identifier of the chip to which the serializer belongs and the identifier of the chip to which the deserializer belongs.

[0099] A single chip may contain multiple serializers, which are connected to multiple deserializers on another chip. Multiple pairs of serializers and deserializers may also exist on the same chip. Each serializer and each deserializer has a unique interface identifier within the chip. In this case, the interface attribute information may also include the interface identifier of the chip interface within its respective chip, that is, the interface identifier of the serializers and the interface identifier of the deserializers included in the chip interface.

[0100] Based on the chip identifier of the chip to which the chip interface belongs and the interface identifier of the chip interface in the chip, it is possible to determine which chip interface needs to be debugged.

[0101] The expected transmission rate represents the expected number of bits transmitted per second, measured in Gbps.

[0102] The signal modulation mode can be 4-level pulse amplitude modulation (PAM4) or non-return-to-zero (NRZ), etc.

[0103] In step S31, the value range of each parameter of the serializer's equalizer (pre-equalizer) is first determined based on the chip identifier of the chip to which the chip interface belongs and the desired transmission rate. The correlation between the chip identifier of the chip to which the chip interface belongs, the desired transmission rate, and the value ranges of different parameters can be predetermined and stored in the form of a lookup table. The value range of the parameter can be directly looked up in the lookup table based on the chip identifier of the chip to which the chip interface belongs and the desired transmission rate. This embodiment of the present disclosure does not limit the type of correlation between the chip identifier of the chip to which the chip interface belongs, the desired transmission rate, and the value ranges of different parameters.

[0104] Based on the value ranges of various parameters, multiple sets of first parameters can be obtained, and the parameter values ​​of at least one parameter in any two sets of first parameters are different. Examples of methods for obtaining multiple sets of first parameters based on the value ranges of various parameters can be found in Table 1 and related descriptions, and will not be repeated here.

[0105] The bit error rate (BER) threshold for each channel can be determined based on the chip identifier of the chip to which the chip interface belongs, the interface identifier of the chip interface within its chip, the expected transmission rate, and the signal modulation mode. The correlation between the chip identifier of the chip to which the chip interface belongs, the interface identifier of the chip interface within its chip, the expected transmission rate, the signal modulation mode, and the BER threshold for each channel can be predetermined and stored in the form of a lookup table. The BER threshold for each channel can be directly retrieved from the lookup table based on the chip identifier of the chip to which the chip interface belongs, the interface identifier of the chip interface within its chip, the expected transmission rate, and the signal modulation mode. This embodiment of the present disclosure does not limit the type of correlation between the chip identifier of the chip to which the chip interface belongs, the interface identifier of the chip interface within its chip, the expected transmission rate, the signal modulation mode, and the BER threshold for each channel.

[0106] Those skilled in the art will understand that the interface attribute information may include more or less content, as long as the multiple first parameter groups of the serializer and the bit error rate threshold of each channel can be determined based on the interface attribute information. This disclosure does not limit the specific content of the interface attribute information or the specific method for determining the multiple first parameter groups and the bit error rate threshold of each channel.

[0107] Setting a bit error rate threshold for each transmission channel based on the desired transmission rate improves the accuracy of selecting parameter groups using the bit error rate threshold.

[0108] The following describes an exemplary method for debugging the chip interface and selecting the target parameter group based on the debugging results. Figure 4 This diagram illustrates a method for debugging a chip interface and selecting a target parameter group based on the debugging results, according to an embodiment of the present disclosure.

[0109] like Figure 4 As shown, in one possible implementation, the process of debugging the chip interface according to multiple first parameter sets includes a first debugging phase and a second debugging phase.

[0110] The chip interface is debugged based on multiple first parameter sets. Based on the debugging results and the bit error rate threshold, at least one target parameter set is selected for the serializer, including:

[0111] In the first debugging phase, the chip interface is debugged according to multiple first parameter groups, with each first parameter group corresponding to one debugging session and one debugging result. Based on the debugging results of the first debugging phase and the bit error rate threshold, at least one second parameter group is selected for the serializer from the multiple first parameter groups.

[0112] In the second debugging phase, the chip interface is debugged according to at least one second parameter group. Each second parameter group corresponds to X debugging times and X debugging results, where X is an integer greater than 1. Based on the debugging results of the second debugging phase and the bit error rate threshold, at least one target parameter group is selected for the serializer from at least one second parameter group.

[0113] For example, the debugging of the chip interface can be divided into two stages. Staged debugging improves the accuracy of the debugging results, thereby improving the accuracy of parameter group selection.

[0114] In the first debugging phase, the chip interface is debugged according to multiple first parameter groups, with each first parameter group corresponding to one debugging session and one debugging result. Based on the debugging results of the first debugging phase and the bit error rate threshold, at least one second parameter group is selected for the serializer from the multiple first parameter groups. Since each first parameter group corresponds to only one debugging session in the first debugging phase, the debugging results of the first debugging phase are suitable for short-term data transmission, and it can be considered that at least one second parameter group selected in the first debugging phase is suitable for short-term data transmission scenarios.

[0115] The following describes an exemplary process for debugging the chip interface once. Figure 5 This diagram illustrates a process for debugging a chip interface according to an embodiment of the present disclosure.

[0116] like Figure 5 As shown, in one possible implementation, any debugging of the chip interface includes:

[0117] Step S51: Write the parameter set to be used into the serializer, and the serializer outputs the test code pattern to at least one channel at the same time.

[0118] Step S52: Reset the deserializer and set its parameter values;

[0119] Step S53: Start the debugging of the deserializer and obtain the status information of at least one channel;

[0120] Step S54: When the status information indicates that at least one channel is in a stable state, reset the counting result of the deserializer;

[0121] In step S55, the deserializer obtains the counting result of each channel based on the actual code pattern and the test code pattern received by each channel, and determines the bit error rate of the channel based on the counting result of each channel.

[0122] For example, when performing any debugging of the serializer and deserializer based on any set of parameters, the central controller can first write that set of parameters into the serializer. Exemplarily, this set of parameters can be written into the serializer's register. The serializer then runs the pre-equalizer based on the set of parameters written into the register, outputting a test pattern to at least one channel participating in the debugging. The output test pattern can be a test pattern processed by the pre-equalizer.

[0123] The central controller can reset the deserializer and set its parameters, such as insertion loss. Afterward, the central controller initiates debugging of the deserializer, acquiring the status information of each channel involved in the debugging process. This status information indicates whether the channel is stable.

[0124] The deserializer may include multiple counters (not shown) to count the number of bits that do not match the actual code pattern received from each channel after comparison with the test code pattern, thus obtaining a count result for each channel. The deserializer can determine the bit error rate (BER) of each channel based on the count result. For example, the counters may be set in the test result checking module, and the BER is determined by the test result checking module. An exemplary calculation method for the BER can be found in [link to documentation]. Figure 2 Related descriptions.

[0125] It should be understood that when a channel is unstable, more bits are transmitted incorrectly, leading to a higher counting result. Therefore, the bit error rate determined using this counting result will also be higher. Thus, when the status information indicates that all channels involved in the debugging are stable, the deserializer's counting result can be reset. After waiting for a certain period of data transmission, the counting result can be used to determine the bit error rate, thereby improving the accuracy of the bit error rate determination.

[0126] Optionally, a time limit for acquiring status information can be preset, such as a first duration. The timer starts from the start of debugging the deserializer. If the channel being debugged is still unstable after the first duration, the current parameter group can be discarded, and the next parameter group can be used to debug the chip interface, thereby improving debugging efficiency. The first duration can be set according to application scenario requirements; this disclosure does not impose any restrictions on the specific value of the first duration.

[0127] In real-world applications, debugging a chip interface may involve more or fewer steps. Figure 6 This diagram illustrates the process of debugging the chip interface during the first debugging phase according to an embodiment of the present disclosure.

[0128] For example, although the parameters in each first parameter group are supported by the serializer, the combination of multiple parameters may exceed the serializer's capabilities. This could lead to excessive load or overheating of the serializer during a single debugging session. Using such parameter groups for debugging will likely result in the debugging process ending because the required status information is not obtained within the first duration. Therefore, based on the serializer's capabilities and the duration of a single debugging session, pre-set appropriate judgment conditions can be implemented so that the parameter group, when applied to the serializer, can complete one debugging session when the judgment conditions are met. And so on... Figure 6 As shown, in the first debugging phase, before starting to debug the chip interface using a certain first parameter group, it is determined whether the first parameter group meets the judgment conditions. The specific judgment conditions can be determined based on existing technology, and this disclosure embodiment does not limit them.

[0129] If the condition is met, the first parameter group is written to the serializer's register, the deserializer is reset, the deserializer's insertion loss and other parameters are set, debugging of the deserializer is started, and the status information of each channel is obtained. If the condition is not met, the next first parameter group is used directly for debugging.

[0130] As mentioned above, the debugging timer starts from the start of the deserializer debugging. If the channel involved in the debugging is still unstable after the first duration, the debugging of the current first parameter group can be terminated. Furthermore, the debugging results of the current first parameter group can be recorded, such as the debugging ending due to the failure to obtain the required status information within the first duration. When needed, these debugging results can be used for further analysis and adjustment of the debugging process. For example, if the analysis finds that the debugging has ended too many times due to the failure to obtain the required status information within the first duration, the value of the first duration can be increased.

[0131] When the status information indicates that all channels participating in the debugging are stable, the interval between the current time and the time when the deserializer debugging was started can also be recorded in the debugging results of the first parameter group of the current group during the first debugging phase. If necessary, the debugging process can be further analyzed and adjusted based on the debugging results. For example, if too many first parameter groups are selected during the first debugging phase, the value of the first duration can be adjusted to reduce it based on the interval between the current time and the time when the deserializer debugging was started recorded in each debugging result.

[0132] When the status information indicates that all channels involved in the debugging are stable, the deserializer's count can be reset. Wait for a period of time so that the deserializer can obtain the count for each channel based on the actual and test code patterns received by each channel. Optionally, it can also obtain information such as eye height and inter-symbol interference. Then, determine the bit error rate of each channel based on its count.

[0133] In one possible implementation, based on the debugging results of the first debugging phase and the bit error rate threshold, at least one second parameter set is selected for the serializer from a plurality of first parameter sets, including:

[0134] Determine whether the debugging result corresponding to each first parameter group meets the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold.

[0135] When the debugging result corresponding to any of the first parameter groups meets the first preset condition, the first parameter group is selected as the second parameter group.

[0136] For example, in the first debugging phase, after debugging the chip interface using any first parameter group, it can be determined whether to select that first parameter group based on the calculated bit error rate and bit error rate threshold of each channel.

[0137] For example, such as Figure 6 As shown, in the first debugging phase, after obtaining the debugging results corresponding to the current first parameter group, it can be determined whether the debugging results of the first parameter group meet the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold. If the debugging results of the first parameter group meet the first preset condition, then the first parameter group is selected as the second parameter group. Further, if the current first parameter group is selected as the second parameter group, a first parameter storage file corresponding to this debugging can be generated. The file name of this file may include interface attribute information, and the first parameter group can be recorded in the first parameter storage file. In this case, the first parameter groups recorded in all the first parameter storage files generated in the first debugging phase are at least one second parameter group selected in the first debugging phase. Different first parameter storage files can be generated for different channels.

[0138] It can generate a debugging result storage file corresponding to this debugging session. The file name can include interface attribute information, and debugging-related information such as the expected transmission rate, mode, inter-symbol interference, eye height, and bit error rate can be recorded in the generated debugging result storage file. Different debugging result storage files can be generated for different channels. The bit error rate and other information for each channel are stored in its corresponding debugging result storage file.

[0139] The first parameter storage file and the debug result storage file can be in CSV format. Then, use the next first parameter group to debug the chip interface.

[0140] If the debugging result obtained by the current first parameter group in the first debugging stage does not meet the first preset condition, then the current first parameter group will not be selected, and the next first parameter group will be used directly to debug the chip interface.

[0141] In this way, the reliability of the selection results in the first debugging phase can be guaranteed.

[0142] In the second debugging phase, the chip interface can be debugged according to at least one second parameter group. Each second parameter group corresponds to X debugging attempts and X debugging results, where X is an integer greater than 1. Based on the debugging results of the second debugging phase and the bit error rate threshold, at least one target parameter group is selected for the serializer from the at least one second parameter group. Since each second parameter group corresponds to multiple debugging attempts in the second debugging phase, the debugging results of the second debugging phase are also compatible with long-term data transmission. The at least one target parameter group selected in the second debugging phase is suitable not only for short-term data transmission scenarios but also for long-term data transmission scenarios.

[0143] Figure 7 This diagram illustrates the process of debugging the chip interface during the second debugging phase according to an embodiment of the present disclosure.

[0144] like Figure 7 As shown, the second debugging phase can perform X rounds of debugging. Each round of debugging follows the same process as the first debugging phase. That is, in each round of debugging, the chip interface is debugged using each second parameter group selected in the first debugging phase. Each second parameter group corresponds to one debugging session and one debugging result. Since there are a total of X rounds of debugging, each second parameter group corresponds to X debugging sessions and X debugging results in the second debugging phase.

[0145] Since each second parameter group participates in debugging more times in the second debugging phase, the requirements for the serializer's capabilities are also higher. Therefore, the judgment conditions used in the second debugging phase can be different from those used in the first debugging phase. For example, if the judgment conditions used in the second debugging phase are met, it can be considered that the serializer can complete at least X debugging cycles when the second parameter group is applied to it. The specific judgment conditions can be determined based on existing technology, and this disclosure does not limit them.

[0146] The control of the serializer and deserializer in the second debugging phase is the same as in the first debugging phase, and will not be repeated here. The following describes an exemplary method for processing the debugging results in the second debugging phase.

[0147] In one possible implementation, based on the debugging results of the second debugging phase and the bit error rate threshold, at least one target parameter set is selected for the serializer from at least one second parameter set, including:

[0148] Determine whether the X debugging results corresponding to each second parameter group meet the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold.

[0149] The total number of debugging results that meet the first preset conditions corresponding to the second parameter group is counted to obtain the first statistical value corresponding to the second parameter group;

[0150] If the first statistical value corresponding to any second parameter group is greater than Y, then select that second parameter group as the target parameter group, where Y is a positive integer less than or equal to X.

[0151] For example, in the second debugging phase, after debugging the chip interface using the second parameter group selected in the first debugging phase, the target parameter group can be selected based on the debugging results and the bit error rate threshold of each channel.

[0152] For example, such as Figure 7 As shown, determine whether the X debugging results corresponding to each second parameter group meet the first preset condition.

[0153] If at least Y out of the X debugging attempts corresponding to the current second parameter group satisfy the first preset condition, then the current second parameter group can be considered to have a high degree of matching with the long-term data transmission scenario. Therefore, the total number of debugging results that satisfy the first preset condition corresponding to each second parameter group can be counted to obtain the first statistical value corresponding to that second parameter group; when the first statistical value corresponding to any second parameter group is greater than Y, that second parameter group is selected as the target parameter group.

[0154] Y is a positive integer less than or equal to X. The value of Y can be set according to the application scenario requirements, for example, set to 1. This embodiment does not limit the specific value of Y.

[0155] At least one set of target parameters selected during the second debugging phase can be stored in a mass production optimization parameter set in CSV format.

[0156] In this way, at least one set of target parameters selected in the second debugging phase is matched with a long-term data transmission scenario.

[0157] In one possible implementation, based on the debugging results of the second debugging phase and the bit error rate threshold, at least one target parameter set is selected for the serializer from at least one second parameter set, including:

[0158] Determine whether the X debugging results corresponding to each second parameter group meet the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold.

[0159] The total number of debugging results that meet the first preset conditions corresponding to the second parameter group is counted to obtain the first statistical value corresponding to the second parameter group;

[0160] When the first statistical value corresponding to any second parameter group is greater than Y, the first statistical value is taken as the second statistical value, where Y is a positive integer less than or equal to X;

[0161] Sort the obtained second statistical values ​​according to their numerical values, and select at least one second parameter group corresponding to at least one second statistical value with the largest value as at least one target parameter group.

[0162] It should be understood that the larger the total number of debugging results corresponding to the second parameter group that meet the first preset condition, the better the transmission effect of the second parameter group in long-term data transmission scenarios. Therefore, when the first statistical value corresponding to any second parameter group is greater than Y, the first statistical value can be used as the second statistical value; the obtained second statistical values ​​can be sorted according to their numerical values, and at least one second parameter group corresponding to at least one second statistical value with the largest value can be selected as at least one target parameter group.

[0163] The number of second statistical values ​​selected in this step can be preset and adjusted according to the actual situation. This embodiment of the disclosure does not limit this.

[0164] For example, the second statistical value of the first second parameter group is equal to 5, the second statistical value of the second second parameter group is equal to 4, and the second statistical value of the third second parameter group is equal to 3. This step can be configured to select two second statistical values, meaning the selected values ​​could be the second statistical values ​​of the first and second second parameter groups.

[0165] In this way, the selected target parameter set is more closely matched with long-term data transmission scenarios.

[0166] Furthermore, if the result of a certain second parameter group's debugging in a particular debugging session meets the first preset condition, a second parameter storage file corresponding to this debugging session can be generated. The file name may include interface debugging information, debugging rounds, etc., and the second parameter group is recorded in the generated second parameter storage file. Different second parameter storage files can be generated for different channels.

[0167] It can generate a debugging result storage file corresponding to this debugging session. The file name can include interface debugging information, debugging rounds, etc. The second parameter set used in this debugging session, as well as information such as expected transmission rate, mode, inter-symbol interference, eye height, and bit error rate, can be recorded in the generated debugging result storage file. Different debugging result storage files can be generated for different channels. The bit error rate and other information for each channel are stored in their respective debugging result storage files. The second parameter storage file and the debugging result storage file can be in CSV format, facilitating mass production testing and parameter solidification.

[0168] During the statistical analysis, relevant second parameter storage files can be identified from the second parameter storage files generated during the second debugging phase, based on the interface attribute information. For example, storage files with the same interface attribute information in their filenames can be identified. For each second parameter group stored in the identified second parameter storage files, the debugging result storage files generated during the second debugging phase are analyzed. The number of times the X debugging results corresponding to that second parameter group satisfy the first preset condition is counted, which is the first statistical value of that second parameter group. If the statistical value is greater than Y, the first statistical value is used as the second statistical value. After all second parameter groups have their corresponding first statistical values ​​counted, the second statistical values ​​are sorted, and at least one second parameter group corresponding to the largest second statistical value is selected as at least one target parameter group. For example, when sorting the second statistical values ​​in descending order of value, the first second statistical value in the sorted order can be selected. It should be understood that the sorting method can also be to sort the second statistical values ​​in ascending order of value, as long as the largest second statistical value can be selected after sorting. This embodiment of the present disclosure does not limit the specific method of sorting the second statistical values.

[0169] In this way, the reliability of the selection results in the second debugging phase can be guaranteed.

[0170] In one possible implementation, the first second parameter group can be debugged X times, then the second second parameter group can be debugged X times, and so on, until the last second parameter group has been debugged X times. This disclosure does not limit the specific debugging process for the second debugging stage.

[0171] It should be understood that if the application scenario involves only short-term data transmission, then when debugging the chip interface based on multiple first parameter sets, only the first debugging stage needs to be performed, without the second debugging stage. Correspondingly, at least one second parameter set can serve as at least one target parameter set. Similarly, if the application scenario requires only long-term data transmission, only the second debugging stage can be performed, without the first debugging stage. In this case, all first parameter sets become second parameter sets.

[0172] The following describes another exemplary method for debugging the chip interface.

[0173] In one possible implementation, the chip interface is debugged based on multiple first parameter sets, and at least one target parameter set is selected for the serializer based on the debugging results and a bit error rate threshold, including:

[0174] For each first parameter group, the chip interface is debugged once according to the first parameter group;

[0175] Determine whether the debugging result obtained in this debugging meets the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold.

[0176] When the debugging result obtained in this debugging meets the first preset condition, the chip interface is debugged X times according to the first parameter group to obtain X debugging results, where X is an integer greater than 1;

[0177] Determine whether each of the X debugging results meets the first preset condition, count the total number of debugging results that meet the first preset condition among the X debugging results, and obtain the third statistical value corresponding to the first parameter group;

[0178] If any third statistical value corresponding to the first parameter group is greater than Y, then the third statistical value is taken as the fourth statistical value, where Y is a positive integer less than or equal to X;

[0179] Sort the obtained fourth statistical values ​​according to their numerical values, and select at least one first parameter group corresponding to at least one fourth statistical value with the largest value as at least one target parameter group.

[0180] For example, for each first parameter group, the chip interface can be debugged once using that first parameter group. If the result of this debugging of the first parameter group meets the first preset condition, then the chip interface can be debugged X times using the first parameter group, resulting in X debugging results. Based on the results of the X debugging times and the bit error rate threshold, the number of times the X debugging results of the first parameter group meet the first preset condition is counted to obtain a third statistical value. When the third statistical value corresponding to the first parameter group is greater than Y, the third statistical value is used as the fourth statistical value. Then, the above process is repeated for the next first parameter group until debugging is completed using each first parameter group. Then, the fourth statistical values ​​are sorted according to their values, and at least one fourth statistical value with the largest value is selected. The at least one first parameter group corresponding to the selected fourth statistical value is used as the target parameter group.

[0181] This disclosure does not limit the specific implementation of debugging the chip interface based on multiple first parameter groups and selecting at least one target parameter group for the serializer based on the debugging results and bit error rate threshold, as long as the debugging results and selection results match the application scenario requirements.

[0182] This disclosure provides a chip interface debugging device. Figure 8 A schematic diagram showing the structure of a chip interface debugging apparatus according to an embodiment of the present disclosure is provided.

[0183] In one possible implementation, such as Figure 8 As shown, the chip interface includes a serializer and a deserializer. The serializer is connected to the deserializer through multiple channels. The device includes:

[0184] The preprocessing module 81 is used to determine multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel based on the interface attribute information of the chip interface.

[0185] The debugging and selection module 82 is used to debug the chip interface according to multiple first parameter groups, and select at least one target parameter group for the serializer according to the debugging results and the bit error rate threshold. When the chip interface is debugged according to any first parameter group, the first parameter group is written to the serializer, the serializer outputs a test code pattern to at least one channel, the deserializer determines the bit error rate of the channel according to the actual code pattern received from each channel and the test code pattern of the channel, and the obtained debugging result includes the bit error rate of at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group.

[0186] In one possible implementation, the process of debugging the chip interface according to the plurality of first parameter groups includes a first debugging stage and a second debugging stage. The debugging and selection module includes a first debugging unit and a second debugging unit. The first debugging unit is used to: in the first debugging stage, debug the chip interface according to the plurality of first parameter groups, each first parameter group corresponding to one debugging session and one debugging result; and select at least one second parameter group for the serializer from the plurality of first parameter groups based on the debugging result of the first debugging stage and the bit error rate threshold. The second debugging unit is used to: in the second debugging stage, debug the chip interface according to the at least one second parameter group, each second parameter group corresponding to X debugging sessions and X debugging results, where X is an integer greater than 1; and select at least one target parameter group for the serializer from the at least one second parameter group based on the debugging result of the second debugging stage and the bit error rate threshold.

[0187] In one possible implementation, the first debugging unit is specifically used to determine whether the debugging result corresponding to each first parameter group meets a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold; when the debugging result corresponding to any first parameter group meets the first preset condition, the first parameter group is selected as the second parameter group.

[0188] In one possible implementation, the second debugging unit is specifically used to: determine whether the X debugging results corresponding to each second parameter group meet a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; count the total number of debugging results corresponding to the second parameter group that meet the first preset condition to obtain a first statistical value corresponding to the second parameter group; when the first statistical value corresponding to any second parameter group is greater than Y, select the second parameter group as the target parameter group, where Y is a positive integer less than or equal to X.

[0189] In one possible implementation, the second debugging unit is specifically used to: determine whether the X debugging results corresponding to each second parameter group meet a first preset condition, wherein the first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold; count the total number of debugging results corresponding to the second parameter group that meet the first preset condition to obtain a first statistical value corresponding to the second parameter group; when the first statistical value corresponding to any second parameter group is greater than Y, use the first statistical value as a second statistical value, where Y is a positive integer less than or equal to X; sort the obtained second statistical values ​​according to their numerical values, and select at least one second parameter group corresponding to at least one second statistical value with the largest numerical value as at least one target parameter group.

[0190] In one possible implementation, the debugging and selection module is specifically used to: for each first parameter group, perform one debugging operation on the chip interface based on the first parameter group; determine whether the debugging result obtained from this debugging operation meets a first preset condition, the first preset condition being that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold; when the debugging result obtained from this debugging operation meets the first preset condition, continue to perform X debugging operations on the chip interface based on the first parameter group to obtain X debugging results, where X is an integer greater than 1; determine whether each of the X debugging results meets the first preset condition, count the total number of debugging results that meet the first preset condition among the X debugging results, and obtain a third statistical value corresponding to the first parameter group; when the third statistical value corresponding to any first parameter group is greater than Y, use the third statistical value as a fourth statistical value, where Y is a positive integer less than or equal to X; sort the obtained fourth statistical values ​​according to their numerical values, and select at least one first parameter group corresponding to at least one fourth statistical value with the largest numerical value as at least one target parameter group.

[0191] In one possible implementation, the interface attribute information includes the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode. The first parameter group includes multiple parameters. The preprocessing module is specifically used to: determine the value range of each parameter based on the chip identifier of the chip to which the chip interface belongs and the expected transmission rate; obtain the multiple first parameter groups based on the value ranges of the multiple parameters, wherein at least one parameter in any two first parameter groups has a different parameter value; and determine the bit error rate threshold for each channel based on the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode.

[0192] In one possible implementation, any debugging of the chip interface includes: writing the parameter set to be used into the serializer, the serializer simultaneously outputting a test pattern to the at least one channel; resetting the deserializer and setting the parameter values ​​of the deserializer; starting the debugging of the deserializer and obtaining the status information of the at least one channel; when the status information indicates that the at least one channel is in a stable state, resetting the counting result of the deserializer; the deserializer obtaining the counting result of each channel based on the actual pattern received by each channel and the test pattern, and determining the bit error rate of the channel based on the counting result of each channel.

[0193] In one possible implementation, during any debugging of the chip interface, the serializer simultaneously outputs test patterns to multiple channels.

[0194] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0195] This disclosure also provides a chip interface debugging device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0196] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0197] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0198] Figure 9 A block diagram of a chip interface debugging apparatus 1900 according to an embodiment of the present disclosure is shown. For example, the chip interface debugging apparatus 1900 may be provided as a server or terminal device. (Refer to...) Figure 9 The chip interface debugging device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0199] The chip interface debugging device 1900 may further include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the chip interface debugging device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM Mac OS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0200] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by a processing component 1922 of a chip interface debugging device 1900 to perform the above-described method.

[0201] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0202] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0203] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0204] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0205] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0206] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0207] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0208] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip interface debugging method, characterized in that, The chip interface includes a serializer and a deserializer, the serializer being connected to the deserializer through multiple channels, and the method includes: Based on the interface attribute information of the chip interface, determine multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel; The chip interface is debugged according to the plurality of first parameter groups, and at least one target parameter group is selected for the serializer according to the debugging results and the bit error rate threshold. Specifically, when the chip interface is debugged once according to any first parameter group, the first parameter group is written into the serializer, the serializer outputs a test code pattern to at least one channel, the deserializer determines the bit error rate of the channel based on the actual code pattern received from each channel and the test code pattern of the channel, and the obtained debugging result includes the bit error rate of the at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group.

2. The method according to claim 1, characterized in that, The process of debugging the chip interface according to the plurality of first parameter groups includes a first debugging stage and a second debugging stage. The step of debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer according to the debugging results and the bit error rate threshold, includes: During the first debugging phase, the chip interface is debugged according to the plurality of first parameter groups, with each first parameter group corresponding to one debugging session and one debugging result; based on the debugging result of the first debugging phase and the bit error rate threshold, at least one second parameter group is selected for the serializer from the plurality of first parameter groups. In the second debugging phase, the chip interface is debugged according to the at least one second parameter group, each second parameter group corresponds to X debugging times and X debugging results, where X is an integer greater than 1; based on the debugging results of the second debugging phase and the bit error rate threshold, at least one target parameter group is selected for the serializer from the at least one second parameter group.

3. The method according to claim 2, characterized in that, The step of selecting at least one second parameter group for the serializer from the plurality of first parameter groups based on the debugging results of the first debugging phase and the bit error rate threshold includes: Determine whether the debugging result corresponding to each first parameter group meets the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold. When the debugging result corresponding to any of the first parameter groups meets the first preset condition, the first parameter group is selected as the second parameter group.

4. The method according to claim 2, characterized in that, The step of selecting at least one target parameter group for the serializer from the at least one second parameter group based on the debugging results of the second debugging phase and the bit error rate threshold includes: Determine whether the X debugging results corresponding to each second parameter group meet the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold. The total number of debugging results that meet the first preset condition corresponding to the second parameter group is counted to obtain the first statistical value corresponding to the second parameter group; If the first statistical value corresponding to any second parameter group is greater than Y, then select that second parameter group as the target parameter group, where Y is a positive integer less than or equal to X.

5. The method according to claim 2, characterized in that, The step of selecting at least one target parameter group for the serializer from the at least one second parameter group based on the debugging results of the second debugging phase and the bit error rate threshold includes: Determine whether the X debugging results corresponding to each second parameter group meet the first preset condition. The first preset condition is that the bit error rate of each channel in the debugging results does not exceed the corresponding bit error rate threshold. The total number of debugging results that meet the first preset condition corresponding to the second parameter group is counted to obtain the first statistical value corresponding to the second parameter group; When the first statistical value corresponding to any second parameter group is greater than Y, the first statistical value is used as the second statistical value, where Y is a positive integer less than or equal to X; Sort the obtained second statistical values ​​according to their numerical values, and select at least one second parameter group corresponding to at least one second statistical value with the largest value as at least one target parameter group.

6. The method according to claim 1, characterized in that, The step of debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer according to the debugging results and the bit error rate threshold, includes: For each first parameter group, the chip interface is debugged once according to the first parameter group; Determine whether the debugging result obtained in this debugging meets the first preset condition, the first preset condition being that the bit error rate of each channel in the debugging result does not exceed the corresponding bit error rate threshold; When the debugging result obtained in this debugging meets the first preset condition, the chip interface is debugged X times according to the first parameter group to obtain X debugging results, where X is an integer greater than 1; Determine whether each of the X debugging results satisfies the first preset condition, count the total number of debugging results that satisfy the first preset condition among the X debugging results, and obtain the third statistical value corresponding to the first parameter group; If any third statistical value corresponding to the first parameter group is greater than Y, then the third statistical value is taken as the fourth statistical value, where Y is a positive integer less than or equal to X; Sort the obtained fourth statistical values ​​according to their numerical values, and select at least one first parameter group corresponding to at least one fourth statistical value with the largest value as at least one target parameter group.

7. The method according to claim 1, characterized in that, The interface attribute information includes the chip identifier of the chip to which the chip interface belongs, the interface identifier within the chip, the desired transmission rate, and the signal modulation mode. The first parameter group includes multiple parameters. The step of determining multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel based on the interface attribute information of the chip interface includes: The value range of each parameter is determined based on the chip identifier of the chip to which the chip interface belongs and the expected transmission rate; Based on the value range of multiple parameters, the plurality of first parameter groups are obtained, wherein the parameter values ​​of at least one parameter in any two first parameter groups are different; The bit error rate threshold for each channel is determined based on the chip identifier of the chip to which the chip interface belongs, the interface identifier in the chip, the expected transmission rate, and the signal modulation mode.

8. The method according to claim 1, characterized in that, Any debugging of the chip interface includes: The parameter set to be used is written into the serializer, and the serializer simultaneously outputs a test code pattern to the at least one channel. Reset the deserializer and set its parameter values; Start the debugging of the deserializer and obtain the status information of the at least one channel; When the status information indicates that at least one channel is in a stable state, the counting result of the deserializer is reset; The deserializer obtains the count result for each channel based on the actual code pattern received by each channel and the test code pattern, and determines the bit error rate of each channel based on the count result.

9. The method according to claim 1, characterized in that, During any debugging of the chip interface, the serializer simultaneously outputs test codes to multiple channels.

10. A chip interface debugging device, characterized in that, The chip interface includes a serializer and a deserializer, the serializer being connected to the deserializer through multiple channels, and the device includes: The preprocessing module is used to determine multiple first parameter groups of the equalizer in the serializer and the bit error rate threshold of each channel based on the interface attribute information of the chip interface. The debugging and selection module is used to debug the chip interface according to the plurality of first parameter groups, and select at least one target parameter group for the serializer according to the debugging results and the bit error rate threshold. Specifically, when the chip interface is debugged once according to any first parameter group, the first parameter group is written into the serializer, the serializer outputs a test code pattern to at least one channel, the deserializer determines the bit error rate of the channel based on the actual code pattern received from each channel and the test code pattern of the channel, and the obtained debugging result includes the bit error rate of the at least one channel. The debugging result is used to determine whether the first parameter group is selected as the target parameter group.

11. A chip interface debugging device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 9.

12. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

13. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

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