A dram cell module capable of increasing the cell gap

Abstract

The application discloses a DRAM particle module capable of increasing the ball gap. The DRAM particle module comprises a DRAM particle and an adapter plate; the bottom of the DRAM particle is provided with a plurality of first solder balls, the bottom of the adapter plate is provided with a plurality of second solder balls, and the DRAM particle is welded to the adapter plate through the plurality of first solder balls; the plurality of first solder balls have a first diameter and a first ball gap, the plurality of second solder balls have a second diameter and a second ball gap, the first diameter is smaller than the second diameter, and the first ball gap is smaller than the second ball gap; and the adapter plate is used for converting the signals transmitted by the plurality of first solder balls into signals transmitted by the plurality of second solder balls, so that the DRAM particle interacts with the outside through the plurality of second solder balls. The application takes into account the high integration of the DRAM particle in the module and the large gap of the solder balls at the bottom of the module, and can effectively solve the problem that the DRAM particle of the POP package is difficult to be applied to a low-order PCB.

Description

Technical Field

[0001] This invention belongs to the field of memory technology, and more specifically, relates to a DRAM chip module that can increase the gap between the spheres. Background Technology

[0002] Low Power Double Data Rate (LPDDR) SDRAM belongs to the DDR SDRAM family. It is a communication standard developed by the JEDEC Solid State Technology Association specifically for mobile electronic products, renowned for its low power consumption. With each generation of evolution, it continuously improves data processing speed and energy efficiency. LPDDR technology has undergone several generations of development, including LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR4X, LPDDR5, and LPDDR5X. The standard specifications for each generation are officially released by the JEDEC Solid State Technology Association, which strives to provide higher memory performance, lower power consumption, and compatibility with the SDRAM NVM interface.

[0003] Package on Package (PoP) is a semiconductor technology that achieves high-density integration by stacking package modules, belonging to the System-in-Package (SiP) technology category. Fine Ball Grid Array (FBGA) is a packaging technology used for integrated circuits, in which solder balls are distributed in an array at the bottom of the package, with a volume close to that of the chip, making it suitable for portable electronic devices and high-performance memory chips.

[0004] There are various packages of LPDDR4 / 4X / 5 / 5X chips available on the market, as well as future iterations such as LPDDR6. Mobile devices primarily use POP-packaged LPDDR chips, while desktop and laptop computers primarily use FBGA-packaged LPDDR chips. POP-packaged LPDDR chips, such as... Figure 1 As shown, the center gap (ballpitch) of the solder balls on the bottom side of the particle is 0.35mm, and the diameter of the solder ball is only 0.22mm. The small solder ball spacing and small solder ball diameter bring great challenges to PCB design.

[0005] POP-packaged memory chips can be stacked with CPU chips, occupying less PCB space and achieving higher integration. However, taking POP-packaged LPDDR chips as an example, their bottom ball pitch is only 0.35mm, while the standard PCB process limit for line width / spacing is 500um. First, using standard PCB processes leads to difficulties in signal fan-out, while using advanced PCB design and manufacturing processes increases costs. Second, the high power ball density and numerous plane divisions result in large power voltage drops and degraded signal integrity. Third, the large number of laser vias leads to a lower yield rate and makes mass production difficult. In contrast, although FBGA-packaged memory chips occupy more PCB space, their PCB process is simpler and easier to manufacture. Therefore, due to considerations such as cost, process complexity, and production yield, low-end manufacturing equipment such as GPUs and laptops do not directly use POP-packaged LPDDR chips. Summary of the Invention

[0006] To address the aforementioned deficiencies or improvement needs of existing technologies, this invention provides a DRAM chip module that increases the ball gap, balancing the high integration of DRAM chips inside the module with the large gap between the solder balls at the bottom of the module. This effectively solves the problem that POP packaged DRAM chips are difficult to apply on low-end PCBs.

[0007] To achieve the above objectives, according to one aspect of the present invention, a DRAM chip module is provided, including a DRAM chip and an adapter board; the DRAM chip has a plurality of first solder balls disposed on its bottom, and the adapter board has a plurality of second solder balls disposed on its bottom, the DRAM chip being soldered to the adapter board through the plurality of first solder balls; the plurality of first solder balls have a first diameter and a first ball gap, and the plurality of second solder balls have a second diameter and a second ball gap, the first diameter being smaller than the second diameter, and the first ball gap being smaller than the second ball gap; the adapter board is used to convert signals transmitted by the plurality of first solder balls into signals transmitted by the plurality of second solder balls, so that the DRAM chip can interact with the outside world through the plurality of second solder balls.

[0008] In some implementations, the bottom of the adapter plate has a functional area, which is composed of J The sub-regions are composed of K matrix arrangements, and multiple second solder balls are set in the sub-regions respectively, with a maximum of one second solder ball in each sub-region.

[0009] In some implementations, sub-regions are used as the smallest constituent units, and the functional areas include power signal areas, ground signal areas, clock signal areas, command / address signal areas, chip select signal areas, other signal areas, and heat dissipation areas.

[0010] In some implementations, the ground signal area includes a first ground signal area and a second ground signal area. The power signal area and the first ground signal area are located around the functional area, wherein the first ground signal area is located at the four corners of the functional area. Each sub-area of ​​the power signal area is provided with a second solder ball for transmitting power signals. Each sub-area of ​​the first ground signal area is provided with a second solder ball for transmitting ground signals.

[0011] In some implementations, each sub-region of the heat dissipation zone is not provided with solder balls; at least some sub-regions of the heat dissipation zone are located on the periphery of the functional area, forming a closed pattern together with the power signal area and the first ground signal area.

[0012] In some implementations, the distribution of sub-regions of the heat dissipation zone within the functional area is asymmetrical, enabling mechanical positioning of the second solder ball through at least one sub-region of the heat dissipation zone.

[0013] In some implementations, the sub-regions of the second ground signal area are distributed in the area surrounded by the closed pattern; each sub-region of the second ground signal area is provided with a second solder ball for transmitting ground signals.

[0014] In some implementations, the clock signal area, command / address signal area, chip select signal area, and other signal areas are located within a region enclosed by a closed pattern; each sub-area of ​​the clock signal area has a second solder ball for transmitting the clock signal; each sub-area of ​​the command / address signal area has a second solder ball for transmitting the command / address signal; each sub-area of ​​the chip select signal area has a second solder ball for transmitting the chip select signal; and each sub-area of ​​the other signal areas has a second solder ball for transmitting other signals, including data signals, data strobe signals, and data mask signals.

[0015] In some implementations, the DRAM chip has a first signal channel, a second signal channel, a third signal channel, and a fourth signal channel; some signals of the first and second signal channels are time-division multiplexed, and some signals of the third and fourth signal channels are time-division multiplexed; some signals include clock signals, command / address signals, and chip select signals.

[0016] In some implementations, a first solder ball corresponding to the multiplexed signal of the first signal channel and a first solder ball corresponding to the multiplexed signal of the second signal channel are connected to a second solder ball for time-division multiplexing of the multiplexed signal of the first signal channel and the second signal channel.

[0017] In some implementations, the lengths of the connections between the second solder ball used for time-division multiplexing signals and the two first solder balls to which it is connected are equal.

[0018] In some implementations, the width of the connection between the second solder ball used for time-division multiplexing signals and the two first solder balls to which it is connected is equal.

[0019] In some implementations, the gap between the second solder ball used for time-division multiplexing signals and the two first solder balls connected to it is equal to that between the other connections.

[0020] In some embodiments, the adapter board includes multiple functional layers and multiple spacer layers disposed between adjacent functional layers; the first group of functional layers is a wiring layer; the second group of functional layers is a ground plane layer; and the third group of functional layers is a reference plane layer.

[0021] In some embodiments, the wiring layer includes a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer; the ground plane layer includes a first ground plane layer and a second ground plane layer; the reference plane layer includes a first reference plane layer and a second reference plane layer; the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer are stacked sequentially, the first ground plane layer is disposed between the first wiring layer and the second wiring layer, the second ground plane layer is disposed between the third wiring layer and the fourth wiring layer, and the first reference plane layer and the second reference plane layer are stacked sequentially between the second wiring layer and the third wiring layer.

[0022] In some implementations, the first ground plane layer and the second ground plane layer are connected to ground signals, the first reference plane layer and the second reference plane layer are connected to power signals, the first reference plane layer serves as the reference plane for the second wiring layer, and the second reference plane layer serves as the reference plane for the third wiring layer.

[0023] In some implementations, a first wiring layer is used to transmit the high-order data signal of the second signal channel and the low-order data signal of the fourth signal channel; a second wiring layer is used to transmit the low-order data signal of the second signal channel and the high-order data signal of the third signal channel; a third wiring layer is used to transmit the high-order data signal of the first signal channel and the high-order data signal of the fourth signal channel; and a fourth wiring layer is used to transmit the low-order data signal of the first signal channel and the low-order data signal of the third signal channel.

[0024] In some embodiments, the spacer layer is made of an insulating material; the spacer layer at the first location and the spacer layer at the second location are made of materials with different dielectric constants.

[0025] According to another aspect of the present invention, an electronic device is provided, including a processor, a PCB, and the aforementioned DRAM chip module; the DRAM chip module is soldered to the PCB via a plurality of second solder balls, and interacts with the processor via the PCB.

[0026] In some implementations, the processor is a CPU or a GPU.

[0027] Overall, compared with the prior art, the above-described technical solutions conceived by this invention have the following beneficial effects: The introduction of an adapter board converts the small-gap solder balls at the bottom of the DRAM chip into large-gap solder balls, reducing the requirements for PCB manufacturing processes while maintaining the high integration of the DRAM chip; it can convert the bottom solder balls of POP packaged DRAM chips with high PCB manufacturing process requirements into the bottom solder balls of FBGA packaged DRAM chips with low PCB manufacturing process requirements, effectively broadening the application scenarios of POP packaged DRAM chips and reducing production costs; the adapter board adopts solutions such as merged wiring design, layered wiring design, and blind / buried via design, converting the solder ball gap from POP package to FBGA package while simplifying the manufacturing process, resulting in DRAM chip modules with small area, high integration, high signal stability, and high yield. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the bottom solder ball structure of a POP packaged DRAM chip;

[0029] Figure 2 This is a schematic diagram of the structure of a DRAM chip module that can increase the inter-sphere gap according to an embodiment of the present invention;

[0030] Figure 3 This is an exploded view of a DRAM chip module that can increase the inter-sphere gap according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the signal distribution in the bottom functional area of ​​the adapter board according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of connecting the first solder ball corresponding to two time-division multiplexed signals to a second solder ball according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the adapter plate according to an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0035] like Figure 2As shown, the DRAM chip module of this embodiment includes a DRAM chip 201 and an adapter board 203. The bottom of the DRAM chip 201 is provided with a plurality of first solder balls 205, each having a first diameter and a first ball gap. The bottom of the adapter board 203 is provided with a plurality of second solder balls 207, each having a second diameter and a second ball gap. The first diameter is smaller than the second diameter, and the first ball gap is smaller than the second ball gap. The DRAM chip 201 is soldered to the adapter board 203 via the plurality of first solder balls 205. The adapter board 203 is used to convert the signals transmitted by the plurality of first solder balls 205 into signals transmitted by the plurality of second solder balls 207, enabling the DRAM chip 201 to interact with the outside world via the plurality of second solder balls 207.

[0036] Without the adapter board 203, the DRAM chip 201 can still interact with the outside world through multiple first solder balls 205. However, due to the small diameter and gap between the first solder balls 205, the requirements for the external PCB board are high, limiting its application scenarios. Therefore, by setting the adapter board 203 below the DRAM chip 201, the multiple first solder balls 205 with smaller diameter and smaller gap are transformed into multiple second solder balls 207 with larger diameter and larger gap, forming a DRAM chip module. This allows the DRAM chip module to interact with the outside world through the multiple second solder balls 207 at the bottom of the adapter board 203, reducing the process requirements for the external PCB board, broadening the application scenarios, and reducing production costs.

[0037] In some implementations, the DRAM chip 201 is a POP-packaged DRAM chip, such as a POP-packaged LPDDR chip. The adapter board 203 is used to convert the plurality of first solder balls 205 on the bottom of the POP-packaged DRAM chip into a plurality of second solder balls 207 in an FBGA package on the bottom of the adapter board 203. Here, LPDDR chip refers to a memory chip belonging to the LPDDR low-power memory technology series, such as LPDDR4 chip, LPDDR4X chip, LPDDR5 chip, LPDDR5X chip, or other upgraded versions based on LPDDR technology.

[0038] In some implementations, the DRAM chip module is soldered to the PCB via multiple second solder balls 207, and the PCB interacts with the processor (e.g., CPU or GPU) via the PCB.

[0039] The dimensions of the adapter board 203 are determined based on the size and process requirements of the DRAM chip 201. In some embodiments, the lateral dimension D of the adapter board 203 is D = 2S + N, where S is the required lateral edge clearance distance and N is the lateral dimension of the DRAM chip 201; the longitudinal dimension L of the adapter board 203 is L = 2T + M, where T is the required longitudinal edge clearance distance and M is the longitudinal dimension of the DRAM chip 201. For example, the size of a POP-packaged LPDDR chip is 14.8mm. The adapter plate is 14.46mm thick and has a diameter of 17.27mm. 17.21mm, the horizontal expansion process dimension is 2.47mm, and the vertical expansion process dimension is 2.75mm.

[0040] Based on the transverse and longitudinal dimensions of the adapter board, and considering both process requirements and the functional requirements of transitioning from the first solder ball to the second solder ball, the initial transverse and longitudinal quantities of the second solder ball 207 are determined, and consequently, the ball spacing of the second solder ball 207 is determined. For example, for POP-packaged LPDDR chips, the initial quantity of the second solder ball 207 is determined to be 20. 20. Therefore, it was determined that the ball gap of the second solder ball 207 was increased to 0.8mm. While ensuring the compact size of the adapter board, the ball gap of the second solder ball 207 at the bottom of the particle module was increased, which reduced the difficulty of the subsequent PCB manufacturing process from "HDI high-density wiring board" to "conventional wiring board with ordinary mechanical drilling".

[0041] An exploded view of the DRAM chip module with increased inter-sphere gap according to an embodiment of the present invention is shown below. Figure 3 As shown, the bottom of the DRAM chip 201 is provided with a plurality of first solder balls 205, each having a first diameter and a first ball gap. The bottom of the adapter board 203 is provided with a plurality of second solder balls 207, which are arranged in a matrix within a region. Each second solder ball 207 has a second diameter and a second ball gap, wherein the first diameter is smaller than the second diameter and the first ball gap is smaller than the second ball gap.

[0042] In some embodiments, the bottom of the adapter plate 203 has a functional area, the functional area being composed of J The sub-regions are composed of K matrix arrangements, and multiple second solder balls 207 are respectively set in these sub-regions, with a maximum of one second solder ball 207 set in each sub-region.

[0043] In some implementations, sub-regions are used as the smallest constituent units, such that the functional areas at the bottom of the adapter board 203 include a power signal area, a ground (GND) signal area, a clock signal area, a command / address signal area, a chip select signal area, other signal areas, and a heat dissipation area.

[0044] In some embodiments, the ground signal area includes a first ground signal area and a second ground signal area. The power signal area and the first ground signal area are located around the periphery of the functional area, with the first ground signal area located at the four corners of the functional area. Each sub-area of ​​the power signal area has a second solder ball 207 for transmitting power signals, and each sub-area of ​​the first ground signal area has a second solder ball 207 for transmitting ground signals. This design of the positions of the power signal area and the first ground signal area satisfies the power signal flow capacity and power integrity requirements of the DRAM chip 201; on the other hand, while meeting the requirement for the number of ground signal solder balls, it also serves to shield high-speed signals and fill the reference ground plane.

[0045] In some embodiments, a plurality of first solder balls 205 are disposed in the peripheral region at the bottom of the DRAM chip 201. In some embodiments, a clock signal region is determined according to the position of the first solder balls 205 corresponding to the clock signal of the DRAM chip 201, and a second solder ball 207 is disposed in each sub-region of the clock signal region for transmitting the clock signal; a command / address signal region is determined according to the position of the first solder balls 205 corresponding to the command / address signal of the DRAM chip 201, and a second solder ball 207 is disposed in each sub-region of the command / address signal region for transmitting the command / address signal; a chip select signal region is determined according to the position of the first solder balls 205 corresponding to the chip select signal of the DRAM chip 201, and a second solder ball 207 is disposed in each sub-region of the chip select signal region for transmitting the chip select signal.

[0046] In some implementations, other signal areas are determined based on the wiring requirements of the adapter board 203 and the requirements for signal integrity. Each sub-area of ​​the other signal areas is provided with a second solder ball 207 to transmit other signals, including data signals, data strobe signals, and data shielding signals. A second ground signal area is determined based on the requirements for shielding high-speed signals and filling the reference ground plane. Each sub-area of ​​the second ground signal area is provided with a second solder ball 207 to transmit ground signals. A heat dissipation area is determined based on the requirements for heat dissipation and mechanical positioning. Each sub-area of ​​the heat dissipation area is not provided with solder balls and is the exposed bottom surface of the adapter board 203.

[0047] In some embodiments, at least a portion of the heat dissipation area is located around the functional area, forming a closed pattern together with the power signal area and the first ground signal area. In some embodiments, a portion of the heat dissipation area forms a closed pattern, while another portion of the sub-regions is located within the area enclosed by the closed pattern. In some embodiments, the distribution of the sub-regions of the heat dissipation area within the functional area is asymmetrical. In some embodiments, the clock signal area, command / address signal area, chip select signal area, and other signal areas are located within the area enclosed by the closed pattern. In some embodiments, the sub-regions of the second ground signal area are dispersed within the area enclosed by the closed pattern; that is, at least one sub-region or a group of adjacent sub-regions of the second ground signal area are not surrounded by other sub-regions of the second ground signal area.

[0048] by Figure 4 Taking the functional area distribution at the bottom of the adapter board as an example, the functional areas at the bottom of the adapter board consist of 20... It consists of 20 sub-areas arranged in a matrix. The power signal area is marked as S, the first ground signal area is marked as GND1, the second ground signal area is marked as GND2, the clock signal area, the command / address signal area, the chip select signal area, and other signal areas are uniformly marked as signal area OT, and the heat dissipation area is unmarked and empty.

[0049] The power signal area S and the first ground signal area GND1 are located on the periphery of the functional area, with GND1 positioned at each of the four corners of the functional area. A portion of the heat dissipation area is located on the periphery of the functional area, forming a closed pattern together with the power signal area S and the first ground signal area GND1. Another portion of the heat dissipation area is located within the area enclosed by this closed pattern. Besides heat dissipation, the heat dissipation area also serves to mechanically position the solder balls. Therefore, the distribution of the heat dissipation area's sub-regions within the functional area is asymmetrical, allowing for mechanical positioning of the second solder ball through at least one sub-region. For example, mechanical positioning of the solder ball can be achieved through either the first sub-region 401 or the second sub-region 403 of the heat dissipation area. The signal area OT is located within the area enclosed by the closed pattern. The sub-regions of the second ground signal area GND2 are dispersed in the area surrounded by the closed pattern to shield high-speed signals and fill the reference ground plane. For example, there are no other sub-regions of the second ground signal area GND2 around the third sub-region 405 of the second ground signal area GND2, and there are also no other sub-regions of the second ground signal area GND2 around a group of adjacent fourth sub-regions 407 of the second ground signal area GND2.

[0050] In some implementations, time-multiplexed signals are connected using combined wiring; that is, the first solder ball corresponding to two time-multiplexed signals is connected to a second solder ball for time-division transmission of the two multiplexed signals. Other signals that are not time-multiplexed are connected using point-to-point wiring; that is, the first solder ball corresponding to the signal is connected to a second solder ball.

[0051] In some implementations, the DRAM chip has four signal channels, namely a first signal channel, a second signal channel, a third signal channel, and a fourth signal channel. The clock signal, command / address signal, and chip select signal of the first signal channel and the second signal channel are time-division multiplexed, and the clock signal, command / address signal, and chip select signal of the third signal channel and the fourth signal channel are time-division multiplexed.

[0052] In some implementations, the first solder ball corresponding to the clock signal of the first signal channel and the first solder ball corresponding to the multiplexed clock signal of the second signal channel are connected to a second solder ball in the clock signal area for time-division multiplexing of the clock signal of the first signal channel and the multiplexed clock signal of the second signal channel; the first solder ball corresponding to the clock signal of the third signal channel and the first solder ball corresponding to the multiplexed clock signal of the fourth signal channel are connected to a second solder ball in the clock signal area for time-division multiplexing of the clock signal of the third signal channel and the multiplexed clock signal of the fourth signal channel.

[0053] In some implementations, the first solder ball corresponding to the command / address signal of the first signal channel and the first solder ball corresponding to the multiplexed command / address signal of the second signal channel are connected to a second solder ball in the command / address signal area for time-division multiplexing of the command / address signal of the first signal channel and the multiplexed command / address signal of the second signal channel; the first solder ball corresponding to the command / address signal of the third signal channel and the first solder ball corresponding to the multiplexed command / address signal of the fourth signal channel are connected to a second solder ball in the command / address signal area for time-division multiplexing of the command / address signal of the third signal channel and the multiplexed command / address signal of the fourth signal channel.

[0054] In some implementations, the first solder ball corresponding to the chip select signal of the first signal channel and the first solder ball corresponding to the multiplexed chip select signal of the second signal channel are connected to a second solder ball in the chip select signal area for time-division multiplexing of the chip select signal of the first signal channel and the multiplexed chip select signal of the second signal channel; the first solder ball corresponding to the chip select signal of the third signal channel and the first solder ball corresponding to the multiplexed chip select signal of the fourth signal channel are connected to a second solder ball in the chip select signal area for time-division multiplexing of the chip select signal of the third signal channel and the multiplexed chip select signal of the fourth signal channel.

[0055] In some implementations, the connection lengths from the second solder ball in the clock signal area to the two first solder balls connected thereto are equal; the connection lengths from the second solder ball in the command / address signal area to the two first solder balls connected thereto are equal; and the connection lengths from the second solder ball in the chip select signal area to the two first solder balls connected thereto are equal. Furthermore, due to the positional constraints of the first and second solder balls, the connection lengths can be made approximately equal by winding the wires.

[0056] In some implementations, the width of the connection between the second solder ball in the clock signal area and the two first solder balls connected thereto is equal; the width of the connection between the second solder ball in the command / address signal area and the two first solder balls connected thereto is equal; the width of the connection between the second solder ball in the chip select signal area and the two first solder balls connected thereto is equal.

[0057] In some implementations, the gap between the second solder ball in the clock signal area and the two first solder balls connected to it is equal to the gap between other connections; the gap between the second solder ball in the command / address signal area and the two first solder balls connected to it is equal to the gap between other connections; the gap between the second solder ball in the chip select signal area and the two first solder balls connected to it is equal to the gap between other connections.

[0058] Furthermore, the clock signal includes a positive clock signal CK and a negative clock signal CKB. Taking the positive clock signal CK as an example, the positive clock signal A_CK of the first signal channel and the positive clock signal B_CK of the second signal channel are time-division multiplexed. Figure 5 As shown, the positive clock signal A_CK of the first signal channel corresponds to the first solder ball 205 on the left, and the positive clock signal B_CK of the second signal channel corresponds to the first solder ball 205 on the right. The first solder ball 205 on the left and the first solder ball 205 on the right are connected to the second solder ball 207 in the clock signal area for time-division transmission of the positive clock signal A_CK of the first signal channel and the positive clock signal B_CK of the second signal channel.

[0059] It should be understood that the first solder ball 205 on the left and the first solder ball 205 on the right are on different planes from the second solder ball 207. The first solder ball 205 on the left and the first solder ball 205 on the right are at the bottom of the DRAM chip, and the second solder ball 207 is at the bottom of the adapter board. Figure 5 For ease of explanation, the first solder ball 205 on the left and the first solder ball 205 on the right are shown in the same plane as the second solder ball 207.

[0060] like Figure 5As shown, the second solder ball 207 is not located between the first solder ball 205 on the left and the first solder ball 205 on the right. The second solder ball 207 is closer to the first solder ball 205 on the left and farther from the first solder ball 205 on the right. If conventional routing is used, the length of the line connecting the second solder ball 207 to the first solder ball 205 on the left will be less than the length of the line connecting the second solder ball 207 to the first solder ball 205 on the right. Therefore, by rerouting the wiring, the length of the first line 507 connecting the second solder ball 207 to the first solder ball 205 on the left can be made approximately equal to the length of the second line 509 connecting the second solder ball 207 to the first solder ball 205 on the right. Furthermore, the width of the first line 507 connecting the second solder ball 207 to the first solder ball 205 on the left is equal to the width of the second line 509 connecting the second solder ball 207 to the first solder ball 205 on the right; the gap between the first line 507 connecting the second solder ball 207 to the first solder ball 205 on the left and the other lines is a1, and the gap between the second line 509 connecting the second solder ball 207 to the first solder ball 205 on the right and the other lines is a2, where a1 = a2.

[0061] The embodiments of the present invention adopt a merged wiring design, which merges two first solder balls into one second solder ball outgoing line, saving one laser hole and helping to improve the yield of DRAM chip modules; by making the connection length from the second solder ball to the two first solder balls equal, the width equal, and the gap with other connections equal, the timing deviation is ensured to be within a reasonable range and the timing budget is met.

[0062] The adapter board of this invention adopts a symmetrical stacked structure design, including multiple functional layers. The functional layers are electrically connected through blind vias, and spacers are provided between adjacent functional layers. Among the multiple functional layers, the first group of functional layers is a wiring layer, the second group of functional layers is a ground plane layer, and the third group of functional layers is a reference plane layer.

[0063] Employing a layered cabling design, such as Figure 6 As shown, the wiring layers include a first wiring layer 601, a second wiring layer 603, a third wiring layer 605, and a fourth wiring layer 607; the ground plane layers include a first ground plane layer 609 and a second ground plane layer 611; and the reference plane layers include a first reference plane layer 613 and a second reference plane layer 615. The first wiring layer 601, the second wiring layer 603, the third wiring layer 605, and the fourth wiring layer 607 are stacked sequentially. The first ground plane layer 609 is disposed between the first wiring layer 601 and the second wiring layer 603; the second ground plane layer 611 is disposed between the third wiring layer 605 and the fourth wiring layer 607; and the first reference plane layer 613 and the second reference plane layer 615 are stacked sequentially between the second wiring layer 603 and the third wiring layer 605. Adjacent functional layers are separated by a spacer layer 617.

[0064] The first ground plane layer 609 and the second ground plane layer 611 are connected to the ground (GND) signal, the first reference plane layer 613 and the second reference plane layer 615 are connected to the power signal, the first reference plane layer 613 serves as the reference plane of the second wiring layer 603, and the second reference plane layer 615 serves as the reference plane of the third wiring layer 605.

[0065] In some implementations, the first wiring layer 601 is used to transmit the high-order data signals (e.g., DQ16 to DQ31) of the second signal channel and the low-order data signals (e.g., DQ0 to DQ15) of the fourth signal channel; the second wiring layer 603 is used to transmit the low-order data signals (e.g., DQ0 to DQ15) of the second signal channel and the high-order data signals (e.g., DQ16 to DQ31) of the third signal channel; the third wiring layer 605 is used to transmit the high-order data signals (e.g., DQ16 to DQ31) of the first signal channel and the high-order data signals (e.g., DQ16 to DQ31) of the fourth signal channel; and the fourth wiring layer 607 is used to transmit the low-order data signals (e.g., DQ0 to DQ15) of the first signal channel and the low-order data signals (e.g., DQ0 to DQ15) of the third signal channel.

[0066] A layered cabling design helps to rationally control the area of ​​the adapter board. In some implementations, more functional layers are set up according to actual cabling needs.

[0067] In some embodiments, the spacer layer 617 is made of an insulating material. Further, in some embodiments, the spacer layer at the first location and the spacer layer at the second location (different from the first location) are made of materials with different dielectric constants to achieve impedance control of the wiring layer; that is, the dielectric constant of each spacer layer can be adjusted according to the impedance control requirements of the wiring layer.

[0068] This invention introduces an adapter board that converts the small-gap solder balls at the bottom of DRAM chips into large-gap solder balls. While maintaining the high integration of DRAM chips, it reduces the requirements for PCB manufacturing processes. It can convert the bottom solder balls of POP packaged DRAM chips with high PCB manufacturing process requirements into the bottom solder balls of FBGA packaged DRAM chips with low PCB manufacturing process requirements, effectively broadening the application scenarios of POP packaged DRAM chips and reducing production costs. The adapter board adopts solutions such as merged wiring design, layered wiring design, and blind and buried via design to convert the solder ball gap from POP package to FBGA package while simplifying the manufacturing process, resulting in DRAM chip modules with small area, high integration, high signal stability, and high yield.

[0069] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0071] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more (two or more) executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0072] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0073] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0074] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0075] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A DRAM chip module, characterized in that, The system includes a POP-packaged DRAM chip and an adapter board. The DRAM chip has multiple first solder balls on its bottom, and the adapter board has multiple second solder balls on its bottom. The DRAM chip is soldered to the adapter board via the multiple first solder balls. The multiple first solder balls have a first diameter and a first ball gap, and the multiple second solder balls have a second diameter and a second ball gap, wherein the first diameter is smaller than the second diameter, and the first ball gap is smaller than the second ball gap. The adapter board is used to convert signals transmitted by the multiple first solder balls into signals transmitted by the multiple second solder balls, enabling the DRAM chip to interact with the outside world via the multiple second solder balls. The bottom of the adapter plate has a functional area, which is composed of J The system is composed of K sub-regions arranged in a matrix, and the plurality of second solder balls are respectively disposed in the sub-regions, with a maximum of one second solder ball disposed in each sub-region; taking the sub-region as the smallest unit, the functional area includes a power signal area, a ground signal area, a clock signal area, a command / address signal area, a chip select signal area, other signal areas, and a heat dissipation area.

2. The DRAM chip module as described in claim 1, characterized in that, The ground signal area includes a first ground signal area and a second ground signal area. The power signal area and the first ground signal area are located on the periphery of the functional area. The first ground signal area is located at the four corners of the functional area. Each sub-area of ​​the power signal area is provided with a second solder ball for transmitting power signals. Each sub-area of ​​the first ground signal area is provided with a second solder ball for transmitting ground signals.

3. The DRAM chip module as described in claim 2, characterized in that, Each sub-region of the heat dissipation area is free of solder balls; at least some sub-regions of the heat dissipation area are located on the periphery of the functional area, forming a closed pattern together with the power signal area and the first ground signal area.

4. The DRAM chip module as described in claim 3, characterized in that, The distribution of the sub-regions of the heat dissipation zone in the functional area is asymmetrical, which allows the mechanical positioning of the second solder ball to be achieved through at least one sub-region of the heat dissipation zone.

5. The DRAM chip module as described in claim 3, characterized in that, The sub-regions of the second ground signal area are distributed in the area surrounded by the closed pattern; each sub-region of the second ground signal area is provided with a second solder ball for transmitting ground signals.

6. The DRAM chip module as described in claim 3, characterized in that, The clock signal area, the command / address signal area, the chip select signal area, and the other signal areas are located within the area enclosed by the closed pattern. Each sub-area of ​​the clock signal area has one second solder ball for transmitting clock signals. Each sub-area of ​​the command / address signal area has one second solder ball for transmitting command / address signals. Each sub-area of ​​the chip select signal area has one second solder ball for transmitting chip select signals. Each sub-area of ​​the other signal areas has one second solder ball for transmitting other signals, including data signals, data strobe signals, and data mask signals.

7. The DRAM chip module as described in claim 6, characterized in that, The DRAM chip has a first signal channel, a second signal channel, a third signal channel, and a fourth signal channel; some signals of the first signal channel and the second signal channel are time-division multiplexed, and some signals of the third signal channel and the fourth signal channel are time-division multiplexed; the partial signals include clock signals, command / address signals, and chip select signals.

8. The DRAM chip module as described in claim 7, characterized in that, The first solder ball corresponding to the multiplexed signal of the first signal channel and the first solder ball corresponding to the multiplexed signal of the second signal channel are connected to a second solder ball for time-division multiplexing of the multiplexed signals of the first signal channel and the second signal channel.

9. The DRAM chip module as described in claim 8, characterized in that, The lengths of the connections between the second solder ball used for time-division multiplexing signals and the two first solder balls to which it is connected are equal.

10. The DRAM chip module as described in claim 8, characterized in that, The width of the connection between the second solder ball used for time-division multiplexing signals and the two first solder balls connected to it is equal.

11. The DRAM chip module as described in claim 8, characterized in that, The gap between the second solder ball used for time-division multiplexing signals and the two first solder balls connected to it is equal to that between the other connections.

12. The DRAM chip module as described in any one of claims 7 to 11, characterized in that, The adapter board includes multiple functional layers and multiple spacer layers disposed between adjacent functional layers; the first group of functional layers is a wiring layer; the second group of functional layers is a ground plane layer; and the third group of functional layers is a reference plane layer.

13. The DRAM chip module as described in claim 12, characterized in that, The wiring layer includes a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer; the ground plane layer includes a first ground plane layer and a second ground plane layer; the reference plane layer includes a first reference plane layer and a second reference plane layer; the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer are stacked sequentially, the first ground plane layer is disposed between the first wiring layer and the second wiring layer, the second ground plane layer is disposed between the third wiring layer and the fourth wiring layer, and the first reference plane layer and the second reference plane layer are stacked sequentially between the second wiring layer and the third wiring layer.

14. The DRAM chip module as described in claim 13, characterized in that, The first ground plane layer and the second ground plane layer are connected to ground signals, the first reference plane layer and the second reference plane layer are connected to power signals, the first reference plane layer serves as the reference plane for the second wiring layer, and the second reference plane layer serves as the reference plane for the third wiring layer.

15. The DRAM chip module as described in claim 14, characterized in that, The first wiring layer is used to transmit the high-order data signal of the second signal channel and the low-order data signal of the fourth signal channel; the second wiring layer is used to transmit the low-order data signal of the second signal channel and the high-order data signal of the third signal channel; the third wiring layer is used to transmit the high-order data signal of the first signal channel and the high-order data signal of the fourth signal channel; the fourth wiring layer is used to transmit the low-order data signal of the first signal channel and the low-order data signal of the third signal channel.

16. The DRAM chip module as described in claim 12, characterized in that, The spacer layer is made of insulating material; the spacer layer at the first position and the spacer layer at the second position are made of materials with different dielectric constants.

17. An electronic device, characterized in that, It includes a processor, a PCB, and a DRAM chip module as described in any one of claims 1 to 16; the DRAM chip module is soldered to the PCB via the plurality of second solder balls and interacts with the processor via the PCB.

18. The electronic device as claimed in claim 17, characterized in that, The processor is either a CPU or a GPU.

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