System and method for updating memory table

Abstract

A method may be performed by a host controller and a memory controller of a computing device. The method synchronizes a memory table between a storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in memory mapping, the first memory table mapping a logical address to a physical address of a memory on the storage device, the indicator identifies one or more address mapping changes of the first memory table; notifying the host device that the first memory table has been modified; and transmitting at least a portion of the first memory table including the one or more address mapping changes to the host device. The storage device processes a memory request from the host device based on the one or more addresses affected by the one or more address mapping changes.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Application No. 18 / 349,206, filed July 10, 2023; the entirety of which is incorporated by reference herein. BACKGROUND

[0003] Developers and users of computing devices are always seeking improved operational performance. One method of improving the operation of a computing device is a host performance booster (HPB) mode in which a host component stores and uses a logical to physical (L2P) address mapping table for the host component to access a memory device component. The logical to physical (L2P) address mapping table enables an understanding of whether data sought by the host component is located at the memory device and whether such locations are active. The ability to quickly ascertain the presence of data and the active state of data locations stored in the memory device reduces input / output transaction time for accessing data by the host component of the memory device, thereby improving operational performance. Due to various memory management processes on the memory device, the L2P table frequently changes and needs to be synchronized with the host device. SUMMARY

[0004] Various aspects include a method performed in a storage device for synchronizing a memory table between the storage device and a host device and a host controller of a computing device, the method including modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table.

[0005] Some aspects can further include notifying the host device that the first memory table has been modified; sending at least a portion of the first memory table including the one or more address mapping changes to the host device; and processing, by the storage device, first memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

[0006] In some aspects, the portion of the first memory table sent to the host device can correspond to one or more address mapping changes. Some aspects can also include receiving, by the storage device, a request for the one or more address mapping changes. Some aspects can also cause the first memory request to include a physical address updated based on the one or more address mapping changes. In some aspects, the indicator can be a bit value assigned to each memory mapping in the first memory table, and the bit value changes when the corresponding memory mapping changes. In some aspects, the indicator can be a value indicating a location in the first memory table, the location corresponding to an interface between a synchronized portion of the first memory table and an unsynchronized portion of the first memory table, the unsynchronized portion of the first memory table corresponding to the one or more mapping address changes.

[0007] Some aspects can also include resetting the indicator upon receiving an acknowledgement from the host device that the portion of the first memory table has been received. Some aspects can also include sending a notification to the host device upon modifying the indicator in the first memory table on the storage device.

[0008] Further aspects include a computing device or a flash storage device configured to perform operations corresponding to any of the methods outlined above. Further aspects include a flash storage device for use in a computing device, the flash storage device including a processor configured to perform operations of any of the methods outlined above. Further aspects include a flash storage device including a non-transitory computer-readable medium having processor-executable instructions configured to perform the methods outlined above. Further aspects include a computing device including a host controller configured to perform operations corresponding to any of the methods outlined above. Further aspects include a computing device including means for performing the functions of any of the methods outlined above. Further aspects include a host controller for use in a computing device, the host controller including a processor configured to perform operations of any of the methods outlined above. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate exemplary embodiments of the claims, and together with the general description given above and the detailed description given below, serve to explain features of the present teachings.

[0010] Figure 1 is a system block diagram illustrating an example memory system suitable for implementing any of the various embodiments.

[0011] Figure 2 is a component block diagram illustrating an example computing device suitable for implementing any of the various embodiments.

[0012] Figure 3 is a component block diagram illustrating an example system configured for host performance booster (HPB) mode management in accordance with some embodiments.

[0013] Figure 4 is a component block diagram and signaling diagram illustrating an example of HPB mode management for host control mode in accordance with some embodiments.

[0014] Figure 5 is a process flow diagram of an example method for HPB mode management and memory table synchronization in accordance with some embodiments.

[0015] Figures 6A to 6D is a process flow diagram of an example method for HPB and memory table management in accordance with some embodiments.

[0016] Figure 7 is a component block diagram illustrating an example computing device suitable for use with various embodiments.

[0017] Figure 8 is a component block diagram illustrating an example server suitable for use with various embodiments.

[0018] Figure 9 is a component block diagram illustrating an example wireless communication device suitable for use with various embodiments. DETAILED DESCRIPTION

[0019] Various embodiments will be described in detail with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the claims.

[0020] Various embodiments include methods and computing devices that facilitate synchronization between logical-to-physical (L2P) tables, the computing devices including a host controller and a storage device. The L2P tables are stored in dynamic random access memory (DRAM) that is communicatively connected to the host controller, and in NAND memory of a universal flash storage (UFS) device that is communicatively connected to the host controller via a link. Various embodiments can determine when the L2P tables are out of sync, and in response, synchronize the L2P tables by exchanging changed portions of the L2P tables.

[0021] Various embodiments include methods and computing devices that include a host controller that manages a host performance booster (HPB) mode based on availability of the host controller, such as a component of a system on a chip (SoC), and / or availability of a memory device controller, also referred to herein as a device controller, such as a component of a universal flash storage (UFS) device. In some embodiments, different HPB modes, such as a host control mode (HCM) and / or a device control mode (DCM), can be enabled based on availability of the host controller and / or availability of the memory device controller. In some embodiments, DCM can be enabled based on the host controller being busy and the memory device controller being available. In some embodiments, HCM can be enabled based on the host controller being available and the memory device controller being busy. In some embodiments, DCM can be enabled based on both the host controller and the memory device controller being busy and after the memory device controller becomes available.

[0022] The term "system on a chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip that contains multiple resources and / or processors integrated on a single substrate. A single SoC can contain circuitry for digital, analog, mixed-signal, and radio-frequency functions. A single SoC can also include any number of general-purpose and / or specialized processors (digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, Flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.). A SoC can also include software for controlling the integrated resources and processors, as well as for controlling peripheral devices.

[0023] The term "system in a package" (SIP) can be used herein to refer to a single module or package that contains multiple resources, computing units, cores and / or processors on two or more IC chips, substrates, or SoCs. For example, a SIP can include a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP can include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a unified substrate. A SIP can also include multiple independent SoCs that are coupled together via high-speed communication circuitry and packaged in close proximity, such as on a single motherboard or in a single computing device. The proximity of the SoCs facilitates high-speed communication as well as sharing of memory and resources.

[0024] Developers and users of computing devices are always seeking improved operational performance. One means for improving operational performance implemented in a computing device is a host performance booster (HPB) mode in which a host memory, such as a dynamic random access memory (DRAM) communicatively connected to a host controller of a SoC, is used as a cache for a flash translation layer (FTL). The FTL maintains a logical to physical (L2P) address map table in a flash memory of a UFS device connected to the host controller. The L2P address map table enables an understanding of whether data sought by the host component is located at the flash memory and whether such location is active. The HPB mode enables the host memory to maintain an L2P address map table that can correspond to at least a portion of the L2P address map table in the flash memory. The L2P address map table entries of the host memory can be read by the host controller and the physical addresses from the L2P address map table entries stored in the host memory can be used to perform memory access transactions to the flash memory at the UFS device faster than performing the memory access transactions using logical addresses to the flash memory located on the UFS device, which requires the UFS device to translate the logical addresses to physical addresses. Improving the speed of the memory access transactions can improve operational performance.

[0025] Various embodiments include methods and computing devices including a host controller that manages a host performance booster (HPB) mode based on availability of the host controller, such as a component of a system on a chip (SoC), and / or availability of a memory device controller, also referred to herein as a device controller, such as a component of a universal flash storage (UFS) device. In some embodiments, different HPB modes, such as a host control mode (HCM) and / or a device control mode (DCM), can be enabled based on availability of the host controller and / or availability of the memory device controller. In some embodiments, the DCM can be enabled based on the host controller being busy and the memory device controller being available. In some embodiments, the HCM can be enabled based on the host controller being available and the memory device controller being busy.

[0026] The L2P address mapping table of the host memory can need to be updated prior to use to ensure that the L2P address mapping tables of the host memory and the flash memory are synchronized. The HPB mode can be set to either HCM or DCM in different situations. When the HPB mode is set to HCM, the host controller can identify which sub-regions of the L2P address mapping table of the host memory are active and / or inactive. When the HPB mode is set to DCM, the memory device controller can identify which sub-regions of the L2P address mapping table of the flash memory are active and / or inactive, and inform the host controller to update the L2P address mapping table of the host memory. The performance improvement enabled by the HPB mode can be negatively impacted when the L2P table of the host device is not updated or requires a long update period.

[0027] For example, in a conventional L2P table, synchronization between the UFS device and the host device requires copying the entire group of L2P table entries in which one or more changes have been made in the group. The group is marked as "dirty" until synchronization. This synchronization method reduces the use of the L2P table because large sections are typically marked as unusable, requiring a lookup of the physical address on the storage device. In addition, synchronizing large chunks of the L2P table to resolve individual changes can result in a large unnecessary transfer of data for synchronization, which slows down the operation of both devices. As storage devices implement more memory management mechanisms, such as garbage collection, defragmentation, and wear leveling, the overhead introduced by these conventional synchronization techniques becomes too large.

[0028] Various embodiments address and overcome the foregoing problems of L2P address mapping table synchronization performance degradation by providing an indicator for each mapping entry in the L2P table on the storage device side of the system that identifies the synchronization status of that mapping entry. The synchronization process can then transfer only the changed or updated L2P table entries, and thus save the overhead associated with conventional L2P address mapping table synchronization processes. Various embodiments can include notifying a host device that a first memory table has been modified, sending at least a portion of the first memory table including one or more address mapping changes to the host device, and the storage device processing a first memory request from the host device based on one or more addresses affected by the one or more address mapping changes.

[0029] A host controller / device can receive a notification indicating that one or more entries in the L2P table of the host device are out of sync and need to be updated. The notification can be an exception sent in response to a read request for data at a logical address that is out of sync. The host controller can request the updated entries from the L2P table of the storage device and can receive a response from the storage device with those out of sync entries of the L2P table. The host controller can then update the local L2P table with these entries. The host controller can then transmit an acknowledgement to the storage device that the L2P table has been synchronized.

[0030] The solution can include an indicator in the L2P table of the storage device indicating one or more memory mappings that are out of sync with the host controller and can include a notification (or exception) sent to the host controller when a read request is received and the L2P table is out of sync. The solution can include a host controller that issues a request for L2P table updates after receiving a notification that the local L2P table is not up to date and can include a host controller configured to update a portion of its L2P table with one or more memory mappings received from the storage device.

[0031] Figure 1 is a system block diagram illustrating an example system suitable for implementing any of the various embodiments. The system 100 can include one or more computing devices or processors for performing L2P table synchronization. For example, the system 100 can include a SoC 102 including a host controller 104, a DRAM 108 communicatively connected to the host controller 104, and a UFS device 106 communicatively connected to the host controller 104 via a link 114. The host controller 104 can include a processor (not shown separately) configured to perform the operations of the host controller described herein. The host controller 104 can maintain and access stored L2P mapping entries (i.e., data) of an L2P-1 address mapping table. In some embodiments, the L2P mapping entries of the L2P-1 address mapping table can be stored in the DRAM 108 or an SRAM (not shown) integral to the SoC 102 and / or the host controller 104. The UFS device 106 can include a device controller 116, a static random access memory (SRAM) 110, and a NAND memory 112. The device controller 116 can be coupled to the SRAM 110 and the NAND memory 112 such that the device controller 116 can transfer L2P mapping entries (i.e., data) of an L2P-2 address mapping table on the device controller between the NAND memory 112 and the SRAM 110.

[0032] The host controller 104 can receive read commands from other components of the SoC 102 and / or from components communicably connected to the SoC 102 (e.g., via I / O of the SoC). When the HPB is enabled, in response to a read command, the host controller 104 can check the operational status of the host controller 104 and the device controller 116, such as available or busy. The operational status of each of the host controller 104 and the device controller 116 can depend on operations that are pending and / or being performed by the respective controller 104, 116. The criteria for different operational statuses of each of the host controller 104 and the device controller 116 can vary between different implementations.

[0033] In response to the host controller 104 having a busy operational status and the device controller 116 having an available operational status, the host controller 104 can enable the DCM for the HPB mode. Enabling the DCM can trigger the device controller 116 to determine the portion of the L2P-2 address mapping table to be synchronized with the L2P-1 address mapping table of the host controller 104. In response to the host controller 104 having an available operational status and the device controller 116 having a busy operational status, the host controller 104 can enable the HCM for the HPB mode. Enabling the HCM can trigger the host controller 104 to determine the portion of the L2P-1 address mapping table to be synchronized with the L2P-2 table.

[0034] If the L2P tables (e.g., L2P-1 of the DRAM 108 and L2P-2 of the NAND memory 112) are synchronized, the host controller 104 can read the data requested by the read command from the DRAM 108, and the DRAM 108 can provide the requested data to the host controller 104. If the L2P tables (e.g., L2P-1 and L2P-2) are not synchronized, the host controller 104 can read the data requested by the read command from the UFS device 106 in DCM or HCM, such that the host controller 104 requests the unsynchronized L2P mapping entry of the L2P-1 table. For Figure 4 Further descriptions of procedures that can be performed when the L2P tables are not synchronized are provided.

[0035] After receiving the read request, the storage device can notify the host controller 104 that one or more L2P table entries have been updated and should be synchronized. The host controller 104 can send a DCM / HCM-based read command to the device controller 116, and the device controller 116 can retrieve the requested one or more L2P mapping entries from the NAND memory 112 or the SRAM 110. The device controller 116 can then send a read response message to the host controller 104 for further processing. Such further processing can include sending the one or more L2P mapping entries received from the device controller 116 to the source device that originated the original read request, and / or updating the L2P-1 table of the DRAM 108 with the one or more L2P-2 mapping entries received from the device controller 116.

[0036] Figure 2 is a component block diagram illustrating an example computing device 200 suitable for implementing any of the various embodiments. The various embodiments can be implemented on a number of single-processor and multi-processor computer systems, including a system on a chip (SoC) or system in a package.

[0037] Referring to Figure 1 and Figure 2 , the illustrated example computing device 200 (which can be a system in a package in some embodiments) includes two SoCs 202, 204 (e.g., SoCs 102) coupled to a clock 206, a voltage regulator 208, at least one subscriber identity module (SIM) 268 and / or SIM interface, a DRAM 270 (e.g., DRAM 108) having a stored L2P address mapping table (e.g., L2P-1), a UFS device 272 (e.g., UFS device 106) having a stored L2P address mapping table (e.g., L2P-2), a wireless transceiver 266 configured to transmit and receive wireless communications to and from a wireless computing device (such as a base station, a wireless device, and / or a computing device (e.g., system 100)) via an antenna (not shown). In some embodiments, the first SoC 202 can operate as a central processing unit (CPU) of the computing device 200 that performs arithmetic, logical, control, and input / output (I / O) operations specified by the instructions of software applications by executing those instructions. In some embodiments, the second SoC 204 can operate as a specialized processing unit. For example, the second SoC 204 can operate as a specialized 5G processing unit responsible for managing high capacity, high speed (e.g., 5 Gbps or the like), and / or very high frequency short wavelength (e.g., 28 GHz millimeter wave spectrum or the like) communications.

[0038] The first SoC 202 can include digital signal processors (DSPs) 210, modem processors 212, graphics processors 214, application processors (APs) 216, one or more coprocessors 218 (e.g., vector co-processor) connected to one or more of the processors, memory 220, custom circuitry 222, system components and resources 224, a host controller 262 (e.g., host controller 104), an interconnect / bus module 226, one or more sensors 230 (e.g., accelerometer, temperature sensor, pressure sensor, optical sensor, infrared sensor, analog sound sensor, etc.), a thermal management unit 232, and a thermal power envelope (TPE) component 234. The second SoC 204 can include low-power processors 252, a power management unit 254, an interconnect / bus module 264, a BT controller 256, memory 258, and various additional processors 260, such as application processors, packet processors, etc.

[0039] Each processor 210, 212, 214, 216, 218, 252, 260 can include one or more cores, and each processor / core can perform operations independently of the other processors / cores. For example, the first SoC 202 can include processors that execute a first type of operating system (e.g., FreeBSD, LINUX, OS X, etc.) and processors that execute a second type of operating system (e.g., MICROSOFT WINDOWS 10). Further, any or all of the processors 210, 212, 214, 216, 218, 252, 260 can be included as part of a processor cluster architecture (e.g., a synchronous processor cluster architecture, an asynchronous or heterogeneous processor cluster architecture, etc.).

[0040] The first SoC 202 and the second SoC 204 can include various system components, resources, and custom circuitry for managing sensor data, analog-to-digital conversion, wireless data transmission, and for performing other specialized operations, such as decoding data packets and processing encoded audio and video signals for presentation in a web browser or audio / video application. For example, the system components and resources 224 of the first SoC 202 can include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting the processors and software clients running on the computing device. The system components and resources 224 and / or the custom circuitry 222 can also include circuitry for interfacing with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0041] The first SoC 202 and the second SoC 204 can communicate via an interconnect / bus module 250. In some embodiments, the interconnect / bus module can be a connection established by transceiver (i.e., receiving and transmitting) components within both SoC 202 and SoC 204. For example, the low-power processor 252 may include a universal asynchronous receiver-transmitter (UART), and the application processor 216 may include a multi-signal message (MSM) UART driver communicatively connected to the UART of the low-power processor 252.

[0042] Various processors 210, 212, 214, 216, and 218 can be interconnected via interconnect / bus module 226 to one or more memory elements 220, system components and resources 224, custom circuitry 222, and thermal management unit 232. Similarly, low-power processor 252 can be interconnected via interconnect / bus module 264 to power management unit 254, BT controller 256, memory 258, and various additional processors 260. Interconnect / bus modules 226, 250, and 264 may include arrays of reconfigurable logic gates and / or implement bus architectures (e.g., CoreConnect, AMBA, etc.). Communication may be provided by advanced interconnects, such as high-performance on-chip networks (NoC).

[0043] The first SoC 202 and / or the second SoC 204 may also include input / output modules (not illustrated) for communicating with external SoC resources such as clock 206, voltage regulator 208, one or more wireless transceivers 266, and at least one SIM 268 and / or SIM interface (i.e., an interface for accepting one or more SIM cards)). External SoC resources (e.g., clock 206, voltage regulator 208) may be shared by two or more internal SoC processors / cores. At least one SIM 268 (or one or more SIM cards coupled to one or more SIM interfaces) may store information supporting multiple subscriptions (including a first 5G NR subscription and a second 5G NR subscription, etc.).

[0044] In addition to the example computing device 200 discussed above, various implementations can also be implemented in a wide variety of computing systems, which may include a single processor, multiple processors, multi-core processors, or any combination thereof.

[0045] In some implementations, the various processors of SoC 202 and SoC 204 may reside within the same SoC. For example, application processor 216 and low-power processor 252 may reside within the same SoC, such as in a single SoC of a wearable device, to perform L2P table synchronization functionality.

[0046] Figure 3 is an example component block diagram illustrating an example system 300 configured to manage synchronization of L2P tables in accordance with some embodiments. Referring to Figures 1 to 3 , system 300 can include one or more computing devices 302 (e.g., system 100, computing device 200) and external resources 318 that can communicate via a communication link 324 (e.g., link 114). External resources 318 can include sources of information external to system 300, external entities that interact with system 300, or other resources. For example, external resources 318 can be a computing device that can send read requests to computing device 302. In some implementations, some or all of the functionality attributed herein to external resources 318 can be provided by resources included in system 300. System 300 can include a number of hardware, software, and / or firmware components that together operate to provide functionality attributed herein to processor 322 (e.g., host controller 104, 262).

[0047] Computing device 302 can include electronic storage 320 that can be configured to store information related to the functionality implemented by operating state notification module 330, HPB mode module 332, synchronization validation module 336, updated mapping module 338, legacy mode module 340, HPB L2P table synchronization module 342, and any other instruction modules.

[0048] Electronic storage 320 can include non-transitory storage media that electronically stores information. Electronic storage 320 can include one or both of

[0049] In various embodiments, electronic storage device 320 (e.g., DRAM 106, SRAM 110) may include one or more of charge-based storage media (e.g., EEPROM, RAM, etc.), solid-state storage media (e.g., flash memory drives, etc.), optically readable storage media (e.g., optical discs, etc.), magnetically readable storage media (e.g., magnetic tape, magnetic hard disk drives, floppy disk drives, etc.), and / or other electronically readable storage media. Electronic storage device 320 may include one or more virtual storage resources (e.g., cloud storage devices, virtual private networks, and / or other virtual storage resources). Electronic storage device 320 may store software algorithms, information determined by processor 322, and / or other information that enables system 300 to operate as described herein. Electronic storage device 320 may store one or more L2P address mapping tables (e.g., L2P-1, L2P-2).

[0050] The computing device 302 can be configured via machine-readable instructions 306. The machine-readable instructions 306 may include one or more instruction modules. Instruction modules may include computer program modules. Instruction modules may include one or more of the following: an operation status notification module 330, an HPB mode module 332, a synchronization verification module 336, an updated mapping module 338, a legacy mode module 340, an HPB L2P address mapping table synchronization module 342, and other instruction modules (not illustrated). The computing device 302 may include a processor 322 configured to implement the machine-readable instructions 306 and corresponding modules.

[0051] Processor 322 may include one of a plurality of local processors that can be configured to provide information processing capabilities in system 300. Therefore, processor 322 may include one or more of a digital processor, an analog processor, digital circuitry designed to process information, analog circuitry designed to process information, a state machine, and / or other mechanisms for electronically processing information. Although processor 322 is... Figure 3 The processor 322 is shown as a single entity, but this is for illustrative purposes only. In some embodiments, the processor 322 may include multiple processing units. These processing units may be physically located within the same device, or the processor 322 may represent the processing functionality of multiple devices distributed throughout the system 300.

[0052] In some embodiments, the processor 322 executing the operational state notification module 330 can be configured to generate a notification regarding one or more operational states of the host controller (e.g., host controller 104, 262) and / or the device controller (e.g., device controller 116). In some embodiments, the operational state of the host controller and / or the device controller can include a synchronization state that describes whether one or more portions of the L2P table on the host controller (e.g., host controller 104, 262) and / or the device controller (e.g., device controller 116) are unsynchronized. The operational state notification module 330 can generate a notification (e.g., a memory exception) upon a particular trigger (e.g., a read request) and / or can generate a notification based on a check or comparison.

[0053] The operational state can include a busy state or an available state, which can be obtained by determining a metric of pending and / or executing operations, such as a number of operations, a duration of execution of operations, etc., and comparing the metric to a threshold value for determining the operational state of the respective controller. In some embodiments, the operational state of the host controller and / or the memory device controller can be obtained by receiving and interpreting a signal from the host controller and / or the memory device controller that is configured to indicate the operational state.

[0054] In some embodiments, the processor 322 executing the HPB mode module 332 can enable the HCM and / or the DCM as HPB mode in response to the operational state of the host controller and / or the memory device controller. For example, the processor 322 executing the HPB mode module 332 can enable the DCM for HPB mode in response to the host controller having a busy operational state and the device controller having an available operational state. The processor 322 executing the HPB mode module 332 can enable the HCM for HPB mode in response to the host controller having an available operational state and the device controller having a busy operational state. Further, the HPB mode module 332 can determine whether the host controller and / or the memory device controller support synchronization of a portion of the L2P table corresponding to updated memory entries. The HPB mode module 332 can determine whether the host controller is enabled for this synchronization mode by checking for exceptions or notifications from the memory device controller. If such exceptions are not received within a predefined time period, the HPB mode module 332 can switch to a legacy mode. Likewise, the HPB mode module 332 can determine whether a host performance booster (HPB) mode is enabled on the host controller and / or the memory device controller, and if the HPB mode is not enabled, can switch to a legacy mode.

[0055] In some embodiments, the processor 322 executing the synchronization validation module 336 can be configured to determine whether the L2P address mapping table stored at the DRAM communicatively connected to the host controller has been synchronized with the L2P address mapping table stored on the NAND memory (e.g., 112) of the UFS device communicatively connected to the host controller via a link (e.g., link 114). As described above, the operating state notification module 330 can determine whether the L2P tables on the host controller and / or the memory device controller need to be updated or are out of sync. Upon synchronization, the synchronization validation module 336 can validate or confirm the synchronization of one or more memory mapping entries in the L2P tables. The synchronization validation module 336 can be configured on the memory device controller to reset one or more indicators corresponding to the memory mapping entries that have been synchronized. The synchronization validation module 336 can be configured on the memory device controller to reset one or more indicators corresponding to the memory mapping entries upon the updated entries being transmitted to the host controller and can encapsulate the updated mapping entries in case of a failed transmission to the host controller.

[0056] In some embodiments, the processor 322 executing the updated mapping module 338 can be configured to manage the recordation of memory mappings that need to be synchronized and memory mappings that have been updated. For example, the memory device controller can update one or more memory mappings as the L2P table synchronization is in progress and can change one or more mappings of logical to physical addresses before the indicator for the mapping being synchronized is reset. The updated mapping module 338 can coordinate with the synchronization validation module 336 and can monitor / control one or more memory operations (e.g., garbage collection) as the synchronization is in progress. The updated mapping module 338 can be configured to manage the updates in memory mappings that occur in the SRAM, NAND, and write boost buffers of the memory device (e.g., UFS device 106).

[0057] In some embodiments, the processor 322 executing the legacy mode module 340 can be configured to perform a legacy mode L2P address mapping table synchronization operation. The legacy mode module 340 can be configured to operate when the HPB mode or synchronization capabilities described herein are not enabled on the devices connected to the host controller and / or the memory device controller. In some embodiments, the legacy mode module 340 can be configured to perform a legacy mode L2P address mapping table synchronization operation when the HPB mode or synchronization capabilities described herein are not enabled on the devices connected to the host controller and / or the memory device controller. Figure 5 and Figure 6A The operation of the legacy mode is also described in

[0058] In some embodiments, the processor 322 executing the HPB L2P address table synchronization module 342 can be configured to perform L2P address mapping table synchronization in the HCM or DCM. The HPB L2P address table synchronization module 342 can be configured to connect to one or more input and output (I / O) functionalities of the host controller and / or the memory device controller to send and receive updated memory mappings and manage other I / O functionalities (e.g., read requests and responses) to coordinate with the synchronization.

[0059] The descriptions of the functionalities provided by the different modules 330-342 are for illustrative purposes and are not intended to be limiting, as any of the modules 330-342 can provide more or less functionality than described. For example, one or more of the modules 330-342 can be eliminated, and some or all of their functionality can be provided by other ones of the modules 330-342. As another example, the processor 322 can execute one or more additional modules that can perform some or all of the functionality attributed below to one of the modules 330-342.

[0060] In some embodiments, the operating state notification module 330, the HPB mode module 332, the synchronization validation module 336, the updated mapping module 338, the legacy mode module 340, the HPB L2P address table synchronization module 342 can be implemented by a host controller (e.g., the host controller 104, 262) of the computing device 302, which can be and / or include the processor 322.

[0061] Figure 4 is an assembly block diagram and signaling diagram illustrating an example for synchronizing L2P tables according to some embodiments. Referring to Figures 1 to 4 The host controller 104 (e.g., the host controller 262, the processor 322) of a SoC (e.g., the SoC 102, 202) can be communicatively connected to a device controller 116 of a UFS device (e.g., the UFS device 106) via a link (e.g., the link 114). The host controller 104 and the device controller 116 can each be configured to execute computer code to implement computing operations. The host controller 104 and the device controller 116 can each be configured to transmit and receive signals between components of a computing device (e.g., the system 100, the computing device 200), including between each other, via the link 114, which can include computing data and / or computing instructions.

[0062] Referring to Figure 4In operation 402, the device controller 116 can send a notification to the host controller 104 that the L2P table of the device controller 116 has been updated. The notification can include a memory exception and can be performed in response to a read request from the host controller 104. The notification can include a memory interrupt or an I / O interrupt to notify the host controller 104 that the memory mapping stored in its memory can not be accurate. The notification, exception, or interrupt can be sent in response to a read request in which the logical address or logical to physical mapping in the read request is incorrect due to a change in the L2P table of the UFS device 106. The notification, exception, or interrupt can be sent in response to a set bit or other indicator in the L2P table being modified that identifies that at least one logical to physical mapping in the L2P table has been updated.

[0063] In operation 404, the host controller 104 can send a request for updated entries to synchronize the L2P table and the memory device controller 116 can receive the request for updated entries to synchronize the L2P table. The request for updated memory mapping entries can be sent in the form of a UFS protocol information unit (UPIU). The request for updated memory mapping entries from the host controller 104 can be communicated in response to the notification / interrupt of operation 402. The request for updated memory mapping entries of operation 404 can be a command (e.g., HPB_UPDATE_MNT command).

[0064] In operation 406, the device controller 116 can send a set of one or more memory mappings and the host controller 104 can receive the set of one or more memory mappings, which can list the 8 byte entries or rows that map logical to physical addresses (e.g., a = B). A leading byte can indicate how many active L2P entries in the update being sent are being updated. The set of one or more memory mappings or mapping entries sent from the L2P table can be ordered in the order of the update time, or ordered for sequential insertion into the host controller's L2P table, or ordered in any other manner or not ordered. The set of one or more memory mappings can be copied from the top (first row) of the L2P table of the UFS device.

[0065] In operation 408, the host controller 104 reads the received set of one or more memory mappings and incorporates them into the local L2P table to update the local L2P table with the received set of entries / mappings. The L2P address mapping table stored in the DRAM 108 can be synchronized by the host controller 104 by finding each logical or physical address in the L2P table that corresponds to the updated entries and replacing the entries / mappings in the host controller's 104 L2P table. The host controller's 104 L2P address mapping table can be updated by other data merging methods. The host controller 104 can process the received set of one or more memory mappings before inserting the received memory mappings into the local L2P table. The received set of one or more memory mappings can be inserted into the host controller's 104 local L2P table individually.

[0066] In operation 410, the host controller 104 can send an acknowledgement that the L2P table update was successful and the device controller 116 can receive the acknowledgement that the L2P table update was successful. In some embodiments, the acknowledgement can include a summary or list of logical addresses that were updated in the host controller's 104 local L2P table. The device controller 116 (or synchronization validation module 336) can acknowledge the list or record the L2P table as synchronized (e.g., change a synchronization state or operational state).

[0067] In operation 412, the memory device controller 116 can reset one or more indicators corresponding to the updated memory mappings. In some embodiments, in operation 412, the memory device controller 116 can reorder the memory device controller's 116 L2P table so that the updated memory mappings are inserted into their ordered position in the L2P table. The memory device controller 116 can then be ready to satisfy read requests from the host controller 104 based on the logical addresses stored in the host controller's 104 L2P table, including the updated addresses.

[0068] Figures 5 to 6D is a process flow diagram of example methods 500, 600a, 600b, 600c, and 600d in accordance with various embodiments. Figure 5 is a process flow diagram of example method 500 that can be performed by a host controller of a computing device (e.g., by a processor within the host controller) for synchronizing an L2P table in accordance with various embodiments. Figures 6B to 6C is a process flow diagram of example operations 600b-600e that can be performed as part of method 600a as described for synchronizing an L2P table in accordance with some embodiments. Reference is made to Figures 1 to 6DMethods 500 and 600a-600e can be performed by a host controller (e.g., 104, 262) and / or a memory device controller 116 of a computing device (e.g., 102, 200, 302). In some embodiments, the host controller (e.g., 104, 262) can include a processor configured to perform operations by processor-executable instructions stored in a non-transitory processor-readable medium (e.g., 108, 220, 258, 320). In some embodiments, the memory device controller (e.g., 116) or UFS device (e.g., 106, 272) can include a processor configured to perform operations by processor-executable instructions stored in a non-transitory processor-readable medium (e.g., 108, 220, 258, 320). The components for performing the operations of methods 500 and 600a-600d can be processors of systems 100, 200, and 300, such as processors 102, 252, 322, etc., as described with reference to Figures 1 to 6D

[0069] Figure 5 In block 502, a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302) can perform operations including initiating a read request from a file system. The read request initiation can include configuring the host controller to receive the read request (e.g., from a component of the SoC 102, 202 or a component or device communicatively connected to the SoC 102, 202 via an I / O interface). The components for performing the operations of block 502 can include a host controller (e.g., 104, 262) and a wireless transceiver (e.g., 266) of a computing device (e.g., 102, 200, 302).

[0070] In block 504, a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302) can perform operations including retrieving a host controller command. The components for performing the operations of block 504 can include a host controller (e.g., 104, 262) and a wireless transceiver (e.g., 266) of a computing device (e.g., 102, 200, 302).

[0071] In determination block 506, a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302) can perform operations including determining whether HPB is enabled. The components for performing the operations of determination block 506 can include a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302) and can include performing HPB mode module 332.

[0072] ​​In response to determining that HPB is not enabled (i.e., determination block 506 = "No"), the host controller can perform memory read legacy operations in blocks 508, 510, and 512. For example, in block 508, the host controller can obtain an address corresponding to a read request from the memory controller (e.g., 116). In block 510, the host controller can update the legacy memory map in the SRAM (e.g., 110) by copying an entire block of the active portion of the legacy memory table from the device controller (e.g., 116). In block 512, the host controller can read data directly from the NAND flash memory (e.g., 112) via the device controller (e.g., 116). The components for performing the operations of blocks 508, 510, and 512 can include the host controller (e.g., 104, 262) of the computing device (e.g., 102, 200, 302) and can include the execute legacy mode module 340.

[0073] In response to determining that HPB is enabled (i.e., determination block 606 = "Yes"), in determination block 514, the host controller and / or the memory controller can determine whether the second L2P table (e.g., L2P-2) of the UFS device 106 includes an indicator that marks which address mappings on the second L2P table are updated. The components for performing the operations of determination block 514 can include the host controller (e.g., 104, 262) of the computing device (e.g., 102, 200, 302) and can include the execute HPB mode module 332.

[0074] In response to determining that the L2P table (e.g., L2P-2) stored in the SRAM (e.g., 110) or the NAND memory 112 of the UFS device (e.g., 106) that is communicatively connected to the host controller via the link (e.g., 114) does not contain any mapping update indicators (e.g., no indicator of whether updated) for the separate memory mapping entries of the L2P table (i.e., determination block 514 = "No"), the host controller can revert to legacy mode and perform blocks 508, 510, and 512. In legacy mode, if the first L2P table (e.g., L2P-1) stored in the DRAM (e.g., 108) that is communicatively connected to the host controller is not synchronized with the L2P table (e.g., L2P-2) stored in the SRAM (e.g., 110) of the UFS device (e.g., 106), the entire active region of the L2P table can be copied from the UFS device to the host controller.

[0075] In response to determining that the L2P table (e.g., L2P-2) stored in the SRAM (e.g., 110) or the NAND memory (e.g., 112) of the UFS device (e.g., 106) communicatively connected to the host controller via a link (e.g., 114) does contain the indicator for the separate memory mapping entries of the L2P table (i.e., determination block 514 =“Yes”), the host controller and / or the memory controller can proceed to block 518. In block 518, the memory controller (e.g., 116) or the UFS device 106 can modify the indicator in the memory table (e.g., L2P-2) on the storage device that maps logical addresses to physical addresses of memory on the storage device in response to a change in the memory mapping, the indicator identifying one or more address mapping changes of the memory table. Components for performing the operations of block 518 can include the host controller (e.g., 104, 262) and / or the memory controller (e.g., 116) of the computing device (e.g., 102, 200, 302), and can include the operational state notification module 330 and the updated mapping module 338.

[0076] In block 520, the memory controller can notify the host controller about the updates to the L2P table on the UFS device. In response to determining that the UFS (e.g., 106) is configured to indicate which memory mapping entries need updates by the host controller (i.e., determination block 514 =“Yes”), the host controller and / or the memory controller can operate together to update those entries in blocks 520, 522, 524, 526, and 528. The device controller managing the UFS device memory can maintain a history of (i) updated L2P table entries and (ii) the last time the L2P table (e.g., L2P-2) was synchronized with the host controller. Components for performing the operations of block 520 can include the host controller (e.g., 104, 262) and / or the memory controller (e.g., 116) of the computing device (e.g., 102, 200, 302), and can include the operational state notification module 330.

[0077] In block 522, the memory controller can receive a request to send only updates with changed L2P mappings, and the host controller can send a request to send only updates with changed L2P mappings. In other words, this request (e.g., HPB_UPDATE_MNT) can be related only to those entries in the L2P table of the memory controller that have been indicated as updated, rather than sending the entire block of the active region of the L2P table. Components for performing the operations of block 522 can include the host controller (e.g., 104, 262) and / or the memory controller (e.g., 116) of the computing device (e.g., 102, 200, 302), and can include the updated mapping module 338.

[0078] In block 524, the memory controller can send changed L2P mappings from a second L2P table (e.g., L2P-2) of the UFS device to the host controller, and the host controller can receive changed L2P mappings from the second L2P table of the UFS device from the memory controller. The sent mappings may correspond to mapping entries indicated as changed or requiring updating. The sent mappings may correspond to mapping entries that have been updated since the last synchronization and were not synchronized at the time of the notification in block 522. The host controller may apply the changed entries from the second L2P table (e.g., L2P-2) to the host controller's first L2P table (e.g., L2P-1) to synchronize the tables. Figure 4 This describes such synchronization or merging / replacement of changed entries in the L2P table of the host controller. Components for performing the operations of box 524 may include host controllers (e.g., 104, 262) of computing devices (e.g., 102, 200, 302) and / or memory device controllers (e.g., 116), and may include a mapping module 338 that performs the update.

[0079] In block 526, the host controller (e.g., 104, 262) may send an acknowledgment of an update to the first L2P table, and the memory controller (e.g., 116) may receive the acknowledgment of an update to the first L2P table. Based on the acknowledgment, the memory controller (e.g., 116) may reset one or more indicators for one or more memory-mapped entries that have been updated and synchronized in the second L2P table. Components for performing the operations of block 526 may include the host controller (e.g., 104, 262) and / or the memory device controller (e.g., 116) of the computing device (e.g., 102, 200, 302), and may include a synchronization verification module 336.

[0080] In box 528, the memory controller can process memory requests from the host device based on one or more addresses affected by one or more address mapping changes. In other words, after synchronization, the memory controller can use the updated and verified physical addresses from the host controller's L2P table. Components used to perform the operations of box 526 may include the host controller (e.g., 104, 262) of the computing device (e.g., 102, 200, 302) and / or the memory device controller (e.g., 116).

[0081] In determination block 530, a host controller (e.g., 104, 262) and / or a memory controller (e.g., 116) of a computing device (e.g., 102, 200, 302) can determine whether the read request is related to an updated entry or an updated region. This determination of determination block 530 can be performed when synchronizing the L2P table as described in blocks 520-526. Since the read request can trigger the notification of block 520, the read request can need to be processed before the L2P table is updated. Means for performing the determination of block 530 can include a host controller (e.g., 104, 262) and / or a memory controller (e.g., 116) of a computing device (e.g., 102, 200, 302).

[0082] In response to determining that the read request is not related to an updated region (i.e., determination block 530 = “No”), in block 532, the memory controller can read from the UFS device using the L2P mapping in the HPB cache. In other words, the read request can be performed in the memory controller using the logical block data (address) received from the host controller. Means for performing the operations of block 532 can include a host controller (e.g., 104, 262) and / or a memory controller (e.g., 116) of a computing device (e.g., 102, 200, 302).

[0083] In response to determining that the read request is related to an updated region (i.e., determination block 530 = “Yes”), the memory controller can perform operations in block 534 including retrieving at least one modified L2P mapping entry from the UFS (e.g., 106), where the at least one modified L2P mapping entry is stored within the local L2P table (e.g., stored in the NAND memory 112 and / or stored in L2P-2 of SRAM 110). In some embodiments, retrieving the at least one modified L2P mapping entry from the UFS can also include sending a read message from the host controller to a device controller (e.g., 116) of the UFS, the read message configured to cause the device controller to read logical block data from a NAND flash memory (e.g., NAND memory 112) within the UFS, where the logical block data is associated with the at least one modified L2P mapping entry (i.e., in the L2P-2 table of NAND 112), and receiving the logical block data from the device controller. Means for performing the operations of block 534 can include a host controller (e.g., 104, 262) and / or a memory controller (e.g., 116) of a computing device (e.g., 102, 200, 302).

[0084] Figure 6A is a process flow diagram of an example method 600a for synchronizing an L2P table that can be performed by a host controller of a computing device according to various embodiments. Figures 6B to 6Dis a process flow diagram of example operations 600b-600d in accordance with some embodiments, which can be performed as part of method 600a as described for a synchronized L2P table. Referring to Figures 1 to 6D , method 600a and operations 600b-600d can be performed by a host controller (e.g., 104, 262) and / or a memory controller (e.g., 116) of a computing device (e.g., 102, 200, 302). In some embodiments, the host controller (e.g., 104, 262) and / or the memory controller (e.g., 116) can be configured to perform the operations by processor-executable instructions stored in a non-transitory processor-readable medium (e.g., 108, 220, 258, 320). The components for performing the operations of method 600a and each of operations 600b-600e can be a processor of systems 100, 200, and 300, such as processor 102, 252, 322, etc., as described with reference to Figures 1 to 6D .

[0085] Referring to Figure 6A and method 600a, in block 602, a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302) can perform operations including initiating a read request from a file system. The read request initiation can include configuring the host controller to receive a read request (e.g., from a component of SoC 102, 202 or a component or device communicatively connected to SoC 102, 202 via an I / O interface). The components for performing the operations of block 602 can include a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302).

[0086] In block 604, the host controller can process the read request at a UFS device (e.g., 106), which can include sending the read request with a logical block address to a memory controller (e.g., 116). The components for performing the operations of block 604 can include a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302).

[0087] In determination block 606, after receiving and processing one or more read requests, the host controller can determine whether a HPB update notification has been received within a time period. The HPB update notification can be an exception event control or an interrupt from the UFS device indicating that an update is available for synchronization. The components for performing the operations of block 604 can include a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302).

[0088] In response to determining that no HPB update notification (e.g., interrupt or exception) has been received within a time period (i.e., determination block 606 = "No"), the host controller can perform memory read legacy operations in blocks 608, 610, and 612. In block 608, the host controller can obtain an address corresponding to a read request from a memory controller (e.g., of SoC 102, 202). In block 610, the host controller can update an address mapping table entry in SRAM (e.g., SRAM 110). In block 612, the host controller can read raw data from NAND flash memory (e.g., NAND memory 112) via a memory device controller (e.g., device controller 116). Regarding Figure 5 The legacy mode is also described. Means for performing the operations of blocks 608, 610, and 612 can include a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302).

[0089] In response to determining that an HPB update notification has been received within a time period (i.e., determination block 606 = "Yes"), in block 614, the host controller can enable an HPB update mechanism of the host controller and the memory device controller. The HPB update mechanism can include the ability of the host controller to send a request for an updated L2P table entry. The HPB update mechanism can include the ability of the memory controller to send a notification that an updated L2P table entry is available (i.e., needs to be synchronized) and send the updated L2P entry to the host controller. The host controller and the memory device controller can proceed to blocks 520-528 after block 614. Means for performing the operations of block 614 can include a host controller (e.g., 104, 262) of a computing device (e.g., 102, 200, 302).

[0090] Referring to Figure 6B And method 600b, the memory controller (e.g., 116) can perform the operations of block 622 as part of block 518, where the modification of the indicator is used to identify one or more L2P mapping entries that need to be synchronized. The operations of block 622 can be performed after the operations in block 514 of method 500, and can be followed by the operations in block 520 of method 500 as described. In block 622, the memory controller (e.g., 116) modifies a bit value of the indicator for each updated L2P entry. In other words, the indicator used by the memory controller to identify L2P entries that have been updated on the UFS device (e.g., 106) can be a bit value assigned to each L2P entry (e.g., 0 = not updated; 1 = updated). Means for performing the operations of block 622 can include a memory controller (e.g., 116) of a computing device (e.g., 106, 200, 302).

[0091] Referring to Figure 6C And method 600c, the memory controller (e.g., 116) can perform the operations of block 624 as part of the operations of block 518, where the modification of the indicator is to identify one or more L2P mapping entries that need to be synchronized. In block 624, the memory controller (e.g., 116) can modify the value of a variable that indicates an interface in the L2P table between the updated L2P entries and the previously synchronized L2P entries. For example, a first pointer can record (or indicate) a starting position where the updated entries start in the L2P table, and a second pointer can record an ending position of the updated entries (e.g., an interface) where the non-updated entries start in the L2P table. The first pointer can be optional if the updated entries are stored at the top (first position) of the table. The operations in block 624 can be performed after the operations of block 514 of method 500, and can be followed by the operations of block 520 of method 500 as described. Means for performing the operations of block 624 can include a memory controller (e.g., 116) of a computing device (e.g., 106, 200, 302).

[0092] Referring to Figure 6D And method 600d, in determination block 630, the host controller can determine whether the L2P address mapping tables are synchronized. The memory device controller (e.g., device controller 116) can determine whether the L2P address mapping table (e.g., L2P-1) stored in the DRAM (e.g., DRAM 108) communicatively connected to the host controller and the L2P address mapping table (e.g., L2P-2) stored in the NAND memory (e.g., NAND memory 112) of the UFS device (e.g., UFS device 102) and communicatively connected to the memory device controller are synchronized or unsynchronized. Means for performing the determination of block 630 can include a memory controller (e.g., 116) of a computing device (e.g., 106, 200, 302).

[0093] In response to determining that the L2P address mapping tables are synchronized and not unsynchronized (i.e., determination block 630 = “No”), the memory controller and / or the host controller can continue other processes, and can repeat the operations in determination block 630 until the updates to the L2P table of the memory controller cause the L2P address mapping tables to be unsynchronized (i.e., determination block 630 = “Yes”).

[0094] In response to determining that the L2P address mapping tables are unsynchronized and thus unsynchronized (i.e., determination block 630 = “Yes”), the memory controller can determine in determination block 632 whether the active or non-active region of the L2P table needs to be updated. Means for performing the determinations of block 630 and block 632 can include a memory controller (e.g., 116) of a computing device (e.g., 106, 200, 302).

[0095] In response to determining that the inactive region of the L2P address mapping table needs to be updated (i.e., determination block 632 =“Yes, Inactive”), the memory controller and / or host controller can revert to the legacy mode to synchronize the L2P table in block 636, which can include updating the full region (i.e., active and inactive). For example, if the UFS device (e.g., 106) exits hibernation, the inactive region of the L2P table can need to be changed. The components for performing the operations of block 636 can include the memory controller (e.g., 116) and / or host controller (e.g., 104) of the computing device (e.g., 106, 200, 302).

[0096] In response to determining that the active region of the L2P address mapping table needs to be updated (i.e., determination block 632 =“Yes, Active”), the memory controller and / or host controller can update the one or more active entries indicated as needing to be updated in block 634 (e.g., as described in methods 600b and 600c). The memory controller can then perform the operations of block 514 of method 500, where it can be determined whether the host controller and / or memory controller support the indicator of individual memory mapping entries that have changed and synchronization. The components for performing the operations of block 634 can include the memory controller (e.g., 116) and / or host controller (e.g., 104) of the computing device (e.g., 106, 200, 302).

[0097] Various embodiments, including but not limited to the embodiments described with reference to Figures 1 to 6D The described embodiments can be implemented in a wide variety of computing systems, which can include laptop computer 700 (e.g., computing device 100, 200, 320), examples of which are illustrated in Figure 7 FIG. 10. With reference to Figures 1 to 7A laptop computer can include a touchpad touch surface 717 that serves as a pointing device for the computer and thus can receive drag, scroll, and tap gestures similar to those implemented on computing devices equipped with touch screen displays and as described above. The laptop computer 700 will typically include a processor 702 coupled to volatile memory 712 and a large capacity nonvolatile memory, such as a disk drive 713. Additionally, the computer 700 can have one or more antennas 708 for transmitting and receiving electromagnetic radiation that can be connected to a wireless data link and / or to a cellular telephone transceiver 716 coupled to the processor 702. The computer 700 can also include a floppy disk drive 714 and a compact disk (CD) drive 715 coupled to the processor 702. The laptop computer 700 can include a touchpad 717, a keyboard 718, and a display 719 all coupled to the processor 702. Other configurations of the computing device can include a computer mouse or trackball coupled to the processor as is well known (e.g., via a USB input), which can also be used in conjunction with various embodiments.

[0098] Figure 8 is a component block diagram of a computing device 800, such as a server, suitable for use with various embodiments. Such a computing device can include at least the illustrated components. Figure 8 Referring to Figures 1 to 8 , the computing device 800 (e.g., computing device 100, 200, 320) can include a processor 801 coupled to volatile memory 802 and a large capacity nonvolatile memory, such as a disk drive 803.

[0099] The computing device 800 can also include a peripheral memory access device coupled to the processor 801, such as a floppy disk drive, compact disk (CD) or digital video disk (DVD) drive 806. The computing device 800 can also include a network access port 804 (or interface) coupled to the processor 801 for establishing data connections with a network, such as the Internet and / or a local area network coupled to other system computers and servers.

[0100] The computing device 800 can include one or more antennas 807 for transmitting and receiving electromagnetic radiation that can be connected to a wireless communication link. The computing device 800 can include additional access ports for coupling to peripheral devices, external memory, or other devices, such as USB, Firewire, Thunderbolt, etc.

[0101] Figure 9 is a component block diagram of a computing device 900 suitable for use with various embodiments. Referring to Figures 1 to 9Various implementation schemes can be implemented on various computing devices 900 (e.g., computing devices 100, 200, 320), examples of which are shown in […]. Figure 9 The example is illustrated in the form of a smartphone. The computing device 900 may include a first SoC 202 (e.g., an SoC-CPU) coupled to a second SoC 204 (e.g., a 5G-capable SoC). The first SoC 202 and the second SoC 204 may be coupled to internal memory 916, a display 912, and a speaker 914. The first SoC 202 and the second SoC 204 may also be coupled to at least one SIM 268 and / or a SIM interface, which may store information supporting a first 5G NR subscription and a second 5G NR subscription, which support services on a 5G non-autonomous (NSA) network.

[0102] The computing device 900 may include an antenna 904 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless transceiver 266 coupled to one or more processors in the first SoC 202 and / or the second SoC 204. The computing device 900 may also include a menu selection button or rocker switch 920 for receiving user input.

[0103] The computing device 900 also includes a sound codec (CODEC) circuit 910 that digitizes sound received from a microphone into data packets suitable for wireless transmission and decodes the received sound data packets to generate an analog signal for use with a speaker to produce sound. Additionally, one or more of the processor in the first SoC 202 and the second SoC 204, the wireless transceiver 266, and the CODEC 910 may include a digital signal processor (DSP) circuitry (not shown separately).

[0104] The processors of computer 700, computing device 800, and computing device 900 can be any programmable microprocessor, microcomputer, or one or more multiprocessor chips that can be configured via software instructions (applications) to perform a variety of functions, including those described in the various embodiments below. In some mobile devices, multiple processors may be provided, such as one processor within SoC 204 dedicated to wireless communication functions and another within SoC 202 dedicated to running other applications. Software applications may be stored in memories 220, 916, and subsequently accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0105] The following paragraphs describe specific implementation examples. While some of the following specific implementation examples are described in terms of example methods that can be performed by a host controller in a computing device, additional example implementations can include: a computing device comprising a host controller configured to perform the methods of the following specific implementation examples; a computing device comprising components to perform the functionality of the following specific implementation examples, a host controller adapted for use in a computing device, wherein the host controller comprises a processor configured to perform the methods of the following specific implementation examples; and a non-transitory processor-readable memory having stored thereon processor-executable instructions configured to cause a host controller in a computing device to be configured to perform the methods of the following specific implementation examples.

[0106] Example 1. A method performed in a storage device for synchronizing a memory table between the storage device and a host device, the method comprising: in response to a change in a memory mapping, modifying an indicator in a first memory table on the storage device, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table; notifying the host device that the first memory table has been modified; sending to the host device at least a portion of the first memory table including the one or more address mapping changes; and processing, by the storage device, a first memory request from the host device based on one or more addresses affected by the one or more address mapping changes.

[0107] Example 2. The method of example 1, wherein the portion of the first memory table sent to the host device corresponds to the one or more address mapping changes.

[0108] Example 3. The method of any of examples 1 or 2, the method further comprising receiving, by the storage device, a request for the one or more address mapping changes

[0109] Example 4. The method of any of examples 1-3, wherein the first memory request includes a physical address updated based on the one or more address mapping changes.

[0110] Example 5. The method of any of examples 1-4, wherein the indicator is a bit value assigned to each memory mapping in the first memory table, and wherein the bit value changes when the corresponding memory mapping changes.

[0111] Embodiment 6. The method of any one of embodiments 1 to 4, wherein the indicator is a value indicative of a location in the first memory table, the location corresponding to an interface between a synchronized portion of the first memory table and an unsynchronized portion of the first memory table, the unsynchronized portion of the first memory table corresponding to the one or more mapped address changes.

[0112] Embodiment 7. The method of any one of embodiments 1 to 6, further comprising resetting the indicator upon receiving an acknowledgement from the host device that the portion of the first memory table has been received.

[0113] Embodiment 8. The method of any one of embodiments 1 to 7, further comprising sending a notification to the host device upon modifying the indicator in the first memory table on the storage device.

[0114] As used in this application, the terms “component,” “module,” “system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution, which is configured to perform particular operations or functions. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be referred to as a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed across one or more processors or cores. Also, these components can execute from various non-transitory computer-readable media, such as main memory or a storage device. Components can communicate via local and / or remote processes, function- or procedure-calls, electronic signals, data packets, memory reads / writes, and other known computer, processor, and / or process related communication methodologies.

[0115] A number of different cellular and mobile communication services and standards are available and contemplated in the future, all of which can implement and benefit from the various embodiments. Such services and standards include, for example, Third Generation Partnership Project (3GPP), Long-Term Evolution (LTE) systems, Third Generation wireless mobile communication technology (3G), Fourth Generation wireless mobile communication technology (4G), Fifth Generation wireless mobile communication technology (5G), and beyond, Global System for Mobile Communication (GSM), Universal Mobile Telecommunication System (UMTS), 3GSM, General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA) systems (e.g., cdmaOne, CDMA1020TM), Enhanced Data Rates for GSM Evolution (EDGE), Advanced Mobile Phone System (AMPS), IS- 136 / TDMA, Evolution-Data Optimized (EV-DO), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WiMAX), Wireless Local Area Network (WLAN), Wi-Fi Protected Access I and II (WPA, WPA2), and Integrated Digital Enhanced Network (iDEN). Each of these technologies relates to the transmission and reception of, for example, voice, data, signaling, and / or content messages. It should be understood that any reference to terminology and / or technical details related to an individual telecommunication standard or technology is for illustrative purposes only and is not intended to limit the scope of the claims to a particular communication system or technology unless specifically recited in the claim language.

[0116] The various embodiments illustrated and described are provided merely as examples of various features of the claims. However, the features shown and described with respect to any given embodiment need not be limited to the associated embodiment and can be used or combined with other embodiments shown and described. Moreover, the claims are not intended to be limited to any one example embodiment. For example, one or more operations of a method can be substituted for or combined with one or more operations of a method.

[0117] The foregoing method descriptions and the process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by one of ordinary skill in the art, the order of operations in the foregoing embodiments can be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the operations; these words are simply used to guide the reader through the description of the methods. Furthermore, any reference to claim elements in the singular, for example, using the articles "one," "the," or "said," is not

[0118] The various illustrative logical blocks, modules, circuits, and algorithm operations described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0119] The hardware used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field

[0120] In one or more embodiments, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of a method or algorithm disclosed herein can be embodied in a processor-executable software module, which can reside on a non-transitory computer- or processor- readable storage medium. Non-transitory computer- or processor-readable storage media can be any storage media that can be accessed by a computer or a processor. By way of example but not limitation, such non-transitory computer- or processor-readable media can include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks and Blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of non-transitory computer- and processor-readable media. Additionally, the operations of a method or algorithm can reside in one or any combination of the above memory hardware, and the operations can be carried out by one or more processors or processor cores. The processor can be implemented as one chip or multiple chips.

[0121] The above description of disclosed embodiments is provided to enable any person skilled in the art to practice or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the claims and the principles and novel features disclosed herein.

Claims

1. A method, performed in a storage device, for synchronizing a memory table between the storage device and a host device, the method comprising: in response to a change in a memory mapping, modifying an indicator in a first memory table on the storage device, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes to the first memory table; notifying the host device that the first memory table has been modified; sending to the host device at least a portion of the first memory table including the one or more address mapping changes; and processing, by the storage device, a first memory request from the host device based on one or more addresses affected by the one or more address mapping changes.

2. The method of claim 1, wherein the portion of the first memory table sent to the host device corresponds to the one or more address mapping changes.

3. The method of claim 1, the method further comprising receiving, by the storage device, a request for the one or more address mapping changes.

4. The method of claim 1, wherein the first memory request includes a physical address updated based on the one or more address mapping changes.

5. The method of claim 1, wherein the indicator is a bit value assigned to each memory mapping in the first memory table, wherein the bit value changes when the corresponding memory mapping changes.

6. The method of claim 1, wherein the indicator is a value indicating a location in the first memory table corresponding to an interface between a synchronized portion of the first memory table and an unsynchronized portion of the first memory table, the unsynchronized portion of the first memory table corresponding to the one or more mapping address changes.

7. The method of claim 1, the method further comprising resetting the indicator upon receiving an acknowledgement from the host device that the portion of the first memory table has been received.

8. The method of claim 1, the method further comprising sending a notification to the host device upon modifying the indicator in the first memory table on the storage device.

9. A flash storage device, the flash storage device comprising: a plurality of logical units of memory; a processor coupled to the memory and configured to: in response to a change in a memory mapping, modify an indicator in a first memory table on the storage device, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes to the first memory table; notify a host device that the first memory table has been modified; send to the host device at least a portion of the first memory table including the one or more address mapping changes; and process a first memory request from the host device based on one or more addresses affected by the one or more address mapping changes.

10. The flash memory storage device of claim 9, wherein the portion of the first memory table sent to the host device corresponds to the one or more address mapping changes.

11. The flash memory storage device of claim 9, wherein the processor is further configured to receive a request for the one or more address mapping changes.

12. The flash memory storage device of claim 9, wherein the first memory request includes a physical address updated based on the one or more address mapping changes.

13. The flash memory storage device of claim 9, wherein the indicator is a bit value assigned to each memory mapping in the first memory table, and wherein the bit value changes when the corresponding memory mapping changes.

14. The flash memory storage device of claim 9, wherein the indicator is a value indicating a location in the first memory table that corresponds to an interface between a synchronized portion of the first memory table and an unsynchronized portion of the first memory table, the unsynchronized portion of the first memory table corresponding to the one or more mapping address changes.

15. The flash memory storage device of claim 9, wherein the processor is further configured to reset the indicator upon receiving an acknowledgement from the host device that the portion of the first memory table has been received.

16. The flash memory storage device of claim 9, wherein the processor is further configured with processor-executable instructions to send a notification to the host device after modifying the indicator in the first memory table on the storage device.

17. A flash memory storage device, the flash memory storage device comprising: means for modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table; means for notifying a host device that the first memory table has been modified; means for sending at least a portion of the first memory table including the one or more address mapping changes to the host device; and means for processing a first memory request from the host device based on one or more addresses affected by the one or more address mapping changes.

18. The flash memory storage device of claim 17, wherein the portion of the first memory table sent to the host device corresponds to the one or more address mapping changes.

19. The flash memory storage device of claim 17, further comprising means for receiving a request for the one or more address mapping changes.

20. The flash memory storage device of claim 17, wherein the first memory request includes a physical address updated based on the one or more address mapping changes.

21. The flash memory storage device of claim 17, wherein the indicator is a bit value assigned to each memory mapping in the first memory table, wherein the bit value changes when the corresponding memory mapping changes.

22. The flash memory storage device of claim 17, wherein the indicator is a value indicating a location in the first memory table that corresponds to an interface between a synchronized portion of the first memory table and an unsynchronized portion of the first memory table, the unsynchronized portion of the first memory table corresponding to the one or more mapping address changes.

23. The flash memory storage device of claim 17, further comprising means for resetting the indicator upon receiving an acknowledgement from the host device that the portion of the first memory table has been received.

24. The flash memory storage device of claim 17, further comprising means for sending a notification to the host device upon modifying the indicator in the first memory table on the storage device.

25. A computing device, the computing device comprising: a host device; and a flash memory storage device communicatively coupled to the host device, the flash memory storage device comprising: a plurality of logical units of memory; and a processor coupled to the memory and configured to: modify an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table; notify the host device that the first memory table has been modified; send to the host device at least a portion of the first memory table including the one or more address mapping changes; and process a first memory request from the host device based on one or more addresses affected by the one or more address mapping changes.

26. The computing device of claim 25, wherein the portion of the first memory table sent to the host device corresponds to the one or more address mapping changes.

27. The computing device of claim 25, wherein the processor is further configured to receive a request for the one or more address mapping changes.

28. The computing device of claim 25, wherein the first memory request includes a physical address updated based on the one or more address mapping changes.

29. The computing device of claim 25, wherein the indicator is a bit value assigned to each memory mapping in the first memory table, and wherein the bit value changes when the corresponding memory mapping changes.

30. The computing device of claim 25, wherein the indicator is a value indicating a location in the first memory table that corresponds to an interface between a synchronized portion of the first memory table and an unsynchronized portion of the first memory table, the unsynchronized portion of the first memory table corresponding to the one or more mapped address changes.

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