Cross-clock domain data transmission method and circuit system

Abstract

The invention discloses a cross-clock domain data transmission method and a circuit system. The method comprises the following steps: firstly, obtaining data to be transmitted; then, based on the to-be-transmitted data, a PLL output phase adjustment function in the FPGA is utilized, the phase of a RESET emission clock is adjusted through fine grit, fine grit adjustment of the RESET pulse phase and the phase of a data sending clock of the analog-to-digital converter is achieved, and the target clock phase of data sending of the analog-to-digital converter is determined; wherein the target clock phase enables the data to be transmitted to be correctly sampled by a system clock domain of the FPGA. And low delay, stable and reliable transmission of clock domain crossing data is realized, and scene requirements of data transmission and the like with extremely high delay and reliability requirements are met.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a method and circuit system for cross-clock domain data transmission. Background Technology

[0002] In existing technology, when the computing module uses the 125MHz serial-to-parallel conversion module generated by the FPGA's internal PLL to acquire data sent from the module, this data is transmitted by a 125MHz clock generated by the BUFR. Although the two clocks have the same frequency, their phases are unknown. There are two main factors that cause the phase unknown: first, the delay of the circuit board and the internal wiring of the chip is unknown; second, it is unknown from which clock edge of 1GHz the frequency divider circuit in the analog-to-digital converter begins to divide the frequency.

[0003] For transmitting large amounts of data between two unknown phase clock domains, the usual practice is to use an asynchronous FIFO. However, an asynchronous FIFO introduces a delay of several cycles. In scenarios where data transmission latency requirements are high, such as the transmission of superconducting quantum bit oscillation waveform data, this delay cannot meet the requirements. Therefore, there is an urgent need for a cross-clock domain data transmission method that can achieve low-latency data transmission. Summary of the Invention

[0004] The purpose of this invention is to provide a method and circuit system for cross-clock domain data transmission to overcome the shortcomings of the prior art. By overcoming the high latency defect in the prior art when using asynchronous FIFO for cross-clock domain data transmission, it provides a method and circuit system for cross-clock domain data transmission to achieve low latency, stable and reliable transmission of cross-clock domain data, meeting the needs of scenarios with extremely high requirements for latency and reliability, such as data transmission.

[0005] One embodiment of this application provides a method for cross-clock domain data transfer, including the following steps: Obtain the data to be transmitted; Based on the data to be transmitted, the phase adjustment function of the PLL output in the FPGA is used to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, in order to determine the target clock phase for the data transmission of the analog-to-digital converter; wherein, the target clock phase enables the data to be transmitted to be correctly sampled by the system clock domain of the FPGA.

[0006] Optionally, the data to be transmitted includes: The oscillation waveform of the superconducting quantum bit, and the starting point of the data to be transmitted is the data clock domain sent by the analog-to-digital converter, and the ending point is the system clock domain of the FPGA.

[0007] Optionally, the step of utilizing the PLL output phase adjustment function in the FPGA to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the analog-to-digital converter (ADC) data transmission clock phase, to determine the target clock phase for ADC data transmission, includes: By utilizing the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA, the phase is adjusted with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter.

[0008] Optionally, the step of utilizing the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA to adjust the phase with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, includes: Configure the PLL to increase the RESET transmit clock phase by 1 / 56ns. The RESET transmit clock is generated by the PLL inside the FPGA and is used to determine the phase of the RESET signal. The analog-to-digital converter determines the phase of the transmit data clock based on the phase of the RESET signal. Output a RESET pulse in response to a flag bit that iterates through all RESET transmit clock phases and records whether the phase of the variable phase clock is compatible, wherein the flag bit is readable; Based on the flag indicating whether the phase of the recorded variable-phase clock is compatible, the target clock phase is filtered, and the PLL is adjusted to the target clock phase.

[0009] Optionally, the step of using the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA to adjust the phase with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, further includes: If not all RESET transmit clock phases are traversed, return to the step of configuring the PLL to increase the RESET transmit clock phase by 1 / 56ns.

[0010] One embodiment of this application provides a circuit system for cross-clock domain data transfer, the system comprising: The communication connection consists of a variable phase clock generation circuit, a RESET generation circuit, a BUFR reset circuit, and a phase detection circuit. The variable phase clock generation circuit is used to generate clock signals, which include a fixed-phase system clock and a RESET transmit clock. The RESET generation circuit is used to generate a RESET signal of a specific phase; The BUFR reset circuit is used to divide the transmitted data originating from the analog-to-digital converter by two to obtain a variable phase clock. The phase detection circuit is used to detect the phase of the clock signal; wherein the clock signal includes the fixed-phase system clock and the variable-phase clock.

[0011] Optionally, the inputs of the variable phase clock generation circuit include a crystal oscillator clock and the phase configuration of the CPU bus for the RESET transmit clock; the outputs of the variable phase clock generation circuit include a fixed phase clock and a variable phase RESET transmit clock; the fixed phase clock and the variable phase RESET transmit clock have the same frequency.

[0012] Optionally, the inputs of the RESET generation circuit include a RESET signal and a RESET transmit clock from the PLL, wherein the phase of the RESET transmit clock is variable and the phase of the RESET signal is determined by the RESET transmit clock.

[0013] Optionally, the inputs of the BUFR reset circuit include the data transmission clock of the digital-to-analog converter and the reset signal of the CPU bus; the output of the BUFR reset circuit includes a clock signal with a frequency that is two times the frequency of the data transmission clock of the digital-to-analog converter.

[0014] Optionally, the inputs of the phase detection circuit include a fixed-phase system clock, a variable-phase clock, and control signals from the CPU bus; the output of the phase detection circuit includes a flag indicating whether the phases of the fixed-phase system clock and the variable-phase clock are compatible.

[0015] Compared with existing technologies, this invention first obtains the data to be transmitted; then, based on the data to be transmitted, it utilizes the PLL output phase adjustment function in the FPGA to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the analog-to-digital converter (ADC) data transmission clock phase to determine the target clock phase for the ADC data transmission. This target clock phase ensures that the data to be transmitted can be correctly sampled by the FPGA's system clock domain. This achieves low-latency, stable, and reliable data transmission across clock domains, meeting the needs of scenarios with extremely high latency and reliability requirements, such as data transmission. Attached Figure Description

[0016] Figure 1 A flowchart illustrating a cross-clock domain data transmission method provided in an embodiment of the present invention; Figure 2 A schematic diagram of an FPGA system architecture is provided for an embodiment of the present invention; Figure 3 A schematic diagram of phase change provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a PLL configuration timing provided in an embodiment of the present invention; Figure 5 A schematic diagram of a circuit system for cross-clock domain data transmission provided in an embodiment of the present invention; Figure 6 A schematic diagram of a circuit system structure for cross-clock domain data transfer using MXT2004 is provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a phase detection circuit system provided in an embodiment of the present invention. Detailed Implementation

[0017] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] The purpose of this invention is to provide a method for cross-clock domain data transmission to solve the problems mentioned in the background section. To achieve the above objective, this invention provides the following technical solution. See [link to relevant documentation]. Figure 1 , Figure 1 A flowchart illustrating a cross-clock domain data transfer method provided in an embodiment of the present invention includes the following steps: S101: Obtain the data to be transmitted.

[0019] Specifically, the data to be transmitted may include the oscillation waveform of a superconducting quantum bit, and the transmission starting point of the data to be transmitted is the data transmission clock domain of the analog-to-digital converter (ADC, such as the MXT2004), and the ending point is the system clock domain of the FPGA.

[0020] For example, see Figure 2 , Figure 2 This is a schematic diagram of an FPGA system architecture provided in an embodiment of the present invention. Taking the MXT2004 analog-to-digital converter as an example, it includes a PLL (Phase Locked Loop), an arithmetic module, a serial conversion module, and a clock divider module. In the prior art, the arithmetic module uses a 125MHz clock generated by the FPGA's internal PLL to acquire data sent from the serial-to-parallel conversion module. However, this data is sent by a 125MHz clock generated by the BUFR. Although these two clocks have the same frequency (because they originate from the same crystal oscillator), their phases are unknown. The common practice for transmitting large amounts of data between two unknown phase clock domains is to use an asynchronous FIFO. However, an asynchronous FIFO introduces a delay of several cycles (here, one cycle is 8ns), so other methods with smaller delays are needed.

[0021] The MXT2004 has an input signal RESET, whose falling edge occurs after a fixed time (a fixed number of 1GHz clock cycles) before the accompanying clock begins to toggle from high to low. In other words, by adjusting the timing of RESET transmission, the phase of the accompanying clock DCLK can be adjusted with 1ns precision. The final result is a 125MHz clock output from BUFR, with eight phase variations. See [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of phase change provided in an embodiment of the present invention.

[0022] S102: Based on the data to be transmitted, the phase adjustment function of the PLL output in the FPGA is used to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, so as to determine the target clock phase for the data transmission of the analog-to-digital converter; wherein, the target clock phase enables the data to be transmitted to be correctly sampled by the system clock domain of the FPGA.

[0023] Specifically, by utilizing the PLL output phase adjustment function in the FPGA, the phase of the RESET transmit clock is finely adjusted to achieve fine-grained control over the RESET pulse phase and the analog-to-digital converter (ADC) data transmission clock phase, thereby determining the target clock phase for ADC data transmission. This can include: By utilizing the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA, the phase is adjusted with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter.

[0024] Specifically, by utilizing the RESET signal of the analog-to-digital converter (ADC) and the phase adjustment function of the PLL in the FPGA, the phase is adjusted with an accuracy of 1 / 56ns to achieve fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the ADC. This can include: Step 1: Configure the PLL to increase the RESET transmit clock phase by 1 / 56ns. The RESET transmit clock is generated by the PLL inside the FPGA and is used to determine the phase of the RESET signal. The analog-to-digital converter determines the phase of the transmit data clock based on the phase of the RESET signal.

[0025] The configuration involves configuring a PLL to increase the RESET transmit clock phase by 1 / 56ns. This RESET transmit clock is generated by the FPGA's internal PLL and determines the phase of the RESET signal. The analog-to-digital converter (ADC) then determines the phase of the transmit data clock based on the RESET signal's phase. During configuration, if the clock frequency is 125MHz (8ns period), the adjustment precision is 1 / 448 of a cycle. This phase adjustment has a dedicated interface and can be controlled by the APB (Advanced Peripheral Bus). PSCLK is a dedicated clock (connected to the APB clock). When PSEN is high, one granularity is adjusted. The adjustment direction is indicated by PSINCDEC, and PSEN cannot be continuously high, as each adjustment requires a certain amount of time. For a 125MHz clock and a VCO (Voltage-Controlled Oscillator) frequency of 1GHz, increasing the granularity by 448 cycles returns the phase to its initial state; further increases result in a cyclical process.

[0026] It should be noted that during PLL configuration, a specific clock can be set to allow precise phase adjustment during FPGA operation, with a granularity of 1 / 56 of the VCO cycle (i.e., 1 / 56 ns). If the clock frequency is 125MHz, or 8ns, then the adjustment precision is 1 / 448 of a cycle. This phase adjustment has its own dedicated interface and can be easily controlled by the APB. See [link / reference] Figure 4 , Figure 4 This is a timing diagram illustrating a PLL configuration according to an embodiment of the present invention. PSCLK is a dedicated clock for this phase adjustment interface; if software adjustment is intended, it can be connected to the APB clock. When PSEN is high, one granularity is adjusted. During adjustment, PSINCDEC indicates whether to increase or decrease the granularity by one unit. Since each adjustment requires a certain amount of time, PSEN cannot be continuously high. For a 125MHz clock and a VCO frequency of 1GHz, increasing the granularity by 448 units will return to the initial phase. This process continues. If the clock of the register that issues the RESET signal from MXT2004 is a dedicated 125MHz clock, then adjusting the phase of this clock with an accuracy of 1 / 56ns will definitely allow control of the accompanying clock DCLK with an accuracy of 1ns. The 125MHz system clock cannot be adjusted; otherwise, adjusting all clocks simultaneously would be ineffective.

[0027] The 125MHz clock of the serial-to-parallel converter, which is the 16-sample parallel data transmit clock, is derived by dividing the input accompanying clock DCLK by two from the BUFR. To ensure a definite phase relationship between this 125MHz clock and DCLK, the BUFR has a reset function. First, the RESET function of the MXT2004 is used to set DCLK to a constant high, then the BUFR is reset (that is, the frequency divider counter inside the BUFR is reset), and then RESET is set low. DCLK begins to toggle, and the BUFR can then output a definite divided clock at a definite time. If there are multiple BUFRs, after going through the above three steps of stopping DCLK, resetting the BUFR, and starting DCLK, the outputs of these BUFRs will necessarily be consistent.

[0028] 2: Output RESET pulse, responding to a flag bit that iterates through all RESET transmit clock phases and records whether the phase of the variable phase clock is compatible, wherein the flag bit is readable.

[0029] Specifically, a RESET pulse is output, responding to a flag bit that iterates through all RESET transmit clock phases and records whether the phase of the variable-phase clock is compatible. This flag bit is readable. The analog-to-digital converter can sample the RESET pulse using a 1GHz clock. It has internal circuitry to eliminate metastability, and even if the setup and hold times are not met, it will only start to toggle the transmit data clock (DCLK) one cycle earlier or later (1ns).

[0030] Step 3: Based on the flag indicating whether the phase of the recorded variable phase clock is compatible, filter the target clock phase and adjust the PLL to the target clock phase.

[0031] In an optional implementation, the step of using the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA to adjust the phase with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, may further include: If not all phases of the RESET transmit clock are traversed, return to the step of configuring the PLL to increase the RESET transmit clock phase by 1 / 56ns, until all phases are traversed.

[0032] It should be noted that only when the PLL output phase, that is, the phase of the RESET transmit clock, is finely adjustable can the phase of the RESET pulse be finely adjusted, thus enabling the phase of the MXT2004 transmit data clock to be finely adjusted. Only then can the most suitable phase of the MXT2004 transmit data clock be found, ensuring the maximum setup and hold time margin and guaranteeing stable and reliable data transmission between the two clock domains.

[0033] As can be seen, this invention first obtains the data to be transmitted; then, based on the data to be transmitted, it utilizes the PLL output phase adjustment function in the FPGA to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the analog-to-digital converter (ADC) data transmission clock phase, to determine the target clock phase for the ADC data transmission; wherein, the target clock phase ensures that the data to be transmitted can be correctly sampled by the FPGA's system clock domain. This achieves low-latency, stable, and reliable data transmission across clock domains, meeting the requirements of scenarios with extremely high latency and reliability requirements, such as superconducting quantum bit oscillating waveform data transmission.

[0034] See Figure 5 In another specific embodiment of the present invention, a circuit system 500 for cross-clock domain data transfer is also provided, the system comprising: The communication connection comprises a variable-phase clock generation circuit 501, a RESET generation circuit 502, a BUFR reset circuit 503, and a phase detection circuit 504. The variable-phase clock generation circuit 501 generates a clock signal, which includes a fixed-phase system clock and a RESET transmit clock. The RESET generation circuit 502 generates a RESET signal with a specific phase. The BUFR reset circuit 503 divides the transmitted data originating from the analog-to-digital converter by two to obtain a variable-phase clock. The phase detection circuit 504 detects the phase of the clock signal. The clock signal includes the fixed-phase system clock and the variable-phase clock.

[0035] The variable phase clock generation circuit 501 has the following inputs: a crystal oscillator clock and a phase configuration of the CPU bus for the RESET transmit clock; the output of the variable phase clock generation circuit includes a fixed phase clock and a variable phase RESET transmit clock; the fixed phase clock and the variable phase RESET transmit clock have the same frequency.

[0036] The inputs to the RESET generation circuit 502 include a RESET signal and a RESET transmit clock from the PLL. The phase of the RESET transmit clock is variable, and the phase of the RESET signal is determined by the RESET transmit clock.

[0037] The inputs of the BUFR reset circuit 503 include the data transmission clock of the digital-to-analog converter and the reset signal of the CPU bus; the output of the BUFR reset circuit includes a clock signal with a frequency that is half the data transmission clock of the digital-to-analog converter.

[0038] The inputs of the phase detection circuit 504 include a fixed-phase system clock, a variable-phase clock, and control signals from the CPU bus; the outputs of the phase detection circuit include a flag indicating whether the phases of the fixed-phase system clock and the variable-phase clock are compatible.

[0039] For example, see Figure 6 , Figure 6 This is a schematic diagram of a circuit system structure for cross-clock domain data transfer using MXT2004, provided as an embodiment of the present invention. Specifically, it consists of a variable phase clock generation circuit, an MXT2004 RESET generation circuit, a BUFR reset circuit, and a phase detection circuit. The phase detection circuit is used to test whether the phases of the two clocks are appropriate. If there is a way to have the ADC send a test sequence, the phase appropriateness can also be determined using the test sequence.

[0040] The hardware implementation scheme includes APB CFGs (CPU bus), BUFR (DIV2) (the starting point of the FPGA's internal regional clock tree with a divide-by-two function), a RESET generation circuit, a variable phase clock generation circuit, and a phase detection circuit. Each module has clearly defined functions, inputs, and outputs, and they work together to achieve data transfer operations.

[0041] The hardware of this solution consists of a variable phase clock generation circuit, an analog-to-digital converter RESET generation circuit, a BUFR reset circuit, and a phase detection circuit. The specific details of each part are as follows: APB CFGs (CPU Bus): Used to issue commands (such as triggering the RESET generation circuit to generate a RESET signal, configuring the phase of the RESET transmit clock, sending control signals for phase detection, etc.) and transmit control signals and status signals (such as whether the phase output by the phase detection circuit is appropriate).

[0042] The BUFR (DIV2) (the starting point of the FPGA's internal regional clock tree, with a divide-by-2 function) divides the transmit data clock originating from the analog-to-digital converter (ADC) by two. Its inputs are the ADC's transmit data clock and a reset signal from the CPU bus; its output is a clock with a frequency half that of the ADC's transmit data clock. To ensure a defined phase relationship between the serial-to-parallel converter's 125MHz clock (the 16-sample parallel data transmit clock, derived from the BUFR's divide-by-two operation of the input clock DCLK) and DCLK, the BUFR's reset function is used. The operation steps are as follows: first, use the ADC's RESET function to set DCLK high; then, reset the BUFR (reset the BUFR's internal divider counter); then, set RESET low. DCLK begins to toggle, and the BUFR outputs a defined divided clock at a defined time. If there are multiple BUFRs, after sequentially performing the stop-DCLK, reset-BUFR, and start-DCLK operations, the outputs of these BUFRs will be consistent.

[0043] The RESET generation circuit functions to generate a RESET signal with a specific phase. Its inputs are a command from the CPU bus to trigger RESET signal generation and a variable-phase RESET transmit clock from the PLL (the phase of the RESET signal is determined by this clock). The output is a RESET signal with a specific phase. Since the configuration clock is the APB clock and the output clock is a variable-phase 125MHz clock, two registers are configured to remove metastability. While removing metastability might cause the output to be 8ns earlier or later, it does not affect the final effect of adjusting the phase within an 8ns time range.

[0044] The function of the variable phase clock generation circuit is to generate two clocks: a fixed-phase system clock and a RESET transmit clock with the same frequency but variable phase; the input is a crystal oscillator clock (the most basic requirement of a PLL). Figure 6 (Not shown) and the CPU bus for phase configuration of the RESET transmit clock; the output is a fixed-phase clock and a variable-phase RESET transmit clock.

[0045] The phase detection circuit checks if the phases of two clocks are appropriate. Specifically, the two clocks are the fixed-phase system clock from the variable-phase clock generation circuit and the variable-phase clock originating from the MXT2004, divided by the start point of the FPGA's internal regional clock tree (with a divide-by-two function). The inputs are the two clocks and control signals from the CPU bus, such as initiating a new detection. The output is the phase appropriateness result, sent to the CPU bus. The FPGA's internal regional clock tree start point (with a divide-by-two function) divides the transmit data clock originating from the MXT2004 by two. The inputs are the transmit data clock from the MXT2004 and a reset signal from the CPU bus. The output is a clock with a frequency half that of the MXT2004's transmit data clock.

[0046] See Figure 7 , Figure 7 This is a schematic diagram of a phase detection circuit system structure provided in an embodiment of the present invention. The BUFR clock domain generates a known pattern, and the system clock domain detects whether the received data matches expectations. The simplest pattern is to continuously increment by 1. A delay is intentionally added to bit 1 of the counter output, so the delays of bit 0 and bit 1 are inconsistent. If the rising edges of two clocks are close together, a new bit 0 and an old bit 1 will be sampled, resulting in an increment that is not always consistent. The delay unit can be implemented using LUT1; if one LUT1 is insufficient, multiple LUT1s can be cascaded.

[0047] Compared with the prior art, the present invention has the following beneficial effects: Low-latency data transmission: It abandons the use of traditional asynchronous FIFO and achieves cross-clock domain data transmission by fine-grained adjustment of clock phase, avoiding the multi-clock cycle delay introduced by asynchronous FIFO, and meeting the needs of scenarios with extremely high latency requirements such as superconducting quantum bit oscillation waveform data transmission.

[0048] High reliability: By utilizing the phase adjustment function of the PLL in the FPGA, the RESET transmit clock phase is adjusted with a high precision of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter. This allows the target clock phase to be found so that the data to be transmitted is correctly sampled by the FPGA system clock domain, ensuring that the setup and hold time margins of data sampling are maximized, and ensuring that the data is transmitted stably and reliably between the two clock domains.

[0049] Highly adaptable: Each module of the circuit system has a clear function and works collaboratively. Moreover, relevant parameters can be flexibly adjusted according to the actual FPGA process and application scenario (such as the number of LUT1 cascades to achieve appropriate delay). It is suitable for a variety of scenarios that require cross-clock domain data transmission, and has broad application prospects, especially in radar, communication, industrial measurement and control and other fields.

[0050] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0051] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0052] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0053] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0054] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0055] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0056] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for data transmission across clock domains, characterized in that, Includes the following steps: Obtain the data to be transmitted; Based on the data to be transmitted, the phase adjustment function of the PLL output in the FPGA is used to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, in order to determine the target clock phase for the data transmission of the analog-to-digital converter; wherein, the target clock phase enables the data to be transmitted to be correctly sampled by the system clock domain of the FPGA.

2. The transmission method according to claim 1, characterized in that, The data to be transmitted includes: The oscillation waveform of the superconducting quantum bit, and the starting point of the data to be transmitted is the data clock domain sent by the analog-to-digital converter, and the ending point is the system clock domain of the FPGA.

3. The transmission method according to claim 2, characterized in that, The method utilizes the PLL output phase adjustment function in the FPGA to finely adjust the phase of the RESET transmit clock, thereby achieving fine-grained adjustment of the RESET pulse phase and the analog-to-digital converter (ADC) data transmission clock phase to determine the target clock phase for ADC data transmission. This includes: By utilizing the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA, the phase is adjusted with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter.

4. The transmission method according to claim 3, characterized in that, The method utilizes the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA to adjust the phase with an accuracy of 1 / 56ns, achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, including: Configure the PLL to increase the RESET transmit clock phase by 1 / 56ns. The RESET transmit clock is generated by the PLL inside the FPGA and is used to determine the phase of the RESET signal. The analog-to-digital converter determines the phase of the transmit data clock based on the phase of the RESET signal. Output a RESET pulse in response to a flag bit that iterates through all RESET transmit clock phases and records whether the phase of the variable phase clock is compatible, wherein the flag bit is readable; Based on the flag indicating whether the phase of the recorded variable-phase clock is compatible, the target clock phase is filtered, and the PLL is adjusted to the target clock phase.

5. The transmission method according to claim 4, characterized in that, The method of utilizing the RESET signal of the analog-to-digital converter and the phase adjustment function of the PLL in the FPGA to adjust the phase with an accuracy of 1 / 56ns, thereby achieving fine-grained adjustment of the RESET pulse phase and the data transmission clock phase of the analog-to-digital converter, also includes: If not all RESET transmit clock phases are traversed, return to the step of configuring the PLL to increase the RESET transmit clock phase by 1 / 56ns.

6. A circuit system for cross-clock domain data transfer, characterized in that, The system includes: The communication connection consists of a variable phase clock generation circuit, a RESET generation circuit, a BUFR reset circuit, and a phase detection circuit. The variable phase clock generation circuit is used to generate clock signals, which include a fixed-phase system clock and a RESET transmit clock. The RESET generation circuit is used to generate a RESET signal of a specific phase; The BUFR reset circuit is used to divide the transmitted data originating from the analog-to-digital converter by two to obtain a variable phase clock. The phase detection circuit is used to detect the phase of the clock signal; wherein the clock signal includes the fixed-phase system clock and the variable-phase clock.

7. The circuit system according to claim 6, characterized in that, The inputs of the variable phase clock generation circuit include a crystal oscillator clock and the phase configuration of the CPU bus for the RESET transmit clock; the outputs of the variable phase clock generation circuit include a fixed phase clock and a variable phase RESET transmit clock; the fixed phase clock and the variable phase RESET transmit clock have the same frequency.

8. The circuit system according to claim 6, characterized in that, The inputs to the RESET generation circuit include a RESET signal and a RESET transmit clock from the PLL. The phase of the RESET transmit clock is variable, and the phase of the RESET signal is determined by the RESET transmit clock.

9. The circuit system according to claim 6, characterized in that, The inputs of the BUFR reset circuit include the data transmission clock of the digital-to-analog converter and the reset signal of the CPU bus; the output of the BUFR reset circuit includes a clock signal with a frequency that is half the data transmission clock of the digital-to-analog converter.

10. The circuit system according to claim 6, characterized in that, The inputs of the phase detection circuit include a fixed-phase system clock, a variable-phase clock, and control signals from the CPU bus; the outputs of the phase detection circuit include a flag indicating whether the phases of the fixed-phase system clock and the variable-phase clock are compatible.

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