Instruction scheduling optimization method for RISC-V variable length vector instruction hardware characteristics

Abstract

The invention discloses an instruction scheduling optimization method aiming at RISC-V variable length vector instruction hardware characteristics. The method comprises the following steps: S1, obtaining a target vector instruction to be scheduled; s2, dynamically determining vector configuration information associated with the target vector instruction; s3, based on the vector configuration information, establishing a dynamic delay calculation model, and dynamically calculating an execution delay estimated value of the target vector instruction; and S4, providing the execution delay estimation value to an instruction scheduler, and performing scheduling optimization on the instruction sequence containing the target vector instruction by the instruction scheduler based on the execution delay estimation value. According to the instruction scheduling optimization method, a dynamic delay modeling and delay information dynamic injection mechanism is introduced, so that a compiler scheduler can sense and adapt to dynamic configuration parameters of the RISC-V variable-length vector instruction, and an accurate instruction delay estimated value is generated in real time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of compiler, and particularly relates to an instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics. BACKGROUND

[0002] RISC-V variable-length vector instruction: RISC-V vector extension (RVV) realizes flexible processing of different scales of data through a "dynamic configuration mechanism" (through a vsetvli instruction). The variable configuration items include: 1) variable vector length (VLEN): supports 128 bit to 1024 bit register width adjustment range, which relates to the number of processable elements of a single vector instruction, and the calculation formula is: ; Wherein, AVL is the total number of elements to be processed; SEW is the element bit width.

[0003] 2) element bit width (SEW): supports 8 / 16 / 32 / 64 bit free configuration to adapt to different data types.

[0004] 3) LMUL (register group size): how many adjacent physical registers are bound into a logical register (for example, when LMUL=8, 8 vector registers are combined into a logical register), which can improve the data throughput of a single vector instruction. For example, LMUL=8 can make the element range processed by a single instruction expand by 8 times, and the number of instructions is greatly reduced.

[0005] 4) mask-driven conditional execution: each vector element corresponds to a 1-bit mask (for example, 1024-bit VLEN needs 128-bit mask storage), which facilitates the efficient and flexible processing of sparse data by vector instructions, and adapts to more complex computing scenarios.

[0006] Actual hardware performance of variable-length vector instruction: The dynamically configurable characteristics of the RISC-V variable-length vector instruction implemented on hardware will cause the execution delay of the vector instruction to change with the changes of the configuration items (such as vsetvli dynamically setting SEW (element bit width), LMUL (register grouping), and VL (vector length)), and the core mechanism of the delay dynamic change includes: 1) data scale multiplication: increasing LMUL will cause the amount of data processed by a single vector instruction to increase exponentially (for example, when LMUL=4, the amount of data processed is 4 times that of LMUL=1). The hardware execution unit (such as ALU) needs more clock cycles to complete the operation of all elements.

[0007] 2) Element number and parallelism: With fixed VLEN (vector register length), smaller SEW means single register can hold more elements (e.g. VLEN=128, SEW=8 can hold 16 elements, SEW=64 only 2). Hardware needs more cycles to process extra elements, especially when execution unit parallelism is not enough.

[0008] 3) Mask and tail processing overhead: SEW affects processing logic of mask (v0) and tail elements (vta control). Smaller SEW needs to process more mask bits and element selection operations, increasing the number of cycles to merge results.

[0009] 4) Execution unit resource limitation: Narrow bit-width elements (e.g. SEW=8) may use low-throughput execution units (e.g. 8-bit multiplier), while wide bit-width (e.g. SEW=64) may invoke high-latency specialized units (e.g. 64-bit multiplier), directly increasing single-instruction latency.

[0010] However, due to the heterogeneity of micro-architecture design and the diversity of resource constraints, the impact of RVV configuration parameters (e.g. SEW, LMUL, VL) on instruction latency varies significantly in different hardware implementations. For example, the vector instruction latency of SpacemlT's X60 processor is mainly related to LMUL and SEW, and is less affected by VL.

[0011] Compiler support for RISCV variable-length vector instructions: RISC-V variable-length vector instructions require compiler support in both functional implementation and performance optimization.

[0012] 1) Functional implementation: Loop analysis: Identify vectorizable loops (e.g. fixed iteration count, no data dependency); Compiler back-end needs to model dynamic vector length, such as the common LLVM compiler introduces <vscale x N x T> IR data type to represent scalable vectors; Width calculation: Determine the number of elements processed per iteration according to VLMAX=LMUL*VLEN / SEW; Implement dynamic insertion of vsetvli instruction: Compiler back-end automatically inserts vsetvli instruction according to data type and loop structure, dynamically configuring SEW (element bit width), LMUL (register grouping) and VL (actual number of elements processed).

[0013] 2) Performance optimization: a, Cost Model: Cost Model: Perform vectorization cost and benefit analysis, such as: calculate the total overhead of scalar version: scalar iteration number x single iteration period; calculate the total overhead of vector version: vector iteration number x (vector instruction overhead + vsetvli overhead) + tail processing overhead; if the scalar cost is greater than the vector cost, the Cost Model considers that vectorization has positive benefits, otherwise it considers that the cost is too large to vectorize.

[0014] b. Redundancy check: Reduce redundant configuration instructions through static analysis (such as merging adjacent identical configuration vsetvli), reduce overhead.

[0015] c. Tail processing optimization: According to the number of VL blocks and the tail loop overhead, select the fixed vector length mode (VLS) or the vector length independent mode (VLA), where: VLS mode: Additional scalar loop processing is required for the tail, suitable for hardware VLEN fixed scenarios; VLA mode: Use VP IR to generate Predicated instructions with masks (such as vadd.vv combined with v0 mask), eliminate tail loops, and improve cross-hardware compatibility.

[0016] d. Scheduling optimization: Common compilers such as LLVM have limited support for RISCV vector instruction scheduling optimization, mainly for backend scheduling model customization. Custom scheduling models can be added for different RISC-V hardware (such as SpacemiT-X60) to accurately describe pipeline characteristics (such as port number, unit delay). If the scheduling model is missing, it will cause the scheduler to be more conservative and the performance will decrease.

[0017] Instruction scheduling principle: Instruction scheduling is a technique of compiler optimization, the purpose is to make the program run efficiently on the central processing unit with instruction pipeline through parallelism at the instruction level. We usually divide it into static scheduling and dynamic scheduling according to the stage of scheduling.

[0018] However, whether it is static scheduling or dynamic scheduling, it is through the reordering of the execution order of instructions to: 1) Reduce the bubble (empty bubble) of instruction flow; 2) Increase IPC (Instruction Per Cycle, an important indicator of processor performance); 3) Relieve register pressure (if the scheduler handles it well, to some extent, it can reduce the life cycle of registers and relieve register pressure).

[0019] If two instructions with dependency are adjacent, for example, instruction a is adjacent to instruction b, instruction a is in front of instruction b, and instruction b depends on instruction a, and the latency of instruction a is greater than 1, then instruction b needs to wait for the latency of instruction a to execute, thus a bubble is generated between the two instructions, as shown in the pipeline of Figure 1 and Figure 2 When the adjacent instructions have no dependency, the instruction pipeline is full, and there is no bubble; if instruction b depends on instruction a, then a bubble is generated between instructions a and b.

[0020] For a specific RISCV CPU, the compiler can obtain the information of the number of ports and unit delay (latency) that each vector instruction depends on, so on the basis of ensuring the function unchanged, the compiler has the opportunity to eliminate bubbles as much as possible through scheduling.

[0021] As we assume in the above example that instruction c has no dependency with instruction a and instruction b, and the execution order of instruction c and instruction b is exchanged without changing the overall function, then instruction c can be moved to the position where the bubble occurs to fill the bubble as much as possible. If the total latency value of the filled instruction c is greater than or equal to the latency of instruction a, then the bubble can be completely eliminated, as shown in Figure 3 .

[0022] The existing compiler (such as LLVM) in the prior art schedules vector instructions based on fixed delay estimation, but the actual delay of RISC-V vector instructions will change in real time with dynamic configuration (such as SEW, LMUL). The static scheduling model cannot perceive such changes, resulting in the following problems: Scheduling distortion: the fixed delay estimation does not match the actual hardware execution period; Performance loss: pipeline bubbles are triggered, which offset the performance benefits brought by vectorization.

[0023] The existing scheduler relies on a static delay model and cannot respond to the dynamic configuration characteristics (such as the SEW bit width and the LMUL register group size set by the vsetvli / vsetvl instruction) of RISC-V vector instructions, resulting in a mismatch between the scheduling decision and the actual hardware behavior, and triggering pipeline bubbles. SUMMARY

[0024] The purpose of this invention is to provide a technical solution for an instruction scheduling optimization method for the hardware characteristics of RISC-V variable-length vector instructions, addressing the shortcomings of existing technologies. This instruction scheduling optimization method introduces a dynamic latency modeling and latency information dynamic injection mechanism, enabling the compiler scheduler to perceive and adapt to the dynamic configuration parameters of RISC-V variable-length vector instructions, and generate accurate instruction latency estimates in real time.

[0025] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: An instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics, characterized by the following steps: S1. Obtain the target vector instruction to be scheduled; S2. Dynamically determine the vector configuration information associated with the target vector command; S3. Based on vector configuration information, establish a dynamic latency calculation model to dynamically calculate the estimated execution latency of the target vector instruction; S4. The execution latency estimate is provided to the instruction scheduler, which then optimizes the scheduling of instruction sequences containing target vector instructions based on the execution latency estimate.

[0026] This instruction scheduling optimization method introduces a dynamic latency modeling and latency information dynamic injection mechanism, enabling the compiler scheduler to perceive and adapt to the dynamic configuration parameters of RISC-V variable-length vector instructions, and generate accurate instruction latency estimates in real time.

[0027] Furthermore, the vector configuration information in step S2 includes element bit width SEW and register block multiplier LMUL.

[0028] Furthermore, the dynamic determination of vector matching information associated with the target vector instruction in step S2 specifically includes the following steps: S2.1 In the basic block where the target vector instruction is located, a reverse traversal search is performed. The search starts from the instruction before the target instruction and scans forward one instruction at a time along the instruction sequence until the first valid vsetvli or vsetvli instruction is encountered. S2.2 If the vsetivli or vsetivli instruction is found within the basic block, the vector configuration information is extracted from that instruction.

[0029] Furthermore, if no valid `vsetvli` or `vsetivli` instruction is found within a basic block, a cross-basic block search is triggered, which includes the following steps: S2.3 Identify all predecessor basic blocks in the control flow graph of the basic blocks; S2.4 Extract the valid vtype state from the exit position of the predecessor basic block; S2.5 extract the vtype state as the vector configuration information of the target vector instruction.

[0030] Further, the extracting the valid vtype state from the exit position of the predecessor basic block in step S2.4 specifically comprises the following steps: S2.4.1 obtaining predecessor basic blocks: for the current basic block MBB_curr, obtaining all the predecessor basic block set Preds = Preds(MBB_curr) in the control flow graph; S2.4.2 checking the exit state of the predecessor basic block; S2.4.3 merging and analyzing the vector configuration information of the predecessor basic block.

[0031] Further, the checking the exit state of the predecessor basic block in step S2.4.2 specifically comprises the following steps: for each predecessor basic block Pred ∈ Preds: S2.4.2.1 if the last instruction of the predecessor basic block is a vsetvli or vsetivli instruction, directly reading the vtype state set by the instruction; S2.4.2.2 if the last instruction of the predecessor basic block is not a vsetvli or vsetivli instruction, performing a backward traversal search in the predecessor basic block, starting from the last instruction of the predecessor basic block and searching forward until the nearest vsetvli or vsetivli instruction is found, and reading the vtype state thereof; S2.4.2.3 if no vector configuration instruction is found in the predecessor basic block, performing the cross-block configuration inheritance process recursively for the predecessor basic block Pred until an effective configuration is found or the program entry is reached.

[0032] Further, the merging and analyzing the vector configuration information of the predecessor basic block in step S2.4.3 specifically comprises the following steps: S2.4.3.1 if the vtype states of all predecessor basic block exits are consistent, taking the uniform configuration as the inheritance configuration of the target vector instruction of the current predecessor basic block; S2.4.3.2 if the vtype states of the predecessor basic block exits are inconsistent, processing according to specific contexts.

[0033] Further, in step S3, the dynamic delay calculation model is established, and the dynamic delay calculation formula is used when dynamically calculating the execution delay estimate value of the target vector instruction: ; wherein Base is the base period, i.e. the number of basic clock cycles required to execute the vector instruction under the reference configuration, LMUL scaleTo set the scaling factor related to the current vector length multiplier LMUL, SEW actual / SEW base For the effective bit width ratio, that is, the effective element bit width SEW currently actually configured actual Relative to the reference bit width SEW base Change.

[0034] Further, the instruction scheduler in step S4 schedules and optimizes the instruction sequence containing the target vector instruction based on the execution delay estimation, specifically comprising: S4.1 The instruction scheduler processes the instruction node sequence in a basic block; S4.2 A highest priority node is selected from the ready sequence for scheduling through the pickNode() algorithm; S4.3 Determine whether the currently selected node corresponds to the target vector instruction; S4.4 If the current node is the target vector instruction, enter the dynamic injection stage; S4.5 Update the node state according to the delay information; S4.6 Loop steps S4.1-S4.5 until all instruction nodes in the basic block are scheduled.

[0035] Further, the entering dynamic injection stage in step S4.4 specifically comprises the following steps: S4.4.1 Determine the vtype state on which the target vector instruction depends through the pickNode() algorithm; S4.4.2 According to the obtained vtype state, calculate the real execution delay of the target vector instruction under the current configuration using the dynamic delay calculation formula; S4.4.3 Update the calculated dynamic delay estimation to the SUnit scheduling unit information corresponding to the node through a callback function, and overwrite the original preset static delay estimation and / or priority in the node.

[0036] The present application has the following beneficial effects due to the adoption of the above technical solutions: 1. The instruction scheduling optimization method of the present application introduces dynamic delay modeling and delay information dynamic injection mechanism, so that the compiler scheduler can perceive and adapt to the dynamic configuration parameters of the RISC-V variable length vector instruction, and generate accurate instruction delay estimation in real time.

[0037] 2. Precise modeling of dynamic delays, eliminating performance loss: Traditional schedulers use fixed delay values, without considering the impact of LMUL and SEW dynamic configurations on actual delays (e.g. when LMUL=8, register port contention causes the delay to increase to 6 cycles). This solution calculates the delay value in real time by dynamically associating the vsetvli configuration, avoiding pipeline bubbles caused by underestimating the delay.

[0038] 3. Unified configuration propagation mechanism: Search vsetvli across basic blocks (e.g. configuration inheritance within loops, predecessor block configuration merging), ensuring the consistency of the context for dynamic delay calculation, and avoiding performance discontinuities caused by missing configurations.

[0039] 4. Support for RVV advanced optimization strategies: Provide an extended TargetTransformInfo (TTI) interface for the construction process of VPlan, i.e. delay query functions based on different configuration information. This interface automatically associates vector instructions with their configuration information, and returns SEW / LMUL-sensitive delay values in real time, providing more detailed information for cost model calculations.

[0040] 5. Seamless integration with existing toolchain: Modify ScheduleDAGRRList::pickNode to dynamically override static delay values, without the need to restructure the entire compilation framework, and maintain compatibility with the standard RVV 1.0 specification.

[0041] 6. Flexible support for heterogeneous hardware: Adapt to the microarchitecture differences of different RISC-V chips, and achieve cross-platform optimization through parameterized delay formulas (e.g. Latency=Base×LMUL_scale×SEW_factor). BRIEF DESCRIPTION OF DRAWINGS

[0042] The present invention will be further described below in conjunction with the accompanying drawings: Figure 1 Schematic diagram of the prior art when there are no bubbles in the pipeline for four instructions without true dependence; Figure 2 Schematic diagram of the prior art when bubbles are generated between the second and third instructions when the third instruction is true dependent on the second instruction; Figure 3 Schematic diagram of the prior art when the compiler eliminates a bubble by scheduling; Figure 4 Flowchart of the instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics according to the present invention; Figure 5 Schematic diagram of the present invention, which traverses all predecessor basic blocks of the current basic block and extracts the vtype state of the last vsetvli instruction; Figure 6 For dynamic injection in the present application, a schematic diagram of node delay covered in the ScheduleDAGRRList scheduling phase of LLVM. DETAILED DESCRIPTION

[0043] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0045] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0046] Interpretation of professional terms described in the present application: ; As Figure 4 shown, the present application is a kind of instruction scheduling optimization method for RISC-V variable length vector instruction hardware characteristics, including the following steps: S1, obtaining the target vector instruction to be scheduled, such as vmul.vv, vadd.vv, etc.; S2, dynamically determine the vector configuration information associated with the target vector instruction; The vector configuration information includes element bit width SEW and register grouping multiplier LMUL.

[0047] Dynamically determining the vector matching information associated with the target vector instruction includes the following steps: S2.1, in the basic block where the target vector instruction is located, lock the basic block (MachineBasicBlock, MBB) in reverse, perform reverse traversal search in the basic block, search from the previous instruction of the target instruction, scan forward along the instruction sequence, until the first valid vsetvli or vsetivli instruction is encountered;This process ensures that the matching is the nearest vector configuration instruction to the target instruction in the program execution flow and actually takes effect.

[0048] S2.2 If a vsetvli or vsetivli instruction is found within the basic block, extract the vector configuration information from this instruction.

[0049] The following example: in the basic block containing the instruction sequence (addi, vsetivli, vadd.vv, vsetvli, vmul.vv, vse.v), when traversing backward for the target instruction "vmul.vv v4, v5, v6", first check its previous instruction "vsetvli x0, a1, e64, m2", which is the matching vector configuration instruction. This configuration explicitly specifies the element bit width as e64 and uses the m2 register group, so "vmul.vv" is executed under this configuration.

[0050] # MachineBasicBlock: addi a0, a1, 1 vsetivli x0, 4, e32, m1 vadd.vv v1, v2, v3 vsetvli x0, a1, e64, m2 vmul.vv v4, v5, v6 vse.v v4, (a2) Among them, vmul.vv v4, v5, v6 is the nearest configuration instruction matched by backward traversal to vsetvli x0, a1, e64, m2.

[0051] If no valid vsetvli or vsetivli instruction is found in the current basic block (i.e. no vsetvli or vsetivli instruction associated with the target vector instruction such as vmul.vv can be found within the current basic block such as BB3), trigger a cross-basic block search (such as tracing back to the dominating node or performing data flow analysis), which includes the following steps: S2.3 Determine all predecessor basic blocks (Predecessors) in the control flow graph (CFG) of the basic block; S2.4 Extract the valid vtype state from the exit position of the predecessor basic block; Extracting the valid vtype state from the exit position of the predecessor basic block includes the following steps: S2.4.1 Get the predecessor basic block: for the current basic block MBB_curr, get its entire predecessor basic block set Preds = Preds(MBB_curr) in the control flow graph; S2.4.2 Check the exit state of the predecessor basic block; The checking of the exit state of a predecessor basic block specifically comprises the following steps: for each predecessor basic block Pred e Preds: S2.4.2.1 If the last instruction of a predecessor basic block is a vsetvli or vsetivli instruction, directly read the vtype state (e.g. SEW, LMUL, TA, MA, etc.) set by the instruction; S2.4.2.2 If the last instruction of a predecessor basic block is not a vsetvli or vsetivli instruction (i.e. not an explicit configuration instruction), perform a backward traversal search (same as the in-basic block search strategy) within the predecessor basic block, starting from the last instruction of the predecessor basic block and searching forward until the nearest vsetvli or vsetivli instruction is found, and read its vtype state; S2.4.2.3 If no vector configuration instruction is found in a predecessor basic block, recursively perform the cross-block configuration inheritance procedure for the predecessor basic block Pred (i.e. continue to trace its predecessor basic blocks) until a valid configuration is found or the program entry is reached.

[0052] S2.4.3 Merge and analyze the vector configuration information of the predecessor basic blocks.

[0053] The merging and analyzing of the vector configuration information of the predecessor basic blocks specifically comprises the following steps: S2.4.3.1 If the vtype states of all predecessor basic block exits are consistent, take the uniform configuration as the inherited configuration of the current predecessor basic block target vector instruction; S2.4.3.2 If the vtype states of the predecessor basic block exits are inconsistent (i.e. there is a configuration conflict between the predecessor basic blocks), handle according to the specific context, for example, insert an explicit vsetvli instruction to unify the configuration, or determine the optimal configuration with the help of global data flow analysis.

[0054] The following example: #BB1: vsetvli t0, a0, e32, m1, ta, ma # configuration: SEW = 32b, LMUL = 1 vle32.v v1, (a1) # load data vadd.vv v2, v1, v1 # calculation j BB3 # jump to BB3 #BB2: vsetvli t0, a1, e64, m2, ta, ma # configuration: SEW = 64b, LMUL = 2 vle64.v v3, (a2) # load data vadd.vv v4, v3, v3 # compute ret # BB3: vmul.vv v3, v2, v2 # direct inheritance of configuration (SEW=32b, LMUL=1) vse32.v v3, (a2) # store result j BB2 As Figure 5 shown, the target instruction vmul.vv v3, v2, v2 in BB3 has no vsetvli instruction within its own basic block. Its only predecessor basic block is BB1. By checking the end of BB1, it is found that its last valid instruction is j BB3, but a vsetvli t0, a0, e32, m1, ta, ma can be found inside BB1 by traversing it backward. Therefore, the vmul.vv instruction in BB3 can successfully inherit the configuration (SEW=32b, LMUL=1) without inserting a redundant configuration instruction.

[0055] S2.5 takes the extracted vtype state as the vector configuration information of the target vector instruction.

[0056] S3, based on the vector configuration information, establishes a dynamic delay calculation model to dynamically calculate the execution delay estimate of the target vector instruction; To more accurately evaluate the execution performance of the target vector instruction under a specific hardware configuration, a dynamic delay calculation model needs to be established, which comprehensively considers the influence of vector register grouping multiplier (LMUL) and element bit width (SEW) and other parameters on the number of instruction execution cycles.

[0057] When establishing a dynamic delay calculation model to dynamically calculate the execution delay estimate of the target vector instruction, a dynamic delay calculation formula is used: ; Where Base is the base period, i.e., the number of basic clock cycles required to execute the vector instruction under the reference configuration, which is usually SEW base =64b, LMUL=1, which is usually defined by the micro-architecture manual or performance model LMUL scale is a scaling factor related to the current vector length multiplier LMUL setting. Since LMUL directly affects the number of vector elements processed simultaneously and the number of physical registers used, it usually affects the emission, execution and completion delay of the instruction in a non-linear manner. Its specific value needs to be determined according to the characteristics of the hardware implementation (for example, when LMUL=2, the factor may be 2, and when LMUL=4, it may be 4, but there may also be a non-linear relationship due to different implementations).

[0058] SEW actual / SEW base is the effective bit-width ratio, i.e. the effective element bit-width SEW actual relative to the base bit-width SEW base . Executing wider or narrower data elements directly changes the number of elements each vector register can hold, thus affecting the number of loop iterations or data throughput that needs to be processed, ultimately scaling the total latency.

[0059] S4, providing the execution latency estimate to an instruction scheduler, the instruction scheduler scheduling optimizes an instruction sequence containing the target vector instruction based on the execution latency estimate.

[0060] In the LLVM compilation framework, instruction scheduling is a key step in the optimization process, aiming to maximize the utilization of micro-architecture features (such as pipelines, functional units, etc.) of the target processor by rearranging the order of instructions. For RISC-V architectures supporting vector extensions, since the execution latency of vector instructions is highly dependent on dynamic vtype configurations (such as SEW and LMUL), traditional static delay models are difficult to meet the accuracy requirements. Therefore, it is necessary to dynamically calculate and inject delay values based on the current configuration during the scheduling stage.

[0061] The implementation is based on the ScheduleDAGRRList scheduler core class of LLVM. The dynamic injection mechanism is integrated into its scheduling loop, covering node delays in the ScheduleDAGRRList scheduling stage of LLVM, as shown in Figure 6 .

[0062] The instruction scheduler scheduling optimizes an instruction sequence containing the target vector instruction based on the execution latency estimate specifically includes: S4.1 The instruction scheduler processes a sequence of instruction nodes (Node) within a basic block; S4.2 Select a node (Node) with the highest priority from the ready queue (Ready queue) for scheduling through the pickNode() algorithm; S4.3 Determine whether the currently selected node corresponds to the target vector instruction, for example, its operation belongs to the RISC-V vector extension instruction set; S4.4 If the current node is the target vector instruction, enter the dynamic injection stage; Entering the dynamic injection stage specifically includes the following steps: S4.4.1 Locate vsetvli configuration: determine the vtype state (i.e. SEW actual and LMUL values) that the target vector instruction depends on through the pickNode() algorithm; S4.4.2 Calculate dynamic latency: according to the acquired vtype state, calculate the real execution delay of the target vector instruction under the current configuration by using the dynamic delay calculation formula; S4.4.3 Update the calculated dynamic latency estimate to the SUnit scheduling unit information corresponding to the node through the callback function, overwrite the original preset static latency estimate (Latency) and / or priority (Priority) in the node.

[0063] S4.5 Update the node state according to the delay information, and after updating, enter the subsequent process, such as adding the node to the scheduling sequence, updating the readiness state of its dependent nodes, etc. S4.6 Loop steps S4.1-S4.5 until all instruction nodes in the basic block are scheduled.

[0064] The instruction scheduling optimization method introduces dynamic delay modeling and dynamic delay information injection mechanism, so that the compiler scheduler can perceive and adapt to the dynamic configuration parameters of the RISC-V variable-length vector instruction, and generate accurate instruction delay estimate in real time.

[0065] The above is only a specific embodiment of the present application, but the technical features of the present application are not limited to this. Any simple change, equivalent replacement or modification made on the basis of the present application to achieve substantially the same technical effect is covered by the protection scope of the present application.

Claims

1. An instruction scheduling optimization method for the hardware characteristics of RISC-V variable-length vector instructions, characterized in that... The method comprises the following steps: S1, obtaining a target vector instruction to be scheduled; S2, dynamically determining vector configuration information associated with the target vector instruction; S3, based on the vector configuration information, establishing a dynamic delay calculation model, and dynamically calculating an execution delay estimate of the target vector instruction; S4, providing the execution delay estimate to an instruction scheduler, and the instruction scheduler performs scheduling optimization on an instruction sequence containing the target vector instruction based on the execution delay estimate.

2. The method of claim 1, wherein the method is performed by a processor that supports the RISC-V variable-length vector instruction hardware feature. The vector configuration information in step S2 comprises an element bit width SEW and a register grouping multiplier LMUL.

3. The method of claim 2, wherein the method further comprises: determining whether the RISC-V variable-length vector instruction hardware feature is supported by the target processor; and if the RISC-V variable-length vector instruction hardware feature is supported by the target processor, then generating the instruction scheduling optimization for the RISC-V variable-length vector instruction hardware feature. The dynamic determination of the vector configuration information associated with the target vector instruction in step S2 comprises the following steps: S2.1 performing a backward traversal search in a basic block where the target vector instruction is located, and searching from a previous instruction of the target instruction along the instruction sequence forward until a first valid vsetvli or vsetivli instruction is encountered; S2.2 if the vsetvli or vsetivli instruction is searched in the basic block, extracting the vector configuration information from the instruction.

4. The instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics according to claim 3, characterized in that: If no valid vsetvli or vsetivli instruction is searched in the basic block, a cross-basic block search is triggered, which comprises the following steps: S2.3 determining all predecessor basic blocks in a control flow graph of the basic block; S2.4 extracting a valid vtype state from an exit position of the predecessor basic block; S2.5 taking the extracted vtype state as the vector configuration information of the target vector instruction.

5. The instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics according to claim 4, characterized in that: The extraction of the valid vtype state from the exit position of the predecessor basic block in step S2.4 comprises the following steps: S2.4.1 obtaining a predecessor basic block: for a current basic block MBB_curr, obtaining a complete set of predecessor basic blocks Preds = Preds(MBB_curr) in a control flow graph; S2.4.2 checking an exit state of the predecessor basic block; S2.4.3 merging and analyzing vector configuration information of the predecessor basic block.

6. The method of claim 5, wherein the method is performed by a processor. The checking of the exit state of the predecessor basic block in step S2.4.2 comprises the following steps: for each predecessor basic block Pred ∈ Preds: S2.4.2.1 if a last instruction of the predecessor basic block is a vsetvli or vsetivli instruction, directly reading a vtype state set by the instruction; S2.4.2.2 if the last instruction of the predecessor basic block is not a vsetvli or vsetivli instruction, performing a backward traversal search in the predecessor basic block, starting from a last instruction of the predecessor basic block and searching forward until a nearest vsetvli or vsetivli instruction is found, and reading a vtype state thereof; S2.4.2.3 if no vector configuration instruction is found in the predecessor basic block, performing a cross-block configuration inheritance process on the predecessor basic block Pred recursively until a valid configuration is found or a program entry is reached.

7. The method of claim 5, wherein the method further comprises: determining whether the RISC-V hardware feature is supported by the processor; and if the RISC-V hardware feature is supported by the processor, then generating the instruction scheduling optimization. The merging and analyzing the vector configuration information of the predecessor basic block in step S2.4.3 specifically includes the following steps: S2.4.3.1 if the vtype states of all the predecessor basic block outlets are consistent, the uniform configuration is taken as the inherited configuration of the target vector instruction of the current predecessor basic block; S2.4.3.2 if the vtype states of the predecessor basic block outlets are inconsistent, the processing is performed according to the specific context.

8. The method of claim 1, wherein: the RISC-V variable-length vector instruction hardware feature is a variable-length vector instruction hardware feature; and the method further comprises: determining that the instruction is a variable-length vector instruction; and in response to determining that the instruction is a variable-length vector instruction, performing the instruction scheduling optimization. The dynamic delay calculation model is established in step S3, and the dynamic delay calculation formula is used when the execution delay estimate of the target vector instruction is dynamically calculated: ； wherein Base is a base period, i.e. the number of basic clock cycles required to execute the vector instruction in a reference configuration, LMUL scale is a scaling factor related to the current vector length multiplier LMUL, SEW actual / SEW base is the ratio of the effective bit width, i.e. the effective element bit width SEW actual of the current actual configuration relative to the reference bit width SEW base .

9. The instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics according to claim 8, characterized in that: The instruction scheduler based on the execution delay estimate schedules and optimizes the instruction sequence containing the target vector instruction in step S4 specifically includes: S4.1 the instruction scheduler processes the instruction node sequence in a basic block; S4.2 a highest priority node is selected from the ready sequence for scheduling by using the pickNode() algorithm; S4.3 it is judged whether the current selected node corresponds to the target vector instruction; S4.4 if the current node is the target vector instruction, the dynamic injection stage is entered; S4.5 the node state is updated according to the delay information; S4.6 steps S4.1-S4.5 are looped until all the instruction nodes in the basic block are scheduled.

10. The instruction scheduling optimization method for RISC-V variable-length vector instruction hardware characteristics according to claim 9, characterized in that: The entering the dynamic injection stage in step S4.4 specifically includes the following steps: S4.4.1 the vtype state on which the target vector instruction depends is determined by using the pickNode() algorithm; S4.4.2 the real execution delay of the target vector instruction under the current configuration is calculated by using the dynamic delay calculation formula according to the obtained vtype state; S4.4.3 the dynamic delay estimate calculated is updated to the SUnit scheduling unit information corresponding to the node by using the callback function, and the original preset static delay estimate and / or priority in the node are overwritten.

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