Automatic generation method for reduction summation hardware structure with optimal power consumption delay product

By collaboratively exploring topology and pipeline partitioning within a unified framework using the CISA algorithm, the global optimality problem of reduction summation structure design in existing technologies is solved, energy efficiency optimization is achieved, and it is applicable to the design of reduction summation units in parallel computing chips.

CN121435874APending Publication Date: 2026-01-30SUZHOU RICORE IC TECH LTD
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Patent Information

Application Number
CN202511500142.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-10-20
Publication Date
2026-01-30

AI Technical Summary

Technical Problem

Existing reduction and summation structure design methods lack global optimality, cannot find a balance between performance and power consumption, have incomplete design space exploration, and lack comprehensive pipeline cost assessment, thus failing to achieve energy efficiency optimization.

Method used

We employ an automatic hardware architecture generation method that uses power-delay product optimization reduction and summation. Through the CISA algorithm, we collaboratively explore topology and pipeline partitioning within a unified framework, and generate the optimal hardware design using precise circuit models and objective functions.

Benefits of technology

It achieves a hardware design with optimal global energy efficiency, improves design efficiency and quality, eliminates uncertainties caused by human factors, and is suitable for the design of reduction and summation units in parallel computing chips.

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Abstract

The invention discloses a power consumption delay product optimal reduction summation hardware structure automatic generation method and a reduction summation hardware system.The power consumption delay product optimal reduction summation hardware structure automatic generation method comprises the steps that S1, an accurate circuit model is established, and an objective function is formalized; the CISA algorithm is realized by a script program, the script can call a synthesis tool for synthesis and analysis, S3, final hardware generation, and S31, after the algorithm is executed, the program outputs a final optimal solution Solbest, that is, the optimal solution is (Tbest netlist, kbest), the optimal solution Solbest comprises an optimal topological structure code, and an exact position of a pipeline register is inserted into the code, so that the optimal topological structure code is obtained. And S32, a designer or a subsequent automatic process generates a final hardware description language file which can be used for physical implementation according to the optimal solution Solbest.
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