Crosstalk cancellation

Abstract

The invention relates to crosstalk cancellation. Signal lines within an electronic system may be aligned in a spiral pattern. Further, two adjacent signal lines, in which at least one of the signal lines is aligned in a spiral pattern, may be arranged in a particular manner, in which signals on the two signal lines are transmitted in opposite directions. Some of the spiral patterns formed within the electronic system may be interwoven with each other.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to electronic systems, and more specifically, to crosstalk cancellation. Background Technology

[0002] Electronic devices (such as application-specific circuits, application-specific integrated circuits (ASICs), memory devices, memory packages) contain and utilize several signal lines, which can be unidirectional or bidirectional, for transmitting signals at various locations within the electronic device. Summary of the Invention

[0003] On one hand, this disclosure provides a system for crosstalk cancellation, comprising: a first signal line coupled between a first node and a second node on one or more planes; and a second signal line arranged adjacent to the first signal line and coupled between a third node and a fourth node on one or more planes, wherein the first signal line is aligned with the first spiral pattern arranged adjacent to the first spiral pattern.

[0004] On the other hand, this disclosure provides a system for crosstalk cancellation, comprising: a first spiral pattern formed on a specific plane by a first signal line coupled between a first inner node and a first outer node of the first spiral pattern; and a second spiral pattern interwoven with the first spiral pattern and formed on the specific plane by a second signal line coupled between a second inner node and a second outer node of the second spiral pattern; wherein the first inner node corresponds to a source node and the first outer node corresponds to a destination node, such that a signal is transmitted on the first signal line in a direction from the first inner node to the first outer node; wherein the second outer node corresponds to a source node and the second inner node corresponds to a destination node, such that a signal is transmitted on the second signal line in a direction from the second outer node to the second inner node.

[0005] On the other hand, this disclosure provides an apparatus for crosstalk cancellation, comprising: a first component; and a first signal line coupled between a first node and a second node of the first component, wherein the first signal line adjacent to one or more other signal lines of the first component is aligned on the first component with a first spiral pattern comprising a series of a certain number of shapes spiraling around a center point in a gradually decreasing manner. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1This describes an example electronic system comprising signal lines aligned in a specific pattern, according to some embodiments of the present disclosure.

[0008] Figure 2A-1 and 2A-2 The illustration shows both three-dimensional and top views of instances of signal lines coupled between various nodes according to some embodiments of this disclosure.

[0009] Figure 2B-1 and 2B-2 The illustration shows two alignments: a three-dimensional and a top view of another instance of signal lines coupled between various nodes according to some embodiments of the present disclosure.

[0010] Figure 2C-1 and 2C-2 The illustration shows two alignments: a three-dimensional and a top view of another instance of signal lines coupled between various nodes according to some embodiments of the present disclosure.

[0011] Figure 3 A top view illustrating the alignment of examples of signal lines positioned adjacent to each other according to some embodiments of this disclosure.

[0012] Figure 4 A top view illustrating another example of signal lines positioned adjacent to each other according to some embodiments of this disclosure.

[0013] Figure 5A and 5B Three-dimensional and top views of example alignments of signal lines positioned adjacent to each other according to some embodiments of the present disclosure are provided.

[0014] Figure 6A and 6B A top view illustrating the alignment of examples of signal lines positioned adjacent to each other according to some embodiments of this disclosure. Detailed Implementation

[0015] This disclosure relates to crosstalk cancellation. Crosstalk is an undesirable phenomenon that can occur in data buses and other communication lines, especially when multiple signals are very close to each other. For example, when a signal is transmitted on a conductor, it can introduce unwanted signals into adjacent conductors, causing interference. Crosstalk can occur in various forms, such as near-end crosstalk (NEXT), far-end crosstalk (FEXT), and external crosstalk. NEXT occurs when a signal transmitted on a conductor introduces unwanted signals into adjacent conductors near the transmission end. NEXT is measured at or near the source of the transmitted signal (e.g., the transmission end). FEXT occurs when a signal transmitted on a conductor introduces unwanted signals into adjacent conductors far from the transmission end. FEXT is measured at the receiving end of the transmitted signal.

[0016] In electronic systems (such as memory systems), the presence of multiple channel components (e.g., signal lines formed by wires) requires various design considerations because if any of these channel components experiences a crosstalk-related bottleneck, the performance of the entire system can be significantly degraded. A crosstalk-related bottleneck refers to a situation where crosstalk becomes a limiting factor for system performance. For example, in data transfer systems (such as solid-state drive (SSD) systems), crosstalk on one or more channel components exceeding acceptable limits can lead to data corruption, reduced read / write speeds, or even system instability. Therefore, optimizing various components within an electronic system without addressing crosstalk issues can result in significantly inefficient efforts to improve overall system performance.

[0017] The aspects of this disclosure address the aforementioned and other drawbacks by providing signal wire alignment with a specific pattern (e.g., a coil pattern), which provides crosstalk cancellation; thereby, system performance can be optimized without crosstalk issues becoming a point of failure for optimization. Signal wire alignment according to embodiments of this disclosure involves eliminating FEXT crosstalk by controlling mutual inductance. For example, consider the following equation for calculating FEXT crosstalk.

[0018]

[0019] In equation (1), V FE It is the voltage level at the far end, V A The voltage level of the aggressor, "length" refers to the length of the cable (e.g., signal line), "vel" refers to the speed, "trise" refers to the rise time, "M" subscript refers to mutual inductance / capacitance, and "L" subscript refers to the inherent inductance / capacitance of the victim's line.

[0020] As shown in the equation, if the relative conductivity of FEXT (e.g., C) M / C L ) and inductance (e.g., L) M / L M If the mutual capacitances (e.g., behavior) are equal, then they cancel each other out, which will minimize and / or zero FEXT (e.g., "0"). M The mutual capacitance can be adjusted (e.g., increased) to minimize and / or zero (e.g., "0") the FEXT, but the increased mutual capacitance can lead to undesirable effects such as insertion loss (IL), inter-symbol interference (ISI), etc. Therefore, embodiments of this disclosure can provide adjustments (e.g., control) to the mutual inductance (instead of mutual capacitance) so that the relative inductive behavior equals the relative conductive behavior, which still minimizes the FEXT to zero. This avoids the undesirable effects of adjusting (e.g., increasing) the mutual capacitance.

[0021] In several embodiments, relative inductance can be adjusted by aligning one or more signal lines (positioned adjacent to each other) in a helical pattern (e.g., a coil pattern) at one or two (e.g., transmit and / or receive) ends. Additionally, the signal lines can be aligned in a specific manner such that signals transmitted through the signal lines are in opposite directions. For example, when a first signal line aligned in a helical manner can carry a signal in a clockwise direction, a second signal line also aligned in a helical manner and adjacent to the first signal line can carry a signal in a counterclockwise direction. Signals transmitted in opposite directions can intentionally create "reverse inductive coupling" (alternatively referred to as "negative inductive coupling" and simply "reverse coupling") along a signal path primarily affected by "primary conductive inductive coupling." As used herein, the term "primary conductive inductive coupling" refers to the phenomenon where electromagnetic interference (EMI) is primarily caused by inductive coupling between two or more electronic circuits. This intentionally introduced reverse coupling can control (e.g., reduce) the mutual inductance between adjacent signal lines, which further reduces / minimizes crosstalk in the "victim" area (e.g., the far end of the signal line). The combination of the spiral pattern and signal direction described above can resolve crosstalk at either end of the signal transmission without compromising the system's ISI performance, such as its ability to accurately decode symbols, thus maintaining overall signal integrity.

[0022] Figure 1 This description describes an example electronic system 100 comprising signal lines 106-1, ..., 106-N aligned in a specific pattern according to some embodiments of this disclosure. The electronic system 100 may be, for example, a desktop computer, laptop computer, television, home theater system, game console, digital camera, network router and / or switch, printer, scanner, medical device, GPS navigation device, home appliance (e.g., thermostat, doorbell camera, security camera, smart lock, etc.), wearable device, industrial control system (e.g., automated industrial and / or control device), mobile computing device, vehicle (e.g., airplane, drone, train, car, or other transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked business device), system-on-a-chip (SoC), chipset (e.g., integrated circuit assembly), chip, field-programmable gate array (FPGA) structure (e.g., segmented FPGA structure), or other such device, or may be part of such device. Although the embodiments are not limited thereto, in some embodiments, the electronic system 100 may be a controller package, such as an application-specific integrated circuit (ASIC) package (e.g., a 6-layer package, an 8-layer package, etc.).

[0023] like Figure 1As described herein, electronic system 100 includes two components 102 and 104. However, embodiments are not limited to the specific number of components that electronic system 100 may include. For example, component 102 may be coupled to more than one component 104, and component 104 may also be coupled to more than one component 102.

[0024] While embodiments are not limited thereto, the component may be a constituent entity of electronic system 100, which may transmit (e.g., transmit, receive, etc.) signals to other components via signal lines 106-1, ..., 106-N. Examples of the component may include, but are not limited to, controllers, memory media and / or modules, one or different layers of a controller package (e.g., an ASIC package), and various communication media within layers of the controller package, such as vias, ball grid array (BGA) balls, etc.

[0025] In some embodiments, components 102 and 104, serving as memory media, may include volatile memory devices, such as (but not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM), or non-volatile memory, such as NAND flash memory, read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM). Components 102 and 104, serving as memory modules, may be dual in-line memory modules (DIMMs) and / or modules containing multiple memory chips (e.g., DRAM chips). In some embodiments, component 102 may correspond to a controller package, and component 104 may correspond to a memory package, but the embodiments are not limited thereto. Components 102 and 104 may be mounted on the same PCB and different PCBs, respectively (e.g., mounted).

[0026] Components of electronic system 100 (e.g., components 102 and 104) are coupled to each other via signal lines 106-1, ..., 106-N (collectively referred to as signal lines 106). Signal lines 106 can carry various types of signals, such as data signals (e.g., in the form of digital signals, analog signals, etc.), address signals (e.g., memory address signals, input / output (I / O) signals, etc.), control signals (read / write signals, chip select signals, etc.), power signals (VCC, VDD, GND, etc.), and clock signals, but embodiments are not limited thereto. In some embodiments, each signal line 106 can be physically connected, such as a physical wire.

[0027] In some embodiments, signal line 106 may (e.g., at least partially) be a single-ended bus, wherein data signals are transmitted along a single conductor and each data signal references a single common ground or voltage level. However, embodiments are not limited thereto. For example, signal line 106 may also be a differential bus, wherein data signals are transmitted along two complementary conductors, wherein the signal is the voltage difference between the complementary conductors.

[0028] Signal lines 106 can be aligned in various patterns between nodes (e.g., nodes 108-1-1, 108-1-2, 108-2-1, 108-2-2, ..., 108-3-1, 108-3-2, 108-4-1, 108-4-2 (collectively referred to as nodes)). For example, although Figure 1 Although not precisely depicted, signal lines 106-1 and 106-2 can be aligned to form various patterns (e.g., spiral patterns, rectangular spiral patterns, etc.) between nodes 108-1-1 and 108-1-2 and nodes 108-2-1 and 108-2-2, respectively. Additionally, for example, although... Figure 1 Although not precisely depicted, signal lines 106-N-1 and 106-N can be aligned to form various patterns (e.g., spiral patterns, rectangular spiral patterns, etc.) between nodes 108-3-2 and 108-3-3 and nodes 108-4-2 and 108-4-3, respectively.

[0029] As used herein, the term "node" refers to a connection point or intermediate point through which a signal line (e.g., signal line 106) is connected / coupled to other components of an electronic system (e.g., electronic system 100). For example, although embodiments are not limited thereto, a node can be a solder joint, connector pin, pad, socket, tube socket, solder ball (e.g., ball grid array (BGA) ball), solder bump, various metal contacts, etc., through which the signal line can be connected / coupled to other components of the electronic system (printed circuit board (PCB), via, substrate, connector, semiconductor die, controller package, memory package, memory module, etc.). The term "intermediate point" refers to a node that serves as an intermediary in a signal line (but may not be part of, for example, components 102 and / or 104), either as part of the signal line or created to extend the signal line, typically to modify the alignment pattern of the signal line. For example, nodes 108-3-2 and 108-4-2 can be used as intermediate nodes for signal lines 106-N-1 and 106-N, respectively. As used herein, a node used as an intermediate point may be referred to as an "intermediate node". In some embodiments, an intermediate node may be used as the starting point of a spiral pattern formed by signal lines.

[0030] like Figure 1 As described herein, nodes that can form patterns according to several embodiments of the present disclosure may be located at different components, such as components 102 and 104. For example, the patterns formed by signal lines 106-1 and 106-2 may be between nodes 108-1-1 and 108-1-2 located on components 102 and 104, respectively, or between nodes 108-2-1 and 108-2-2. However, the embodiments are not limited thereto. For example, the patterns formed by signal lines 106-N-1 and 106-N may be between nodes 108-3-2 and 108-3-3 located on component 104 but not on component 102, or between nodes 108-4-2 and 108-4-3.

[0031] The pattern that can be formed by signal line 106 can be a "spiral" or "coil" pattern. As used herein, the terms "spiral pattern" and "coil pattern" refer to a geometric arrangement in which a series of shapes, lines, or structures repeat around a central point or axis in a manner similar to a spiral shape. In various embodiments, the size of the shapes in a spiral pattern may gradually decrease (e.g., become smaller) as they spiral around a central point or axis. As used herein, the term "rectangular spiral pattern" refers to a spiral pattern in which a series of rectangular shapes repeat around a central point or axis in a spiral manner in a gradually decreasing manner. Additionally, depending on the context, the term "spiral pattern" may be used interchangeably with the term "spiral shape" and may have the same / substantially the same meaning. As further illustrated in Figures 2A to 2C, 3 to 4, 5A to 5B, and 6A to 6B, a spiral pattern / shape may be an "open shape," which refers to a shape having distinct endpoints that are not connected to form a complete boundary (therefore, no closed loop is formed), rather than a "closed shape" in which the endpoints form a continuous and unbroken boundary, thereby allowing the closed shape to have a region shape. Further details of the various ways in which signal lines can form spiral patterns are described below with reference to Figures 2A to 2C, 3 to 4, 5A to 5B, and 6A to 6B.

[0032] Figure 2A-1 and 2A-2 (Collectively referred to as FIG. 2A) illustrates both a three-dimensional and top view of an example alignment of signal lines 206-1, 206-2 coupled between various nodes according to some embodiments of the present disclosure. For example, as Figure 2A-2 As illustrated in the top view, signal line 206-1 is coupled between nodes 208-2-1 and 208-2-2, while signal line 206-2 is coupled between nodes 208-1-2 and 208-1-1. In other words, nodes 208-2-1 and 208-2-2 are coupled to each other via signal line 206-1, while nodes 208-1-2 and 208-1-1 are coupled to each other via signal line 206-2. Signal lines 206-1 and 206-2 can be similar to... Figure 1 Signal line 106 as described in the document.

[0033] Figure 2A-1 China (and) Figure 2B-1 , 2C-1The views (e.g., top views) shown in Figures 2A to 2C (3, 4, 5A to 5B and 6) provide a two-dimensional representation of the electronic system 200. The views capture the intersections of features of the electronic system 200 as seen from a specific angle. This specific angle may be a depiction of a “plane” (e.g., a two-dimensional surface extending infinitely in all directions (e.g., on the “X” and “Y” axes), which may or may not be at the same height as the signal lines 206 and nodes 208 illustrated in Figures 2A to 2C, and may exist in a third dimension (e.g., corresponding to the “z” axis) not defined by the two dimensions of the plane. For example, although the signal lines 206 and nodes 208 may not be precisely located on the plane shown in Figures 2A to 2C, Figures 2A to 2C can illustrate points, lines, and / or patterns obtained (e.g., generated) on the plane by projecting the signal lines 206 and nodes 208 onto the plane.

[0034] While embodiments are not limited thereto, the plane (e.g., a virtual plane) may be parallel to a particular memory component on which node 208 is arranged / formed. For example, the plane may be parallel to a printed circuit board, a controller located on (and parallel to) the printed circuit board, and / or the top surface of a memory medium / module.

[0035] Nodes 208-2-1, 208-1-2, 208-2-2, and 208-1-1 can be considered as parts of components 210-1-1, 210-2-2, 210-1-2, and 210-2-1 (collectively referred to as component 210), respectively. Component 210 can be similar to... Figure 1 Components 102 and 104 are described herein. While embodiments are not limited thereto, components 210-1-1, 210-2-1, 210-1-2, and 210-2-2 may be through-holes, BGA balls, etc., of a controller package (e.g., a 6-layer ASIC package). More specifically, components 210-1-1 and 210-2-1 may be through-holes on one layer of the controller package, while components 210-1-2 and 210-2-2 may be through-holes or BGA balls on another layer or the bottom of the controller package. For example, components 210-2-1 and / or 210-2-2 may be BGAs with solder balls, through which the package (e.g., a controller package, a memory package, etc.) can be mounted on a PCB.

[0036] Each signal line is aligned in a spiral pattern (e.g., a rectangular spiral pattern). For example, both signal lines 206-1 and 206-2 are aligned in a spiral pattern. Figure 2A-2The rectangular spiral pattern of several rectangular shapes is aligned as described herein. In a more specific instance, signal line 206-1 is aligned with a rectangular spiral pattern to form two rectangular shapes (e.g., substantially rectangular shapes): one rectangular shape has line segments 216-1-1 and 216-1-2 that are substantially perpendicular to each other, and another rectangular shape has line segments 216-2-1 and 216-2-2 that are substantially perpendicular to each other. As used herein, the term “substantially” means that the characteristic need not be absolute, but is close enough to achieve the advantages of the characteristic. For example, “substantially rectangular” is not limited to the shape of an absolute rectangle, but can be a shape that is desired to be rectangular but may not be precisely rectangular due to various limitations (e.g., manufacturing limitations). In another instance, “substantially perpendicular” is not limited to a right angle between two line segments, but can be an angle that is desired to be perpendicular but may not be precisely perpendicular due to various limitations (e.g., manufacturing limitations).

[0037] like Figure 2A-1 and 2A-2 As explained, the two spiral patterns corresponding to signal lines 206-1 and 206-2 are formed in an "interlaced" manner. For example, the two spiral patterns are formed in an "interlaced" manner such that the line segment drawn between nodes 208-2-1 and 208-2-2 (not shown in Figure 2A) intersects signal line 206-2, while the line segment drawn between nodes 208-1-2 and 208-1-1 (not shown in Figure 2A) intersects signal line 206-1.

[0038] In several embodiments, signal lines 206-1 and 206-2 are formed in an interlaced manner along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as along the height or z-axis), and also as... Figure 2A-1 As explained in the description. In other words, signal lines 206-1 and 206-2 are substantially adjacent to each other in their respective planes (e.g., height or z-axis). For example, a portion of signal line 206-2 near (or adjacent to) node 208-1-2 lies in the same plane (e.g., height) as a portion of signal line 206-1 near (or adjacent to) node 208-2-1. Similarly, the aforementioned portions of signal lines 206-1 and 206-2 are substantially formed in the same plane as they extend toward nodes 208-1-1 and 208-2-2, respectively.

[0039] Signal lines 206-1 and 206-2 can be aligned such that the signals on signal lines 206-1 and 206-2 are transmitted in opposite directions. For example, consider an instance where signals are transmitted from one layer (the layer containing components 210-1-1 and 210-2-1) to another layer (the layer containing components 210-1-2 and 210-2-2) via signal lines 206-1 and 206-2, respectively. In this example, the signal on signal line 206-2 is transmitted in a certain (e.g., clockwise) direction from the “outer” node 208-1-1 (which is part of component 210-2-1) of the spiral pattern to the “inner” node 208-1-2 (which is part of component 210-2-2). In contrast, the signal on signal line 206-1 is transmitted in a certain (e.g., counterclockwise) direction from the “inner” node 208-2-1 (which is part of component 210-1-1) of the spiral pattern to the “outer” node 208-2-2 (which is part of component 210-1-2). These signals, which are transmitted in opposite directions on adjacent signal lines (e.g., signal lines 206-1, 206-2), can intentionally generate reverse inductive coupling, which can eliminate and / or mitigate the adverse effects of crosstalk on signal lines 206-1, 206-2 (more specifically, on nodes 208-2-2 and 208-1-2, which are the distal ends of signal lines 206-1, 206-2, respectively).

[0040] Figure 2B-1 and 2B-2 (Collectively referred to as FIG. 2B) illustrates both a three-dimensional and a top view of another example alignment of signal lines coupled between various nodes according to some embodiments of the present disclosure. The alignment of signal line 206 shown in FIG. 2B is generally similar to the alignment of signal line 206 shown in FIG. 2A. For example, as illustrated in the top view of FIG. 2B, signal line 206-1 is coupled between nodes 208-2-1 and 208-2-2, while signal line 206-2 is coupled between nodes 208-1-2 and 208-1-1.

[0041] Additionally, signal lines 206-1 and 206-2 can be aligned such that the signals on signal lines 206-1 and 206-2 are transmitted in opposite directions. For example, the signal on signal line 206-2 can be transmitted in a certain (e.g., clockwise) direction from the “outer” node 208-1-1 (which is part of component 210-2-1) of the spiral pattern to the “inner” node 208-1-2 (which is part of component 210-2-2). In contrast, the signal on signal line 206-1 can be transmitted in a certain (e.g., counterclockwise) direction from the “inner” node 208-2-1 (which is part of component 210-1-1) of the spiral pattern to the “outer” node 208-2-2 (which is part of component 210-1-2).

[0042] Additionally, signal lines 206-1 and 206-2 are formed (e.g., in an interlaced manner) along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as on the height or z-axis), and also as... Figure 2B-1 As explained in the description. In other words, signal lines 206-1 and 206-2 are substantially adjacent to each other in their respective planes (e.g., height or z-axis). For example, a portion of signal line 206-2 near (or adjacent to) node 208-1-2 lies in the same plane (e.g., height) as a portion of signal line 206-1 near (or adjacent to) node 208-2-1. Similarly, the aforementioned portions of signal lines 206-1 and 206-2 are substantially formed in the same plane as they extend toward nodes 208-1-1 and 208-2-2, respectively.

[0043] However, signal lines 206 can be aligned in a "less" spiral manner (e.g., with fewer coils). In other words, the spiral pattern formed by signal lines 206-1 and 206-2 of FIG. 2B can contain fewer shapes than the spiral pattern shown in FIG. 2A. For example, compared to the spiral pattern shown in FIG. 2A which has at least two rectangular shapes, the spiral pattern shown in FIG. 2B has a single rectangular shape (with line segments 216-1-1 and 216-1-2 that are substantially perpendicular to each other). The spiral pattern of FIG. 2B, with fewer coils compared to the spiral pattern of FIG. 2A, can result in a reduction in the inductance (e.g., mutual inductance) between signal lines 206-1 and 206-2.

[0044] Figure 2C-1 and 2C-2 (Collectively referred to as FIG. 2C) illustrates both a three-dimensional and a top view of another example alignment of signal lines coupled between various nodes according to some embodiments of the present disclosure. The alignment of signal line 206 shown in FIG. 2C is generally similar to the alignment of signal line 206 shown in FIG. 2B. For example, as illustrated in the top view of FIG. 2C, signal line 206-1 is coupled between nodes 208-2-1 and 208-2-2, while signal line 206-2 is coupled between nodes 208-1-2 and 208-1-1.

[0045] Additionally, signal lines 206-1 and 206-2 can be aligned such that the signals on signal lines 206-1 and 206-2 are transmitted in opposite directions. For example, the signal on signal line 206-2 can be transmitted in a certain (e.g., clockwise) direction from the “outer” node 208-1-1 (which is part of component 210-2-1) of the spiral pattern to the “inner” node 208-1-2 (which is part of component 210-2-2). In contrast, the signal on signal line 206-1 can be transmitted in a certain (e.g., counterclockwise) direction from the “inner” node 208-2-1 (which is part of component 210-1-1) of the spiral pattern to the “outer” node 208-2-2 (which is part of component 210-1-2).

[0046] Additionally, signal lines 206-1 and 206-2 are formed (e.g., in an interlaced manner) along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as on the height or z-axis), and also as... Figure 2C-1 As explained in the description. In other words, signal lines 206-1 and 206-2 are substantially adjacent to each other in their respective planes (e.g., height or z-axis). For example, a portion of signal line 206-2 near (or adjacent to) node 208-1-2 lies in the same plane (e.g., height) as a portion of signal line 206-1 near (or adjacent to) node 208-2-1. Similarly, the aforementioned portions of signal lines 206-1 and 206-2 are substantially formed in the same plane as they extend toward nodes 208-1-1 and 208-2-2, respectively.

[0047] However, the alignment shown in Figure 2C may differ from that shown in Figure 2B regarding the distance between the two signal lines 206-1 and 206-2 within the spiral pattern (measured from the top views shown in Figures 2B and 2C, respectively). For example, the distance between the two signal lines 206-1 and 206-2 within the spiral shown in Figure 2C (shown as 223 in Figure 2C) may be larger (e.g., longer) than the distance between the two signal lines 206-1 and 206-2 within the spiral shown in Figure 2B (shown as 222 in Figure 2B). This larger distance between the two signal lines 206-1 and 206-2 may result in a relatively smaller capacitance between the two signal lines 206-1 and 206-2 shown in Figure 2C compared to the capacitance between the two signal lines 206-1 and 206-2 shown in Figure 2B.

[0048] Figure 3This is a top view illustrating the alignment of examples of signal lines (e.g., signal lines 306-1, 306-2, 306-3, 306-4, 306-5, 306-6) positioned adjacent to each other according to some embodiments of this disclosure. Signal lines 306-1, 306-2, 306-3, 306-4, 306-5, 306-6 (alternately referred to as signal line 306) can be similar to... Figure 1 The signal line 106 is described in the document. For example... Figure 3 As explained, signal lines 306-1, 306-2, 306-3, 306-4, 306-5 and 306-6 are coupled to nodes 308-1, 308-2, 308-3, 308-4, 308-5 and 308-6, respectively.

[0049] Although the embodiments are not limited to this, Figure 3 The top view illustrated herein may be a portion of electronic system 300 (similar to electronic system 100), which may correspond to a portion of a controller package (e.g., a multilayer ASIC package). More specifically, signal lines may be coupled to nodes of one layer (e.g., the top layer) of the multilayer controller. Figure 3 (Not shown in the text) and is used to carry signals, for example, open NAND flash interface (ONFI) communication.

[0050] As described in this article, Figure 3 The top view described herein may correspond to a plane (e.g., a virtual plane) on which signal line 306 and node 308 are projected. For example, although the signal line 306 and node 308 may not be precisely located... Figure 3 On the plane shown in the document, but Figure 3 This can be illustrated by points, lines, and / or patterns generated on a plane by projecting signal lines 306 and nodes 308 onto the plane. While embodiments are not limited thereto, the plane (e.g., a virtual plane) may be parallel to a specific memory component on which signal lines 306 and nodes 308 are arranged / formed. For example, the plane may be parallel to a printed circuit board, a controller located on (and parallel to) the printed circuit board, and / or the top surface of a memory media / module.

[0051] Furthermore, signal lines 306-1, ..., 306-6 are formed (e.g., in an interlaced manner) along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as on the height or z-axis). In other words, signal lines 306-1, ..., 306-6 are substantially adjacent to each other on their respective planes (e.g., on the height or z-axis). For example, signal line 306-3 is near (or adjacent to) a portion of region 317 on the same plane (e.g., on the height) as signal line 306-4 is near (or adjacent to) a portion of said region.

[0052] like Figure 3 The text further explains that signal line 306-3 is aligned in a (e.g., partially) spiral pattern (e.g., at least partially) within the area indicated by 317. As used herein, the term "partial spiral pattern" refers to a pattern characterized by elements of incomplete or irregular shape whose size decreases or changes as said elements advance / spiral around a center point or axis. Consider an example where signals on signal lines 306-1, 306-2, 306-3, 306-4, 306-5, and 306-6 are respectively oriented in the corresponding directions. Figure 3 The nodes 308-1, 308-2, 308-3, 308-4, 308-5, and 308-6 shown are transmitted. In this example, the spiral pattern formed by signal line 306-3 in zone 317 causes the two signals on signal lines 306-3 and 306-4 to be in opposite directions at least in zone 317 (also as shown by...). Figure 3 (As indicated by the arrow shown in the diagram). This intentionally creates reverse inductive coupling, which eliminates and / or mitigates the adverse effects of crosstalk on signal line 306 that was already present on signal line 306 prior to zone 317 due to the main conductor inductive coupling along signal line 306.

[0053] Figure 4 This illustration shows a top view of another example of signal lines (e.g., signal lines 406-1, 406-2, 406-3, 406-4, 406-5, 406-6, 406-7, 406-8) positioned adjacent to each other according to some embodiments of this disclosure. Signal lines 406-1, 406-2, 406-3, 406-4, 406-5, 406-6, 406-7, 406-8 (alternately referred to as signal line 406) may be similar to... Figure 1 Signal line 106 as described in the document.

[0054] Although the embodiments are not limited to this, Figure 4 The top view illustrated herein may be a portion of electronic system 400 (similar to electronic system 100), which may correspond to a portion of a controller package (e.g., a multi-layer ASIC package). More specifically, the signal lines may be analogous to an 8-input / output (DQ) data bus on a layer (e.g., the bottom layer) of a multi-layer controller and used to carry signals for a specific communication protocol (e.g., double data rate (DDR), such as low-power DDR (LPDDR)).

[0055] As described in this article, Figure 4 The top view described herein may correspond to a plane (e.g., a virtual plane) on which signal line 406 and node 408 are projected. For example, although the signal line 406 and node 408 may not be precisely located... Figure 4 On the plane shown in the document, but Figure 4This can be illustrated by points, lines, and / or patterns generated on a plane by projecting signal lines 406 and nodes 408 onto the plane. While embodiments are not limited thereto, the plane (e.g., a virtual plane) may be parallel to a specific memory component on which signal lines 406 and nodes 408 are arranged / formed. For example, the plane may be parallel to a printed circuit board, a controller located on (and parallel to) the printed circuit board, and / or the top surface of a memory media / module.

[0056] In several embodiments, each pair of signal lines 406 (e.g., a pair of signal lines 406-1 and 406-2, a pair of signal lines 406-3 and 406-4, and / or a pair of signal lines 406-5 and 406-6) are formed in an interlaced manner along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as on the height or z-axis). In other words, signal lines 406-1 and 406-2 are substantially adjacent to each other in their respective planes (e.g., on the height or z-axis). For example, a portion of signal line 406-2 near (or adjacent to) node 408-2-2 lies in the same plane (e.g., on the height) as a portion of signal line 406-1 near (or adjacent to) node 408-1-1. Similarly, the portions of signal lines 406-1 and 406-2 are formed substantially in the same plane as they extend toward nodes 408-1-2 and 408-2-1, respectively.

[0057] like Figure 4 As described, signal line 406-1 is coupled between nodes 408-1-1 and 408-1-2; signal line 406-2 is coupled between nodes 408-2-1 and 408-2-2; signal line 406-3 is coupled between nodes 408-3-1 and 408-3-2; signal line 406-4 is coupled between nodes 408-4-1 and 408-4-2; signal line 406-5 is coupled between nodes 408-5-1 and 408-5-2; signal line 406-6 is coupled between nodes 408-6-1 and 408-6-2; and signal line 406-7 is coupled between nodes 408-7-1 and 408-7-2.

[0058] The spiral patterns formed by at least some signal lines 406 are intertwined. For example, such as Figure 4 As explained, the spiral pattern formed by signal line 406-1 intertwines with the spiral pattern formed by signal line 406-2; the spiral pattern formed by signal line 406-3 intertwines with the spiral pattern formed by signal line 406-4; and the spiral pattern formed by signal line 406-5 intertwines with the spiral pattern formed by signal line 406-6.

[0059] Assuming signal line 406 is a "unidirectional" signal line, signal line 406 is aligned to form corresponding spiral patterns in such a way that signals on the two signal lines forming interlaced spiral patterns are transmitted in opposite directions. For example, node 408-1-1, which is the source of the signal transmitted on signal line 406-1, is located inside the corresponding spiral pattern, while node 408-2-1, which is the source of the signal transmitted on signal line 406-2, is located outside the corresponding spiral pattern interlaced with the spiral pattern formed by signal line 406-1. This results in two signals being transmitted in opposite directions on signal lines 406-1 and 406-2, respectively. For example, the signal is transmitted counterclockwise on signal line 406-1, while the signal is transmitted clockwise (e.g., at least partially) on signal line 406-2.

[0060] Similarly, node 408-3-1, which is the source of the signal transmitted on signal line 406-3, is located inside the corresponding spiral pattern, while node 408-4-1, which is the source of the signal transmitted on signal line 406-4, is located outside the corresponding spiral pattern interwoven with the spiral pattern formed by signal line 406-3. For example, the signal is transmitted counterclockwise on signal line 406-3, while the signal is transmitted clockwise (e.g., at least partially) on signal line 406-4. Similarly, node 408-5-1, which is the source of the signal transmitted on signal line 406-5, is located outside the corresponding spiral pattern, while node 408-6-1, which is the source of the signal transmitted on signal line 406-6, is located inside the corresponding spiral pattern interwoven with the spiral pattern formed by signal line 406-5. For example, the signal is transmitted clockwise on signal line 406-5, while the signal is transmitted counterclockwise (e.g., at least partially) on signal line 406-6.

[0061] Figure 5A and 5B Three-dimensional and top views of example alignments of signal lines positioned adjacent to each other according to some embodiments of the present disclosure are provided. Signal lines 506-1, 506-2, 506-3 (alternately referred to as signal lines 506) may be similar to Figure 1 Signal line 106 as described in the document.

[0062] Although the embodiments are not limited to this, Figures 5A to 5B The view described herein may be part of electronic system 500 (similar to electronic system 100), which may correspond to a portion of a memory package (e.g., NAND). Figures 5A to 5B As shown, nodes 508-1-1, 508-2-1, and 508-3-1 can be used as intermediate nodes for signal lines 506-1, 506-2, and 506-3, respectively.

[0063] As described in this article, Figure 5B The top view described herein may correspond to a plane (e.g., a virtual plane) on which signal line 506 and node 508 are projected. For example, although the signal line 506 and node 508 may not be precisely located... Figure 5B On the plane shown in the document, but Figure 5B This can be illustrated by points, lines, and / or patterns generated on a plane by projecting signal lines 506 and nodes 508 onto the plane. While embodiments are not limited thereto, the plane (e.g., a virtual plane) may be parallel to a specific memory component on which signal lines 506 and nodes 508 are arranged / formed. For example, the plane may be parallel to a printed circuit board, a controller located on (and parallel to) the printed circuit board, and / or the top surface of a memory media / module.

[0064] In several embodiments, signal lines 506-1, 506-2, and / or 506-3 are formed in an interlaced manner along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as along the height or z-axis), and also as... Figure 5A As explained in the description. In other words, signal lines 506-1 and 506-2 are substantially adjacent to each other in their respective planes (e.g., height or z-axis). For example, a portion of signal line 506-2 near (or adjacent to) node 508-2-2 lies in the same plane (e.g., height) as a portion of signal line 506-1 near (or adjacent to) node 508-1-1. Similarly, the aforementioned portions of signal lines 506-1 and 506-2 are substantially formed in the same plane as they extend toward nodes 508-1-2 and 508-2-1, respectively.

[0065] like Figure 5A and 5B As described, at least three signal lines 506-1, 506-2, and 506-3 are aligned in a manner that forms corresponding / various spiral patterns. While the spiral patterns formed by signal lines 506-1 and 506-2 interweave, the spiral pattern formed by signal line 506-3 does not interweave with them. Figure 5B Other spiral patterns shown in the image are interwoven.

[0066] Given that portions of electronic system 500 correspond to memory packages (e.g., NAND packages), spiral patterns can be formed (via corresponding signal lines) at various locations within electronic system 500, such as within controller packages (e.g., ASIC packages). For example, spiral patterns can be formed only on the memory package, only on the controller package, or on both. While additional spiral patterns in different areas of electronic system 500 (e.g., both the controller and memory packages) can further improve crosstalk cancellation, the decision regarding the number and placement of these spiral patterns may involve balancing benefits with costs (e.g., implementation costs) to optimize / maximize benefits.

[0067] Figure 6A and 6B This illustration shows three-dimensional and top views of examples of signal lines positioned adjacent to each other according to some embodiments of the present disclosure. Signal lines 606-1 and 606-2 (alternately referred to as signal lines 606) may be similar to... Figure 1 Signal line 106 as described in the document.

[0068] Although the embodiments are not limited to this, Figures 6A to 6B The view described herein may be part of electronic system 600 (similar to electronic system 100), which may correspond to a portion of a memory package (e.g., NAND). Figures 6A to 6B As shown, nodes 608-1-1 and 608-2-1 can be used as intermediate nodes for signal lines 606-1 and 606-2, respectively.

[0069] Component 610 can be similar to Figure 1 Components 102 and 104 are described herein. Although the embodiments are not limited thereto, components 610-1 and 610-2 may be through-holes, BGA balls, etc. of electronic system 600, and electronic system 600 may be a controller package (e.g., a 6-layer ASIC package) and / or a memory package (e.g., a NAND package).

[0070] As described in this article, Figure 6B The top view described herein may correspond to a plane (e.g., a virtual plane) on which signal line 606 and node 608 are projected. For example, although the signal line 606 and node 608 may not be precisely located... Figure 6B On the plane shown in the document, but Figure 6B This can be illustrated by points, lines, and / or patterns generated on a plane by projecting signal lines 606 and nodes 608 onto the plane. While embodiments are not limited thereto, the plane (e.g., a virtual plane) may be parallel to a specific memory component on which signal lines 606 and nodes 608 are arranged / formed. For example, the plane may be parallel to a printed circuit board, a controller located on (and parallel to) the printed circuit board, and / or the top surface of a memory media / module.

[0071] In several embodiments, signal lines 606-1 and 606-2 are formed in an interlaced manner along substantially the same plane (e.g., a two-dimensional surface as mentioned above, such as along the height or z-axis), and also as... Figure 6A As explained in the description. In other words, signal lines 606-1 and 606-2 are substantially adjacent to each other in their respective planes (e.g., height or z-axis). For example, a portion of signal line 606-2 near (or adjacent to) node 608-2-1 lies in the same plane (e.g., height) as a portion of signal line 606-1 near (or adjacent to) node 608-1-2. Similarly, the aforementioned portions of signal lines 606-1 and 606-2 are substantially formed in the same plane as they extend toward nodes 608-1-1 and 608-2-2, respectively.

[0072] Similar to Figures 2A to 2C and 3 to 5, the signal lines are aligned to form corresponding spiral patterns. Furthermore, the spiral patterns formed by signal lines 606-1 and 606-2 intertwine with each other. In other words, the plane between the two nodes (608-1-1 and 608-1-2 or 608-2-1 and 608-2-2) of a signal line (606-1 or 606-2) (corresponding to...) Figure 6B The line on the top view intersects with another signal line.

[0073] Node 608-2-1, serving as an intermediate node, is configured to change the direction of the signal transmitted on signal line 606-2 relative to the direction of the signal transmitted on signal line 606-1. For example, consider an instance where signals are transmitted on signal lines 606-1 and 606-2, respectively, and towards components 610-1 and 610-2 (e.g., in the direction from node 608-1-1 or 608-2-1 to node 608-1-2 or 608-2-2). When the signal transmitted on signal line 606-1 is transmitted counterclockwise in the spiral pattern formed by signal lines 606-1, due to intermediate node 608-2-1, the signal transmitted on signal line 606-2, which has already been transmitted in a similar direction to the signal on signal line 606-1, is transmitted clockwise in the spiral pattern formed by signal lines 606-2. This results in signals being transmitted in opposite directions on those adjacent portions of signal lines 606-1 and 606-2.

[0074] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. The algorithms described herein are generally considered as self-consistent sequences of operations that lead to the desired results. An operation is an operation that requires the physical manipulation of physical quantities. Typically, although not always necessary, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that, primarily for common use, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or similar terms.

[0075] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0076] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0077] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with programs taught herein, or it may prove convenient to construct more specialized devices to execute the methods. The architectures of many such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0078] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0079] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive manner.

Claims

1. A system for crosstalk cancellation, comprising: a first signal line (106-1,..., 106-N; 206-1; 306-1,..., 306-6; 406-1, 406-3, 406-5; 506-1; 606-1) coupled between a first node (108-1-1,..., 108-4-3; 208-1-1; 308-1,..., 308-6; 408-1-1, 408-3-1, 408-5-1; 508-1-1; 608-1-1) and a second node (108-1-1,..., 108-4-3; 208-1-2; 308-1,..., 308-6; 408-1-2, 408-3-2, 408-5-2; 508-1-2; 608-1-2) in one or more planes; and 406-1、406-3、406-5； a second signal line (106-1,..., 106-N; 206-2; 306-1,..., 306-6; 406-2, 406-4, 406-6; 506-2, 506-3; 606-2) disposed adjacent to the first signal line and coupled between a third node (108-1-1,..., 108-4-3; 208-2-1; 308-1,..., 308-6; 408-2-1, 408-4-1, 408-6-1; 508-2-1; 608-2-1) and a fourth node (108-1-1,..., 108-4-3; 208-2-2; 308-1,..., 308-6; 408-2-2, 408-4-2, 408-6-2; 508-2-2; 608-2-2) in one or more planes, wherein the first signal line is aligned with a first spiral pattern disposed adjacent to the first spiral pattern.

2. The system of claim 1, wherein: the first nodes correspond to inner nodes (208-1-2, 208-2-1; 408-1-1, 408-2-2, 408-3-1, 408-4-2, 408-5-2, 408-6-1; 508-1-1, 508-2-2; 608-1-2, 608-2-1) of the first spiral pattern and the second nodes correspond to outer nodes (208-1-1, 208-2-2; 408-1-2, 408-2-1, 408-3-2, 408-4-1, 408-5-1, 408-6-2; 508-2-1; 608-1-1, 608-2-2) of the first spiral pattern; the second signal line is also aligned with a second spiral pattern interleaved with the first spiral pattern; and the first and second spiral patterns are interleaved in a manner that the first and second nodes of the first spiral pattern are aligned with the third and fourth nodes of the second spiral pattern, respectively. ​ ​ ​ The third nodes correspond to inner nodes (208-1-2, 208-2-1; 408-1-1, 408-2-2, 408-3-1, 408-4-2, 408-5-2, 408-6-1; 508-1-1, 508-2-2; 608-1-2, 608-2-1) of the second spiral pattern, while the fourth nodes correspond to outer nodes (208-1-1, 208-2-2; 408-1-2, 408-2-1, 408-3-2, 408-4-1, 408-5-1, 408-6-2; 508-2-1; 608-1-1, 608-2-2) of the second spiral pattern.

3. The system of claim 2, wherein: the first and fourth nodes correspond to source nodes (480-1-1, 408-3-1, 408-6-1), respectively; and the second and third nodes correspond to destination nodes (408-1-2, 408-3-2, 408-6-2), respectively.

4. The system of claim 2, further comprising: a third signal line (106-1,..., 106-N, 306-1,..., 306-6, 406-1, 406-3, 406-5) aligned in a third spiral pattern; a fourth signal line (106-1,..., 106-N, 306-1,..., 306-6, 406-2, 406-4, 406-6) aligned in a fourth spiral pattern interleaved with the third spiral pattern.

5. The system of claim 4, wherein: a first distance (223) between the first signal line and the second signal line, respectively, within the first spiral pattern or the second spiral pattern, is substantially constant; and a second distance (222) between the third signal line and the fourth signal line, respectively, within the third spiral pattern or the fourth spiral pattern, is substantially constant.

6. The system of claim 5, wherein: the second distance is shorter than the first distance to achieve a relatively reduced mutual capacitance between the third and fourth signal lines compared to the mutual capacitance between the first and the second signal lines.

7. The system of any one of claims 4-6, wherein: the first spiral pattern, the second spiral pattern, or both, include a first number of shapes spiraled in a progressively decreasing manner around a first center point; and the third spiral pattern, the fourth spiral pattern, or both, include a second number of shapes spiraled in a progressively decreasing manner around a second center point.

8. The system of claim 7, wherein the first number of shapes has a greater number than the second number of shapes to achieve a relatively increased mutual inductance between the first and the second signal lines compared to the mutual capacitance between the third and the fourth signal lines.

9. A system for crosstalk cancellation, comprising: a first spiral pattern formed on a particular plane by first signal lines (106-1,..., 106-N; 206-1; 306-1,..., 306-6; 406-1, 406-3, 406-5; 506-1; 606-1) coupled between first inner nodes (108-1-1,..., 108-4-3; 208-1-2, 208-2-1; 308-1,..., 308-6; 408-1-1, 408-3-1, 408-5-1; 508-1-1; 608-1-1) of the first spiral pattern and first outer nodes (108-1-1,..., 108-4-3; 208-1-1, 208-2-2; 308-1,..., 308-6; 408-1-2, 408-3-2, 408-5-2; 508-1-2; 608-1-2) of the first spiral pattern; and a second spiral pattern interleaved with the first spiral pattern and formed on the particular plane by second signal lines (106-1,..., 106-N; 206-2; 306-1,..., 306-6; 406-2, 406-4, 406-6; 506-2; 506-3; 606-2) coupled between second inner nodes (108-1-1,..., 108-4-3; 208-2-1, 208-1-2; 308-1,..., 308-6; 408-2-1, 408-4-1, 408-6-1; 508-2-1; 608-2-1) of the second spiral pattern and second outer nodes (108-1-1,..., 108-4-3; 208-2-2, 208-1-1; 308-1,..., 308-6; 408-2-2, 408-4-2, 408-6-2; 508-2-2; 608-2-2) of the second spiral pattern; wherein the first inner nodes correspond to source nodes and the first outer nodes correspond to destination nodes, such that signals are transmitted on the first signal lines in a direction from the first inner nodes to the first outer nodes; wherein the second outer nodes correspond to source nodes and the second inner nodes correspond to destination nodes, such that signals are transmitted on the second signal lines in a direction from the second outer nodes to the second inner nodes.

10. The system of claim 9, wherein: the first spiral pattern includes a series of a first number of shapes spiraled in a progressively decreasing manner around a first center point, wherein the first inner nodes are substantially located on the first center point; the second spiral pattern includes a series of a second number of shapes spiraled in a progressively decreasing manner around a second center point, wherein the second inner nodes are substantially located on the second center point; the first outer nodes are located outside of the first number of shapes; and the second outer nodes are located outside of the second number of shapes.

11. An apparatus for crosstalk cancellation, comprising: a first component (102); and first signal lines (106-1,..., 106-N; ​ ​ ​ ​ ​ 206-1；306-1、…、306-6；406-1、406-3、406-5； 506-1; 606-1) coupled between a first node (108-1-1,..., 108-4-3; 208-1-1; 308-1,..., 308-6; 408-1-1, 408-3-1, 408-5-1; 508-1-1; 608-1-1) and a second node (108-1-1,..., 108-4-3; 208-1-2; 308-1,..., 308-6; 408-1-2, 408-3-2, 408-5-2; 508-1-2; 608-1-2) of the first component, wherein the first signal line of one or more other signal lines (106-1,..., 106-N; 206-2; 306-1,..., 306-6; 406-2, 406-4, 406-6; 506-2; 506-3; 606-2) adjacent to the first component is aligned in a first spiral pattern comprising a series of a number of shapes that spiral in a progressively decreasing manner around a center point on the first component.

12. The apparatus of claim 11, wherein the second node is an intermediate node that is part of the first signal line but not part of the first component.

13. The apparatus of claim 12, wherein the first node is a destination node for a signal transmitted on the first signal line.

14. The apparatus of claim 11, wherein the second node is part of a second component (104).

15. The apparatus of claim 14, wherein: the apparatus corresponds to a multi-layer controller; the first component corresponds to a via of a first layer; and the second component corresponds to a via of a second layer or a ball grid array (BGA) ball coupled between the second layer of the controller and a printed circuit board (PCB).

16. The apparatus of any of claims 14-15, wherein: the first component, the second component, or both correspond to a memory package, a controller package, or any combination thereof.

17. The apparatus of any of claims 11-14, further comprising: a second signal line (106-1,..., 106-N; 206-2; 306-1,..., 306-6; 406-2、406-4、406-6； 506-2; 506-3; 606-2) coupled between a third node (108-1-1,..., 108-4-3; 208-2-1; 308-1,..., 308-6; 408-2-1, 408-4-1, 408-6-1; 508-2-1; 608-2-1) and a fourth node (108-1-1,..., 108-4-3; 208-2-2; 308-1,..., 308-6; 408-2-2, 408-4-2, 408-6-2; 508-2-2; 608-2-2) of the second component, wherein the second signal line is aligned in a second spiral pattern comprising a series of a number of shapes that spiral in a progressively decreasing manner around a center point.

18. The apparatus of claim 17, wherein the second spiral pattern is interleaved with the first spiral pattern such that: a first line on a particular plane intersects a pattern on the particular plane resulting from projecting the second spiral pattern onto the particular plane, wherein the first line on the particular plane is between two points obtained by projecting the first node and the second node onto the particular plane; and a second line on the particular plane intersects a pattern on the particular plane resulting from projecting the first spiral pattern onto the particular plane, wherein the second line on the particular plane is between two points obtained by projecting the third node and the fourth node onto the particular plane.

19. The apparatus of claim 17, wherein the first spiral pattern and the second spiral pattern are interleaved such that: a first line on a particular plane intersects a pattern on the particular plane resulting from projecting the first spiral pattern onto the particular plane, wherein the first line on the particular plane is between two points obtained by projecting the first node and the second node onto the particular plane; and a second line on the particular plane intersects a pattern on the particular plane resulting from projecting the second spiral pattern onto the particular plane, wherein the second line on the particular plane is between two points obtained by projecting the third node and the fourth node onto the particular plane.

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