ESD protection device with snapback trigger mechanism and method of making the same

Abstract

The application relates to the technical field of semiconductors, and particularly discloses an ESD protection device with a folding trigger mechanism and a preparation method thereof. The method comprises a P-type substrate; an N-type well layer and a P-type well layer formed in the substrate; at least one P-type doped layer formed on the surface of the N-type well layer; at least one N-type doped layer formed on the surface of the P-type well layer; a third groove arranged between the N-type well layer and the P-type well layer; and a suspended electric field modulation structure arranged on the third groove. The application introduces the suspended electric field modulation structure, realizes dynamic electric field regulation of the SCR trigger process without increasing the device leakage and changing the main discharge path, and makes the device have low trigger voltage, moderate holding voltage, excellent large-current discharge capacity and good static reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an ESD protection device with a foldback trigger mechanism and a preparation method thereof. BACKGROUND

[0002] With the continuous shrinking of the process node of integrated circuits and the diversification of system operating voltage, the chip input / output port (I / O) puts forward higher requirements for electrostatic discharge (ESD) protection devices. On the one hand, the ESD protection device needs to withstand and discharge a large current electrostatic pulse in a very short time to prevent internal functional circuits from breakdown or thermal failure; on the other hand, in the normal working state, the ESD protection device must maintain a high resistance state to avoid excessive leakage current, thereby affecting the power consumption and reliability of the chip.

[0003] In the prior art, the commonly used ESD protection structure mainly includes GGNMOS (gate-grounded NMOS) devices and SCR (Silicon Controlled Rectifier) devices based on parasitic bipolar transistors. The GGNMOS device has simple structure and good process compatibility, but its trigger mechanism depends on the avalanche breakdown of the drain region, the trigger voltage is high, and the clamping voltage is large in the middle and high current discharge stage, which is difficult to meet the needs of middle and high working voltage or high reliability applications; at the same time, due to the parasitic effect of the MOS structure itself, its leakage current in the normal working state is relatively large.

[0004] SCR type ESD protection devices have strong current carrying capacity and low on-resistance, which can effectively protect the internal circuit in the large current discharge stage. However, the traditional SCR structure usually depends on the avalanche trigger of the parasitic PNP and NPN transistors by reverse bias of PN junction, and its trigger voltage is greatly affected by process parameters, and the trigger position is not easy to control accurately, which may cause the problem that the trigger voltage and holding voltage are difficult to balance in small size or low voltage process. In order to improve the trigger characteristics, some schemes introduce Zener diodes or gate control structures, but still mainly control through the change of current path or current injection mode, which is difficult to further reduce the trigger voltage while maintaining low leakage.

[0005] Therefore, how to effectively regulate the SCR trigger process without introducing additional direct current conduction path, so as to reduce the trigger voltage and improve the trigger consistency while maintaining low leakage and high current discharge capacity is the technical problem that the present application technical scheme wants to solve. SUMMARY

[0006] The present application aims to provide an ESD protection device with a foldback trigger mechanism and a preparation method thereof to solve the problems raised in the background art.

[0007] To achieve the above object, the present application provides the following technical solutions.

[0008] An ESD protection device with a foldback trigger mechanism, the device comprising:

[0009] A P-type substrate;

[0010] An N-type well layer and a P-type well layer formed in the substrate;

[0011] At least one P-type doped layer formed on the surface of the N-type well layer, and a first trench between the P-type doped layers;

[0012] At least one N-type doped layer formed on the surface of the P-type well layer, and a gate structure between the N-type doped layers;

[0013] A third trench arranged between the N-type well layer and the P-type well layer, and a floating field modulation structure arranged on the third trench; the floating field modulation structure is arranged at the junction layer domain of the N-type well layer and the P-type well layer, and the floating field modulation structure is electrically isolated from the substrate by a dielectric layer; the floating field modulation structure does not participate in any direct current or transient conduction path;

[0014] When an electrostatic discharge pulse is applied to the protection device, the floating field modulation structure applies additional field modulation to the junction layer domain under the action of a transient high electric field, so as to establish a conduction path for the electrostatic discharge current in a predetermined layer domain.

[0015] As a further scheme of the present application, the floating field modulation structure is a floating gate structure formed of a conductive material selected from one of polysilicon, metal and metal silicide; and the floating field modulation structure is displaced towards the junction layer domain under the action of an electrostatic discharge pulse.

[0016] As a further scheme of the present application, when the floating field modulation structure is displaced, the floating field modulation structure still maintains an electrically isolated state, and the floating field modulation structure does not make electrical contact with any conductive doped layer.

[0017] As a further scheme of the present application, the N-type well layer is provided with an N-type inner doped layer adjacent to one of the surface P-type doped layers, and the N-type inner doped layer is used to provide an initial breakdown point under the condition of electrostatic discharge; the dopant of the N-type inner doped layer is of the same type as the dopant of the N-type well layer, and the dopant concentration of the N-type inner doped layer is higher than the dopant concentration of the N-type well layer.

[0018] As a further scheme of the present application, the N-type doped layer in the N-type well layer and the P-type doped layer adjacent thereto jointly constitute a trigger structure, which is used to cooperatively reduce the trigger voltage under the action of the electric field of the floating field modulation structure.

[0019] As a further scheme of the present application: the N-type well layer and the P-type well layer and the corresponding doped layers form at least one parasitic bipolar transistor structure in the substrate, and the parasitic bipolar transistor structure constitutes a main discharge path in an electrostatic discharge state.

[0020] As a further scheme of the present application: the number of the suspended electric field modulation structures on the same chip is a preset value, when the number exceeds one, the suspended electric field modulation structure array is distributed, the initial displacement of different suspended electric field modulation structures is different, and the initial response characteristics of different suspended electric field modulation structures are determined by the suspended gap, material characteristics and geometric size thereof.

[0021] The present application also provides a preparation method of an ESD protection device with a folding trigger mechanism, the preparation method comprising:

[0022] Step S1: providing a P-type silicon substrate as a base of the device;

[0023] Step S2: forming an N-type well layer and a P-type well layer in the substrate by ion implantation and high-temperature driving process; wherein the N-type well layer and the P-type well layer are arranged adjacent to each other in the lateral direction and have opposite conductivity types, and a PN junction layer domain is formed at the interface thereof;

[0024] Step S3: forming a trench isolation structure on the surface of the N-type well layer and the P-type well layer by photolithography, etching and dielectric filling process;

[0025] Step S4: forming at least one P-type doped layer on the surface of the N-type well layer by ion implantation process, and performing annealing activation treatment;

[0026] Step S5: forming at least one N-type doped layer on the surface of the P-type well layer by ion implantation process, and performing annealing activation treatment;

[0027] Step S6: forming an N-type inner doped layer in the N-type well layer close to the interface layer domain by ion implantation;

[0028] Step S7: depositing a layer of dielectric material on the surface of the substrate containing the well layer, the conductive doped layer and the trench isolation structure as a lower dielectric layer of the subsequent suspended electric field modulation structure;

[0029] Step S8: depositing a layer of sacrificial layer material above the lower dielectric layer, and performing patterning treatment on the sacrificial layer by photolithography process so that the sacrificial layer is only reserved at the interface of the N-type well layer and the P-type well layer;

[0030] Step S9: depositing a conductive material above the sacrificial layer, and forming a suspended electric field modulation structure by photolithography and etching process;

[0031] Step S10: removing the sacrificial layer by a selective etching process to form a suspended gap between the dielectric layers under the suspended electric field modulation structure;

[0032] Step S11: depositing a dielectric encapsulation layer above the suspended electric field modulation structure for limiting the maximum displacement range of the suspended electric field modulation structure;

[0033] Step S12: connecting the P-type doped layer and the N-type doped layer to external electrodes respectively.

[0034] Compared with the prior art, the beneficial effects of the present application are: the present application introduces a suspended electric field modulation structure, realizes dynamic electric field regulation of the SCR triggering process without increasing the device leakage and changing the main discharge path, makes the device have low trigger voltage, moderate holding voltage, excellent large-current discharge capacity and good static reliability, and overcomes the technical defects that the existing GGNMOS and traditional SCR protection devices are difficult to balance between trigger voltage, leakage current and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application.

[0036] Figure 1 is a cross-sectional view of a traditional holding voltage SCR device.

[0037] Figure 2 is a first cross-sectional view of an ESD protection device with a foldback triggering mechanism.

[0038] Figure 3 is a first preparation flowchart of an ESD protection device with a foldback triggering mechanism.

[0039] Figure 4 is a second preparation flowchart of an ESD protection device with a foldback triggering mechanism.

[0040] In the figure: 1-P-type substrate, 2-N-type well layer, 3-P-type well layer, 4-first trench, 5-suspended electric field modulation structure, 6-second trench, 7-gate structure, 8-first P-type doped layer, 9-second P-type doped layer, 10-first N-type doped layer, 11-second N-type doped layer, 12-third P-type doped layer, 13-N-type internal doped layer, 14-third trench. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application and not to limit the present application.

[0042] Please refer to Figure 1 , Figure 1 is a cross-sectional view of a conventional hold voltage SCR device, in which an N-type inner doped layer 13 and a P-type doped layer (P+) above form a Zener diode, and a P+ / N well structure formed by a P+ implantation region connected to an electrical anode and an N well below forms a Zener trigger path of the device. A parasitic PNP transistor in the SCR is formed by the P+ implantation region connected to the electrical anode (equivalent to an emitter), the N well below the P+ implantation region connected to the electrical anode (equivalent to a base), and a P well (equivalent to a collector). A parasitic NPN transistor is formed by the N well (equivalent to a collector), the P well (equivalent to a base), and an N+ implantation region connected to an electrical cathode (equivalent to an emitter). When an ESD event occurs (a transient voltage appears), the anode potential will quickly rise, and when the sum of the forward bias voltage of the P+ / N well and the reverse bias voltage of the Zener diode is reached, the Zener trigger path is turned on. At this time, the base-emitter junction of the PNP transistor is forward biased, which turns on the PNP transistor. At the same time, the collector-emitter junction of the NPN transistor is reverse biased, and the emitter-base junction is forward biased, which turns on the NPN transistor. Finally, the PNP and NPN transistors form a positive feedback path to quickly discharge a large amount of ESD current. Embodiment 1

[0043] This embodiment provides an ESD protection device with a foldback trigger mechanism. Please refer to Figure 2 , which comprises:

[0044] a P-type substrate 1; the P-type substrate 1 serves as a base of the device, and is used to carry each well layer and doped structure, and to provide a longitudinal parasitic current path during ESD conduction;

[0045] an N-type well layer 2 and a P-type well layer 3 formed in the substrate; the N-type well layer 2 and the P-type well layer 3 are arranged laterally adjacent to each other in the substrate, and have opposite conductivity types, and form a PN junction region at the interface thereof;

[0046] at least one P-type doped layer formed on the surface of the N-type well layer 2; first grooves 4 are arranged between the P-type doped layers; the P-type doped layers include a first P-type doped layer 8 and a second P-type doped layer 9, and the first grooves 4 are also arranged between the first P-type doped layer 8 and the second P-type doped layer 9;

[0047] At least one N-type doped layer is formed on the surface of the P-type well layer 3, and a gate structure 7 is arranged between the N-type doped layers; the N-type doped layers include a first N-type doped layer 10 and a second N-type doped layer 11, and the gate structure 7 is arranged between the first N-type doped layer 10 and the second N-type doped layer 11;

[0048] At least one P-type doped layer is formed on the surface of the N-type well layer 2, and a trench is arranged between the P-type doped layers; at least one N-type doped layer is formed on the surface of the P-type well layer 3, and a trench is arranged between the N-type doped layers, and the trenches serve as isolation; in the above structure, the N-type well layer 2 forms a base region of a parasitic PNP transistor, the P-type well layer 3 forms a base region of a parasitic NPN transistor, and the two together form a core current channel region of the SCR; in combination with the doped layers, a current conducting path of the SCR can be formed; in addition, one of the P-type doped layers is connected to a device anode (I / O) and forms an anode diode with the N-type well layer 2; as for the N-type doped layer on the surface of the P-type well layer 3, two N-type doped layers form an auxiliary parasitic NPN transistor with the P-type well, and one of the N-type doped layers serves as a cathode end of a main discharge path of the SCR.

[0049] It is worth mentioning that the P-type doped layer actually further has a third P-type doped layer 12 connected to ground, the third P-type doped layer 12 is a ground well potential stabilizing region, forms a low-resistance ohmic contact with the P-type well layer, is used for stabilizing the potential of the P-type well in the electrostatic discharge and non-electrostatic discharge states, inhibiting excessive positive feedback of the parasitic bipolar transistor, preventing the device from entering a latch-up state, and reducing the leakage current of the device under normal working conditions, which is equivalent to providing a "potential discharge outlet" for the P-type well, limiting the overall drift speed and amplitude of the potential of the P-type well.

[0050] Preferably, the N-type well layer 2 and the P-type well layer 3 and the corresponding doped layers form at least one parasitic bipolar transistor structure in the substrate, and the parasitic bipolar transistor structure forms a main discharge path in the electrostatic discharge state.

[0051] As a preferred embodiment of the technical scheme of the present application, the N-type well layer 2 is provided with an N-type inner doped layer 13 adjacent to one of the surface P-type doped layers, and the N-type inner doped layer 13 is used for providing an initial breakdown point in the electrostatic discharge condition; the dopant of the N-type inner doped layer 13 is of the same type as the dopant of the N-type well layer 2, and the dopant concentration of the N-type inner doped layer 13 is higher than the dopant concentration of the N-type well layer 2; at this time, the N-type inner doped layer 13 and the P-type doped layer also form a diode, which is called a Zener diode, and serves as one of the main trigger ends of the SCR; as for the N-type inner doped layer 13, it is an N-type heavily doped region, and the filler used is the same, only the concentration is different; the N-type inner doped layer 13 and one of the P-type doped layers form a Zener diode, provide a stable low-voltage breakdown point in the initial stage of ESD, and are used for reducing Vtrip.

[0052] As a preferred embodiment of the technical scheme of the present application, the gate structure 7 is arranged between the N-type doped layers on the surface of the P-type well layer 3, at this time, the two N-type doped layers, the P-type well layer 3 and the gate structure 7 jointly form an NMOS transistor, which serves as an auxiliary discharge path under ESD condition, shunts a small current before the SCR is turned on, and reduces local heat concentration.

[0053] In addition, regarding the trench serving as an isolation function, the trench isolation structure is formed by an STI process, including: the first trench 4 for isolating two P-type doped layers, the second trench 6 for isolating an N-type doped layer and a P-type doped layer arranged at one end and grounded, and the third trench 14 for isolating the P-type doped layer and the N-type doped layer (corresponding to the junction of the P-type well region and the N-type well region).

[0054] In an example of the technical scheme of the present application, when the ESD voltage reaches the sum of the anode diode forward conduction voltage and the Zener breakdown voltage, the P-type doped layer, the N-type well layer 2 and the N-type inner doped layer 13 form a trigger path conduction, when the voltage is further increased, the P-type doped layer, the N-type well layer 2, the P-type well layer 3 and the N-type doped layer form an SCR structure conduction, and bear a large current ESD discharge; at the same time, the N-type doped layer, the P-type well layer 3 and another N-type doped layer form an auxiliary parasitic NPN transistor conduction, and play a shunt and heat buffering role.

[0055] As a preferred embodiment of the technical scheme of the present application, the third trench 14 is arranged between the N-type well layer 2 and the P-type well layer 3, and the suspended electric field modulation structure 5 is arranged on the third trench 14; the suspended electric field modulation structure 5 is arranged at the junction layer domain of the N-type well layer 2 and the P-type well layer 3, the suspended electric field modulation structure 5 is electrically isolated from the substrate through a dielectric layer, and the electric field modulation structure does not participate in any direct current or transient conduction path; when an electrostatic discharge pulse is applied to the protection device, the suspended electric field modulation structure 5 applies additional electric field modulation to the junction layer domain under the action of a transient high electric field, so as to establish a conduction path for the electrostatic discharge current in a predetermined layer domain.

[0056] In the technical solution of the present application, a new component, called suspended electric field modulation structure 5, is introduced on the silicon body surface above the third groove 14. It is an additional component of the silicon body surface, and can be compared with the gate structure 7, but their functions are completely different. The gate structure 7 is a standard structure, including gate oxide, gate electrode and clear channel control function. It is combined with two N-type doped layers and P-type well layer 3 to build a standard MOS gate structure 7, which modulates the channel region potential distribution through capacitive coupling under the condition of electrostatic discharge pulse, so as to control the avalanche breakdown position and reduce the triggering voltage of the device. The suspended electric field modulation structure 5 has no channel, no source drain and no DC bias, and does not form MOS. The suspended electric field modulation structure 5 is a conductive structure arranged above the junction region of the N-type well layer 2 and the P-type well layer 3. It is electrically isolated from the substrate through a dielectric layer (although it is not in contact with the substrate, it is not necessarily not conductive just because it is not in contact. Here, it is electrically isolated), and a suspended gap is formed below it, so that it is micro-displaced under the action of the transient high electric field generated by the electrostatic discharge pulse, thereby modulating the electric field distribution in the junction layer domain. The shape of the suspended electric field modulation structure 5 is usually strip-shaped (strip), cantilever-shaped (cantilever), and frame-shaped or U-shaped (covering the PN junction), which is essentially a "conductive film suspended by releasing the process through a sacrificial layer".

[0057] Further, regarding the junction layer domain, it specifically refers to the junction region between the N-type well layer 2 and the P-type well layer 3, which is a PN junction, including the depletion region on the N-well side, the depletion region on the P-well side, and the spatial region affected by the electric field. It is equivalent to the electric field sensitive region with spatial thickness formed around the PN junction. When ESD occurs, the PN junction is reverse biased, the depletion region expands to both sides, and the local electric field reaches a peak value near the junction. The suspended electric field modulation structure 5 superimposes a vertical component of the electric field above the region, which can change the equivalent breakdown condition.

[0058] As a preferred embodiment of the technical solution of the present application, the suspended electric field modulation structure 5 is not electrically connected with any doped layer or gate structure 7, and does not participate in the DC or transient conduction path of the device. Its action mechanism is based on electric field coupling rather than current conduction.

[0059] As a preferred embodiment of the technical solution of the present application, the suspended electric field modulation structure 5 is a suspended gate structure formed of a conductive material, and the material is selected from one of polysilicon, metal and metal silicide. It is displaced in the direction of the junction layer domain under the action of the electrostatic discharge pulse.

[0060] As a preferred embodiment of the technical solution of the present application, when the suspended electric field modulation structure 5 is displaced, the suspended electric field modulation structure 5 still maintains an electrically isolated state, and the suspended electric field modulation structure 5 does not electrically contact any conductive doped layer.

[0061] As a preferred embodiment of the technical scheme of the present application, the N-type doped layer in the N-type well layer 2 and the P-type doped layer adjacent thereto jointly constitute a trigger structure for cooperatively reducing a trigger voltage under the action of the electric field of the floating electric field modulation structure 5.

[0062] With the introduction of the floating electric field modulation structure 5, the working principle of the structure provided by the technical scheme of the present application is as follows:

[0063] In a static off state, the P-type substrate 1 and the N-type well region are in an isolated state, the main trigger gate of the gate structure 7 is not applied with a signal, the floating electric field modulation structure 5 is suspended above the trigger region, the device is in a high-resistance state, IR<100nA, and the N-type well region is isolated to suppress a parasitic channel. It should be noted that the floating electric field modulation structure 5 does not contact the silicon body and does not form a conductive path; when an ESD pulse exists, the main trigger gate of the gate structure 7 senses a signal, and an avalanche effect occurs at the junction of the P-type well region and the N-type well region. At this time, a parasitic PNP / NPN positive feedback and an SCR are turned on. The avalanche and the positive feedback jointly constitute a standard mechanism of a foldback trigger.

[0064] In cooperation with the above content, an ESD high voltage can cause the floating electric field modulation structure 5 to be displaced downward, the local electric field is enhanced, and Vtrip is reduced. However, in a normal state, the floating electric field modulation structure 5 is reset, which can suppress a false trigger condition. Embodiment 2

[0065] In an example of the technical scheme of the present application, the application of the floating electric field modulation structure 5 is extended. Since the floating electric field modulation structure 5 has a parameter, which is equivalent to a trigger voltage, and its structure is not complex, in actual application, multiple floating electric field modulation structures 5 can be built-in in the same chip, so that they can conduct in different degrees. Specifically, the number of the floating electric field modulation structures 5 on the same chip is a preset value. When the number exceeds one, the floating electric field modulation structures 5 are arrayed, the initial displacements of different floating electric field modulation structures 5 are different, and the initial response characteristics of different floating electric field modulation structures 5 are jointly determined by the floating gap, material characteristics and geometric size thereof.

[0066] The above scheme is based on the Gated-SCR structure of deep well isolation. On the basis of the traditional folded ESD protection path, multiple suspended active electric field modulation components are introduced. Through the displacement behavior of the suspended active electric field modulation components under ESD transient, the dynamic modulation of the trigger electric field and the trigger threshold is realized. At the same time, in the normal working state, high resistance isolation is maintained, so as to balance low leakage, high reliability and adjustable trigger characteristics. When there is no ESD stress and the device is in normal working state, an effective electrical isolation structure is formed between the P-type substrate 1 and the N-type well region. The SCR main conduction path between the anode side P+ region (P-type doped region) and the cathode side N+ region (N-type doped region) is not activated. The main trigger gate does not apply any bias signal, and the trigger region is in the off state. The suspended active electric field modulation component is arranged above the trigger region through the suspended structure, and there is an insulating gap between the suspended active electric field modulation component and the silicon surface, so that no ohmic contact or MOS conduction channel is formed. When the device pin is subjected to ESD pulse impact: the anode potential rises rapidly in a very short time, the main trigger gate and the trigger region potential are subjected to transient electric field coupling, the lightly doped trigger region located at the junction of the N-type well region and the P-type well region first bears high electric field, stress concentration leads to avalanche breakdown, and the avalanche generated carriers inject the parasitic NPN and PNP transistors. The two parasitic transistors form a positive feedback mechanism, and the SCR main conduction path is quickly established. At this time, the device changes from high resistance state to low resistance state, realizing folded conduction.

[0067] It should be noted that under the condition of ESD high voltage, in addition to the traditional SCR trigger mechanism, the active electric field modulation component also participates in the work. The ESD pulse generates a significant vertical electric field between the suspended active electric field modulation component and the silicon trigger region. The suspended active electric field modulation component is subjected to a small displacement downward under the action of electrostatic force. The equivalent distance between the suspended active electric field modulation component and the trigger region is reduced, resulting in a significant increase in local electric field strength. The avalanche condition of the trigger region is met in advance, thereby effectively reducing the transient trigger voltage Vtrip. In addition, multiple suspended active electric field modulation components can respond simultaneously or in groups to realize cooperative electric field modulation of the trigger region.

[0068] After the ESD event ends, the suspended active electric field modulation component resets under the action of its own mechanical restoring force, and the electric field of the trigger region returns to the initial state, thereby avoiding false triggering of the device under normal working conditions.

[0069] It should be noted that the concept of "displacement" in the above content actually describes an electric field phenomenon, not an actual spatial displacement. Its actual meaning is to produce effective deformation or equivalent position change under the action of electrostatic force, which is equivalent to the distance parameter and has an equivalent change. Example 3

[0070] Please refer to Figures 3-4The application provides a preparation method of an ESD protection device with a folding trigger mechanism.

[0071] Step S1: providing a P-type silicon substrate as a base of the device; the material of the P-type substrate 1 is monocrystalline silicon (Si), and the resistivity is 20 Ω·cm;

[0072] Step S2: forming an N-type well layer 2 and a P-type well layer 3 in the substrate through ion implantation and high-temperature driving processes; the N-type well layer 2 and the P-type well layer 3 are arranged adjacent to each other in the lateral direction and have opposite conductive types, and a PN junction layer domain is formed at the junction thereof; the annealing parameters of the well layer are 1100 ℃ and 4 h;

[0073] Step S3: forming a trench isolation structure on the surface of the N-type well layer 2 and the P-type well layer 3 through photolithography, etching and dielectric filling processes; the trench depth is 0.5 microns, and the trench width is 0.4 microns; the doping element of the N-type well layer 2 is P; and the doping element of the P-type well layer 3 is B;

[0074] Step S4: forming at least one P-type doping layer on the surface of the N-type well layer 2 through an ion implantation process and performing annealing activation treatment; the depth of the P-type doping layer is 0.3 microns, and the doping element is B;

[0075] Step S5: forming at least one N-type doping layer on the surface of the P-type well layer 3 through an ion implantation process and performing annealing activation treatment; the depth of the N-type doping layer is 0.3 microns, and the doping element is P;

[0076] Step S6: forming an N-type inner doping layer 13 in the N-type well layer 2 close to the junction layer domain through ion implantation; and the doping element is As;

[0077] Step S7: depositing a layer of dielectric material on the surface of the substrate containing the well layer, the conductive doping layer and the trench isolation structure as a lower dielectric layer of a subsequent suspended electric field modulation structure 5; the lower dielectric layer material comprises thermal oxygen SiO2, has a thickness of 10 nm and a temperature of 1000 ℃;

[0078] Step S8: depositing a layer of sacrificial layer material above the lower dielectric layer, performing patterning treatment on the sacrificial layer through a photolithography process, and making the sacrificial layer remain only at the junction of the N-type well layer 2 and the P-type well layer 3; the sacrificial layer material is PSG, has a thickness of 100 nm and a P content of 6 wt%, and is deposited by using an LPCVD method;

[0079] Step S9: depositing a conductive material above the sacrificial layer, and forming a suspended electric field modulation structure 5 through a photolithography and etching process; the conductive material is polycrystalline silicon, is deposited by using an LPCVD method, has a temperature of 600 ℃ and a thickness of 100 nm.

[0080] Step S10: remove the sacrificial layer by a selective etching process to form a suspended gap between the dielectric layers under the suspended electric field modulation structure 5; the etching process uses a wet HF process; the concentration of HF is 1%, and the time is 60s, forming a 100nm suspended gap;

[0081] Step S11: deposit a dielectric encapsulation layer above the suspended electric field modulation structure 5 for limiting the maximum displacement range of the suspended electric field modulation structure 5; the encapsulation layer material is SiN, and the encapsulation process uses PECVD, with a thickness of 200nm;

[0082] Step S12: connect the P-type doped layer and the N-type doped layer to external electrodes, respectively.

[0083] The device formed by the above steps has three layers in total:

[0084] The first layer: the silicon body structure layer (this is the "physical device"), from bottom to top, it is P-type substrate 1, N-type well layer 2, P-type well layer 3, well doped region, and trench isolation structure, wherein the PN junction layer domain is between the N-type well layer 2 and the P-type well layer 3, and the current path is also completely closed in this layer;

[0085] The second layer: dielectric isolation layer, on the surface of silicon: thermal oxygen, TEOS or high-k dielectric covers the entire well region and trench structure, at this time, the "conductive silicon body" and the "upper structure" are completely separated, preventing any direct current or transient electrical contact;

[0086] The third layer: suspended electric field modulation structure 5: polysilicon, metal or metal silicide, which is completely located on the silicon body, with a dielectric layer and a suspended gap between the silicon, covering only two-thirds of the junction layer domain in the vertical direction, without penetrating into the silicon body, nor inserting between the N-type well layer 2 and the P-type well layer 3. Example 4

[0087] Different from Example 3, the parameters of the suspended electric field modulation structure 5 are as follows:

[0088] Suspended material: TiN metal gate;

[0089] Suspended thickness: 50nm;

[0090] Suspended gap: 60nm;

[0091] Lower dielectric: HfO2, k value 30;

[0092] Lower dielectric thickness: 6nm;

[0093] Specific process parameters:

[0094] Specific process parameters:

[0095] Lower dielectric layer: HfO2, ALD, 300℃, thickness 6nm;

[0096] Sacrificial layer: PSG, LPCVD, thickness 60nm;

[0097] Suspension structure: TiN, PVD, thickness 50nm;

[0098] Release: 0.5%HF, 45s;

[0099] Encapsulation layer: SiN, PECVD, thickness 150nm;

[0100] The difference between the above scheme and example 3 is that high-k dielectric is used, the electric field concentration ability is increased, the gap is reduced, the electrostatic force is larger, the displacement occurs earlier, in addition, the metal TiN has stronger capacitive coupling. Example 5

[0101] Different from example 3, the parameters of the suspension type electric field modulation structure 5 are as follows:

[0102] Suspension material: lightly doped Poly-Si (1×10¹ 8 cm⁻³);

[0103] Suspension thickness: 150nm;

[0104] Suspension gap: 150nm;

[0105] Lower dielectric: SiO2;

[0106] Lower dielectric thickness: 15nm.

[0107] The difference between the above scheme and example 3 is that the suspension mass is increased, the displacement threshold value and the gap are increased, and the static stability is better, which is suitable for high noise environment.

[0108] Comparative example 1: using traditional GGNMOS device.

[0109] Comparative example 2: using traditional hold voltage SCR device.

[0110] The above examples 3 to 5, comparative examples 1 and 2 are tested, the testing means adopts conventional testing means, the same for different examples, the test items and test results are as follows:

[0111] Experimental data table:

[0112] Parameters Example 3 Example 4 Example 5 Comparative Example 1 Comparative Example 2 VR 3.3V 3.3V 3.3V 3.3V 5.0V IR 50 nA 100 nA 20 nA 1.6 μA 100 nA Vbr(min) 5.2V 4.7V 5.8V 8.0V 7.0V Vtrip 5.5V 5.0V 6.3V 8.0V 7.0V Vc@1A(TLP) 1.8V 1.6V 2.1V 3.2V 2.8V VcTyp@4A(TLP) 2.5V 2.2V 2.7V 4.6V 2.4V Cj 0.28 pF 0.32 pF 0.24 pF 0.5 pF 0.38 pF

[0113] From the above experimental data, it can be seen that the comparative example 1 adopts the traditional GGNMOS structure, and its triggering mechanism depends on the avalanche breakdown of the drain region. When the device is subjected to an electrostatic discharge pulse, it will only be turned on when the drain junction voltage reaches a high avalanche voltage, resulting in a high minimum breakdown voltage Vbr, and the clamping voltage is significantly high in the medium and low current stage. At the same time, due to the channel leakage and gate-induced leakage of the MOS structure itself, the leakage current IR of the device in the normal working state is large, which is not conducive to low-power circuit applications.

[0114] The comparative example 2 adopts the traditional SCR protection structure, which has certain advantages in terms of large current discharge capability, but its triggering process mainly depends on the PN junction reverse bias avalanche and the natural positive feedback of the parasitic bipolar transistor, and lacks active means to control the triggering electric field distribution. Therefore, its minimum breakdown voltage Vbr is still at a high level, and the triggering consistency is greatly affected by process fluctuations.

[0115] In contrast, the embodiment 3 introduces a suspended electric field modulation structure 5 above the junction region of the N-type well layer 2 and the P-type well layer 3 based on the traditional folded SCR structure. The suspended electric field modulation structure 5 is electrically isolated from the silicon body by a dielectric layer and does not participate in any direct current or transient conduction path. Its mechanism is based on transient electric field coupling. When an electrostatic discharge pulse is applied, the electric field in the junction region increases rapidly, and the suspended electric field modulation structure 5 undergoes a small displacement under the action of electrostatic force, thereby further concentrating the local electric field in the PN junction region, making the avalanche condition meet in advance, and thus reducing the triggering voltage Vtrip and the minimum breakdown voltage Vbr of the device. After the SCR is turned on, the main discharge path is completely taken over by the parasitic PNP / NPN structure inside the silicon body, so it maintains a low on-resistance and stable clamping voltage during the large current discharge stage.

[0116] The embodiment 4 further uses a high dielectric constant dielectric as the lower dielectric layer of the suspended electric field modulation structure 5 and reduces the suspended gap based on the embodiment 3, thereby significantly enhancing the capacitive coupling effect between the suspended structure and the junction region. Under the same electrostatic stress conditions, the suspended electric field modulation structure 5 can produce effective electric field modulation effect at a lower applied voltage, further enhancing the electric field concentration effect in the triggering region, so the embodiment 4 exhibits a lower triggering voltage and clamping voltage in the medium and low current stage, and is suitable for low-voltage I / O scenarios with higher ESD triggering sensitivity requirements.

[0117] The embodiment 5 increases the thickness of the suspended electric field modulation structure 5 and the suspended gap, and uses a material combination with relatively low electric field modulation strength, so that the suspended structure has higher mechanical and electrical stability in static and noise environments. This structure maintains the suspended electric field modulation effect while moderately increasing the triggering threshold, thereby effectively suppressing false triggering, and is suitable for application scenarios with higher stability and reliability requirements.

[0118] It should be noted that the above experimental data, in addition to the high and low, it actually has a hidden information, that is, the material of the suspension type electric field modulation structure 5 itself can affect the corresponding technical parameters, and the suspension type electric field modulation structure 5 itself is an accessory with low installation difficulty, in actual application, different material size suspension type electric field modulation structure 5 can be installed on the same chip, thereby forming a gradient ESD release architecture, when multiple suspension type electric field modulation structures 5 are arranged in the ESD protection unit of the same chip, and the structures have differences in material, thickness or suspension gap, a gradient triggering and release mechanism is naturally formed, and the working process is as follows:

[0119] In the initial stage of the ESD pulse (low to medium electric field), the suspension type electric field modulation structure 5 (such as metal material, smaller gap) most sensitive to the electric field is first displaced; the local interface layer domain electric field is enhanced in advance; the corresponding region of the SCR or trigger path is first turned on, and part of the ESD energy is released.

[0120] In the enhanced stage of the ESD pulse (higher electric field), the suspension type electric field modulation structure 5 (such as thick polysilicon, larger gap) with higher trigger threshold is sequentially involved in the modulation; more trigger regions are activated; the discharge path is expanded from local to distributed.

[0121] High current discharge stage: multiple SCR discharge channels are in low resistance conduction state at the same time, and the ESD current is dispersed in space, avoiding single hot spot or current congestion; this behavior essentially forms an "electric field driven, logic control free, physical adaptive hierarchical trigger network", which does not need to introduce control circuit, in fact, the device itself cannot introduce additional circuit.

[0122] The above only describes the preferred embodiment of the present application, and does not limit the present application, any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An ESD protection device with a foldback triggering mechanism, characterized in that, The device includes: A P-type substrate; An N-type well layer and a P-type well layer are formed in the substrate; the N-type well layer and the P-type well layer are arranged adjacent to each other in the lateral direction and have opposite conductivity types, forming a PN junction layer domain at their junction; At least two P-type doped layers are formed on the surface of the N-type well layer; a first trench is provided between the P-type doped layers; the first trench is an isolation trench; At least two N-type doped layers are formed on the surface of the P-type well layer; a gate structure is provided between the N-type doped layers; A third trench is disposed between an N-type well layer and a P-type well layer, and a suspended electric field modulation structure is disposed on the third trench; the suspended electric field modulation structure is disposed at the interface region between the N-type well layer and the P-type well layer, and the suspended electric field modulation structure is electrically isolated from the substrate through a dielectric layer, and the electric field modulation structure does not participate in any DC or transient conduction path; the third trench is an isolation trench and is not a through structure, and the electric field modulation structure is made of a conductive material; When an electrostatic discharge pulse is applied to the protection device, the suspended electric field modulation structure applies an additional electric field modulation to the boundary layer under the action of a transient high electric field, so that the electrostatic discharge current establishes a conduction path within the predetermined layer.

2. The ESD protection device with a foldback triggering mechanism according to claim 1, characterized in that, The suspended electric field modulation structure is a suspended gate structure formed of conductive material, which is selected from polycrystalline silicon, metal and metal silicide; under the action of electrostatic discharge pulse, it is displaced in the direction of the interface layer domain.

3. The ESD protection device with a foldback triggering mechanism according to claim 2, characterized in that, When the suspended electric field modulation structure is displaced, it remains electrically isolated and does not come into electrical contact with any conductive doped layer.

4. The ESD protection device with a foldback triggering mechanism according to claim 1, characterized in that, The N-type well layer has an N-type inner doped layer adjacent to one of the surface P-type doped layers. The N-type inner doped layer is used to provide an initial breakdown point under electrostatic discharge conditions. The dopant in the N-type inner doped layer is of the same type as the dopant in the N-type well layer, and the dopant concentration in the N-type inner doped layer is higher than that in the N-type well layer.

5. The ESD protection device with a foldback triggering mechanism according to claim 1, characterized in that, The N-type doped layer in the N-type well layer and its adjacent P-type doped layer together form a trigger structure, which is used to synergistically reduce the trigger voltage under the electric field of the suspended electric field modulation structure.

6. The ESD protection device with a foldback triggering mechanism according to claim 1, characterized in that, The N-type well layer, the P-type well layer, and the corresponding doped layer form at least one parasitic bipolar transistor structure in the substrate, and the parasitic bipolar transistor structure constitutes the main discharge path under electrostatic discharge conditions.

7. The ESD protection device with a foldback triggering mechanism according to claim 6, characterized in that, The number of the suspended electric field modulation structures on the same chip is a preset value. When the number exceeds one, the suspended electric field modulation structures are distributed in an array. The initial displacements of different suspended electric field modulation structures are different. The initial response characteristics of different suspended electric field modulation structures are determined by their suspension gap, material properties and geometric dimensions.

8. A method for fabricating an ESD protection device with a foldback triggering mechanism as described in any one of claims 1 to 7, characterized in that, The preparation method includes: Step S1: Provide a P-type silicon substrate as the substrate for the device; Step S2: In the substrate, an N-type well layer and a P-type well layer are formed by ion implantation and high-temperature driving process; wherein the N-type well layer and the P-type well layer are arranged adjacent to each other in the lateral direction and have opposite conductivity types, and a PN junction layer domain is formed at their junction. Step S3: On the surfaces of the N-type well layer and the P-type well layer, a trench isolation structure is formed by photolithography, etching and dielectric filling processes; the trench isolation structure includes a first trench on the N-type well layer, a second trench on the P-type well layer, and a third trench disposed between the N-type well layer and the P-type well layer, the third trench is not a through structure; Step S4: On the surface of the N-type well layer, at least two P-type doped layers are formed by ion implantation and then annealed for activation. Step S5: On the surface of the P-type well layer, at least two N-type doped layers are formed by ion implantation and then annealed for activation. Step S6: An N-type inner doped layer is formed by ion implantation at a position near the boundary layer region within the N-type well layer; the N-type inner doped layer is directly below one of the P-type doped layers and in contact with the P-type doped layer directly above it; Step S7: Deposit a dielectric material on the substrate surface containing the well layer, conductive doped layer and trench isolation structure as the lower dielectric layer of the subsequent floating electric field modulation structure; Step S8: Deposit a sacrificial layer material above the lower dielectric layer, and pattern the sacrificial layer using photolithography so that it is only retained above the junction of the N-type well layer and the P-type well layer; Step S9: Deposit conductive material above the sacrificial layer, and form a suspended electric field modulation structure by photolithography and etching processes; the suspended electric field modulation structure is a conductive structure disposed above the junction region of the N-type well layer and the P-type well layer, and is electrically isolated from the substrate through a dielectric layer. Step S10: Remove the sacrificial layer by selective etching process to form a floating gap between the floating electric field modulation structure and the lower dielectric layer; Step S11: Deposit a dielectric encapsulation layer above the suspended electric field modulation structure to limit the maximum displacement range of the suspended electric field modulation structure; Step S12: Connect the P-type doped layer and the N-type doped layer to the external electrode respectively.

Images