Tunneling field effect transistor with vertical channel, preparation method of tunneling field effect transistor and electronic equipment

Abstract

The invention provides a tunneling field effect transistor with a vertical channel, a preparation method of the tunneling field effect transistor and electronic equipment. The transistor comprises a substrate, a first source-drain layer, a channel layer and a second source-drain layer, a first transverse groove surrounding the first channel region and a second transverse groove surrounding the second channel region are formed between the first source-drain layer and the second source-drain layer; a gate dielectric layer; and a gate layer including a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction. According to the invention, the tunneling field effect transistor with the vertical channel is realized, the area occupied by the device in the horizontal direction is reduced, and the density of the device is improved; and meanwhile, the control effect on the tunneling effect of the channel layer is improved by utilizing the ring gate design, the first channel region and the second channel region are combined, the preparation of the channel with the controllable length is realized, meanwhile, self-alignment during the preparation of the gate layer is formed, the requirement of the device on a photoetching process is effectively reduced, and the performance of the device is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and in particular to a vertical channel tunneling field-effect transistor, its fabrication method, and electronic devices. Background Technology

[0002] In the ongoing pursuit of high integration and low power consumption in semiconductor technology, metal-oxide-semiconductor field-effect transistors (MOSFETs) have been limited by thermodynamic constraints, making it difficult to break through the 60mV / decade subthreshold swing, resulting in persistently high power consumption. Tunneling field-effect transistors (TFETs), on the other hand, utilize the quantum tunneling mechanism to achieve a subthreshold swing below 60mV / decade, significantly reducing operating voltage and static power consumption, thus becoming one of the key technologies for continuing Moore's Law.

[0003] However, existing horizontal channel TFETs have significant disadvantages. Their channel direction is parallel to the substrate, which limits the effective channel length due to the photolithography process, making it difficult to further shrink. At the same time, the parasitic capacitance in the source and drain regions is large, affecting the switching speed. Furthermore, the interband tunneling area under the horizontal structure is limited, which restricts the improvement of the drive current. Summary of the Invention

[0004] The purpose of this disclosure is to provide a vertical channel tunneling field-effect transistor, its fabrication method, and an electronic device, in order to solve the problems existing in the prior art.

[0005] The embodiments of this disclosure employ the following technical solution: a vertical channel tunneling field-effect transistor, comprising: a substrate; a first source / drain layer, a channel layer, and a second source / drain layer sequentially stacked on the surface of the substrate; wherein the outer periphery of the orthographic projection of the second source / drain layer on the substrate is located within the orthographic projection of the first source / drain layer on the substrate, the channel layer includes a first channel region and a second channel region that are not connected to each other, the orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the second source / drain layer, so that a first lateral groove surrounding the first channel region and a second lateral groove surrounding the second channel region are formed between the first source / drain layer and the second source / drain layer; a gate dielectric layer, the gate dielectric layer covering the surfaces of the first source / drain layer, the second source / drain layer, the first lateral groove, and the second lateral groove; a gate layer, the gate layer including a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction, the first gate region covering a portion of the upper surface of the second source / drain layer, the second gate region completely filling the first lateral groove and the second lateral groove, and extending to the upper surface of the second source / drain layer and connecting with the first gate region.

[0006] In some embodiments, the first channel region and the second channel region are disposed along a first direction; the first gate region includes a horizontal extension extending along the first direction and a first extension and a second extension extending along a second direction, wherein the second direction and the first direction are perpendicular to each other in a horizontal plane parallel to the surface of the substrate, one end of the first extension is connected to one end of the horizontal extension, one end of the second extension is connected to the other end of the horizontal extension, the orthographic projection of the first extension on the substrate completely covers the orthographic projection of the first channel region on the substrate, the orthographic projection of the second extension on the substrate covers the orthographic projection of the second channel region on the substrate, and there is a gap region between the orthographic projection of the first extension on the substrate and the orthographic projection of the second extension on the substrate.

[0007] In some embodiments, the device further includes: an insulating layer covering the substrate and all layers disposed on the substrate; and lead-out electrodes including a first source-drain lead-out electrode, a second source-drain lead-out electrode, and a gate lead-out electrode that are mutually insulated from each other, wherein the first source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the first source-drain layer, and the second source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the second source-drain layer.

[0008] In some embodiments, the gate layer and the lead-out electrode are made of any one of tungsten, titanium nitride, or a stacked material of tungsten and titanium nitride.

[0009] In some embodiments, the first source / drain layer is made of a semiconductor material of a first doping type, and the second source / drain layer is made of a semiconductor material of a second doping type; the semiconductor material is any one of silicon, germanium, germanium-silicon, and gallium arsenide.

[0010] This disclosure also provides a method for fabricating a vertical channel tunneling field-effect transistor, comprising: providing a substrate; sequentially fabricating a first source / drain layer, a channel layer, and a second source / drain layer on the surface of the substrate; wherein the outer periphery of the orthographic projection of the second source / drain layer on the substrate is located within the orthographic projection of the first source / drain layer on the substrate, the channel layer includes a first channel region and a second channel region that are not connected to each other, and the orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the second source / drain layer, so that a first lateral groove is formed between the first source / drain layer and the second source / drain layer surrounding the first channel region and surrounding the second channel region. The second lateral groove of the second channel region is described; a gate dielectric layer is grown on the exposed surfaces of the first source / drain layer, the second source / drain layer, the first lateral groove, and the second lateral groove; a gate material layer is grown on the surface of the gate dielectric layer, and the gate material layer is patterned and etched to form a gate layer; the gate layer includes a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction, the first gate region covers a portion of the upper surface of the second source / drain layer, the second gate region completely fills the first lateral groove and the second lateral groove, and extends to the upper surface of the second source / drain layer and connects with the first gate region.

[0011] In some embodiments, the step of sequentially fabricating a first source / drain layer, a channel layer, and a second source / drain layer on the surface of the substrate includes: growing a semiconductor material of a first doped type on the surface of the substrate to form the first source / drain layer; fabricating an insulating material layer on the surface of the first source / drain layer away from the substrate; etching the insulating material layer to form a first via and a second via penetrating the insulating material layer, the first via and the second via being formed along a first direction; filling the first via and the second via with a channel material; planarizing the surface of the channel material away from the substrate so that the surface of the channel material away from the substrate is flush with the surface of the insulating material layer away from the substrate; growing a semiconductor material of a second doped type on the surface of the insulating material layer away from the substrate; patterning the second doped semiconductor material to form the second source / drain layer; and removing the insulating material layer to form the channel layer having a first channel region and a second channel region.

[0012] In some embodiments, patterning the gate material layer to form a gate layer includes: patterning the gate material layer to form a first gate region and a second gate region; the first gate region includes a horizontal extension extending along a first direction and a first extension and a second extension extending along a second direction, wherein the second direction and the first direction are perpendicular to each other in a horizontal plane parallel to the surface of the substrate, one end of the first extension is connected to one end of the horizontal extension, one end of the second extension is connected to the other end of the horizontal extension, the orthographic projection of the first extension on the substrate completely covers the orthographic projection of the first channel region on the substrate, the orthographic projection of the second extension on the substrate covers the orthographic projection of the second channel region on the substrate, and there is a gap region between the orthographic projection of the first extension on the substrate and the orthographic projection of the second extension on the substrate.

[0013] In some embodiments, after patterning the gate material layer to form a gate layer, the method further includes: preparing an insulating layer to cover the substrate and all layers disposed on the substrate; performing via etching on the insulating layer and preparing lead-out electrodes; the lead-out electrodes include a first source / drain lead-out electrode, a second source / drain lead-out electrode, and a gate lead-out electrode that are mutually insulated, wherein the first source / drain lead-out electrode penetrates the insulating layer and is electrically connected to the first source / drain layer, and the second source / drain lead-out electrode penetrates the insulating layer and is electrically connected to the second source / drain layer.

[0014] This disclosure also provides an electronic device that includes at least a vertical channel tunneling field-effect transistor as described above.

[0015] The beneficial effects of the embodiments disclosed herein are as follows: a tunneling field-effect transistor with a vertical channel is designed and implemented, which reduces the area occupied by the device in the horizontal direction and improves the device density; at the same time, the control effect of tunneling effect of the channel layer is improved by using a ring gate design, and by combining the vertical first channel region and the second channel region, the self-alignment of the gate layer is formed while the channel with controllable length is fabricated, which effectively reduces the device's requirements for photolithography process and improves the device's performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a cross-sectional hierarchical structure diagram of the tunneling field-effect transistor with a vertical channel along a first direction in the first embodiment of this disclosure; Figure 2 for Figure 1 Hierarchical structure diagram of the cross section at point B (middle dashed line); Figure 3 for Figure 1 Hierarchical structure diagram of the cross section at point B' (middle dashed line); Figure 4 for Figure 1 A top view of a tunneling field-effect transistor with a vertical channel. Figure 5 This is a flowchart illustrating the fabrication method of the vertical channel tunneling field-effect transistor in the second embodiment of this disclosure; Figures 6 to 27 This is a schematic diagram of the hierarchical structure at different steps during the preparation process in the second embodiment of this disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0019] In the ongoing pursuit of high integration and low power consumption in semiconductor technology, traditional MOSFETs, limited by thermodynamic constraints, struggle to break through the 60mV / decade subthreshold swing, resulting in persistently high power consumption. Tunneling field-effect transistors (TFETs), leveraging the quantum tunneling mechanism, can significantly reduce operating voltage and static power consumption, becoming a key technology for extending Moore's Law. However, existing horizontal channel TFETs have significant disadvantages: their channel direction is parallel to the substrate, limiting the effective channel length to be further miniaturized by photolithography processes; simultaneously, the large parasitic capacitance in the source and drain regions affects switching speed; and the limited inter-band tunneling area under the horizontal structure restricts the improvement of drive current.

[0020] To address the aforementioned problems, the first embodiment of this disclosure provides a vertical channel tunneling field-effect transistor, the device hierarchy of which is shown in the figure below. Figures 1 to 4 As shown, where, Figure 1 This is a cross-sectional hierarchical structure diagram of the transistor along the first direction. Figure 2 for Figure 1 Hierarchical structure diagram of the cross section at point B (dashed line). Figure 3 for Figure 1 Hierarchical structure diagram of the cross section at point B' (middle dashed line). Figure 4 This is a top view of a transistor.

[0021] like Figures 1 to 3 As shown, the tunneling field-effect transistor of this embodiment mainly includes a substrate 10, in Figure 1 and Figure 2 In the substrate 10, a silicon substrate (Si), a trap layer (well), and a germanium material layer (Ge) are stacked sequentially from bottom to top. A first source / drain layer 20, a channel layer 30, and a second source / drain layer 40 are sequentially disposed on one side surface of the substrate 10. The outer periphery of the orthographic projection of the second source / drain layer 40 onto the substrate lies within the orthographic projection of the first source / drain layer 20 onto the substrate. The channel layer 30 includes a first channel region 31 and a second channel region 32 that are not connected to each other. The orthographic projections of the first channel region 31 and the second channel region 32 onto the substrate both lie within the orthographic projection of the second source / drain layer 40, thereby forming a first lateral groove around the first channel region 31 between the first source / drain layer 20 and the second source / drain layer 40. A second lateral groove surrounds the second channel region 32; a gate dielectric layer 50 covers the surfaces of the first source / drain layer 20, the second source / drain layer 40, the first lateral groove, and the second lateral groove, for achieving insulation isolation between the gate layer 60 and the channel region 30; the gate layer 60 includes a first gate region 61 parallel to the surface of the substrate and a second gate region 62 extending in a vertical direction. The first gate region 61 covers a portion of the upper surface of the second source / drain layer, and the second gate region 62 completely fills the first and second lateral grooves, extending to the upper surface of the second source / drain layer 40 and connecting with the first gate region 61 to form a complete gate layer 60. In some embodiments, the end of the second gate region 62 near the substrate 10 may also extend horizontally, so that its orthographic projection covers a portion of the orthographic projection of the first source / drain layer 20, facilitating subsequent electrode lead-out.

[0022] It is important to note that, such as Figures 1 to 3 As shown, the substrate 10 and the gate dielectric layer 50 in this embodiment also include a gray shallow trench isolation (STI), which is actually used to achieve the insulation and isolation between different transistors during the fabrication process. Since multiple transistors can be fabricated on the same substrate at the same time, and the same process steps are applied to all transistors at the same time during the process, the shallow trench isolation (STI) is used to achieve the separation and insulation of independent transistors during the fabrication process.

[0023] Further according to Figure 4As can be seen from the schematic diagram, in this embodiment, the first channel region 31 and the second channel region 32 are disposed along the first direction X. The first gate region 61 includes a horizontal extension 610 extending along the first direction X and a first extension 611 and a second extension 612 extending along the second direction Y. One end of the first extension 611 is connected to one end of the horizontal extension 610, and one end of the second extension 612 is connected to the other end of the horizontal extension 610. In this embodiment, the second direction Y and the first direction X are perpendicular to each other in a horizontal plane parallel to the surface of the substrate 10, so that the gate layer 60 presents a "U" shape in this horizontal plane. Simultaneously combined with... Figure 1 and Figure 2 The orthographic projection of the first extension 611 onto the substrate completely covers the orthographic projection of the first channel region 31 onto the substrate, and the orthographic projection of the second extension 612 onto the substrate covers the orthographic projection of the second channel region 32 onto the substrate. Furthermore, there is a gap region 613 between the orthographic projections of the first extension 611 and the second extension 612 onto the substrate. This embodiment utilizes a patterned gate layer, which, while enabling control of the channel layer, facilitates the extraction of the second source / drain layer and the gate layer, effectively simplifying the device structure and subsequent fabrication processes.

[0024] at the same time, Figures 1 to 3 The device hierarchy structure also includes an insulating layer 70 and various lead-out electrodes. The insulating layer 70 covers the substrate and all layers disposed on the substrate to protect and insulate the device structure. The lead-out electrodes mainly include a first source-drain lead-out electrode 81, a second source-drain lead-out electrode 82, and a gate lead-out electrode 83, which are mutually insulated. The first source-drain lead-out electrode 81 penetrates the insulating layer 70 and is electrically connected to the first source-drain layer 20. The second source-drain lead-out electrode 82 penetrates the insulating layer 70 and is electrically connected to the second source-drain layer 40. In addition, the lead-out electrodes also include a trap layer lead-out electrode 84 that penetrates the insulating layer and the gate dielectric layer and is electrically connected to the trap layer well.

[0025] In some embodiments, the first source / drain layer 20 is made of a semiconductor material of a first doping type, and the second source / drain layer 40 is made of a semiconductor material of a second doping type. The semiconductor material can be any one of silicon, germanium, germanium-silicon, or gallium arsenide. In this embodiment, gallium arsenide (GaAs) is selected as the semiconductor material. The first doping type semiconductor material is P-type doped gallium arsenide (GaAs), and the second doping type semiconductor material is N-type doped gallium arsenide (GaAs). The channel layer is an intrinsic semiconductor material, gallium arsenide (GaAs). Additionally, the gate layer and the lead-out electrode can be made of tungsten (W), titanium nitride (TiN), or a stack of both. Other materials with conductive properties can also be used. This embodiment does not impose specific limitations.

[0026] It should be noted that the thickness, width, length and other dimensions of each layer shown in this embodiment are for illustrative purposes only and are used to indicate the positional relationship between layers. They do not represent the actual thickness, width, length and other dimensions of the layers during actual fabrication.

[0027] This embodiment designs and implements a tunneling field-effect transistor with a vertical channel, which reduces the area occupied by the device in the horizontal direction and improves the device density. At the same time, the ring gate design improves the control of the tunneling effect of the channel layer, and combined with the vertical first channel region and second channel region, it realizes the self-alignment of the gate layer during the fabrication of the channel with controllable length, effectively reducing the device's requirements for photolithography process and improving the device's performance.

[0028] Based on the same inventive concept, the second embodiment of this disclosure provides a method for fabricating a vertical channel tunneling field-effect transistor, the flowchart of which is shown below. Figure 5 As shown, Figures 6 to 27 This is a schematic diagram of the hierarchical structure at different steps in the preparation process.

[0029] S1 provides a substrate; the substrate is a stacked structure consisting of a silicon substrate (Si), a trap layer (well), and a germanium material layer (Ge).

[0030] S2, a first source / drain layer, a channel layer, and a second source / drain layer are sequentially prepared on the surface of a substrate; wherein, the outer periphery of the orthographic projection of the second source / drain layer on the substrate is located within the orthographic projection of the first source / drain layer on the substrate, and the channel layer includes a first channel region and a second channel region that are not connected to each other, and the orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the second source / drain layer, so that a first lateral groove surrounding the first channel region and a second lateral groove surrounding the second channel region are formed between the first source / drain layer and the second source / drain layer.

[0031] In practice, the first source / drain layer, the channel layer, and the second source / drain layer can be fabricated according to the following steps: S21, a first-doped semiconductor material is grown on the surface of the substrate to form a first source / drain layer; forming a first source / drain layer. Figure 6 The hierarchical structure shown in this embodiment indicates that the first doping type of semiconductor material can be P-type doped GaAs. S22, an insulating material layer is prepared on the surface of the first source / drain layer away from the substrate, such as... Figure 7 As shown, the insulating material layer is then etched to form a first through-hole H1 and a second through-hole H2 penetrating the insulating material layer. The first through-hole H1 and the second through-hole H2 are formed along a first direction, as shown. Figure 8 and Figure 9 As shown, where Figure 9 This is a top view of the current hierarchical structure; the insulating material in this embodiment is silicon dioxide (SiO2). S23, fill the first and second through holes with channel material, and planarize the surface of the channel material away from the substrate so that the surface of the channel material away from the substrate is flush with the surface of the insulating material layer away from the substrate; such as Figure 10 As shown, the channel material in this embodiment is intrinsic GaAs (corresponding to i GaAs in the figure). S24, a second type of doped semiconductor material is grown on the surface of the insulating material layer away from the substrate, and the two semiconductor materials with different doping types are patterned to form a second source / drain layer and a first source / drain layer with steps; as shown Figures 11 to 13 As shown, the second doping type of semiconductor material in this embodiment is N-type doped GaAs; S25, the insulating material layer is removed to form a trench layer having a first trench region and a second trench region, such as Figures 14 to 15 As shown.

[0032] In some embodiments, after step S2 is performed, a step of shallow trench isolation of the above-mentioned levels is further included, such as... Figures 16 to 19 As shown, shallow trench isolation (STI) is used to achieve isolation of the first source and drain regions of different transistors.

[0033] S3, a gate dielectric layer is grown on the exposed surfaces of the first source / drain layer, the second source / drain layer, the first lateral groove, and the second lateral groove. In this embodiment, the gate dielectric layer can be made of HfO material. S4, a gate material layer is grown on the surface of the gate dielectric layer, and the gate material layer is patterned and etched to form a gate layer; the gate layer includes a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction. The first gate region covers part of the upper surface of the second source / drain layer, and the second gate region completely fills the first lateral groove and the second lateral groove, and extends to the upper surface of the second source / drain layer and connects with the first gate region. In this embodiment, the gate layer is made of a stacked material of tungsten (W) and titanium nitride (TiN), which is represented in the figure by the same layer filled with oblique shading.

[0034] Specifically, Figures 20 to 22 This diagram illustrates the layer hierarchy after the gate dielectric layer and gate material layer have been grown. Figures 23 to 25The diagram shows a layer hierarchy after patterning etching of the gate material layer. The first gate region includes a horizontal extension extending along a first direction and a first extension and a second extension extending along a second direction. The second direction and the first direction are perpendicular to each other in a horizontal plane parallel to the surface of the substrate. One end of the first extension is connected to one end of the horizontal extension, and one end of the second extension is connected to the other end of the horizontal extension. The orthographic projection of the first extension on the substrate completely covers the orthographic projection of the first channel region on the substrate. The orthographic projection of the second extension on the substrate covers the orthographic projection of the second channel region on the substrate. There is a gap between the orthographic projections of the first extension on the substrate and the orthographic projections of the second extension on the substrate.

[0035] In some embodiments, the fabrication process further includes fabricating an insulating layer and lead-out electrodes. Figure 26 and Figure 27 The layer structure after the insulating layer is prepared is shown, that is, the substrate and all layers disposed on the substrate are covered by the insulating layer; then the insulating layer is etched with vias and the lead-out electrodes are prepared; the lead-out electrodes include a first source-drain lead-out electrode, a second source-drain lead-out electrode and a gate lead-out electrode that are insulated from each other, wherein the first source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the first source-drain layer, and the second source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the second source-drain layer.

[0036] In addition, the lead-out electrodes also include trap layer lead-out electrodes that penetrate the insulating layer and the gate dielectric layer and are electrically connected to the trap layer well.

[0037] This embodiment designs and implements a tunneling field-effect transistor with a vertical channel, which reduces the area occupied by the device in the horizontal direction and improves the device density. At the same time, the ring gate design improves the control of the tunneling effect of the channel layer, and combined with the vertical first channel region and second channel region, it realizes the self-alignment of the gate layer during the fabrication of the channel with controllable length, effectively reducing the device's requirements for photolithography process and improving the device's performance.

[0038] It should be noted that, in the embodiments of this disclosure, the various film layers of the transistor structure can be patterned using a patterning process to fabricate the respective film layers.

[0039] It should be noted that the "patterning process" mentioned in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this disclosure includes processes such as coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0040] In the description of the embodiments of this disclosure, it should be understood that a "layer" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire fabrication process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".

[0041] Based on the same inventive concept, a third embodiment of this disclosure provides an electronic device that should at least include the vertical channel tunneling field-effect transistor (VSTET) proposed in the first embodiment of this disclosure, or include a memory device composed of VSTETs proposed in the first embodiment of this disclosure. In this embodiment, the electronic device can be a smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A vertical-channel tunneling field-effect transistor, characterized in that, include: Substrate; A first source / drain layer, a channel layer, and a second source / drain layer are sequentially stacked on the surface of the substrate; wherein the outer periphery of the orthographic projection of the second source / drain layer on the substrate is located within the orthographic projection of the first source / drain layer on the substrate, and the channel layer includes a first channel region and a second channel region that are not connected to each other, and the orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the second source / drain layer, so that a first lateral groove surrounding the first channel region and a second lateral groove surrounding the second channel region are formed between the first source / drain layer and the second source / drain layer; A gate dielectric layer, the gate dielectric layer covering the first source / drain layer, the second source / drain layer, the first lateral groove, and the surface of the second lateral groove; A gate layer comprising a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction, the first gate region covering a portion of the upper surface of the second source / drain layer, the second gate region completely filling the first lateral groove and the second lateral groove, and extending to the upper surface of the second source / drain layer and connecting with the first gate region.

2. The tunneling field-effect transistor according to claim 1, characterized in that, The first trench area and the second trench area are arranged along a first direction; The first gate region includes a horizontal extension extending along the first direction and a first extension and a second extension extending along the second direction, wherein the second direction and the first direction are perpendicular to each other in a horizontal plane parallel to the surface of the substrate. One end of the first extension is connected to one end of the horizontal extension, and one end of the second extension is connected to the other end of the horizontal extension. The orthographic projection of the first extension on the substrate completely covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second extension on the substrate covers the orthographic projection of the second channel region on the substrate. There is a gap between the orthographic projections of the first extension and the second extension on the substrate.

3. The tunneling field-effect transistor according to claim 2, characterized in that, Also includes: An insulating layer that covers the substrate and all layers disposed on the substrate; The lead-out electrode includes a first source-drain lead-out electrode, a second source-drain lead-out electrode, and a gate lead-out electrode that are insulated from each other. The first source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the first source-drain layer, and the second source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the second source-drain layer.

4. The tunneling field-effect transistor according to claim 3, characterized in that, The gate layer and the lead-out electrode are made of any one of tungsten, titanium nitride, or a stacked material of tungsten and titanium nitride.

5. The tunneling field-effect transistor according to any one of claims 1 to 4, characterized in that, The first source / drain layer is made of a semiconductor material of a first doping type, and the second source / drain layer is made of a semiconductor material of a second doping type; the semiconductor material is any one of silicon, germanium, germanium-silicon, and gallium arsenide.

6. A method for fabricating a vertical-channel tunneling field-effect transistor, characterized in that, include: Provide a substrate; A first source / drain layer, a channel layer, and a second source / drain layer are sequentially fabricated on the surface of the substrate; wherein the outer periphery of the orthographic projection of the second source / drain layer on the substrate is located within the orthographic projection of the first source / drain layer on the substrate, and the channel layer includes a first channel region and a second channel region that are not connected to each other, and the orthographic projections of the first channel region and the second channel region on the substrate are both located within the orthographic projection of the second source / drain layer, so that a first lateral groove surrounding the first channel region and a second lateral groove surrounding the second channel region are formed between the first source / drain layer and the second source / drain layer; A gate dielectric layer is grown on the exposed surfaces of the first source / drain layer, the second source / drain layer, the first lateral groove, and the second lateral groove. A gate material layer is grown on the surface of the gate dielectric layer, and the gate material layer is patterned and etched to form a gate layer; the gate layer includes a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction, the first gate region covers a portion of the upper surface of the second source / drain layer, the second gate region completely fills the first lateral groove and the second lateral groove, and extends to the upper surface of the second source / drain layer and connects with the first gate region.

7. The preparation method according to claim 6, characterized in that, The step of sequentially fabricating a first source / drain layer, a channel layer, and a second source / drain layer on the surface of the substrate includes: A semiconductor material of a first doping type is grown on the surface of the substrate to form the first source / drain layer; An insulating material layer is prepared on the surface of the first source / drain layer away from the substrate. The insulating material layer is etched to form a first through-hole and a second through-hole that penetrate the insulating material layer. The first through-hole and the second through-hole are formed along a first direction. The first and second through holes are filled with channel material, and the surface of the channel material away from the substrate is planarized so that the surface of the channel material away from the substrate is flush with the surface of the insulating material layer away from the substrate. A second type of doped semiconductor material is grown on the surface of the insulating material layer away from the substrate, and the second type of doped semiconductor material is patterned to form the second source / drain layer; The insulating material layer is removed to form the trench layer having a first trench region and a second trench region.

8. The preparation method according to claim 7, characterized in that, The step of patterning and etching the gate material layer to form the gate layer includes: The gate material layer is patterned and etched to form a first gate region and a second gate region. The first gate region includes a horizontal extension extending along a first direction and a first extension and a second extension extending along a second direction, wherein the second direction and the first direction are perpendicular to each other in a horizontal plane parallel to the surface of the substrate. One end of the first extension is connected to one end of the horizontal extension, and one end of the second extension is connected to the other end of the horizontal extension. The orthographic projection of the first extension on the substrate completely covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second extension on the substrate covers the orthographic projection of the second channel region on the substrate. There is a gap between the orthographic projections of the first extension and the second extension on the substrate.

9. The preparation method according to claim 8, characterized in that, After patterning and etching the gate material layer to form the gate layer, the method further includes: An insulating layer is prepared such that the insulating layer covers the substrate and all layers disposed on the substrate; Through-hole etching is performed on the insulating layer to prepare lead-out electrodes; the lead-out electrodes include a first source-drain lead-out electrode, a second source-drain lead-out electrode, and a gate lead-out electrode that are insulated from each other, wherein the first source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the first source-drain layer, and the second source-drain lead-out electrode penetrates the insulating layer and is electrically connected to the second source-drain layer.

10. An electronic device, characterized in that, It includes at least a tunneling field-effect transistor with a vertical channel as described in any one of claims 1 to 5.

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