DMA (Direct Memory Access)-based FFT (Fast Fourier Transform) automatic calculation structure and control method

Abstract

The invention provides an FFT (Fast Fourier Transform) automatic calculation structure based on DMA (Direct Memory Access), which relates to the field of communication technology signal processing, and comprises the following steps: a bus interface adaptation unit determines a space address of write-in data, a write-in data interface, a space address of output data and an output data interface of direct memory access; the FFT calculation input control unit writes write-in data into the asynchronous FIFO module through the write-in data interface according to the write request signal, and analyzes the write-in data through the data unpacking module to obtain analyzed data; the analysis data is input into the FFT calculation unit; the FFT calculation unit performs FFT calculation on the analysis data to obtain calculation data; the FFT calculation output control unit caches calculation data to an output data cache module; packaging the calculation data to obtain output data; and writing the output data into the spatial address of the output data through the output data interface. According to the invention, the calculation efficiency of FFT can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology signal processing, in particular to a DMA (Direct Memory Access)-based FFT (Fast Fourier Transform) automatic calculation structure and control method. BACKGROUND

[0002] In the field of communication systems, the fast Fourier transform is a very critical and commonly used signal processing technology, which is applied in various aspects of signal receiving and sending.

[0003] With the continuous improvement of the performance requirements of communication systems, in order to more effectively guarantee the system operation, the FFT calculation is often realized through the control mode of software and hardware combination. However, this control mode of software and hardware combination needs to frequently schedule the hardware for FFT calculation, which leads to a large number of software and hardware interactions. Each software and hardware interaction will increase the overhead of the communication system and reduce the calculation efficiency of the FFT, thereby affecting the real-time performance and stability of the communication system. SUMMARY

[0004] In view of the above deficiencies of the prior art, the purpose of the embodiments of the present application is to provide a DMA-based FFT automatic calculation structure and control method, which can solve the technical problem of low calculation efficiency of the FFT in the prior art.

[0005] The first aspect of the embodiments of the present application provides a DMA-based FFT automatic calculation structure, which comprises a bus interface adaptation unit, an FFT calculation input control unit, an FFT calculation output control unit and an FFT calculation unit. The FFT calculation input control unit comprises a write request management module, a write asynchronous FIFO module, a data unpacking module and an input data cache module. The FFT calculation output control unit comprises a read request management module, a read asynchronous FIFO module, a data packing module and an output data cache module. Wherein: The bus interface adaptation unit is used to determine the spatial address of the write data of the direct memory access, and determine the write data interface; and determine the spatial address of the output data, and determine the output data interface; The FFT calculation input control unit is used to write the write data into the asynchronous FIFO module through the write data interface according to the write request signal, and analyze the write data through the data unpacking module to obtain analysis data; and input the analysis data into the FFT calculation unit through the input data cache module; The FFT calculation unit is used to perform FFT calculation on the analysis data to obtain calculation data; The FFT calculation output control unit is used to cache the calculation data to the output data cache module; package the calculation data to obtain output data; and write the output data to the space address of the output data through the output data interface according to the read request signal.

[0006] Optionally, the bus interface adapter unit is connected to the FFT calculation input control unit and the FFT calculation output control unit respectively; the FFT calculation unit is also connected to the FFT calculation input control unit and the FFT calculation output control unit respectively. Furthermore, the bus interface adapter unit is connected to the write request management module, the write request management module is connected to the write asynchronous FIFO module, the write asynchronous FIFO module is connected to the data unpacking module, the data unpacking module is connected to the input data cache module, and the input data cache module is connected to the FFT calculation unit; Furthermore, the bus interface adapter unit is connected to the read request management module, the read request management module is connected to the read asynchronous FIFO module, the read asynchronous FIFO module is connected to the data packaging module, the data packaging module is connected to the output data cache module, and the output data cache module is connected to the FFT calculation unit.

[0007] Optionally, the FFT calculation input control unit writes the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and parses the write data through the data unpacking module to obtain parsed data; and the method of inputting the parsed data into the FFT calculation unit through the input data buffer module is specifically as follows: The write request management module generates a write request signal; The write request management module writes the write data to the asynchronous FIFO module through the write data interface based on the write request signal; The asynchronous FIFO module determines the target bit width based on the input packing mode, and parses the written data based on the target bit width to obtain parsed data; The input data caching module performs a ping-pong operation on the parsed data to input the parsed data into the FFT calculation unit.

[0008] Optionally, the write request management module generates the write request signal in the following specific way: The written data is counted to obtain the current written data count value; The input channels for the written data are counted to obtain the current input channel count value; If a write half-full signal is detected in the write asynchronous FIFO module, then it is determined whether a read half-full signal exists in the read asynchronous FIFO module. If the asynchronous FIFO module does not have the read half-full signal, a write burst request signal is generated when the current write data count is less than or equal to the preset number of FFT calculation points and the current input channel count is less than or equal to the preset total number of channels.

[0009] Optionally, the write request management module is further configured to: After counting the input channels of the written data to obtain the current input channel count value, if it is detected that the write asynchronous FIFO module does not have a write full signal, then a write single request signal is generated if the current written data count value is less than or equal to the preset number of FFT calculation points and the current input channel count value is less than or equal to the preset total number of channels.

[0010] Optionally, the FFT calculation output control unit caches the calculation data in the output data cache module; packages the calculation data to obtain output data; and writes the output data to the spatial address of the output data through the output data interface according to the read request signal. The output data caching module stores the real and imaginary parts of the calculated data separately. The data packaging module determines the bus width based on the output packaging mode, and packages the real and imaginary parts of the calculated data based on the bus width to obtain output data; and writes the output data into the read asynchronous FIFO module; The read request management module generates a read request signal; Based on the read request signal, the read request management module writes the output data to the space address of the output data through the output data interface.

[0011] Optionally, the read request management module generates read request signals in the following specific way: The output data is counted to obtain the current output data count value; The output channels of the output data are counted to obtain the current output channel count value; If a half-full read signal is detected in the asynchronous read FIFO module, then it is determined whether a half-full write signal exists in the asynchronous write FIFO module. If the asynchronous FIFO module does not have the write half-full signal, a read burst request signal is generated when the current output data count is less than or equal to the preset number of FFT calculation points and the current output channel count is less than or equal to the preset total number of channels.

[0012] Optionally, the read request management module is further configured to: After counting the output channels of the output data to obtain the current output channel count value, if it is detected that the asynchronous FIFO module does not have a full read signal, a read single request signal is generated if the current read data count value is less than or equal to the preset number of FFT calculation points and the current read channel count value is less than or equal to the preset total number of channels.

[0013] Optionally, the FFT calculation unit performs FFT calculations on the parsed data to obtain the calculated data in the following specific manner: The FFT calculation unit performs FFT calculations on the parsed data based on the preset number of FFT calculation points to obtain calculated data; wherein, the calculated data includes a real part and an imaginary part.

[0014] In a second aspect, this invention proposes a DMA-based automatic FFT calculation control method, applied to the DMA-based automatic FFT calculation structure described in the first aspect. The DMA-based automatic FFT calculation control method includes: The bus interface adapter unit determines the space address for writing data to direct memory access, the write data interface, the space address for output data, and the output data interface. The FFT calculation input control unit writes the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and parses the write data through the data unpacking module to obtain parsed data; and inputs the parsed data to the FFT calculation unit through the input data buffer module. The FFT calculation unit performs FFT calculations on the parsed data to obtain the calculated data; The FFT calculation output control unit caches the calculated data to the output data cache module; packages the calculated data to obtain output data; and writes the output data to the space address of the output data through the output data interface according to the read request signal.

[0015] A third aspect of the present invention provides a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the DMA-based automatic FFT calculation control method as described in the second aspect.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present invention include at least the following: In this embodiment of the invention, a dedicated bus interface adapter unit is set up to accurately determine the data read / write space address and interface, reducing data transmission addressing time. The FFT calculation input control unit utilizes a write request management module and a write asynchronous FIFO module to orderly and quickly parse the data and input it into the FFT calculation unit, ensuring a stable data supply. The FFT calculation unit focuses on calculation, improving the core computing speed. The FFT calculation output control unit uses an output data caching module and a data packaging module to efficiently process the calculated data and quickly write it to the specified address. The collaborative work of each unit avoids the calculation delays caused by frequent software and hardware interactions and chaotic data transmission in traditional methods, effectively optimizing the data flow and processing flow, thereby significantly improving the calculation efficiency of FFT. Attached Figure Description

[0017] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of an automatic FFT calculation structure based on DMA provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of writing / reading a specified space provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of a write / read packaging mode provided by an embodiment of the present invention; Figure 4 This is a flowchart illustrating an automatic FFT calculation and control method based on DMA provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] The following description, in conjunction with the accompanying drawings, details the DMA-based automatic FFT calculation structure provided by the present invention through specific embodiments and application scenarios.

[0021] Reference manual attached Figure 1 The diagram shows a schematic of an automatic FFT calculation structure based on DMA provided in an embodiment of the present invention.

[0022] This invention provides a DMA-based automatic FFT calculation structure, which may include: a bus interface adaptation unit, an FFT calculation input control unit, an FFT calculation output control unit, and an FFT calculation unit. The FFT calculation input control unit includes a write request management module, a write asynchronous FIFO module, a data unpacking module, and an input data buffer module. The FFT calculation output control unit includes a read request management module, a read asynchronous FIFO module, a data packing module, and an output data buffer module. The bus interface adapter unit is connected to the FFT calculation input control unit and the FFT calculation output control unit respectively; the FFT calculation unit is also connected to the FFT calculation input control unit and the FFT calculation output control unit respectively. Furthermore, the bus interface adapter unit is connected to the write request management module, the write request management module is connected to the write asynchronous FIFO module, the write asynchronous FIFO module is connected to the data unpacking module, the data unpacking module is connected to the input data cache module, and the input data cache module is connected to the FFT calculation unit; Furthermore, the bus interface adapter unit is connected to the read request management module, the read request management module is connected to the read asynchronous FIFO module, the read asynchronous FIFO module is connected to the data packaging module, the data packaging module is connected to the output data cache module, and the output data cache module is connected to the FFT calculation unit.

[0023] In this embodiment, the DMA-based FFT automatic calculation structure adopts an AHB bus architecture with a fixed bus data width of 32 bits. It supports up to 7 channels of FFT calculation and the preset number of FFT calculation points is N. The value of N can be 32, 64, 128, 256, 1024, etc. The input and output data width of the FFT calculation unit is 22 bits.

[0024] Specifically, the bus interface adapter unit is used to determine the space address of the write data for direct memory access; and to determine the write data interface; as well as to determine the space address of the output data; and to determine the output data interface.

[0025] In this embodiment, the bus interface adapter unit can convert bus data into a general write data stream according to the write data interface.

[0026] In this embodiment, the method for DMA writing or reading data from a specified space is as follows: the number of channels is configured to support reading data from multiple channels from the source data address for FFT calculation; the source data base address is configured as the starting address of the memory space for all channel data; the starting offset address is configured as the starting address for calculating all channel data; and the output data starting destination address is configured as the starting address for outputting all channel data to the memory space. During FFT calculation, sufficient data is automatically read from the source data starting address of each channel sequentially according to the above configuration for calculation, and then the calculation result is output to the set target storage space. The input / output data length of each channel is determined by the input / output data width and the number of FFT calculation points N.

[0027] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of writing / reading a specified space provided by an embodiment of the present invention; a cache space is allocated in memory to cache the written data, all based on a source data address SRC_DMA_ADDR. Each cache start address corresponds to a channel and each has its own separate offset address START_OFFSET. The required cache space length BUF_IN_LEN is: BUF_IN_LEN >= SRC_DW * 2 * N; SRC_DW is the bit width of the input data for the FFT calculation unit.

[0028] For DMA reading of FFT calculation output data, it can share a contiguous address space with the write side, both based on a single destination address DST_DMA_ADDR. In this case, the cache space length BUF_OUT_LEN is: BUF_OUT_LEN>=DST_DW*2*N.

[0029] Where DST_DW is the bit width of the output data of the FFT calculation unit.

[0030] The FFT calculation input control unit is used to write the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and to parse the write data through the data unpacking module to obtain parsed data; and to input the parsed data to the FFT calculation unit through the input data buffer module.

[0031] In this embodiment, the FFT calculation input control unit writes the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and parses the write data through the data unpacking module to obtain parsed data; and the method of inputting the parsed data to the FFT calculation unit through the input data buffer module is as follows: The write request management module generates a write request signal; The write request management module writes the write data to the asynchronous FIFO module through the write data interface based on the write request signal; The asynchronous FIFO module determines the target bit width based on the input packing mode, and parses the written data based on the target bit width to obtain parsed data; The input data caching module performs a ping-pong operation on the parsed data to input the parsed data into the FFT calculation unit.

[0032] In this implementation, the write request management module proactively generates and writes data to the asynchronous FIFO module based on signals, achieving ordered data transmission. The asynchronous FIFO module determines the target bit width parsing data according to the input packing mode, accurately adapting it to subsequent calculations. The input data caching module uses ping-pong operation to input parsing data, ensuring seamless connection between data input and FFT calculation unit processing. This avoids data waiting and transmission blockage, reduces intermediate steps and time loss in data processing, effectively improving the data input efficiency of FFT calculations and ensuring overall efficient computation.

[0033] In this embodiment, the asynchronous FIFO writing module determines the target bit width based on the input packing mode and parses the written data based on the target bit width. The method to obtain the parsed data can be as follows: the written data is sent from the bus and the data bit width is fixed. It can be classified according to the bus bit width, such as the input packing mode being divided into 16 bits, 24 bits, 32 bits, etc. First, the data output from the FIFO is split into 16 bits, 24 bits, 32 bits, etc. according to actual needs. Finally, the required bit width of the input is calculated based on FFT and then truncated.

[0034] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram of a write / read packaging mode provided by an embodiment of the present invention; as shown below. Figure 3As shown in the lower half, the IN_BUS_DW value is 32, and there are three unpacking paths available. The path for bit width conversion can be selected according to the input packing mode: 16 bits, 24 bits, and 32 bits. The input and output data bit widths (DW) of the FFT computation unit are both 22 bits. Therefore, for 16-bit links, a sign bit needs to be added, while for 24-bit and 32-bit links, only the lower DW bits need to be taken.

[0035] Next, we will start the FFT calculation unit. We will then perform an N-point FFT calculation on the input data. After a period of time, the FFT calculation result will be output, including both the real and imaginary parts.

[0036] Then, the real and imaginary parts of the FFT calculation result are stored in two separate data buffer modules. When the asynchronous FIFO is not empty, the data is packaged and output to the asynchronous FIFO. The data packaging method is as follows: Figure 3 As shown in the upper part, the input and output data bit width (DW) of the FFT computation unit is 22 bits. Therefore, for a 16-bit link, the high 16 bits need to be taken, and for 24-bit and 32-bit links, sign bits need to be padded. The OUT_BUS_DW value is 32, and there are three possible packing paths. The bit width conversion path can be selected according to the output packing mode, which are 16 bits, 24 bits, and 32 bits, respectively. After bit width conversion, all data are output as 32 bits. Next, the FFT computation output data is moved based on the read request signal.

[0037] In this embodiment of the application, the input data caching module performs a ping-pong operation on the parsed data as follows: each time FFT input data is written, if the channel count value is <= 1, the data can be written continuously until both caching modules are full; otherwise, before each new channel data is written to a single caching module, it is necessary to wait for the FFT calculation unit to complete the calculation result of the previous channel.

[0038] As an optional implementation, the write request management module generates write request signals in the following specific way: The written data is counted to obtain the current written data count value; The input channels for the written data are counted to obtain the current input channel count value; If a write half-full signal is detected in the write asynchronous FIFO module, then it is determined whether a read half-full signal exists in the read asynchronous FIFO module. If the asynchronous FIFO module does not have the read half-full signal, a write burst request signal is generated when the current write data count is less than or equal to the preset number of FFT calculation points and the current input channel count is less than or equal to the preset total number of channels.

[0039] This implementation method, by counting the written data and input channels separately, allows for precise control of data volume and channel status. When a half-full signal is detected in the asynchronous FIFO module, the status of the asynchronous FIFO module is further assessed to prevent data accumulation. A write burst request signal is generated when the current written data count and input channel count meet preset conditions, enabling efficient batch data writing, reducing the overhead of frequent small-volume writes, optimizing the data transmission process, improving the efficiency of writing data to the asynchronous FIFO module, and thus ensuring the data supply for FFT calculations.

[0040] In addition, the write request management module is also used for: After counting the input channels of the written data to obtain the current input channel count value, if it is detected that the write asynchronous FIFO module does not have a write full signal, then a write single request signal is generated if the current written data count value is less than or equal to the preset number of FFT calculation points and the current input channel count value is less than or equal to the preset total number of channels.

[0041] In this implementation, after obtaining the current input channel count value, if the asynchronous FIFO module does not have a write-full signal, and the current write data count value and the input channel count value meet the conditions, a write single request signal is generated. This method allows for flexible selection of the single data write mode based on the actual state of the FIFO module and the amount of data. Compared to batch writing, single writing is more suitable when the data volume is small or the remaining space in the FIFO is limited. It effectively avoids the risk of data overflow, while making reasonable use of the FIFO space, further improving the accuracy and flexibility of data writing, and ensuring stable data input for FFT calculations.

[0042] In this embodiment of the application, if both a write burst request and a write single request exist simultaneously, only the write burst request will be responded to.

[0043] The FFT calculation unit is used to perform FFT calculations on the parsed data to obtain calculated data.

[0044] In this embodiment of the application, the FFT calculation unit performs FFT calculations on the parsed data to obtain the calculated data in the following specific manner: The FFT calculation unit performs FFT calculations on the parsed data based on the preset number of FFT calculation points to obtain calculated data; wherein, the calculated data includes a real part and an imaginary part.

[0045] This implementation method, by pre-setting the number of FFT calculation points, provides a clear specification for the calculation, ensuring a standardized calculation process. This allows data from different batches and sources to be processed according to a unified standard, guaranteeing the consistency and reliability of the calculation results. Furthermore, the calculated data, including both real and imaginary parts, fully preserves the frequency domain characteristics of the signal, providing a rich and accurate data foundation for subsequent more precise signal analysis and processing. This effectively enhances the practicality and effectiveness of FFT calculations in application scenarios such as communication systems.

[0046] The FFT calculation output control unit is used to cache the calculation data to the output data cache module; package the calculation data to obtain output data; and write the output data to the space address of the output data through the output data interface according to the read request signal.

[0047] In this embodiment of the application, the FFT calculation output control unit caches the calculation data to the output data cache module; packages the calculation data to obtain output data; and writes the output data to the space address of the output data through the output data interface according to the read request signal. Specifically, the method is as follows: The output data caching module stores the real and imaginary parts of the calculated data separately. The data packaging module determines the bus width based on the output packaging mode, and packages the real and imaginary parts of the calculated data based on the bus width to obtain output data; and writes the output data into the read asynchronous FIFO module; The read request management module generates a read request signal; Based on the read request signal, the read request management module writes the output data to the space address of the output data through the output data interface.

[0048] In this implementation, the output data caching module stores the real and imaginary parts of the calculated data separately, avoiding data confusion and facilitating subsequent processing. The data packaging module determines the bus width based on the output packaging mode, flexibly adapting to different bus requirements and improving data transmission compatibility. The packaged output data is written to the asynchronous FIFO module for buffering. The read request management module generates and writes data to a specified address based on signals, ensuring accurate and orderly data output. This series of operations optimizes the data output process, reduces data transmission errors and latency, and improves the efficiency and reliability of FFT calculation result output.

[0049] In this embodiment, the data packaging module determines the bus width based on the output packaging mode, and packages the real and imaginary parts of the calculated data based on the bus width. The output data can be obtained in the following ways: the data reading is controlled by the bus and the data width is fixed. The FFT calculation output data needs to be truncated or the sign bit is filled to convert it to a width of 16 bits, 24 bits, 32 bits, etc. The selection can be based on the closest actual width. Finally, it is converted into data that conforms to the bus width for output.

[0050] As an optional implementation, the read request management module generates read request signals in the following specific way: The output data is counted to obtain the current output data count value; The output channels of the output data are counted to obtain the current output channel count value; If a half-full read signal is detected in the asynchronous read FIFO module, then it is determined whether a half-full write signal exists in the asynchronous write FIFO module. If the asynchronous FIFO module does not have the write half-full signal, a read burst request signal is generated when the current output data count is less than or equal to the preset number of FFT calculation points and the current output channel count is less than or equal to the preset total number of channels.

[0051] This implementation method, by counting the output data and output channels separately, allows for precise control of the output data volume and channel status. When a half-full signal is detected in the asynchronous FIFO module, the write status to the asynchronous FIFO module is further assessed to avoid data transmission conflicts. A read burst request signal is generated when the current output data count and output channel count meet preset conditions, enabling efficient batch data reading, reducing the overhead of frequent small-volume reads, optimizing the data reading process, improving the efficiency of data output from the asynchronous FIFO module, and ensuring the smooth transmission of FFT calculation results.

[0052] In addition, the read request management module is also used for: After counting the output channels of the output data to obtain the current output channel count value, if it is detected that the asynchronous FIFO module does not have a full read signal, a read single request signal is generated if the current read data count value is less than or equal to the preset number of FFT calculation points and the current read channel count value is less than or equal to the preset total number of channels.

[0053] In this implementation, after acquiring the current output channel count value, if the asynchronous FIFO module is not detected to have a full read signal, and the current read data count value and read channel count value meet the conditions, a read single request signal is generated. This method allows for flexible selection of the single data read mode based on the actual state of the FIFO module and the amount of data. When the data volume is small or the remaining space in the FIFO is limited, single reads can effectively avoid the risk of data overflow, make reasonable use of the FIFO space, improve the accuracy and flexibility of data reading, ensure stable and efficient output of FFT calculation results, and improve the overall system performance.

[0054] In this embodiment of the application, if both a read burst request and a read single request exist simultaneously, only the read burst request will be responded to.

[0055] The beneficial effects of the technical solutions provided by the embodiments of the present invention include at least the following: The input and output packing modes adopted in this invention support adaptation to various bus interface bit widths, which is beneficial for integration and reuse and provides adaptation flexibility. The DMA-based write-read method used in this invention can read computational data from a specified space and output the computational results to a specified space, reducing the need for software and hardware interaction control, providing computational flexibility, and effectively reducing the area of ​​internal hardware cache data. The FFT automatic calculation system structure and control flow proposed in this invention achieves automatic FFT calculation based on DMA data transfer by effectively managing write / read signal requests on the calculation input and output sides, thus achieving the effect of module sharing.

[0056] In this embodiment of the invention, a dedicated bus interface adapter unit is set up to accurately determine the data read / write space address and interface, reducing data transmission addressing time. The FFT calculation input control unit utilizes a write request management module and a write asynchronous FIFO module to orderly and quickly parse the data and input it into the FFT calculation unit, ensuring a stable data supply. The FFT calculation unit focuses on calculation, improving the core computing speed. The FFT calculation output control unit uses an output data caching module and a data packaging module to efficiently process the calculated data and quickly write it to the specified address. The collaborative work of each unit avoids the calculation delays caused by frequent software and hardware interactions and chaotic data transmission in traditional methods, effectively optimizing the data flow and processing flow, thereby significantly improving the calculation efficiency of FFT.

[0057] Reference manual attached Figure 4 The diagram shows a flowchart of an automatic FFT calculation control method based on DMA provided in an embodiment of the present invention.

[0058] This invention provides a DMA-based automatic FFT calculation control method, which can be applied to the aforementioned DMA-based automatic FFT calculation structure. The method includes: 401. The space address of the write data, the write data interface, the space address of the output data, and the output data interface for direct memory access are determined by the bus interface adapter unit. 402. The FFT calculation input control unit writes the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and parses the write data through the data unpacking module to obtain parsed data; and inputs the parsed data to the FFT calculation unit through the input data buffer module. 403. Perform FFT calculations on the parsed data using the FFT calculation unit to obtain calculated data; 404. The FFT calculation output control unit caches the calculation data to the output data cache module; packages the calculation data to obtain output data; and writes the output data to the space address of the output data through the output data interface according to the read request signal.

[0059] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0060] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0061] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0063] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0064] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0066] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0067] This invention provides a readable storage medium comprising: storing a program or instructions on the readable storage medium, wherein when the program or instructions are executed by a processor, the program or instructions implement the steps of the above-described DMA-based FFT automatic calculation control method and achieve the same technical effect. To avoid repetition, this invention will not elaborate further.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A DMA-based automatic FFT calculation structure, characterized in that, The DMA-based automatic FFT calculation structure includes: a bus interface adaptation unit, an FFT calculation input control unit, an FFT calculation output control unit, and an FFT calculation unit. The FFT calculation input control unit includes a write request management module, a write asynchronous FIFO module, a data unpacking module, and an input data buffer module. The FFT calculation output control unit includes a read request management module, a read asynchronous FIFO module, a data packing module, and an output data buffer module. The bus interface adapter unit is used to determine the space address of the write data for direct memory access; and to determine the write data interface; and to determine the space address of the output data; and to determine the output data interface. The FFT calculation input control unit is used to write the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and to parse the write data through the data unpacking module to obtain parsed data; and to input the parsed data to the FFT calculation unit through the input data buffer module. The FFT calculation unit is used to perform FFT calculations on the parsed data to obtain calculated data; The FFT calculation output control unit is used to cache the calculation data to the output data cache module; package the calculation data to obtain output data; and write the output data to the space address of the output data through the output data interface according to the read request signal.

2. The DMA-based automatic FFT calculation structure according to claim 1, characterized in that, The bus interface adapter unit is connected to the FFT calculation input control unit and the FFT calculation output control unit respectively; the FFT calculation unit is also connected to the FFT calculation input control unit and the FFT calculation output control unit respectively. Furthermore, the bus interface adapter unit is connected to the write request management module, the write request management module is connected to the write asynchronous FIFO module, the write asynchronous FIFO module is connected to the data unpacking module, the data unpacking module is connected to the input data cache module, and the input data cache module is connected to the FFT calculation unit; Furthermore, the bus interface adapter unit is connected to the read request management module, the read request management module is connected to the read asynchronous FIFO module, the read asynchronous FIFO module is connected to the data packaging module, the data packaging module is connected to the output data cache module, and the output data cache module is connected to the FFT calculation unit.

3. The DMA-based automatic FFT calculation structure according to claim 2, characterized in that, The FFT calculation input control unit writes the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and parses the write data through the data unpacking module to obtain parsed data; and the method of inputting the parsed data to the FFT calculation unit through the input data buffer module is as follows: The write request management module generates a write request signal; The write request management module writes the write data to the asynchronous FIFO module through the write data interface based on the write request signal; The asynchronous FIFO module determines the target bit width based on the input packing mode, and parses the written data based on the target bit width to obtain parsed data; The input data caching module performs a ping-pong operation on the parsed data to input the parsed data into the FFT calculation unit.

4. The DMA-based automatic FFT calculation structure according to claim 3, characterized in that, The write request management module generates write request signals in the following specific way: The written data is counted to obtain the current written data count value; The input channels for the written data are counted to obtain the current input channel count value; If a write half-full signal is detected in the write asynchronous FIFO module, then it is determined whether a read half-full signal exists in the read asynchronous FIFO module. If the asynchronous FIFO module does not have the read half-full signal, a write burst request signal is generated when the current write data count is less than or equal to the preset number of FFT calculation points and the current input channel count is less than or equal to the preset total number of channels.

5. The DMA-based automatic FFT calculation structure according to claim 4, characterized in that, The write request management module is also used for: After counting the input channels of the written data to obtain the current input channel count value, if it is detected that the write asynchronous FIFO module does not have a write full signal, then a write single request signal is generated if the current written data count value is less than or equal to the preset number of FFT calculation points and the current input channel count value is less than or equal to the preset total number of channels.

6. The DMA-based automatic FFT calculation structure according to claim 2, characterized in that, The FFT calculation output control unit caches the calculation data into the output data cache module; packages the calculation data to obtain output data; and writes the output data into the space address of the output data through the output data interface according to the read request signal. The output data caching module stores the real and imaginary parts of the calculated data separately. The data packaging module determines the bus width based on the output packaging mode, and packages the real and imaginary parts of the calculated data based on the bus width to obtain the output data. And write the output data into the asynchronous FIFO module; The read request management module generates a read request signal; Based on the read request signal, the read request management module writes the output data to the space address of the output data through the output data interface.

7. The DMA-based automatic FFT calculation structure according to claim 6, characterized in that, The specific method by which the read request management module generates read request signals is as follows: The output data is counted to obtain the current output data count value; The output channels of the output data are counted to obtain the current output channel count value; If a half-full read signal is detected in the asynchronous read FIFO module, then it is determined whether a half-full write signal exists in the asynchronous write FIFO module. If the asynchronous FIFO module does not have the write half-full signal, a read burst request signal is generated when the current output data count is less than or equal to the preset number of FFT calculation points and the current output channel count is less than or equal to the preset total number of channels.

8. The DMA-based automatic FFT calculation structure according to claim 7, characterized in that, The read request management module is also used for: After counting the output channels of the output data to obtain the current output channel count value, if it is detected that the asynchronous FIFO module does not have a full read signal, a read single request signal is generated if the current read data count value is less than or equal to the preset number of FFT calculation points and the current read channel count value is less than or equal to the preset total number of channels.

9. The DMA-based automatic FFT calculation structure according to claim 4, characterized in that, The FFT calculation unit performs FFT calculations on the parsed data to obtain the calculated data in the following specific manner: The FFT calculation unit performs FFT calculations on the parsed data based on the preset number of FFT calculation points to obtain calculated data; wherein, the calculated data includes a real part and an imaginary part.

10. A DMA-based automatic FFT calculation control method, applied to the DMA-based automatic FFT calculation structure according to any one of claims 1 to 9, characterized in that, The DMA-based automatic FFT calculation control method includes: The bus interface adapter unit determines the space address for writing data to direct memory access, the write data interface, the space address for output data, and the output data interface. The FFT calculation input control unit writes the write data to the asynchronous FIFO module through the write data interface according to the write request signal, and parses the write data through the data unpacking module to obtain parsed data; and inputs the parsed data to the FFT calculation unit through the input data buffer module. The FFT calculation unit performs FFT calculations on the parsed data to obtain the calculated data; The FFT calculation output control unit caches the calculated data to the output data cache module; packages the calculated data to obtain output data; and writes the output data to the space address of the output data through the output data interface according to the read request signal.

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