Monolithic integrated power device structure for improving anti-interference capability of grid electrode and preparation method of monolithic integrated power device structure

Abstract

The invention relates to a monolithic integrated power device structure capable of improving the anti-interference capability of a grid electrode and a preparation method thereof.The monolithic integrated power device structure comprises a substrate, a power device structure and a filtering structure, the power device structure and the filtering structure are located on the same substrate, monolithic integration of the power device structure and the filtering structure is achieved, and the anti-interference capability of the grid electrode is improved. The structure is simple. The filtering structure is connected with the grid electrode of the power device structure, voltage oscillation signals generated by high-power microwave radiation on the grid electrode can be effectively restrained, the anti-interference capability of the grid electrode is improved, and stable work of the device is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a monolithic integrated power device structure and a preparation method thereof. BACKGROUND

[0002] Wide bandgap power devices represented by gallium nitride (GaN) and silicon carbide (SiC) can effectively improve the power density of power electronic systems and have important applications in power management modules and motor drive converters of unmanned aerial vehicles and other power electronic systems. However, when subjected to high-power microwave (HPM) radiation, the radiation pulse is coupled into the power electronic system to induce high disturbance voltage and current, which can cause degradation or failure of the power device. SUMMARY

[0003] Therefore, it is necessary to provide a monolithic integrated power device structure and a preparation method thereof which can resist high-power microwave radiation.

[0004] In a first aspect, the present application provides a monolithic integrated power device structure, comprising:

[0005] a substrate;

[0006] a power device structure located on the substrate, the power device structure comprising a source electrode, a gate electrode and a drain electrode arranged along a first direction;

[0007] a filter structure located on the substrate and arranged along the first direction with the power device structure, the filter structure being connected to the gate electrode and configured to filter out interference signals generated at the gate electrode by high-power microwave radiation.

[0008] In one embodiment, the filter structure comprises a capacitor unit and a resistor unit arranged along the first direction, wherein the capacitor unit is connected to the gate electrode, the source electrode and the resistor unit, respectively.

[0009] In one embodiment, the resistor unit comprises:

[0010] a resistor material layer located on the substrate;

[0011] a first electrode located on a side of the resistor material layer away from the substrate and partially extending to the resistor material layer;

[0012] a second electrode located on a side of the resistor material layer away from the substrate and partially extending to the resistor material layer, the second electrode being arranged along the first direction with the first electrode, and the second electrode being connected to the gate electrode.

[0013] In one embodiment, the resistor material layer comprises:

[0014] a first semiconductor portion located on the substrate;

[0015] a first barrier portion located on a side of the first semiconductor portion away from the substrate;

[0016] wherein a two-dimensional electron gas exists between the first semiconductor portion and the first barrier portion.

[0017] In one of the embodiments, the capacitor unit comprises a third electrode, a capacitor dielectric layer and a fourth electrode which are sequentially stacked in a direction perpendicular to the substrate, wherein the third electrode is connected to the source electrode and the fourth electrode is connected to the gate electrode.

[0018] In one of the embodiments, the power device structure further comprises:

[0019] a second semiconductor portion located on the substrate;

[0020] a second barrier portion located on a side of the second semiconductor portion away from the substrate;

[0021] a gate cap layer located on a side of the second barrier portion away from the second semiconductor portion;

[0022] wherein a two-dimensional electron gas exists between the second semiconductor portion and the second barrier portion; the source electrode is located on a side of the second barrier portion away from the second semiconductor portion, the drain electrode is located on a side of the second barrier portion away from the second semiconductor portion, and the gate electrode is located on a side of the gate cap layer away from the second barrier portion.

[0023] In a second aspect, the application further provides a method for manufacturing a monolithic integrated power device structure, comprising:

[0024] providing a substrate;

[0025] forming power device structures and filter structures arranged in a first direction on the substrate;

[0026] wherein the power device structures comprise source electrodes, gate electrodes and drain electrodes arranged in the first direction, and the filter structures are connected to the gate electrodes and used for filtering out interference signals generated by high-power microwave radiation on the gate electrodes.

[0027] In one of the embodiments, forming filter structures on the substrate comprises:

[0028] forming a semiconductor layer on the substrate;

[0029] forming a barrier layer on a side of the semiconductor layer away from the substrate;

[0030] etching the barrier layer and the semiconductor layer to form a first groove and a second groove arranged along a first direction, taking the barrier layer located on a side of the second groove close to the first groove as a first barrier part, and taking the semiconductor layer located on a same side of the second groove as the first barrier part as a first semiconductor part;

[0031] forming a capacitor unit in the first groove, and forming a first electrode and a second electrode on a side of the first barrier part away from the first semiconductor part, respectively;

[0032] wherein the first barrier part, the second barrier part, the first electrode and the second electrode constitute a resistance unit, and the resistance unit and the capacitor unit constitute the filter structure.

[0033] In one embodiment, the forming a capacitor unit in the first groove, and forming a first electrode and a second electrode on a side of the first barrier part away from the first semiconductor part, respectively, comprises:

[0034] forming a third electrode on a bottom of the first groove, and forming a first electrode and a second electrode on a side of the first barrier part away from the first semiconductor part, respectively;

[0035] forming a capacitor dielectric layer on a side of the third electrode away from the bottom of the first groove;

[0036] forming a fourth electrode on a side of the capacitor dielectric layer away from the third electrode.

[0037] In one embodiment, taking the barrier layer located on a side of the second groove away from the first groove as a second barrier part, and taking the semiconductor layer located on a same side of the second groove as the second barrier part as a second semiconductor part;

[0038] forming the power device structure on the substrate, comprising:

[0039] forming a gate cap layer on a side of the second barrier part away from the second semiconductor part;

[0040] forming the source and the drain on a side of the second barrier part away from the second semiconductor part;

[0041] forming a gate on a side of the gate cap layer away from the second barrier part.

[0042] The monolithic integrated power device structure and the preparation method thereof, the monolithic integrated power device structure comprises a substrate, a power device structure and a filter structure, the power device structure and the filter structure are located on the same substrate, the monolithic integration of the power device structure and the filter structure is realized, and the structure is simple. The gate of the filter structure is connected with the power device structure, the voltage oscillation signal generated by high-power microwave radiation at the gate can be effectively inhibited, the anti-interference ability of the gate is improved, and the stable work of the device is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0044] Figure 1 The cross-sectional schematic view of the structure obtained in step S221 of the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0045] Figure 2 The cross-sectional schematic view of the structure obtained in step S221 of the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0046] Figure 3 The cross-sectional schematic view of the structure obtained in step S213 of the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0047] Figure 4 The cross-sectional schematic view of the structure obtained after forming the insulating layer in the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0048] Figure 5 The cross-sectional schematic view of the structure obtained after etching the insulating layer in the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0049] Figure 6 The cross-sectional schematic view of the structure obtained in step S222 of the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0050] Figure 7 The cross-sectional schematic view of the structure obtained in step S2142 of the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0051] Figure 8 The cross-sectional schematic view of the structure obtained in step S200 of the preparation method of the monolithic integrated power device structure provided in an embodiment;

[0052] Figure 9 A top view of the structure obtained in step S200 of the method for manufacturing a monolithic integrated power device structure provided in an embodiment;

[0053] Figure 10 An equivalent circuit diagram of the monolithic integrated power device structure provided in an embodiment;

[0054] Figure 11 A flow chart of the method for manufacturing a monolithic integrated power device structure provided in an embodiment.

[0055] BRIEF DESCRIPTION OF DRAWINGS

[0056] 100 - substrate, 200 - power device structure, 210 - source, 220 - gate, 230 - drain, 240 - second semiconductor part, 250 - second barrier part, 260 - gate cap layer, 261 - gate cap material layer, 300 - filter structure, 310 - resistance unit, 311 - first semiconductor part, 312 - first barrier part, 313 - first electrode, 314 - second electrode, 320 - capacitance unit, 321 - third electrode, 322 - capacitance dielectric layer, 323 - fourth electrode, 400 - insulating layer, 500 - semiconductor layer, 600 - barrier layer, 710 - first groove, 720 - second groove, 730 - third groove, 740 - fourth groove, 750 - fifth groove, 760 - sixth groove, 770 - seventh groove. DETAILED DESCRIPTION

[0057] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various parts, layers, and slots, these parts, layers, and slots should not be limited by these terms. These terms are only used to distinguish one part, layer, and slot from another part, layer, and slot. Therefore, without departing from the teachings of this invention, the first part, layer, and slot discussed below may be referred to as the second part, layer, and slot; for example, the first slot may be referred to as the second slot, and similarly, the second slot may be referred to as the first slot; the first slot and the second slot are different slots.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0063] In one embodiment, this application provides a monolithic integrated power device structure; please refer to [link to relevant documentation]. Figures 8-9 It includes a substrate 100, a power device structure 200, and a filter structure 300.

[0064] The substrate 100 can be made of silicon carbide, silicon, gallium nitride, or combinations thereof. The power device structure 200 and the filter structure 300 are both located on the substrate 100 and arranged along a first direction. The first direction can be any direction parallel to the plane of the substrate 100. The power device structure 200 includes a source 210, a gate 220, and a drain 230 arranged along the first direction. The power device structure 200 can include, but is not limited to, wide-bandgap semiconductor power devices such as gallium nitride and silicon carbide, as well as silicon-based power devices. For example, it can be a depletion-mode Schottky gate device, a p-type gate enhancement-mode device, a depletion-mode insulated-gate device, an enhancement-mode insulated-gate device, a cascaded cascaded device, a planar gate device, a trench gate device, etc., without limitation.

[0065] The filter structure 300 is connected to the gate 220 and can be used to filter out interference signals generated by high-power microwave radiation on the gate 220. The filter structure 300 can be a first-order RC filter, a second-order RC filter, a third-order RC filter, etc.

[0066] In this embodiment, the monolithically integrated power device structure includes a substrate 100, a power device structure 200, and a filter structure 300. The power device structure 200 and the filter structure 300 are located on the same substrate 100, achieving monolithic integration of the two structures, resulting in a simple structure. The gates 220 of the filter structure 300 and the power device structure 200 are connected, effectively suppressing voltage oscillation signals generated by high-power microwave radiation at the gate 220, improving the anti-interference capability of the gate 200, and ensuring stable device operation.

[0067] In one embodiment, please refer to... Figures 8-9 The filter structure 300 includes capacitor units 320 and resistor units 310 arranged along a first direction. The capacitor unit 320 is connected to the gate 220, the source 210, and the resistor unit 310, respectively.

[0068] The equivalent circuit diagram of a monolithic integrated power device structure is as follows: Figure 10 As shown, capacitor unit 320 and resistor unit 310 constitute an RC low-pass filter. Since high-power microwaves have characteristics such as high frequency, high power and wide spectrum, the RC low-pass filter can be used to filter out high-frequency interference signals generated on the gate 220 by high-power microwave radiation.

[0069] In one embodiment, please refer to... Figures 8-9 The resistor unit 310 includes a resistive material layer, a first electrode 313, and a second electrode 314.

[0070] The resistive material layer is located on the substrate 100. The resistive material layer may include, but is not limited to, semiconductor materials such as AlGaN, AlN, GaN, AlInN, Si, and SiC, or insulating materials such as SiO2, SiN, SiON, and Al2O3.

[0071] The first electrode 313 is located on the side of the resistive material layer away from the substrate 100 and partially extends into the resistive material layer. The material of the first electrode 313 may include, but is not limited to, one or more layers of conductive materials such as IZO, ITO, TiN, W, Pt, Ru, and Al. The second electrode 314 is located on the side of the resistive material layer away from the substrate 100 and partially extends into the resistive material layer. The second electrode 314 and the first electrode 313 are arranged along a first direction. The material of the second electrode 314 may include, but is not limited to, one or more layers of conductive materials such as IZO, ITO, TiN, W, Pt, Ru, and Al. The second electrode 314 is connected to the gate 220, and the first electrode 313 can be connected to an external circuit.

[0072] Furthermore, the resistive material layer includes a first semiconductor portion 311 and a first barrier portion 312. The first semiconductor portion 311 is located on the substrate 100. The material of the first semiconductor portion 311 may include, but is not limited to, AlGaN, GaN, etc. The first barrier portion 312 is located on the side of the first semiconductor portion 311 away from the substrate 100, and the first barrier portion 312 may include, but is not limited to, one or more layers of AlGaN, GaN, AlN, AlInN, etc.

[0073] A two-dimensional electron gas exists between the first semiconductor portion 311 and the first barrier portion 312. The two-dimensional electron gas is generated due to the polarization effect of the first semiconductor portion 311 and the first barrier portion 312. The resistance value of the resistive material layer is related to the size of the first semiconductor portion 311, the size of the first barrier portion 312, the concentration of the two-dimensional electron gas, and the doping concentration of the first semiconductor portion 311 and the first barrier portion 312.

[0074] In one embodiment, please refer to... Figures 8-9The capacitor unit 320 includes a third electrode 321, a capacitor dielectric layer 322, and a fourth electrode 323 stacked sequentially along a direction perpendicular to the substrate. The third electrode 321 is connected to the source 210, the fourth electrode 323 is connected to the gate 220, and the capacitor dielectric layer 322 isolates the third electrode 321 and the fourth electrode 323 to prevent them from contacting each other.

[0075] The third electrode 321 may include, but is not limited to, one or more layers of conductive materials such as IZO, ITO, TiN, W, Pt, Ru, and Al. The capacitor dielectric layer 322 may include, but is not limited to, insulating materials such as SiO2, SiN, and SiON, or High-K materials (dielectric constant ≥ 3.9) such as Al2O3 and HfO. The fourth electrode 323 may include, but is not limited to, one or more layers of conductive materials such as IZO, ITO, TiN, W, Pt, Ru, and Al.

[0076] In one embodiment, please refer to... Figures 8-9 The power device structure 200 also includes a second semiconductor section 240, a second barrier section 250, and a gate cap layer 260.

[0077] The second semiconductor portion 240 is located on the substrate 100, and the material of the second semiconductor portion 240 may include, but is not limited to, AlGaN, GaN, etc. The second barrier portion 250 is located on the side of the second semiconductor portion 240 away from the substrate 100, and the second barrier portion 250 may include, but is not limited to, one or more layers of AlGaN, GaN, AlN, AlInN, etc. The second semiconductor portion 240 and the second barrier portion 250 can form a heterojunction structure. A two-dimensional electron gas exists between the second semiconductor portion 240 and the second barrier portion 250 due to a polarization effect.

[0078] The gate cap layer 260 is located on the side of the second barrier portion 250 away from the second semiconductor portion 240. The material of the gate cap layer 260 may include, but is not limited to, GaN or High-K materials.

[0079] The source 210 is located on the side of the second barrier portion 250 away from the second semiconductor portion 240, the drain 230 is located on the side of the second barrier portion 250 away from the second semiconductor portion 240, and the gate 220 is located on the side of the gate cap layer 260 away from the second barrier portion 250.

[0080] In one embodiment, please refer to... Figures 8-9The monolithic integrated power device structure also includes an insulating layer 400, which is disposed on the exposed surface of the third electrode 321 near the substrate 100, the first barrier portion 312, the first semiconductor portion 311, the second barrier portion 250, the second semiconductor portion 240, and the gate cap layer 260. The material of the insulating layer 400 includes, but is not limited to, silicon oxide, silicon oxycarbide, silicon oxynitride, etc.

[0081] In one embodiment, please refer to... Figure 9 The monolithic integrated power device structure also includes multiple drains 230, gates 220 and sources 210 arranged alternately in the horizontal direction.

[0082] In one embodiment, based on the same inventive concept, such as Figure 11 As shown, this application also provides a method for fabricating a monolithic integrated power device structure, including steps S100-S200.

[0083] S100 provides a substrate.

[0084] S200, forming a power device structure and a filter structure arranged along a first direction on a substrate.

[0085] Please continue reading. Figures 8-9 A power device structure 200 and a filter structure 300, arranged along a first direction, can be formed on a substrate 100 using processes such as epitaxial growth, deposition, photolithography, and etching. The power device structure 200 includes a source 210, a gate 220, and a drain 230 arranged along the first direction, and the filter structure 300 is connected to the gate 220. The filter structure 300 can be used to filter out interference signals generated by high-power microwave radiation at the gate 220.

[0086] In this embodiment, by providing a substrate 100 and forming a power device structure 200 and a filter structure 300 arranged along a first direction on the substrate 100, monolithic integration of the power device structure 200 and the filter structure 300 is achieved, resulting in a simple structure. The gates 220 of the filter structure 300 and the power device structure 200 are connected, which can effectively suppress the voltage oscillation signal generated by high-power microwave radiation at the gate 220, improve the anti-interference capability of the gate 200, and ensure the stable operation of the device.

[0087] In one embodiment, a filter structure is formed on a substrate, including steps S211-S214.

[0088] S211, a semiconductor layer is formed on the substrate.

[0089] Please see Figure 2Epitaxial growth processes, such as metal-organic chemical vapor deposition or molecular beam epitaxy, can be used to form a semiconductor layer 500 on the substrate 100. The semiconductor layer 500 can be, but is not limited to, one or more layers of materials such as AlGaN or GaN.

[0090] S212, a barrier layer is formed on the side of the semiconductor layer away from the substrate.

[0091] Please continue reading. Figure 2 Epitaxial growth processes, such as metal-organic chemical vapor deposition or molecular beam epitaxy, can be used to form a barrier layer 600 on the side of the semiconductor layer 500 away from the substrate 100. The barrier layer 600 can be, but is not limited to, one or more layers of materials such as AlGaN, GaN, AlN, and AlInN.

[0092] S213, etching the barrier layer and semiconductor layer to form a first trench and a second trench arranged along a first direction.

[0093] Please see Figures 2-3 The barrier layer 500 and the semiconductor layer 600 can be etched using wet etching, dry etching, or a combination of wet and dry etching processes to form a first trench 710 and a second trench 720 arranged along a first direction. The barrier layer 500 and the semiconductor layer 600 are important film layers of the power device structure 200. The barrier layer located on the side of the second trench 720 closest to the first trench 710 is designated as the first barrier portion 311, and the semiconductor layer located on the same side of the second trench 720 as the first barrier portion 311 is designated as the first semiconductor portion 312. The first barrier portion 311 and the first semiconductor portion 312 can serve as resistive material layers, which can simplify the process flow.

[0094] S214, a capacitor unit is formed in the first trench, and a first electrode and a second electrode are formed on the side of the first barrier portion away from the first semiconductor portion, respectively.

[0095] Please see Figure 8 A deposition process, such as low-pressure vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or magnetron sputtering, can be used to form a capacitor cell 320 within the first trench 710, and a first electrode 313 and a second electrode 314 are formed on the side of the first barrier portion 312 away from the first semiconductor portion 311. Specifically, S214 includes steps S2141-S2143.

[0096] S2141, a third electrode is formed at the bottom of the first trench, and a first electrode and a second electrode are formed on the side of the first barrier portion away from the first semiconductor portion, respectively.

[0097] Please see Figure 6A third electrode 321 can be formed at the bottom of the first trench 710 through processes such as deposition, photolithography and etching, and a first electrode 313 and a second electrode 314 can be formed on the side of the first barrier portion 312 away from the first semiconductor portion 311.

[0098] S2142, a capacitor dielectric layer is formed on the side of the third electrode away from the bottom of the first trench.

[0099] Please see Figure 7 A capacitor dielectric layer 322 can be formed on the side of the third electrode 321 away from the bottom of the first trench 710 through processes such as deposition, photolithography and etching.

[0100] S2143, a fourth electrode is formed on the side of the capacitor dielectric layer away from the third electrode.

[0101] Please see Figure 6 A fourth electrode 323 can be formed on the side of the capacitor dielectric layer 322 away from the third electrode 321 through processes such as deposition, photolithography, and etching. The third electrode 321, the capacitor dielectric layer 322, and the fourth electrode 323 form a capacitor unit 320. The first semiconductor part 311, the first barrier part 312, the first electrode 313, and the second electrode 314 constitute a resistor unit 310. The resistor unit 310 and the capacitor unit 320 constitute a filter structure 300.

[0102] Before step S214, please refer to Figure 4 Alternatively, an insulating layer 400 can be formed first via a deposition process on the inner wall of the first trench 710, within the second trench 720, and on the exposed surface of the barrier layer 600. The material of the insulating layer 400 can be, but is not limited to, insulating materials such as silicon oxide, silicon carbide, silicon oxynitride, and silicon nitride. Then, please refer to... Figure 5 The third trench 730, the fourth trench 740, the fifth trench 750 and the sixth trench 760 arranged along the first direction can be formed by etching a portion of the insulating layer 400 covering the barrier layer 600 through an etching process. The third trench 730, the fourth trench 740, the fifth trench 750 and the sixth trench 760 all expose the barrier layer 600. The third trench 730 is used to locate the first electrode 313, the fourth trench 740 is used to locate the second electrode 314, the fifth trench 750 is used to locate the source electrode 210, and the sixth trench 760 is used to locate the drain electrode 230.

[0103] In one embodiment, see Figure 3 The barrier layer located on the side of the second trench 720 away from the first trench 710 can be used as the second barrier portion 250, and the semiconductor layer located on the same side of the second trench 720 as the second barrier portion 250 can be used as the second semiconductor portion 240.

[0104] Forming a power device structure on a substrate includes steps S221-S223.

[0105] S221, a gate cap layer is formed on the side of the second barrier portion away from the second semiconductor portion.

[0106] Please see Figures 1-2 A gate cap material layer 261 can be formed on the side of the second barrier portion away from the second semiconductor portion through processes such as deposition, photolithography and etching, and a portion of the gate cap material layer 261 can be etched to form a gate cap layer 260.

[0107] S222 forms a source and a drain on the side of the second barrier portion away from the second semiconductor portion.

[0108] Please see Figure 6 The source electrode 210 and drain electrode 230 can be formed on the side of the second barrier portion 250 away from the second semiconductor portion 240 through processes such as deposition, photolithography, and etching. The source electrode 210 and drain electrode 230 can be formed simultaneously with the formation of the third electrode 321, the first electrode 313, and the second electrode 314 in step S2141 described above. The source electrode 210, drain electrode 230, third electrode 321, first electrode 313, and second electrode 314 are made of the same material.

[0109] S223, a gate is formed on the side of the gate cap layer away from the second barrier.

[0110] Please see Figure 8 The gate 220 can be formed on the side of the gate cap layer 260 away from the second barrier portion 250 through processes such as deposition, photolithography, and etching. The gate 220 can be formed simultaneously with the formation of the fourth electrode 323 in the above step S2143. The gate 220 and the fourth electrode 323 are made of the same material.

[0111] In one embodiment, before step S223, please refer to Figure 5 Alternatively, a portion of the insulating layer 400 covering the gate cap layer 260 can be etched first to form the seventh trench 770, which is used to position the gate 220.

[0112] It should be understood that each step in the above embodiments of the method for fabricating a monolithic integrated power device structure may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a part of the steps or stages in other steps.

[0113] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A monolithic integrated power device structure, characterized in that, include: Substrate; A power device structure is located on the substrate, the power device structure including a source, a gate, and a drain arranged along a first direction; A filter structure is located on the substrate and arranged along the first direction with the power device structure. The filter structure is connected to the gate and is used to filter out interference signals generated by high-power microwave radiation on the gate.

2. The monolithic integrated power device structure according to claim 1, characterized in that, The filter structure includes capacitor units and resistor units arranged along the first direction, wherein the capacitor units are respectively connected to the gate, the source, and the resistor units.

3. The monolithic integrated power device structure according to claim 2, characterized in that, The resistor unit includes: A resistive material layer is located on the substrate; The first electrode is located on the side of the resistive material layer away from the substrate and extends partially into the resistive material layer; The second electrode is located on the side of the resistive material layer away from the substrate and extends partially into the resistive material layer. The second electrode and the first electrode are arranged along the first direction, and the second electrode is connected to the gate.

4. The monolithic integrated power device structure according to claim 3, characterized in that, The resistive material layer includes: A first semiconductor section is located on the substrate; The first barrier portion is located on the side of the first semiconductor portion away from the substrate; There is a two-dimensional electron gas between the first semiconductor part and the first barrier part.

5. The monolithic integrated power device structure according to claim 2, characterized in that, The capacitor unit includes a third electrode, a capacitor dielectric layer, and a fourth electrode stacked sequentially along a direction perpendicular to the substrate, wherein the third electrode is connected to the source electrode, and the fourth electrode is connected to the gate electrode.

6. The monolithic integrated power device structure according to claim 1, characterized in that, The power device structure also includes: A second semiconductor section is located on the substrate; The second barrier portion is located on the side of the second semiconductor portion away from the substrate; The gate cap layer is located on the side of the second barrier portion away from the second semiconductor portion; There is a two-dimensional electron gas between the second semiconductor portion and the second barrier portion; the source is located on the side of the second barrier portion away from the second semiconductor portion, the drain is located on the side of the second barrier portion away from the second semiconductor portion, and the gate is located on the side of the gate cap layer away from the second barrier portion.

7. A method for fabricating a monolithic integrated power device structure, characterized in that, include: Provide substrate; A power device structure and a filter structure arranged along a first direction are formed on the substrate; The power device structure includes a source, a gate, and a drain arranged along a first direction. The filter structure is connected to the gate and is used to filter out interference signals generated by high-power microwave radiation on the gate.

8. The method according to claim 7, characterized in that, A filter structure is formed on the substrate, comprising: A semiconductor layer is formed on the substrate; A barrier layer is formed on the side of the semiconductor layer away from the substrate; The barrier layer and the semiconductor layer are etched to form a first trench and a second trench arranged along a first direction. The barrier layer located on the side of the second trench closer to the first trench is used as the first barrier portion, and the semiconductor layer located on the same side of the second trench as the first barrier portion is used as the first semiconductor portion. A capacitor unit is formed in the first trench, and a first electrode and a second electrode are formed on the side of the first barrier portion away from the first semiconductor portion, respectively. The first barrier portion, the first semiconductor portion, the first electrode, and the second electrode constitute a resistor unit, and the resistor unit and the capacitor unit constitute the filter structure.

9. The method according to claim 8, characterized in that, The method of forming a capacitor unit in the first trench and forming a first electrode and a second electrode on the side of the first barrier portion away from the first semiconductor portion includes: A third electrode is formed at the bottom of the first trench, and a first electrode and a second electrode are formed on the side of the first barrier portion away from the first semiconductor portion, respectively. A capacitor dielectric layer is formed on the side of the third electrode away from the bottom of the first trench; A fourth electrode is formed on the side of the capacitor dielectric layer away from the third electrode.

10. The method according to claim 8, characterized in that, The barrier layer located on the side of the second trench away from the first trench is designated as the second barrier portion, and the semiconductor layer located on the same side of the second trench as the second barrier portion is designated as the second semiconductor portion. The power device structure is formed on the substrate, including: A gate cap layer is formed on the side of the second barrier portion away from the second semiconductor portion; The source and the drain are formed on the side of the second barrier portion away from the second semiconductor portion; A gate is formed on the side of the gate cap layer away from the second barrier portion.

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