Phase rotator in spread spectrum clock generator and spread spectrum clock generator

Abstract

The invention discloses a phase rotator in a spread spectrum clock generator and the spread spectrum clock generator, relates to the technical field of clock spread spectrum, and aims to solve the problems that the phase rotator of the spread spectrum clock generator in the prior art is not suitable for high-frequency signals and is high in power consumption. The phase rotator comprises a coarse adjustment loop and a fine adjustment loop. The coarse adjustment loop is connected with the fine adjustment loop; the coarse tuning loop is used for performing first phase segmentation on an input high-frequency differential clock signal to obtain multiple paths of modulation phase signals, and selecting a target single-path modulation phase signal from the multiple paths of modulation phase signals based on a phase selection signal; and the fine adjustment loop is used for performing second phase segmentation on the target single-path modulation phase signal to obtain multiple paths of high-resolution phase signals, and selecting the target single-path high-resolution phase signal from the multiple paths of high-resolution phase signals based on the phase selection signal. The invention is used for realizing the processing of the clock spread spectrum generator on the high-frequency clock signal and reducing the power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock spread spectrum technology, in particular to a phase rotator in a spread spectrum clock generator and the spread spectrum clock generator. BACKGROUND

[0002] With the rapid development of communication and artificial intelligence fields, high-speed serial interface technology has become the mainstream scheme of data transmission, and the stable processing and precise phase control of high-frequency differential clock signals are increasingly urgent. However, the phase rotator technology currently matched with the spread spectrum clock generator (SSCG) has significant defects: when processing high-frequency differential clock signals, the phase adjustment accuracy of the existing phase rotator is difficult to meet the requirement of precise phase output for high-speed data transmission, and the adaptability to high-frequency differential clock signals is insufficient, which leads to the problem of clock jitter deterioration in high-frequency scenarios, directly affecting the data transmission reliability of high-speed serial interface.

[0003] At the same time, the existing phase rotator has obvious power consumption defects: in the face of high-frequency differential clock processing requirements, one type of scheme needs to constantly compress the delay time of the delay unit to adapt to high-frequency scenarios, which is greatly limited by process and has a limit; another type of scheme has a constant current path, even without dynamic signal input, there is still a milliamperes of static current, and to meet the requirement of fast phase switching at high frequency, the bias current needs to be further increased, making the power consumption problem more prominent. This high power consumption problem makes the existing scheme difficult to meet the low power consumption requirement of high-speed serial interface system, and cannot effectively solve the coordination problem of electromagnetic interference (EMI) suppression and high-frequency signal adaptation, and a phase rotator technology with better performance is needed to break through the above limitations. SUMMARY

[0004] The purpose of the present application is to provide a phase rotator in a spread spectrum clock generator and a spread spectrum clock generator for realizing the processing of high-frequency clock signals by the phase rotator in the clock spread spectrum generator and reducing power consumption.

[0005] In order to achieve the above purpose, the present application provides the following technical scheme: In a first aspect, the present application provides a phase rotator in a spread spectrum clock generator, comprising: a coarse adjustment loop and a fine adjustment loop; the coarse adjustment loop is connected with the fine adjustment loop; The coarse adjustment loop is used for performing first phase division on the input high-frequency differential clock signal to obtain a plurality of modulated phase signals, and selecting a target single modulated phase signal from the plurality of modulated phase signals; The fine adjustment loop is configured to perform second phase division on the target single-channel modulation phase signal to obtain a plurality of high-resolution phase signals, and select a target single-channel high-resolution phase signal from the plurality of high-resolution phase signals.

[0006] Optionally, the coarse adjustment loop comprises a coarse adjustment voltage-controlled delay line and a first phase selection circuit; an output end of the coarse adjustment voltage-controlled delay line is connected to an input end of the first phase selection circuit. The coarse adjustment voltage-controlled delay line is configured to perform first phase division on the high-frequency differential clock signal to output the plurality of modulation phase signals. The first phase selection circuit is configured to select the target single-channel modulation phase signal from the plurality of modulation phase signals based on a phase selection signal.

[0007] Optionally, the fine adjustment loop comprises a fine adjustment voltage-controlled delay line and a second phase selection circuit; an output end of the first phase selection circuit is connected to an input end of the fine adjustment voltage-controlled delay line, and an output end of the fine adjustment voltage-controlled delay line is connected to an input end of the second phase selection circuit. The fine adjustment voltage-controlled delay line is configured to perform second phase division on the target single-channel modulation phase signal to output the plurality of high-resolution phase signals. The second phase selection circuit is configured to select the target single-channel high-resolution phase signal from the plurality of high-resolution phase signals based on the phase selection signal.

[0008] Optionally, the coarse adjustment voltage-controlled delay line comprises a first number of first delay units; each first delay unit comprises a first inverter, a second inverter, and an NMOS tail current source controlled by a first control voltage. The first inverter and the second inverter are connected in series. A bias current end of the first inverter and a bias current end of the second inverter are connected to a first end of the NMOS tail current source; a second end of the NMOS tail current source is grounded. The first number of first delay units divide the high-frequency differential clock signal into a first number of modulation phase signals.

[0009] Optionally, when the first control voltage increases, the synchronous bias current output by the NMOS tail current source increases, the on-resistance of the first inverter and the second inverter decreases, and the first delay time of the first delay unit is shortened. When the first control voltage decreases, the synchronous bias current output by the NMOS tail current source decreases, the on-resistance of the first inverter and the second inverter increases, and the first delay time is prolonged.

[0010] Optionally, the fine-tuning voltage-controlled delay line comprises a second number of second delay units; the first number is less than the second number. Each of the second delay units comprises a third inverter, a fourth inverter, and a capacitor array; the third inverter and the fourth inverter are connected in series; The output of the third inverter and the input of the fourth inverter are both connected to a first end of the capacitor array; a second end of the capacitor array is connected to a second control voltage; the capacitor array comprises N selectable capacitors; N is a positive integer greater than 1. The second control voltage adjusts the load capacitance of the second delay unit by controlling the number of selectable capacitors in the capacitor array, so as to control the second delay time of the second delay unit to step by a preset precision.

[0011] Optionally, the second control voltage also changes the second delay time by regulating the signal flipping speed of the inverter, so as to match the clock cycle requirement under different working frequencies.

[0012] Optionally, the coarse-tuning loop further comprises a first phase detector, a first charge pump, and a first low-pass filter; the output signal of the first phase detector is processed by the first charge pump and the first low-pass filter to generate the first control voltage.

[0013] Optionally, the fine-tuning loop further comprises a second phase detector, a second charge pump, and a second low-pass filter; the output signal of the second phase detector is processed by the second charge pump and the second low-pass filter to generate the second control voltage.

[0014] Compared with the prior art, the phase rotator in the spread spectrum clock generator provided by the application is connected to the coarse-tuning loop and the fine-tuning loop through a double-loop structure, which specifically solves two major problems of the prior art: one is to solve the problem that the prior art cannot be applied to high-frequency signals: the coarse-tuning loop first performs first phase division on the high-frequency differential clock signal to generate multiple modulation phase signals to preliminarily adapt to high-frequency signal processing; and then the fine-tuning loop performs second phase division on the target single modulation phase signal to generate a high-resolution phase signal, thereby breaking through the process limitation of the traditional DLL relying on gate delay and meeting the accurate phase requirement in the high-frequency scene; the other is to solve the problem of high power consumption: the double-loop structure does not need the constant current path of the traditional current mode circuit, and only generates dynamic power consumption when the signal flips, thereby avoiding the consumption of milliamperes of static current; finally, through two-stage phase division and low-power structure design, the applicability and energy efficiency in the high-frequency scene are improved.

[0015] In a second aspect, the present application provides a spread spectrum clock generator, comprising a digital control circuit and a phase rotator in the spread spectrum clock generator according to any one of the above; the phase rotator is connected to the digital control circuit; the digital control circuit is configured to generate a phase selection signal in real time and send the phase selection signal to the phase rotator. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings: Figure 1 Structure diagram of the phase rotator in the spread spectrum clock generator according to an embodiment of the present application; Figure 2 Structure diagram of the first delay unit according to an embodiment of the present application; Figure 3 Structure diagram of the second delay unit according to an embodiment of the present application; Figure 4 Transient simulation waveform diagram of the coarse adjustment and fine adjustment output phase according to an embodiment of the present application; Figure 5 Power consumption simulation result diagram according to an embodiment of the present application; Figure 6 Structure diagram of the spread spectrum clock generator according to an embodiment of the present application; The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings: DETAILED DESCRIPTION

[0017] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", etc. are used to distinguish the same or similar items or components with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the order. Those skilled in the art can understand that the terms of "first", "second", etc. do not limit the number and execution order, and the terms of "first", "second", etc. also do not necessarily mean different.

[0018] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the embodied words are used merely to present certain examples, instances, or illustrations.

[0019] In the present application, "at least one" means one or more, and "multiple" means two or more. The relationship between the associated objects is described as "and / or", which means that there can be three relationships.

[0020] It should be noted that when the spread spectrum clock generator SSCG in the prior art uses a phase rotator to solve technical problems, two traditional schemes are mainly included.

[0021] The first traditional scheme proposes a phase rotator structure in SSCG based on DLL, which realizes the generation of multiple phases by introducing multiple groups of inverter delay units on the flow control delay line, accurately divides the clock full period into multiple parts, and has good linearity. At the same time, the use of current control delay also expands the working frequency range of the phase rotator.

[0022] However, the first traditional scheme depends on the gate delay of the inverter delay unit itself for phase cutting, and it is difficult to further compress the gate delay even in advanced process nodes, which cannot break through the process limit, that is, the phase resolution is limited. This technology can only serve the SSCG working at low frequency, and cannot meet the growing demand for data transmission rate.

[0023] The second traditional scheme proposes a phase rotator structure realized based on a current mode phase interpolator, which realizes phase synthesis in the interval by controlling the weights of two current sources driven by two-phase clocks. Since this structure uses large current for phase interpolation, rather than relying on delay units to generate independent phases, it can easily break through the resolution limit and is very suitable for high-speed application occasions.

[0024] However, the second traditional scheme must use current mode circuits to realize phase interpolation, which introduces a constant current path between the power supply and the ground. Even when there is no dynamic signal input, there is still a milliamperes of static current, causing unavoidable static power consumption. In addition, in high-speed applications, the phase rotator needs to support fast phase switching, which further improves the response capability of the current source, so a larger static bias current is required.

[0025] As shown in FIG. 1, the phase rotator in the spread spectrum clock generator according to an embodiment of the present application can include a coarse adjustment loop 1 and a fine adjustment loop 2. Figure 1 The coarse adjustment loop 1 is connected to the fine adjustment loop 2. The coarse adjustment loop 1 is used for first phase division of the input high-frequency differential clock signal, to obtain a plurality of modulated phase signals, and selects a target single modulated phase signal from the plurality of modulated phase signals based on a phase selection signal; The fine adjustment loop 2 is used for second phase division of the target single modulated phase signal, to obtain a plurality of high-resolution phase signals, and selects a target single high-resolution phase signal from the plurality of high-resolution phase signals based on the phase selection signal.

[0026] It should be noted that the double-loop structure composed of the coarse adjustment loop and the fine adjustment loop has no static bias current, only generates dynamic power consumption when the signal flips, and the average current in the period is in the order of microamperes, which has low power consumption.

[0027] Beneficial effect analysis of the embodiment: 1) solve the problems of limited phase resolution, poor low-frequency high-frequency adaptation, and insufficient precision in the prior art: the coarse adjustment loop first divides the high-frequency differential clock to generate a plurality of modulated phase signals, and the fine adjustment loop then divides the target single modulated signal to generate a plurality of high-resolution phase signals, two-stage progressive division breaks through the process limit of DLL, improves the phase precision, and adapts to high-frequency clock processing. 2) solve the problem of high-frequency clock jitter deterioration in the prior art: high-precision phase division of the double-loop structure reduces phase mutation under high frequency, avoids jitter caused by phase jump disorder, and ensures the reliability of high-speed data transmission. 3) solve the problem of high power consumption caused by constant current path, static current, and high-frequency bias current in the prior art: the double-loop structure only generates dynamic power consumption when the signal flips, has no static bias current, and the average current in the period is in the order of microamperes, which completely avoids the static power consumption problem of current mode circuit and reduces the overall power consumption.

[0028] Referring to Figure 1 , the coarse adjustment loop comprises a first phase detector 10, a first charge pump 11, a first low-pass filter 12, a coarse adjustment voltage-controlled delay line 13, and a first phase selection circuit 14.

[0029] The first phase detector 10, the first charge pump 11, and the first low-pass filter 12 are connected in series, and the output signal of the first phase detector 10 is processed by the first charge pump 11 and the first low-pass filter 12 to generate a first control voltage . Specifically, the signal output by the first phase detector 10 is converted into a current signal by the first charge pump 11, and then filtered by the first low-pass filter 12 to generate the first control voltage .

[0030] The output of the coarse-adjustment voltage-controlled delay line 13 is connected to the input of the first phase selection circuit 14. The coarse-adjustment voltage-controlled delay line 13 is used to perform the first phase split on the high-frequency differential clock signal and output multiple modulated phase signals. The first phase selection circuit 14 is used to select the target single modulated phase signal from the multiple modulated phase signals based on the phase selection signal.

[0031] Needs and Figure 1 The corresponding explanation is that the first phase detector 10 is shown in the figure. The first charge pump 11 is shown in the figure. The first low-pass filter 12 is shown in the figure. Coarse adjustment of voltage-controlled delay line 13, as shown in the figure. The first phase selection circuit 14 is shown in the figure. .

[0032] In practice, Receives two clock signals, one of which is a high-frequency differential clock signal. The other route is right The processed output phase feedback signal is also the delayed signal to be compared.

[0033] By comparing the phase difference between the two signals, i.e., the edge arrival time, it can be determined whether a phase deviation has occurred. The rising edge (or falling edge) arrives first Then output This signal informs what follows. The current needs to be increased, ultimately allowing The shortening of the delay time allows the phase of the phase feedback signal to keep up. ;like The rising edge (or falling edge) of the output phase feedback signal arrives first. Then output This signal informs what follows. The current needs to be reduced, ultimately allowing The extended delay time allows the phase energy of the phase feedback signal to be aligned. If the edges of both signals arrive simultaneously , No output and That is, both signals are at a low level. The delay time remains unchanged.

[0034] Output or Incoming , The signal is converted into a corresponding current, which is then transmitted. , After filtering out fluctuations, a stable first control voltage is generated. .

[0035] First control voltage control Another clock signal in the high-frequency differential clock signal Perform the first phase split and output multiple modulated phase signals. , , ..., ;in It is a positive integer greater than 1.

[0036] Specifically, the coarse-adjustment voltage-controlled delay line 13 includes a first number of first delay units; the first number of first delay units are connected in a cascaded manner. See also Figure 2 Each first delay unit includes a first inverter 131, a second inverter 132, and is controlled by a first control voltage. NMOS tail current source 133; The first inverter 131 and the second inverter 132 are connected in series; the input terminal of the first inverter 131 serves as the signal input terminal. When the input signal to be delayed is received, the output terminal of the first inverter 131 is connected to the input terminal of the second inverter 132, and the output terminal of the second inverter 132 serves as the signal output terminal. The output signal is the result of two stages of inversion.

[0037] The bias current terminals of the first inverter 131 and the second inverter 132 are both connected to the first terminal, i.e., the drain terminal, of the NMOS tail current source 133; the second terminal, i.e., the source terminal, of the NMOS tail current source 133 is grounded; the gate terminal of the NMOS tail current source 133 is connected to... The NMOS tail current source provides synchronous bias current for the two inverters. The first number of first delay units divide the high-frequency differential clock signal into the first number of modulated phase signals.

[0038] Understandably, the core of coarse-tuning the delay split of the voltage-controlled delay line is through... Adjusting the inverter's delay time divides the period of a high-frequency clock signal into multiple segments, generating multi-channel modulated phase signals. The principle is as follows: The inverter's delay time (the time difference between the signal's input and output) is strongly correlated with the operating current: the larger the current, the faster the inverter charges and discharges the input signal, and the shorter the delay time; the smaller the current, the slower the charging and discharging, and the longer the delay time. The on-state current of the NMOS tail current source is determined by the gate voltage. This is because, for a MOSFET, the higher the gate voltage, the greater the conduction current between the drain and source.

[0039] The adjustment process is as follows: when the first control voltage increases, the synchronous bias current output by the NMOS tail current source increases, and the on-resistance of the first inverter and the second inverter decreases, so as to shorten the first delay time of the first delay unit; when the first control voltage decreases, the synchronous bias current output by the NMOS tail current source decreases, and the on-resistance of the first inverter and the second inverter increases, so as to prolong the first delay time.

[0040] It should be noted that the NMOS tail current sources of all first delay units in the coarse adjustment loop are controlled by the same first control voltage. This design ensures that the conduction current of the first number of first delay units is completely consistent, thereby making the first delay time of each unit uniform and avoiding the disorder of coarse phase interval due to the delay difference between units.

[0041] The coarse-tuned voltage-controlled delay line comprises a first number of cascaded first delay units, through which the high-frequency differential clock signal sequentially passes. The delay time of each unit is determined by... After unified adjustment and accumulation of delays from multiple units, one cycle of the high-frequency clock signal is divided into a first number of time segments, each segment corresponding to a modulation phase signal, and finally outputting the first number of modulation phase signals.

[0042] For example, the first quantity is 8. It outputs 8 channels of modulated phase signals. Then... Receive the high 3 bits of the phase selection signal DIG_SEL from the 8-channel modulated phase signal , , ..., The target single-channel modulation phase signal is selected and fed into the fine-tuning loop. It's important to note that the seven unselected modulation phase signals are not lost. The coarse-tuning loop's delay line contains eight cascaded first delay units, through which the input high-frequency differential clock signal sequentially passes. Furthermore, the NMOS tail current sources of all first delay units are synchronously controlled by the same first control voltage, ensuring a uniform first delay time for each unit. This ultimately divides one cycle of the high-frequency clock signal into eight segments, generating eight independent coarse-tuning phase signals, such as eight signals with 20ps intervals. All signals are stored in the circuit's signal nodes. One signal is selected for fine-tuning, used only as needed for the current phase; the remaining seven remain in reserve. When switching to other phases later, such as adjusting the spread spectrum amplitude for SSCG, this can be done directly via DIG_SEL without re-splitting the signal, avoiding power waste caused by repeated splitting.

[0043] See Figure 1The fine-tuning loop includes a second phase detector 20, a second charge pump 21, and a second low-pass filter 22; the output signal of the second phase detector 20 is processed by the second charge pump 21 and the second low-pass filter 22 to generate a second control voltage. The fine-tuning loop 2 also includes: a fine-tuning voltage-controlled delay line 23 and a second phase selection circuit 24; the output of the first phase selection circuit 14 is connected to the input of the fine-tuning voltage-controlled delay line 23, and the output of the fine-tuning voltage-controlled delay line 23 is connected to the input of the second phase selection circuit 24; the output of the first phase selection circuit 14 is also connected to the input of the second phase detector 20. In other words, the fine-tuning voltage-controlled delay line 23 is used to perform a second phase split on the target single-channel modulated phase signal, outputting multiple high-resolution phase signals. , , ..., m is a positive integer greater than 1.

[0044] The second phase selection circuit 24 is used to select the target single high-resolution phase signal from multiple high-resolution phase signals based on the phase selection signal DIG_SEL.

[0045] Needs and Figure 1 The corresponding explanation is that the second phase detector 20 is shown in the figure. The second charge pump 21 is shown in the figure. The second low-pass filter 22 is shown in the figure. Fine-tune the voltage-controlled delay line 23, as shown in the figure. The second phase selection circuit 24 is shown in the figure. .

[0046] For example, both the first phase selection circuit 14 and the second phase selection circuit 24 are implemented using multiplexers in conjunction with phase selection signals. The first phase selection circuit is controlled by the high 3 bits of a 7-bit phase selection signal, which is used to select a target single-path modulated phase signal from the 8 modulated phase signals output from the coarse adjustment loop. The adjacent intervals of these 8 modulated phase signals are on the order of 10~20ps, providing a basic phase range for subsequent fine adjustment and segmentation.

[0047] For example, It outputs 16 modulated phase signals, with adjacent intervals on the order of 1 ps, and is processed by the lower 4 bits of digital signal. It can achieve precise phase selection every 1ps, which significantly improves the resolution compared to the phase signal with an adjacent interval of 10~20ps output by the coarse adjustment loop. Receive the lower 4 bits of the phase selection signal DIG_SEL from the 16-channel modulated phase signal , , ..., The target single-channel modulated phase signal is selected and fed into the fine-tuning loop. The signal transmission and processing process of the fine-tuning loop 2 in its specific implementation is the same as that of the coarse-tuning loop 1. Its core logic is consistent with the closed-loop control of the coarse-tuning loop: the second phase detector 20 compares the reference signal output by the first phase selection circuit 14 with the feedback signal output by the fine-tuning voltage-controlled delay line 23 to generate a phase difference signal, which is then converted into a stable signal by the second charge pump 21 and the second low-pass filter 22. The delay accuracy of the voltage-controlled delay line 23 is adjusted in reverse; the specific process will not be described here.

[0048] The fine-tuning voltage-controlled delay line 23 includes a second number of second delay units; the first number is less than the second number; wherein the second number of second delay units are connected in a cascaded manner. For example, the first number is the number of delay units in the coarse-tuning loop, specifically 8; the second number is the number of delay units in the fine-tuning loop, specifically 16. The design of 8 < 16 can achieve the synergistic effect of large-range coverage of coarse-tuning and high-precision completion of fine-tuning.

[0049] See Figure 3 Each second delay unit includes a third inverter 231, a fourth inverter 232, and a capacitor array 233; the third inverter 231 and the fourth inverter 232 are connected in series; the signal input terminal VIN of the third inverter 231 is connected to the signal to be delayed, and the output terminal of the third inverter 231 and the input terminal of the fourth inverter 232 are both connected to the first terminal of the capacitor array 233; the second terminal of the capacitor array 233 is connected to the second control voltage. The capacitor array 233 includes N selectable capacitors; N is a positive integer greater than 1. For example, N can be 16 capacitors.

[0050] Second control voltage By controlling the number of selectable capacitors connected in the capacitor array from 1 to N to adjust the load capacitor of the second delay unit, the second delay time of the second delay unit is controlled to step according to a preset precision; for example, the preset precision is 1ps as exemplified above, which is achieved by the gradient connection of 16 selectable capacitors.

[0051] It should be noted that the capacitor arrays of all the second delay units in the fine-tuning loop are controlled by the same second control voltage. This design ensures that the number of capacitors connected to the second number of second delay units changes according to the same rule, making the delay increment of each unit uniform, avoiding the deviation of the fine-tuning phase interval due to the difference in delay increment between units, and ensuring the sub-picosecond adjustment accuracy of the fine-tuning loop.

[0052] The core of the fine-tuning loop's breakthrough over traditional process limitations is replacing gate delay dependence with load regulation: In the first traditional solution of the prior art, a traditional DLL is used for phase segmentation. The traditional DLL depends on the inverter gate delay, which is limited by the process: for example, the minimum gate delay of 3ps in the 28nm process makes it impossible to achieve 1ps-level resolution. The fine-tuning loop in this embodiment of the invention avoids this problem by adjusting the load capacitance through a capacitor array. Since the delay time of the inverter is proportional to the load capacitance, and each capacitor in the capacitor array has the same capacitance value (e.g., 1fF), each additional capacitor increases the load capacitance by 1fF and the delay time by 1ps. This load regulation method does not depend on gate delay, and even if the process remains unchanged, subps-level resolution can be achieved by increasing the number of capacitors, completely breaking through the limitations of traditional processes.

[0053] Specifically, the second control voltage is used to select 1 to N capacitors connected in the capacitor array at different operating frequencies.

[0054] The second number of second delay units will perform a second phase split on the target single-channel modulated phase signal selected from the first number of modulated phase signals, and output the second number of high-resolution phase signals.

[0055] The second control voltage also adjusts the second delay time by regulating the signal switching speed of the inverter to match the clock cycle requirements at different operating frequencies. For example, high-frequency clock cycles are short, so the inverter switching speed needs to be increased to shorten the delay; low-frequency clock cycles are long, so the switching speed can be slowed down to extend the delay. This, together with the adjustment of the number of capacitors connected, forms a double guarantee to ensure delay adaptability across the entire frequency range.

[0056] It needs further explanation that the core purpose of the second control voltage regulating the inverter's switching speed is to solve the problem of delay mismatch with clock period at different frequencies: When the input clock frequency increases, for example from 6GHz to 10GHz, and the period decreases from 166ps to 100ps, if the inverter delay is fixed, it will lead to incomplete phase splitting. At this time, the second control voltage will increase, thereby increasing the inverter's on-current to speed up the switching speed and shorten the delay, for example, from 20ps to 10ps, to match the short period. When the frequency decreases, that is, the period becomes longer, the second control voltage decreases, thereby reducing the on-current to slow down the switching speed and lengthening the delay, avoiding excessive phase intervals that would damage linearity. In other words, this ensures that the phase rotator operates at different frequencies, working in synergy with the high-precision adjustment of the capacitor array.

[0057] The core requirement of the SSCG is to output clock signals of different phases through a phase rotator, achieving slight fluctuations in clock frequency to suppress electromagnetic interference peaks. The SSCG needs to simultaneously meet the requirements of anti-interference and anti-jitter, both achieved collaboratively through a dual-loop structure: ① Anti-interference, i.e., avoiding clustering: The SSCG controls DIG_SEL to switch slowly between multiple phases, for example from... Switch to This allows the clock frequency to fluctuate within a small range, such as 5.99~6.01GHz, dispersing energy and avoiding interference; ② Anti-jitter, meaning no sudden early or late transitions: The dual-ring structure ensures precise phase switching steps, such as coarse adjustment of 10~20ps and fine adjustment of 1ps, without irregular jumps. The receiver can accurately predict the clock edge, avoiding data transmission errors.

[0058] Following the above Output 8 channels of modulated phase signals , , ..., The following examples illustrate different work requirements: Scenario 1: Output required As the target single-channel modulated phase signal.

[0059] During the initial startup of SSCG, a reference phase signal needs to be output to provide the initial phase for subsequent fine-tuning loops; the high 3 bits of the selection signal DIG_SEL are '000'. After receiving the signal, conduction is activated. The signal path will The target single-channel modulated phase signal is fed into the fine-tuning loop.

[0060] Scenario 2: Output required As the target single-channel modulated phase signal.

[0061] When SSCG performs spread spectrum, the clock phase needs to be shifted by 30ps to achieve frequency fluctuation and suppress EMI peaks; the high 3 bits of the selected signal DIG_SEL are set to '011'. After receiving the signal, conduction is activated. The signal path will The target single-channel modulated phase signal is fed into the fine-tuning loop.

[0062] Scenario 3: Output required As the target single-channel modulated phase signal.

[0063] When spreading the SSCG to its maximum phase offset, the clock phase needs to be shifted by 70ps to ensure that the EMI suppression effect covers the target frequency band; select the high 3 bits of the signal DIG_SEL as '111'. After receiving the signal, conduction is activated. The signal path will The target single-channel modulated phase signal is fed into the fine-tuning loop.

[0064] Based on the aforementioned dual-loop structure design of coarse and fine adjustment loops and phase output characteristics, the core numerical relationship between it and the input high-frequency differential clock signal can be quantitatively expressed by a general formula, realizing a closed loop of period coverage, interval refinement and control matching, which is suitable for selection scenarios with different numbers of delay units.

[0065] See the formula: (1) in, This is the number of the first delay units in the coarse adjustment loop, also known as the first quantity; To coarsely adjust the interval between adjacent phase signals; The period of the input high-frequency differential clock signal.

[0066] Understandably, in the coarse adjustment loop Each first delay unit needs to cover one complete clock cycle, which is the period of the input high-frequency differential clock signal. Evenly divided into Section. Formula (1) ensures the coarse adjustment output. The modulation phase signal can completely cover a single clock cycle, avoiding missing period segments in phase segmentation, ensuring the lower limit of linearity, and providing a large range and low precision phase base interval for subsequent fine-tuning loops, adapting to the period variation requirements at different frequencies.

[0067] See the formula: (2) in, To fine-tune the number of the second delay units in the loop, which is also the second quantity; To fine-tune the interval between adjacent phase signals.

[0068] Understandably, in the fine-tuning loop A second delay unit, with the interval between adjacent phase signals in the coarse adjustment loop. To cut the object, the large intervals in the coarse adjustment loop are uniformly refined into smaller intervals. High-resolution small intervals Formula (2) ensures that fine-tuning accuracy can compensate for the lack of coarse-tuning accuracy, realizing progressive phase control of coarse-tuning range and fine-tuning accuracy, and meeting the needs of high-frequency scenarios for sub-picosecond level adjustment accuracy.

[0069] See the formula: (3) in, This represents the total number of output phases of the phase rotator. The number of bits for the phase selection signal. It is a positive integer greater than 1.

[0070] Understandably, this formula ensures that the digital control circuit can pass... Precise selection of bit signals Any one of the phase paths can be controlled to avoid phase selection omissions caused by insufficient control bits, thus achieving coordinated control of the dual-loop structure.

[0071] For example, , If the clock frequency of the input high-frequency clock signal is... , ,but Completely covers the clock cycle; if , ,but It also meets the periodic coverage requirements.

[0072] ,or, This achieves high-precision segmentation at the 1ps level.

[0073] It should be noted that the dual-ring structure mentioned in the above-mentioned embodiments of the present invention only has dynamic current during the brief time of clock flipping, and has no static bias current. The principle analysis is as follows.

[0074] The first thing to understand is that the key premise for the existence of static bias current is that there must be a continuous current path when the current is static.

[0075] The essence of static bias current is that when there is no signal change in the circuit (such as the clock signal being fixed at a high / low level and not flipping), there is still a constantly conducting current path between the power supply VDD and ground, resulting in continuous current consumption. For example, in the current-mode phase interpolator of the second traditional scheme mentioned above, there is a constantly conducting current path from the power supply to ground, so there is still a milliampere-level static current even without dynamic signals.

[0076] The core reason why the dual-ring structure has no static bias current is that the delay units of coarse and fine adjustment both cut off the continuous current path in the static state, and only generate current briefly when the signal flips (dynamically).

[0077] Secondly, in this invention, the first delay unit of the coarse adjustment loop essentially employs a current-starved inverter: it has no continuous current path in the static state. Each first delay unit contains two inverters, namely a first inverter and a second inverter. The inverters are powered to ground using an NMOS tail current source controlled by VCTRL,1. The principle of having no static current involves two steps: (1) Static characteristics of inverter: single tube conduction, current path is broken.

[0078] The inverter in the first delay unit of the coarse adjustment loop consists of one PMOS transistor (connected to power supply VDD) and one NMOS transistor (connected to the NMOS tail current source): When the input signal is statically high: the NMOS transistor is turned on, but the PMOS transistor is turned off → in the current path VDD → PMOS → inverter output → NMOS → tail current source → GND, the PMOS is turned off, and the path is broken; When the input signal is statically low: the PMOS transistor is turned on, but the NMOS transistor is turned off → the NMOS transistor is turned off in the current path, and the path is also broken.

[0079] In short, when an inverter is in a static state, only one transistor is always conducting, making it impossible to form a complete current path from power supply to ground, and there is no continuous current.

[0080] (2) Static state of NMOS tail current source: synchronously cut off with NMOS transistor.

[0081] The NMOS tail current source is controlled by the first control voltage, providing synchronous bias current for the two inverters: In the static state, the NMOS transistor of the inverter is turned off, and the first control voltage will synchronously control the tail current source to stop outputting current, maintaining only a very small standby state, which can be ignored. Only when the signal flips, the PMOS and NMOS of the inverter are briefly turned on simultaneously, and the tail current source outputs dynamic current to adjust the inverter's conduction speed and thus adjust the delay. This is completely different from the normally-on static current source in the existing technology.

[0082] Furthermore, the third and fourth inverters in the fine-tuning loop constitute a standard inverter structure. The standard inverter structure in the fine-tuning loop, combined with the capacitor array, also has no continuous current path in the static state.

[0083] (1) Standard inverter: No tail current source, static characteristics are consistent with coarse adjustment inverter.

[0084] The fine-tuning standard inverter and the coarse-tuning inverter have the same core structure (PMOS+NMOS), but the NMOS tail current source without the coarse-tuning unit is different: in the static state, it is also a single transistor conducting, with no continuous current path from power supply to inverter to ground.

[0085] (2) Capacitor array: static with no charge flow and no current consumption.

[0086] The function of the capacitor array is to adjust the delay time by changing the number of load capacitors. The physical characteristics of capacitors dictate that there is no current in the static state: in the static state, the inverter output voltage is fixed, the voltage across the capacitor is stable, and there is no continuous flow of charge. Current is only generated when the dynamic signal flips, causing the capacitor to charge / discharge briefly. Therefore, the capacitor array does not constitute a current path in the static state, further ensuring that the fine-tuning unit has no static power consumption.

[0087] Based on the above principle analysis, it can be seen that the entire dual-ring structure only generates dynamic current briefly when the signal is flipped, in the coarse-adjustment inverter, fine-adjustment inverter, and capacitor. There is no current consumption when the signal is static, so the average current during the cycle is only in the microamp level.

[0088] Figure 4 and Figure 5 The simulation was implemented using a 28nm process. Figure 4 and Figure 5 Examples are given respectively. , The simulation results of the output phase and power consumption are shown. Figure 4 The invention demonstrates the improvement in phase rotator resolution achieved by using a dual-ring structure in this embodiment, achieving a phase interval of almost 1 ps. Furthermore, the two-stage structure and coarse-tuned voltage-controlled delay line ensure good linearity of the phase rotator, thus guaranteeing its practicality. Figure 5 The transient power consumption distribution of the phase rotator is shown. It can be seen that there is no static current for most of the time during a complete working cycle, and there is only a dynamic transient current during the short time when the clock flips. The average current during the cycle is about 200uA, which is only in the microamp level. This is a significant reduction compared to the milliamp level of traditional phase interpolators, thus reducing power consumption.

[0089] As can be seen from the above, the technical advantages of the embodiments of the present invention can be summarized into four core dimensions: 1) High resolution: Breaking through process limitations, it is suitable for high-frequency precision control.

[0090] The dual-ring progressive segmentation achieves a phase spacing of less than 1ps. For example, the eight first delay units in the coarse adjustment loop generate a baseband phase with a spacing of 10~20ps, and the 16 second delay units in the fine adjustment loop refine it to a 1ps level spacing, far exceeding the process limit of traditional DLLs. For example, the minimum gate delay of traditional DLLs under the 28nm process is about 3ps.

[0091] The fine-tuning loop replaces gate delay dependence with "capacitor array load control". Even at a fixed process node, sub-ps level resolution can still be achieved by increasing the number of capacitors, meeting the stringent phase accuracy requirements of high-frequency SSCG such as 6.25~10GHz.

[0092] 2) Low power consumption: Dynamic power consumption design significantly improves energy efficiency.

[0093] Dynamic current is generated only when the clock signal flips, and there is no continuous current path when it is static. The average current during the cycle is in the microamp level. Compared with the milliamp-level static current of traditional current-mode phase interpolators, the power consumption is reduced by more than an order of magnitude, which is fully compatible with the low power consumption requirements of high-speed serial interface systems.

[0094] 3) High linearity: Coarse adjustment ensures basic performance and improves practical reliability.

[0095] All the first delay units of the coarse-tuned voltage-controlled delay line are synchronously controlled by the same first control voltage to ensure that the delay time of each unit is uniform, avoid phase interval disorder caused by the delay difference between units, provide a stable lower limit of linearity for the phase rotator, and ensure the clock jitter performance during high-frequency data transmission. Simulation verification shows that there are no irregular phase jumps.

[0096] 4) Strong adaptability: Full frequency band coverage and excellent structural reusability.

[0097] The fine-tuning loop uses a dual mechanism of adjusting the number of capacitor arrays and controlling the inverter switching speed to match the clock cycle of different operating frequencies, such as 6GHz→10GHz, and the cycle 166ps→100ps, without the need for additional module configuration adjustments.

[0098] The core protection point of this invention is the double-ring structure, which realizes a high-resolution, low-power phase rotator for SSCG. The technical effects such as high resolution, low power consumption, linearity, and adaptability are all based on this double-ring structure. Any scheme that uses coarse and fine adjustment double rings to realize SSCG phase rotation falls within the protection scope of this invention.

[0099] See Figure 6 This invention also provides a spread spectrum clock generator, which may include a digital control circuit and a phase rotator; the phase rotator is connected to the digital control circuit; the phase rotator is completely identical to the phase rotator of the spread spectrum clock generator in any of the above embodiments; the digital control circuit is used to generate a phase selection signal in real time and send it to the phase rotator; the phase rotator includes a coarse adjustment loop and a fine adjustment loop; the coarse adjustment loop is connected to the fine adjustment loop; the coarse adjustment loop is used to perform a first phase division on the input high-frequency differential clock signal to obtain multiple modulated phase signals, and select a target single-channel modulated phase signal from the multiple modulated phase signals based on the phase selection signal; the fine adjustment loop is used to perform a second phase division on the target single-channel modulated phase signal to obtain multiple high-resolution phase signals, and select a target single-channel high-resolution phase signal from the multiple high-resolution phase signals based on the phase selection signal.

[0100] The target single-channel high-resolution phase signal is used to achieve slight frequency fluctuations in the spread spectrum clock to suppress electromagnetic interference radiation peaks and reduce clock jitter of the spread spectrum clock, thereby meeting the high-frequency data transmission requirements of the high-speed serial interface.

[0101] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0102] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A phase rotator in a spread spectrum clock generator, characterized in that, include: Coarse adjustment loop and fine adjustment loop; The coarse adjustment loop is connected to the fine adjustment loop; The coarse adjustment loop is used to perform the first phase division on the input high-frequency differential clock signal to obtain multiple modulation phase signals, and select the target single modulation phase signal from the multiple modulation phase signals; The fine-tuning loop is used to perform a second phase split on the target single-channel modulated phase signal to obtain multiple high-resolution phase signals, and to select the target single-channel high-resolution phase signal from the multiple high-resolution phase signals.

2. The phase rotator in the spread spectrum clock generator according to claim 1, characterized in that, The coarse adjustment loop includes a coarse adjustment voltage-controlled delay line and a first phase selection circuit; the output terminal of the coarse adjustment voltage-controlled delay line is connected to the input terminal of the first phase selection circuit. The coarse-tuned voltage-controlled delay line is used to perform the first phase division of the high-frequency differential clock signal and output the multi-channel modulated phase signal. The first phase selection circuit is used to select the target single-channel modulated phase signal from the multiple modulated phase signals based on the phase selection signal.

3. The phase rotator in the spread spectrum clock generator according to claim 2, characterized in that, The fine-tuning loop includes a fine-tuning voltage-controlled delay line and a second phase selection circuit; the output terminal of the first phase selection circuit is connected to the input terminal of the fine-tuning voltage-controlled delay line, and the output terminal of the fine-tuning voltage-controlled delay line is connected to the input terminal of the second phase selection circuit. The fine-tuned voltage-controlled delay line is used to perform a second phase split on the target single-channel modulated phase signal and output the multi-channel high-resolution phase signal. The second phase selection circuit is used to select the target single high-resolution phase signal from the multiple high-resolution phase signals based on the phase selection signal.

4. The phase rotator in the spread spectrum clock generator according to claim 3, characterized in that, The coarse-adjusted voltage-controlled delay line includes a first number of first delay units; each first delay unit includes a first inverter, a second inverter, and an NMOS tail current source controlled by a first control voltage; The first inverter and the second inverter are connected in series; The bias current terminals of both the first inverter and the second inverter are connected to the first terminal of the NMOS tail current source; the second terminal of the NMOS tail current source is grounded. The first number of first delay units divide the high-frequency differential clock signal into a first number of modulated phase signals.

5. The phase rotator in the spread spectrum clock generator according to claim 4, characterized in that, When the first control voltage increases, the synchronous bias current output by the NMOS tail current source increases, reducing the on-resistance of the first inverter and the second inverter, thereby shortening the first delay time of the first delay unit. When the first control voltage decreases, the synchronous bias current output by the NMOS tail current source decreases, increasing the on-resistance of the first inverter and the second inverter, thereby prolonging the first delay time.

6. The phase rotator in the spread spectrum clock generator according to claim 4, characterized in that, The fine-tuning voltage-controlled delay line includes a second number of second delay units; the first number is less than the second number. Each of the second delay units includes a third inverter, a fourth inverter, and a capacitor array; the third inverter and the fourth inverter are connected in series; The output terminal of the third inverter and the input terminal of the fourth inverter are both connected to the first terminal of the capacitor array; the second terminal of the capacitor array is connected to the second control voltage; the capacitor array includes N selectable capacitors; N is a positive integer greater than 1; The second control voltage adjusts the load capacitance of the second delay unit by controlling the number of selectable capacitors connected in the capacitor array, so as to control the second delay time of the second delay unit to advance in steps with a preset precision.

7. The phase rotator in the spread spectrum clock generator according to claim 6, characterized in that, The second control voltage also changes the second delay time by adjusting the signal switching speed of the inverter to match the clock cycle requirements at different operating frequencies.

8. The phase rotator in the spread spectrum clock generator according to claim 4, characterized in that, The coarse adjustment loop further includes: a first phase detector, a first charge pump, and a first low-pass filter; the output signal of the first phase detector is processed by the first charge pump and the first low-pass filter to generate the first control voltage.

9. The phase rotator in the spread spectrum clock generator according to claim 6, characterized in that, The fine-tuning loop also includes a second phase detector, a second charge pump, and a second low-pass filter; the output signal of the second phase detector is processed by the second charge pump and the second low-pass filter to generate the second control voltage.

10. A spread spectrum clock generator, characterized in that, It includes a digital control circuit and a phase rotator in the spread spectrum clock generator as described in any one of claims 1-9; the phase rotator is connected to the digital control circuit; the digital control circuit is used to generate a phase selection signal in real time and send it to the phase rotator.

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