PCIe-based hardware acceleration AES remote dynamic encryption method and system

Abstract

The invention relates to the field of encryption processing, and provides a PCIe-based hardware acceleration AES remote dynamic encryption method and system. The method comprises the following steps: generating an initial encryption key, and transmitting the initial encryption key to a local host to obtain local key data; sending the to-be-encrypted data to the FPGA hardware module, and performing encryption processing on the to-be-encrypted data through a pipeline to obtain encrypted output data; during encryption processing, receiving updated key information through the double-buffer key storage structure, and switching keys through the updated key information to obtain dynamically updated encryption configuration; performing randomized adjustment on the time sequence characteristics and the power consumption characteristics in the pipeline encryption processing process to generate an encryption execution environment; and performing encryption processing on the encrypted output data based on the encryption execution environment and the dynamic update encryption configuration to obtain final output data. On-line dynamic updating of the secret key is achieved through a double-buffering secret key storage structure, the PCIe bus bandwidth is fully utilized in combination with a full-assembly-line encryption architecture, and side channel attacks are effectively resisted through random delay insertion and a power consumption balancing mechanism.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of encryption processing, in particular to a PCIe-based hardware-accelerated AES remote dynamic encryption method and system. BACKGROUND

[0002] With the rapid development of cloud computing, 5G communication and financial technology, data encryption has become the core technology in the field of information security. Traditional data encryption schemes mainly rely on CPU software implementation, such as using OpenSSL library to execute AES encryption algorithm. In typical application scenarios, servers are connected to high-speed storage devices or network adapters through PCIe interfaces, and need to perform real-time encryption transmission on a large amount of data. Existing software encryption schemes usually adopt a fixed key management strategy, and the key is loaded into the memory at system initialization and remains unchanged throughout the running period. Some high-performance application scenarios introduce FPGA hardware acceleration cards, which implement parallel encryption processing by porting the AES algorithm to FPGA logic resources, which can achieve certain performance improvement compared with pure software solutions. In terms of key management, existing technologies mostly use local storage methods to save key files in server hard disks or secure chips, and protect them through operating system access control mechanisms. In terms of PCIe data transmission, traditional schemes use polling or interrupt methods to handle DMA transmission, and the host CPU needs to frequently participate in data transfer process and perform encryption operations in the software layer before writing the results back to the target device.

[0003] However, the existing technology has the following shortcomings: First, the performance bottleneck problem of software encryption scheme is prominent, and in the PCIe Gen3 x8 link environment, the CPU encryption throughput based on OpenSSL can only reach 1.2GB / s, which is far lower than the theoretical bandwidth of PCIe of 6.4GB / s, causing serious bandwidth waste and failing to meet the needs of high-speed storage and real-time communication; second, the static key management mechanism has major security risks, and the long-term fixed use of the key increases the risk of being cracked, and once the key is leaked, the key needs to be replaced by interrupting the business and restarting the system, which seriously affects the service continuity; third, the existing FPGA encryption scheme lacks effective side-channel attack protection measures, and attackers can infer key information by analyzing the power consumption waveform or timing characteristics in the encryption process, especially in cloud environments and shared hardware platforms, which face higher security threats; fourth, the protection of end-to-end key transmission is insufficient, and the transmission process of the key from the management server to the encryption device lacks multi-layer encryption protection, and the key exists in the host memory in plaintext or weakly encrypted form, which is vulnerable to memory dump attacks or man-in-the-middle attacks; finally, the process of DMA transmission and encryption processing is not closely connected, and data needs to be copied multiple times between the host memory, PCIe bus and FPGA, introducing additional delay overhead, and CPU participating in data transfer occupies a large amount of computing resources, reducing the overall efficiency of the system. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, the present invention aims to provide a hardware-accelerated AES remote dynamic encryption method and system based on PCIe.

[0005] This invention provides a PCIe-based hardware-accelerated AES remote dynamic encryption method, comprising: S1: Generate an initial encryption key through the key management server, and transmit the initial encryption key to the local host through a secure transmission channel to obtain local key data; S2: Send the data to be encrypted to the FPGA hardware module, and encrypt the data to be encrypted through a pipeline according to the local key data to obtain encrypted output data; S3: When the pipeline performs encryption processing, it receives updated key information through a double-buffered key storage structure, and switches the key through the updated key information to obtain a dynamically updated encryption configuration; S4: Based on the anti-side channel attack protection mechanism, the timing and power consumption characteristics of the pipeline encryption process are randomly adjusted to generate an encryption execution environment; S5: Based on the encrypted execution environment and the dynamically updated encryption configuration, perform encryption processing on the encrypted output data to obtain the final output data.

[0006] According to the hardware-accelerated AES remote dynamic encryption method based on PCIe provided by the present invention, step S1 further includes: S11: On the key management server, a temporary key pair is generated using the elliptic curve key exchange algorithm, and the public key data in the temporary key pair is extracted. S12: Send the public key data to the local host via a TLS encrypted channel, and receive the device public key information returned by the local host; S13: Perform key negotiation calculation based on the device public key information and the private key of the key management server to generate a shared session key; S14: Encapsulate and encrypt the AES encryption key to be distributed using the shared session key to obtain the key transmission payload; S15: The key transmission payload is transmitted to the key receiving interface of the FPGA hardware module through the user-mode API, and after the key is decapsulated, it is stored in the key buffer to obtain the local key data.

[0007] According to the hardware-accelerated AES remote dynamic encryption method based on PCIe provided by the present invention, step S2 further includes: S21: Align and pad the data to be encrypted in the host memory according to the AES block length to generate a standardized data block sequence; S22: Construct a DMA descriptor structure, which includes a source address field, a destination address field, a data length field, and a control flag field; S23: Write the memory address of the standardized data block sequence into the source address field, write the physical address of the FPGA hardware module into the target address field, and start DMA transfer; S24: The standardized data block sequence is converted into AXI Stream data stream format by the PCIe XDMA controller, and metadata tag information is injected; S25: Input the AXI Stream data stream into the pipeline processing unit of the AES encryption core, and perform multiple rounds of cryptographic transformation operations in combination with the local key data to obtain encrypted output data.

[0008] According to the hardware-accelerated AES remote dynamic encryption method based on PCIe provided by the present invention, the multi-round cipher transformation operation step S25 further includes: S251: Extract the original key from the local key data and generate an extended key sequence through the key expansion unit; S252: Perform an XOR operation between the plaintext data block in the AXI Stream data stream and the initial round key of the extended key sequence to obtain the initial state matrix; S253: The initial state matrix is ​​sequentially fed into a multi-level pipeline encryption stage, wherein each pipeline encryption stage performs byte substitution, row shifting, column obfuscation and round key addition operations, and the final state matrix is ​​extracted from the output of the final pipeline encryption stage and sent back to the host memory as the encrypted output data.

[0009] According to the hardware-accelerated AES remote dynamic encryption method based on PCIe provided by the present invention, step S3 further includes: S31: Set up a first key register group and a second key register group inside the FPGA hardware module, wherein the first key register group serves as the active key storage area and the second key register group serves as the standby key storage area; S32: When the updated key information is received, the latest key data is written into the second key register group, and the first key register group is kept performing the current encryption operation; S33: Monitor the encryption completion signal of the current data block, and switch the selection state of the key selector in the next clock cycle after the encryption completion signal is valid; S34: Using the key selector, the second key register group is set as the updated active key storage area, and the original active key storage area is converted to a standby state to obtain the dynamically updated encryption configuration.

[0010] According to the hardware-accelerated AES remote dynamic encryption method based on PCIe provided by the present invention, step S4 further includes: S41: Generate a pseudo-random number sequence based on a linear feedback shift register, and extract the low-order bits from the pseudo-random number sequence as delay control parameters; S42: Based on the delay control parameters, insert idle states with variable clock cycles between pipeline encryption levels to make the processing time intervals of adjacent data blocks exhibit random distribution characteristics. S43: Collect the power-on initial state value of the SRAM cell inside the FPGA hardware module, perform error correction processing on the power-on initial state value through the fuzzy extractor algorithm, and generate a unique root key for the device; S44: Perform a binding operation between the device's unique root key and the local key data to bind the encryption operation to a specific hardware device; S45: Dynamically adjusts the drive strength parameters of the output drive circuit of the FPGA hardware module to keep the power consumption waveform under different data modes within the preset standard deviation range, thereby generating an encrypted execution environment.

[0011] This invention also provides a PCIe-based hardware-accelerated AES remote dynamic encryption system, comprising: A remote management terminal is used to generate and manage encryption keys, and the remote management terminal includes a key management server and a web management platform; The local host is used to receive key information issued by the remote management terminal and to execute encryption task scheduling. The local host includes PCIe drivers and user-space API libraries. An FPGA hardware module, connected to the local host via a PCIe bus, is used to perform hardware-accelerated encryption operations. The FPGA hardware module includes: The PCIe XDMA controller is used to implement PCIe protocol communication and perform DMA data transfer. The AES encryption core, employing a fully pipelined architecture, is used to perform AES-256 encryption on input data. The security module is used to generate a unique key root for the device and to implement key binding; The key memory contains a double-buffered key register set for storing the current encryption key and the key to be updated; The side-channel attack resistance module is used to randomize the timing and power consumption characteristics of the encryption process.

[0012] According to the present invention, a hardware-accelerated AES remote dynamic encryption system based on PCIe is provided, wherein the AES encryption core includes: A key expansion unit is used to expand the original key into a multi-round key sequence; The multi-level encryption round operation unit includes a byte substitution module, a row shifting module, a column obfuscation module, and a round key addition module in each level. The levels are pipelined and separated by registers. The initial round key addition unit, located before the multi-level encryption round operation unit, is used to perform an XOR operation between the plaintext data and the initial round key; The output buffer unit is used to temporarily store the encryption results and connect to the DMA return channel.

[0013] According to the present invention, a hardware-accelerated AES remote dynamic encryption system based on PCIe is provided, wherein the double-buffered key register group includes: The first key register array contains multiple single-bit registers for storing the first set of encryption keys; The second key register array contains multiple single-bit registers for storing the second set of encryption keys; A key selection multiplexer selects a set of keys from the first key register array and the second key register array according to the key selection signal and outputs it to the AES encryption core; A key update controller is used to detect new key write requests and switch the logical state of the key selection signal after the current data block encryption is completed.

[0014] According to the present invention, a PCIe-based hardware-accelerated AES remote dynamic encryption system is provided, wherein the anti-side-channel attack module includes: A linear feedback shift register is used to generate a pseudo-random number sequence through XOR feedback at specific tap positions; A random delay insertion unit extracts low-order bits from the pseudo-random number sequence and inserts a random delay of multiple clock cycles between round operations of the AES encryption core; The power consumption balancing circuit, including a drive intensity dynamic adjustment module and a virtual load matching module, is used to smooth the power consumption waveform of the FPGA output port under different data modes. The power consumption monitoring unit is used to collect real-time power consumption data and calculate the standard deviation of the power consumption waveform, and feed the standard deviation back to the drive intensity dynamic adjustment module.

[0015] This invention firstly, through the coordinated operation of a double-buffered key storage structure and a key selection multiplexer, enables key switching to be completed while the encryption pipeline is continuously running. Key update time can be controlled within an extremely short period without interrupting any currently processed data blocks, thus completely solving the problem of system downtime required for key replacement in traditional solutions. This significantly improves system service continuity and security response speed, allowing keys to be rotated frequently according to security policies without affecting business operations. Secondly, through the tight coupling of the PCIe XDMA controller and the multi-level fully pipelined AES encryption core, data is directly transferred from host memory to the encryption pipeline via DMA, eliminating the need for CPU involvement in intermediate processing. This improves encryption throughput compared to traditional software encryption schemes and also enhances PCIe Gen3 performance. The x8 bandwidth utilization fully leverages the transmission capabilities of the hardware bus. Furthermore, the invention utilizes a pseudo-random delay insertion mechanism generated by a linear feedback shift register and dynamic drive strength adjustment of the power balancing circuit. This results in an unpredictable random distribution of the timing characteristics of the encryption process, reducing the standard deviation of the power consumption waveform and effectively resisting side-channel attacks such as differential power analysis and timing attacks, significantly enhancing the physical security of the key. Additionally, the invention binds the device-unique root key generated by the SRAM PUF with the transmission key, ensuring a strong association between the encryption operation and the specific hardware device. Even if the key data is copied to other devices, decryption cannot be performed normally. Combined with the end-to-end protection system built using the TLS 1.3 encryption channel and elliptic curve key exchange algorithm, the entire process from key generation and transmission to use is under encrypted protection, completely eliminating the risk of key leakage during transmission and storage. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of a PCIe-based hardware-accelerated AES remote dynamic encryption method provided in this application embodiment; Figure 2 This is a schematic diagram of a PCIe-based hardware-accelerated AES remote dynamic encryption system architecture provided in an embodiment of this application. Detailed Implementation

[0017] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 As shown, this invention provides a PCIe-based hardware-accelerated AES remote dynamic encryption method, comprising: S1: Generate an initial encryption key through the key management server, and transmit the initial encryption key to the local host through a secure transmission channel to obtain local key data.

[0020] Step S1 further includes: S11: On the key management server, a temporary key pair is generated using the elliptic curve key exchange algorithm, and the public key data in the temporary key pair is extracted.

[0021] Furthermore, the key management server integrates a key generation engine, which uses a hardware random number generator as an entropy source to generate random number seeds. Specifically, this invention first performs key pair generation based on the SECP384R1 elliptic curve parameters. This curve is defined on a 384-bit prime field. The key generation engine generates a 384-bit random integer as the private key d. Then, the private key d is multiplied by the curve base point G to obtain the public key point Q. Subsequently, this invention serializes the coordinate data of the public key point according to the DER encoding format to generate a byte sequence containing the curve identifier, public key coordinates, and length information. The obtained byte sequence is the extracted public key data.

[0022] S12: Send the public key data to the local host via a TLS encrypted channel, and receive the device public key information returned by the local host.

[0023] In step S12, this invention aims to establish an encrypted channel between the server and the local host via the TLS 1.3 protocol. Specifically, during the TLS handshake process, the server encapsulates the public key data generated in step S11 in the payload field of the ServerKeyExchange message. This message includes a message type identifier (0x0C), a message length field, and the public key data payload. Upon receiving this message, the local host extracts the public key data from the payload field and performs DER decoding to recover the server's public key coordinates. The local host's FPGA hardware module's internal security module has pre-generated a device-specific key pair, where the device private key is stored in the SRAM PUF protected area, and the device public key is stored in a readable register. The local host driver reads the coordinates of the device public key, serializes it into 120 bytes of data according to DER encoding, encapsulates it in a ClientKeyExchange message, and sends it back to the server.

[0024] S13: Perform key negotiation calculation based on the device public key information and the private key of the key management server to generate a shared session key.

[0025] Furthermore, in step S13, after receiving the device's public key, the key management server executes the elliptic curve Diffie-Hellman key exchange algorithm. The server uses its own private key and the device's public key to perform a scalar multiplication operation to calculate the shared point. Subsequently, this invention extracts the x-coordinate of the shared point as the original key material. Since the x-coordinate of the shared point is 384 bits of data, this invention performs a SHA-384 hash operation on it, and truncates the first 256 bits of the hash output as the shared session key. This shared session key is a 256-bit symmetric key. The local host uses the device's private key and the server's public key to perform the same scalar multiplication calculation. Due to the mathematical properties of elliptic curve key exchange, the shared point calculated by the local host is the same as the result calculated by the server. After the same SHA-384 hash processing, the same shared session key is obtained.

[0026] S14: Use the shared session key to encapsulate and encrypt the AES encryption key to be distributed, and obtain the key transmission payload.

[0027] Furthermore, this invention uses the shared session key generated in step S13 as the encryption key to perform AES-GCM authentication encryption on the AES encryption key generated by the key generation engine of the key management server. During the encryption process, a random initialization vector is first generated. Then, the AES encryption key is used as plaintext input, and the shared session key is used as the encryption key input to the AES-GCM algorithm, outputting 32 bytes of ciphertext and a 16-byte authentication tag. Subsequently, this invention concatenates the initialization vector, ciphertext, and authentication tag in sequence to form the key transmission payload. Finally, this invention further calculates the SHA3-256 hash value of the key transmission payload as the HMAC, and appends this 32-byte HMAC to the end of the key transmission payload.

[0028] S15: The key transmission payload is transmitted to the key receiving interface of the FPGA hardware module through the user-mode API, and after the key is decapsulated, it is stored in the key buffer to obtain the local key data.

[0029] In step S15, the present invention sends the payload to the local host through the TLS channel. After the local host user-space API library receives the payload, it first separates the HMAC at the end, recalculates the SHA3-256 hash value of the key transmission payload, and compares the calculation result with the received HMAC byte by byte to verify the integrity. After the verification is successful, the initialization vector, ciphertext, and authentication tag are extracted from the payload.

[0030] Subsequently, the user-space API library passes these three parts of data to the PCIe driver through the ioctl system call. The driver writes the data into the reserved address area of ​​the FPGA's BAR space: the initialization vector is written to 0x1000-0x100B, the ciphertext is written to 0x100C-0x102B, and the authentication tag is written to 0x102C-0x103B.

[0031] After detecting a write event, the FPGA's internal security module reads these three parts of data and performs AES-GCM decryption using the locally stored shared session key. During decryption, the validity of the tag is first verified; if the verification is successful, 32 bytes of plaintext are output, which is the AES encryption key.

[0032] The security module performs an XOR operation between the AES encryption key and the device-unique root key generated by the SRAM PUF to obtain the binding key. This binding key is written into the first key register array of the key memory, where each of the 256 registers stores one bit of the binding key. This binding key is the local key data.

[0033] S2: The data to be encrypted is sent to the FPGA hardware module, and the data to be encrypted is processed through a pipeline according to the local key data to obtain encrypted output data.

[0034] Step S2 further includes: S21: The data to be encrypted is aligned and padded in the host memory according to the AES block length to generate a standardized data block sequence.

[0035] Furthermore, the data to be encrypted is stored in a user-space buffer in the host memory. The starting address of this buffer is recorded as the user address, and the data length is the original number of bytes. This invention first calculates the padded length by adding 15 to the original number of bytes, dividing by 16, and then multiplying by 16. This calculation rounds the data length up to an integer multiple of 16 bytes. This invention uses the PKCS#7 padding standard, calculating the number of padded bytes as the padded length minus the original number of bytes. This invention allocates a new buffer of the padded length in the host memory and copies the original data from the user address to the beginning of the new buffer. Then, padded bytes are appended to the end of the new buffer, with each padded byte set to the number of padded bytes. For example, if the original data is 42 bytes, the padded length is calculated to be 48 bytes, and the padded byte count is 6. Therefore, the values ​​0x06 are filled in positions 43 to 48. The new buffer after padding contains a complete 16-byte aligned data block, which is the normalized data block sequence.

[0036] S22: Construct a DMA descriptor structure, which includes a source address field, a destination address field, a data length field, and a control flag field.

[0037] This invention allocates an aligned DMA descriptor structure in kernel space. This structure contains multiple fields: a target address field stores the physical address of the standardized data block sequence in the host physical memory; a data length field stores the padded length value; a control flag field, where bit 0 is set to 1 to indicate an encryption operation, bits 1 to 7 store the key index value indicating which key is used, and bit 8 is set to 1 to indicate that an interrupt is triggered after DMA is completed; a status field, initially set to 0, which is written by the FPGA hardware to indicate whether the transmission is complete or an error code is present; and a next descriptor pointer field, which is set to 0 if there are no subsequent descriptors, and stores the physical address of the next descriptor to form a linked list if batch transmission is required. The remaining bytes of the structure are padded with 0 to maintain byte alignment.

[0038] S23: Write the memory address of the standardized data block sequence into the source address field, write the physical address of the FPGA hardware module into the target address field, and start DMA transfer.

[0039] This invention maps a standardized data block sequence buffer from user space to kernel space via a system call, and locks the physical page corresponding to the buffer using a page locking function to prevent it from being swapped out by the operating system. Then, a virtual address to physical address function is called to obtain the physical address of the buffer, and this address value is written to the source address field of the DMA descriptor. This invention adds the base address of the FPGA encryption module to a preset offset to obtain the target physical address, and writes this address to the target address field. The padded length value is written to the data length field, and a control flag value is written to the control flag field to indicate encryption operation and enable interrupts. This invention initiates DMA transfer through the XDMA register in the PCIe configuration space. Specifically, the physical address of the descriptor structure is written to the XDMA descriptor queue base address register, the number of descriptors is written to the queue length register, and the start command is written to the control register. After detecting the start command, the XDMA controller reads 64 bytes of descriptor data from the descriptor queue base address, parses the source address, target address, and data length fields, and begins data transfer.

[0040] S24: The standardized data block sequence is converted into AXI Stream data stream format by the PCIe XDMA controller, and metadata tag information is injected.

[0041] Furthermore, the PCIe XDMA controller's internal DMA engine generates memory read request transactions starting from the host memory source address, according to the PCIe transaction layer protocol. Each transaction has a maximum payload of 256 bytes. The host memory controller responds to the read request and returns a completed transaction, with the payload containing the data content of a standardized sequence of data blocks. After receiving the completed transaction, the XDMA controller extracts the payload data and stores it in an internal 512-bit wide first-in-first-out buffer. When the buffer accumulates 512 bits (64 bytes) of data, the AXI interface conversion unit reads the data from the buffer and converts it to AXI Stream format. AXI Stream packets contain 512 bits of data carried by data signals. A data valid signal is set to 1 to indicate valid data, all 64 bits of the byte hold signal are set to 1 to indicate that all bytes are valid, and the tail packet signal is set to 1 for the last packet.

[0042] This invention injects metadata tag information into the 64-bit width of the user-defined signal. The lower 32 bits store the current key index value extracted from the control identifier field. Bits 33 to 48 store the processed data block count value, initially 0. Bits 49 to 56 store the operation mode extracted from bit 0 of the control identifier field; 0 indicates encryption. Bits 57 to 64 are filled with 0. Finally, the converted AXI Stream data stream is transmitted to the AES encryption core input port through a 512-bit wide data bus.

[0043] S25: Input the AXI Stream data stream into the pipeline processing unit of the AES encryption core, and perform multiple rounds of cryptographic transformation operations in combination with the local key data to obtain encrypted output data.

[0044] The multi-round cryptographic transformation operation in step S25 further includes: S251: Extract the original key from the local key data and generate an extended key sequence through the key expansion unit; S252: Perform an XOR operation between the plaintext data block in the AXI Stream data stream and the initial round key of the extended key sequence to obtain an initial state matrix; S253: Send the initial state matrix sequentially into a multi-level pipeline encryption stage, where each pipeline encryption stage performs byte substitution, row shifting, column obfuscation, and round key addition operations. The final state matrix is ​​extracted from the output of the final pipeline encryption stage and sent back to the host memory as the encrypted output data.

[0045] Furthermore, after receiving the AXI Stream data stream, the AES encryption core extracts 512 bits of data from the data signal, which contains four AES data blocks. This invention decomposes the 512 bits of data into four independent 128-bit plaintext blocks, designated as blocks 0 to 3. Subsequently, this invention extracts the key index value from the user-defined signal and reads the local key data from the first or second key register array of the key memory based on this index value. After receiving the local key data, the key expansion unit executes the AES-256 key expansion algorithm to generate 11 sets of 128-bit round keys. The expansion process includes byte looping, S-box substitution, and round constant XOR operation. The generated 11 sets of round keys, totaling 1408 bits of data, are stored in the expanded key register group.

[0046] The initial round key addition unit performs a 128-bit XOR operation between the 0th plaintext block and the 0th round key to obtain the initial state matrix. This initial state matrix is ​​input to the first-level pipeline encryption stage. Within this stage, the byte substitution module replaces the 16 bytes of the state matrix with their corresponding S-box output values ​​by looking up the S-box table. The row shifting module circularly shifts the first row of the state matrix left by 1 byte, the second row left by 2 bytes, and the third row left by 3 bytes. The column obfuscation module performs matrix multiplication on each column in the Galois field. The round key addition module XORs the result with the first-level key to obtain the first-level output state. The first-level output state is passed to the second-level encryption stage via a pipeline register. The same byte substitution, row shifting, column obfuscation, and round key addition operations are repeated, but using the second-level key. This process is executed sequentially in the 10-level pipeline. The 10th-level encryption stage outputs the final state matrix, which is a 128-bit ciphertext block. Similarly, the first, second, and third plaintext blocks are processed sequentially in the pipeline to obtain the corresponding ciphertext blocks.

[0047] Finally, this invention concatenates the four ciphertext blocks sequentially into 512-bit ciphertext data. This data is temporarily stored in the output buffer unit, and then the DMA engine generates a memory write request transaction to write it back to the host memory address. After completion, the XDMA controller sets the descriptor status field to a success flag and triggers an interrupt vector to notify the PCIe driver. The driver wakes up the wait queue of the user-space API library, and the user-space API library reads the ciphertext data from the host memory and copies it to the user-space output buffer. The data in this buffer is the encrypted output data.

[0048] S3: When the pipeline performs encryption processing, it receives updated key information through a double-buffered key storage structure, and switches the key through the updated key information to obtain a dynamically updated encryption configuration.

[0049] Step S3 further includes: S31: Set up a first key register group and a second key register group inside the FPGA hardware module, wherein the first key register group serves as the active key storage area and the second key register group serves as the standby key storage area.

[0050] Furthermore, the FPGA hardware module's internal key memory contains two completely independent key register arrays. The first key register array consists of 256 single-bit flip-flops, each storing one bit of local key data. The 256 flip-flops are arranged according to bit indices from 0 to 255, collectively forming a 256-bit key storage space. The second key register array also consists of 256 single-bit flip-flops, with the same structure as the first array.

[0051] In the system initialization phase, this invention writes the local key data obtained in step S15 bit by bit into the first key register group. The 0th bit of key data is written to flip-flop number 0, the 1st bit to flip-flop number 1, and so on until the 255th bit is written to flip-flop number 255. All flip-flops in the second key register group are initially set to 0. This invention sets the key selection signal to a single-bit register; an initial value of 0 indicates selection of the first key register group. Subsequently, a key selection multiplexer is connected to the outputs of both register groups. When the key selection signal is 0, the multiplexer transmits the 256-bit output of the first key register group to the AES encryption core; when the key selection signal is 1, it transmits the output of the second key register group. During the period when the key selection signal is 0, the first key register group acts as the active key storage area, continuously supplying keys to the encryption core, while the second key register group acts as the standby key storage area, remaining idle.

[0052] S32: When the updated key information is received, the latest key data is written into the second key register group, and the first key register group is kept performing the current encryption operation.

[0053] In step S32, the remote key management server generates a new 256-bit AES key and transmits it to the local host via the TLS channel following the process in steps S11 to S15. After receiving the encrypted key transmission payload, the user-space API library initiates a key update request via a system call. This request contains 92 bytes of payload data.

[0054] After the PCIe driver responds to the request, it writes the payload data into the FPGA's configuration register space, writes the initialization vector to the base address plus 0x1000, writes the ciphertext to the base address plus 0x100C, writes the authentication tag to the base address plus 0x102C, and writes the update flag to the base address plus 0x1040 and sets it to 1.

[0055] Once the FPGA's internal key update controller detects that the update flag has changed to 1, it reads three parts of data from the designated address: the initialization vector, the ciphertext, and the authentication tag. Subsequently, the security module uses the shared session key to perform AES-GCM decryption on the ciphertext. It first verifies whether the 16 bytes of data in the authentication tag match the recalculated tag. If they match, the output 32 bytes of plaintext, which is the new AES key. This new key is XORed bit-by-bit with the device's unique root key to generate a new binding key. The 256 bits of this binding key are written bit-by-bit to the second key register group, with the 0th bit written to the 0th trigger, and so on up to the 255th bit. During the writing process, the key selection signal remains at 0. The first key register group continues to supply the original key data to the currently executing encryption pipeline. Each stage of the 10-stage pipeline of the AES encryption core continuously processes the input plaintext data blocks, performing byte substitution, row shifting, column obfuscation, and round key addition operations.

[0056] S33: Monitor the encryption completion signal of the current data block, and switch the selection state of the key selector in the next clock cycle after the encryption completion signal is valid.

[0057] Furthermore, after encrypting a 128-bit data block, the 10th pipeline encryption stage of the AES encryption core generates an encryption completion signal in its output buffer unit. This signal is a single-bit pulse signal lasting for one clock cycle. The key update controller internally includes a completion signal monitoring circuit. The input of this circuit is connected to the encryption completion signal line, and the output is connected to the control logic of the key selection signal.

[0058] The monitoring circuit samples the encryption completion signal level at each rising edge of the clock. When the sampled value changes from 0 to 1, it indicates that the current data block is encrypted. In the same clock cycle in which the encryption completion signal is detected as valid, this invention does not immediately change the key selection signal, but instead stores the switching request in an internal single-bit switching request register.

[0059] At the rising edge of the next clock cycle, the switching control logic reads the value of the switching request register. If the value is 1, it performs a toggle operation on the key selection signal. The toggle operation inverts the current value of the key selection signal; if it is currently 0, it becomes 1, and if it is currently 1, it becomes 0. This toggle takes effect on the rising edge of the next clock cycle, at which point it is ensured that the data block currently being processed in the pipeline has been output from stage 10. New data blocks entering the pipeline will use the new key starting from the initial round key addition unit.

[0060] S34: Using the key selector, the second key register group is set as the updated active key storage area, and the original active key storage area is converted to a standby state to obtain the dynamically updated encryption configuration.

[0061] Furthermore, in step S34, after the key selection signal flips from 0 to 1, the control terminal of the key selection multiplexer detects the change in the selection signal. Internally, the multiplexer consists of a parallel array of 256 two-to-one selectors. Each selector receives the output of the corresponding bit from the first and second key register groups as two inputs, and determines which output to use based on the key selection signal. When the key selection signal becomes 1, all 256 selectors switch simultaneously, passing the 256-bit output of the second key register group as the 256-bit output of the multiplexer to the key input port of the AES encryption core.

[0062] After receiving the new 256-bit key, the key expansion unit re-executes the key expansion operation to generate 11 new round keys. The 0th round key is directly taken from the first 128 bits of the input key. The 1st round key is obtained by performing byte looping and S-box replacement on the last 4 bytes of the 0th round key, XORing it with the round constant, and then XORing it with the first 4 bytes of the 0th round key. Subsequent round keys are generated in sequence through similar operations.

[0063] After the expansion is complete, the new round key sequence overwrites the old data in the expanded key register group. At this time, the second key register group becomes a new active key storage area, continuously supplying new key data to the encryption pipeline. After the key selection signal of the first key register group becomes 1, it is no longer selected by the multiplexer, and this group of registers enters a standby state, still retaining the old key data in the registers but not outputting it to the encryption core.

[0064] If a key update request is received again, the new key will be written to the first key register group which is in standby mode at this time. The key will be switched again through the same completion signal monitoring and selection signal toggling mechanism. The timing of the switching mechanism ensures that each key switch occurs at the data block boundary and the switching delay does not exceed 10 nanoseconds. The pipeline does not need to stop or insert idle cycles during the entire switching process, and the obtained configuration is the dynamically updated encryption configuration.

[0065] S4: Based on the side-channel attack protection mechanism, the timing and power consumption characteristics in the pipeline encryption process are randomly adjusted to generate an encryption execution environment.

[0066] Step S4 further includes: S41: Generate a pseudo-random number sequence based on a linear feedback shift register, and extract the low-order bits from the pseudo-random number sequence as delay control parameters.

[0067] Furthermore, the FPGA hardware module's internal anti-side-channel attack module includes a 32-bit linear feedback shift register, which consists of 32 flip-flops connected in series. During system initialization, the shift register is loaded with a non-zero initial value, which is a seed extracted from the power-on state value acquired by the SRAM PUF. At each rising clock edge, the shift register performs shift and feedback operations, performing a four-input XOR operation on the outputs of the 31st, 21st, 1st, and 0th flip-flops, with the XOR result serving as the feedback bit. Subsequently, all flip-flops are synchronously shifted left by one bit, with the 31st bit receiving the feedback bit value, and the remaining bits receiving the output of the previous bit sequentially. After one shift and feedback operation, the 32-bit value of the register is updated to a new pseudo-random number, and this operation is continuously executed to generate a pseudo-random number sequence. The random delay insertion unit extracts the 0th and 1st bits from the current 32-bit output of the shift register; these two bits are combined to form an integer value from 0 to 3, which serves as the delay control parameter.

[0068] S42: Based on the delay control parameters, insert idle states with variable clock cycles between pipeline encryption levels to make the processing time intervals of adjacent data blocks exhibit random distribution characteristics.

[0069] Furthermore, the 10 pipeline encryption levels of the AES encryption core are connected through pipeline registers. In this invention, a delay control circuit is inserted after each pipeline register. The circuit receives delay control parameters and the state matrix output from the upper level. Internally, it contains a counter and a data holding register. The initial value of the counter is set to the value of the delay control parameter.

[0070] When the upper-level state matrix arrives, if the counter value is 0, the state matrix is ​​immediately passed to the next stage, and new delay control parameters are obtained from the pseudo-random number sequence to reload the counter. If the counter value is non-zero, the state matrix is ​​stored in the data holding register. The counter decrements by 1 every clock cycle, and only when it decrements to 0 is the held data output to the next stage. Since the delay control parameters range from 0 to 3, 0 to 3 clock cycles of idle states are inserted between each pipeline stage, making the time interval between adjacent data blocks entering the pipeline and being output randomly distributed.

[0071] S43: Collect the power-on initial state value of the SRAM cell inside the FPGA hardware module, perform error correction processing on the power-on initial state value through the fuzzy extractor algorithm, and generate a unique root key for the device.

[0072] Furthermore, upon power-up of the FPGA hardware module, each storage bit of the internal SRAM memory cell is randomly initialized to either 0 or 1. This invention selects 256 SRAM memory cells as the entropy source for the physically unclonable function, and immediately reads the bit values ​​of these 256 cells as the initial power-up state value. Subsequently, this invention inputs the initial power-up state value into the fuzzy extractor circuit. During its first run, this circuit generates 512 bits of auxiliary data using a BCH error-correcting code encoder and stores it in non-volatile memory. Each subsequent power-up reads the new 256-bit initial power-up state value and the stored 512-bit auxiliary data, performs error detection and correction using the BCH decoder, flips the erroneous bits in the initial power-up state value to restore the correct values, and outputs 256 bits of stable data after error correction. Finally, this invention performs a SHA-256 hash operation on this stable data, and the 256-bit hash output serves as the device's unique root key.

[0073] S44: Bind the device's unique root key to the local key data to bind the encryption operation to a specific hardware device.

[0074] In step S44, the local key data obtained in step S15 is a 256-bit binding key, which is generated by XORing the transmitted AES encryption key with the device's unique root key. The internal key binding operation unit of the security module contains a 256-bit XOR gate array. One input of this array is connected to the binding key, and the other input is connected to the device's unique root key. The XOR gate array performs an XOR operation on corresponding bits of the two inputs. The 0th bit of the binding key is XORed with the 0th bit of the root key to obtain the 0th bit of the unbinding key, and so on up to the 255th bit. Since the binding key is equal to the AES key XORed with the root key, the result of the unbinding operation is the original AES key. This unbound AES key is passed to the key expansion unit to generate a round key sequence for use in the encryption pipeline. Because the device's unique root key is generated by a specific hardware SRAM PUF and cannot be copied, the encryption operation is strongly bound to the specific FPGA hardware device that generates the root key.

[0075] S45: Dynamically adjusts the drive strength parameters of the output drive circuit of the FPGA hardware module to keep the power consumption waveform under different data modes within the preset standard deviation range, thereby generating an encrypted execution environment.

[0076] Furthermore, regarding the current magnitude when the FPGA output driver circuit controls the chip pins to transmit signals externally, this invention integrates a dynamic drive strength adjustment module in the output driver circuit. This module includes a digital-to-analog converter and a drive strength register. Subsequently, the power consumption monitoring unit samples the current value of the FPGA core power supply in each clock cycle, accumulating the current sampling values ​​for 256 consecutive clock cycles within a sliding window, and calculating the average and standard deviation of these 256 sampling values. Following this, the dynamic drive strength adjustment module adjusts the drive strength parameters according to the bit pattern of the current encrypted data. When the number of 1 bits in the output data is greater than the number of 0 bits, the drive strength parameter is decreased; when the number of 0 bits is greater than the number of 1 bits, the drive strength parameter is increased. The adjusted parameters are converted into an analog voltage by the digital-to-analog converter and applied to the gate of the output driver transistor. Meanwhile, the virtual load matching module activates an additional virtual load circuit during low-activity cycles, consuming current to compensate for power consumption differences, thus reducing the standard deviation of the power consumption waveform under different data modes to a preset range.

[0077] S5: Based on the encrypted execution environment and the dynamically updated encryption configuration, perform encryption processing on the encrypted output data to obtain the final output data.

[0078] In step S5, the AES encryption core operates within the encryption execution environment generated in step S4. Data transmission between pipeline stages is controlled by random delays, and the power consumption characteristics of the output drive circuit are balanced. The encryption core uses the dynamically updated encryption configuration from step S3 to read the latest key data from the currently active key register group. This key is debonded with the device's unique root key to generate a valid AES key. The key expansion unit generates a currently valid round key sequence based on this AES key. Each stage of the pipeline uses this round key sequence to perform encryption transformation on the input data block. The encrypted output data generated in step S2 is the result of encryption using the old key, and the data block to be encrypted in step S5 is the newly arrived data. The new data block is converted to AXI Stream format through steps S21 to S24 and enters the encryption core. After being XORed with the new round 0 key in the initial round key addition unit, it enters the pipeline. When the data block is transmitted in the 10-stage pipeline, the delay control circuit between each stage inserts random idle periods according to the delay control parameters generated in step S41, making the processing timing of the data block unpredictable. The ciphertext data output from level 10 is transmitted back to the host memory through the output buffer unit. During the transmission, the output drive circuit outputs a signal according to the drive strength adjusted in step S45, and the power consumption waveform remains balanced. The ciphertext data in the host memory is the final output data, which is generated by encryption with the updated key. The timing and power consumption characteristics of the encryption process are resistant to side-channel attacks.

[0079] like Figure 2As shown, the present invention also provides a PCIe-based hardware-accelerated AES remote dynamic encryption system, comprising: A remote management terminal is used to generate and manage encryption keys, and the remote management terminal includes a key management server and a web management platform; The local host is used to receive key information issued by the remote management terminal and to execute encryption task scheduling. The local host includes PCIe drivers and user-space API libraries. An FPGA hardware module, connected to the local host via a PCIe bus, is used to perform hardware-accelerated encryption operations. The FPGA hardware module includes: The PCIe XDMA controller is used to implement PCIe protocol communication and perform DMA data transfer. The AES encryption core, employing a fully pipelined architecture, is used to perform AES-256 encryption on input data. The security module is used to generate a unique key root for the device and to implement key binding; The key memory contains a double-buffered key register set for storing the current encryption key and the key to be updated; The side-channel attack resistance module is used to randomize the timing and power consumption characteristics of the encryption process.

[0080] The AES encryption core includes: A key expansion unit is used to expand the original key into a multi-round key sequence; The multi-level encryption round operation unit includes a byte substitution module, a row shifting module, a column obfuscation module, and a round key addition module in each level. The levels are pipelined and separated by registers. The initial round key addition unit, located before the multi-level encryption round operation unit, is used to perform an XOR operation between the plaintext data and the initial round key; The output buffer unit is used to temporarily store the encryption results and connect to the DMA return channel.

[0081] The double-buffered key register group includes: The first key register array contains multiple single-bit registers for storing the first set of encryption keys; The second key register array contains multiple single-bit registers for storing the second set of encryption keys; A key selection multiplexer selects a set of keys from the first key register array and the second key register array according to the key selection signal and outputs it to the AES encryption core; A key update controller is used to detect new key write requests and switch the logical state of the key selection signal after the current data block encryption is completed.

[0082] The side-channel attack resistance module includes: A linear feedback shift register is used to generate a pseudo-random number sequence through XOR feedback at specific tap positions; A random delay insertion unit extracts low-order bits from the pseudo-random number sequence and inserts a random delay of multiple clock cycles between round operations of the AES encryption core; The power consumption balancing circuit, including a drive intensity dynamic adjustment module and a virtual load matching module, is used to smooth the power consumption waveform of the FPGA output port under different data modes. The power consumption monitoring unit is used to collect real-time power consumption data and calculate the standard deviation of the power consumption waveform, and feed the standard deviation back to the drive intensity dynamic adjustment module.

[0083] The following describes a PCIe-based hardware-accelerated AES remote dynamic encryption system according to the present invention, with specific parameter configurations.

[0084] The encryption system provided by this invention consists of three main parts. A remote management terminal establishes an encrypted communication link with the local host via the TLS 1.3 protocol. A key management server integrates a hardware random number generator to generate a 256-bit AES key conforming to the FIPS 140-2 standard, and the key is stored in an encryption database. A web management platform provides a visual configuration interface, allowing administrators to set the key rotation cycle and encryption strategy through a browser. The configuration parameters are converted to JSON format and sent to the key management server via a TLS channel.

[0085] The local host's PCIe driver runs in the operating system kernel space and accesses the FPGA hardware module's base address register BAR0 through the PCIe configuration space. This register maps to a 64KB configuration area of ​​the XDMA controller. The driver calls memory allocation functions to allocate a 4MB physically contiguous DMA buffer in host memory. The virtual and physical address mapping of the buffer is stored in the page table. The user-space API library runs in user space and interacts with the PCIe driver through system calls, providing interfaces for encrypted request submission, memory page locking, and zero-copy transfers.

[0086] The FPGA hardware module connects to the local host via a PCIe Gen3 x8 physical link. This link uses 8 differential signal pairs, each operating at 8.0 GT / s with a theoretical bandwidth of 7.877 GB / s. The FPGA chip is a Xilinx Virtex-7 series, with an internal PCIe XDMA controller occupying 15,000 logic units, 24 DSP modules, and 2 Mb of memory, implementing PCIe transaction layer, data link layer, and physical layer protocols. The AES encryption core occupies 2,800 logic units, 48 ​​DSPs, and 8 BRAM blocks, operating at 250 MHz. The security module occupies 800 logic units, including 256 SRAM units serving as the PUF entropy source, BCH codec, and SHA-256 hash engine. The key memory uses 512 flip-flops to form two 256-bit register arrays. The side-channel attack mitigation module occupies 600 logic units.

[0087] The PCIe XDMA controller is configured using Xilinx IP core version 4.1, with parameters set via Vivado's Tcl scripts. The PCIe physical location is set to X0Y1, with an 8-channel link width, a 512-bit AXI data width, and a clock frequency of 250MHz. Internally, the controller includes a descriptor resolver, a data transfer controller, and an interrupt manager. The descriptor resolver reads 64-byte aligned DMA descriptors from host memory, containing the source address, destination address, data length, control fields, status fields, and a next descriptor pointer. The data transfer controller generates a PCIe Memory Read Request (TLP) based on the source address and data length. Each TLP has a maximum payload of 256 bytes. After the host returns a Completion TLP, the controller extracts the data and stores it in a 512-bit wide FIFO buffer with a depth of 512 entries (32KB capacity). The AXI interface conversion unit reads data from the FIFO and converts it to AXI Stream format. The 512-bit TDATA signal carries the data, and the 64-bit TUSER signal carries metadata including the key index, data block count, and operating mode. The interrupt manager uses the MSI-X mechanism to configure two interrupt vectors. Vector 0 notifies that the DMA transfer is complete, and vector 1 notifies that the key update is ready. Interrupt messages are written to the host at a specified address via Memory Write TLP.

[0088] The AES encryption core comprises a key expansion unit, an initial round key addition unit, a 10-level encryption round operation unit, and an output buffer unit. The key expansion unit's input is connected to the 256-bit output of the key selection multiplexer. It executes the AES-256 key expansion algorithm to generate 11 sets of 128-bit round keys, totaling 1408 bits, which are stored in the expanded key register set. The expansion process takes 14 clock cycles. The initial round key addition unit receives 512 bits of data from the AXI Stream, containing four 128-bit plaintext blocks. Internally, four sets of 128-bit XOR gate arrays XOR each plaintext block with the round 0 key to generate an initial state matrix. The 10-level encryption round operation unit adopts a pipelined structure. Each stage contains four modules: byte substitution, row shifting, column obfuscation, and round key addition. The byte substitution module processes 16 bytes using 16 parallel S-box lookup tables. The row shifting module performs a circular left shift. The column obfuscation module performs matrix multiplication in the GF(2^8) field. The round key addition module performs XOR operations. Level 10 does not include a column obfuscation module and outputs a 128-bit final ciphertext block to the output buffer unit. The output buffer unit contains a 512-bit wide FIFO with a depth of 64 entries. It concatenates four consecutive ciphertext blocks into 512-bit data. The DMA engine reads data from the FIFO, generates a Memory Write Request (TLP), and writes it back to host memory.

[0089] The double-buffered key register array occupies 512 D flip-flops, divided into two groups of 256 each. The 256 flip-flops in the first key register array are numbered from 0 to 255, with the clock input connected to the 250MHz system clock. The write enable signal controls data writing. The second register array has the same structure but its write enable signal is independent. The outputs of both groups are connected to a key selection multiplexer, which consists of 256 parallel 2-to-1 selectors. Based on the key selection signal, it selects to output either the first or second group of 256-bit data to the AES encryption core. The key update controller is a state machine module with four states: idle, receive, wait, and switch. In the receive state, a new 256-bit key is read from the BAR space and written to the standby register group, taking 256 clock cycles. In the wait state, the encryption completion signal of the AES encryption core is monitored; upon detecting a signal transition, the system enters the switch state. In the switch state, the key selection signal is toggled, the multiplexer switches its output source, the original standby group becomes the new active group, and the key expansion unit regenerates the round key sequence. The switching delay does not exceed 10 nanoseconds.

[0090] The anti-side-channel attack module includes a 32-bit linear feedback shift register, composed of 32 cascaded D flip-flops. The feedback logic is a four-input XOR gate at bits 31, 21, 1, and 0. The register is initialized with a 32-bit seed read from the SRAM PUF and generates a new pseudo-random number every clock cycle. A random delay insertion unit extracts bits 0 and 1 from the 32-bit output as delay control parameters, ranging from 0 to 3. Ten delay control circuits are inserted between each stage of the pipeline, each containing a 2-bit counter and a 128-bit data holding register, inserting idle states for 0 to 3 clock cycles based on the delay control parameters. The power consumption monitoring unit's current sensor measures the FPGA core power supply current at a sampling rate of 250MHz. A 256-entry circular buffer stores the most recent 256 sampled values, and the statistics module calculates the standard deviation every 256 cycles. The drive strength dynamic adjustment module adjusts the drive strength parameters based on the number of 1 bits of output data and the standard deviation. These parameters are converted into gate voltages by a digital-to-analog converter to control the output transistors. The virtual load matching module includes 16 100-ohm resistors and 16 NMOS switches, which adjust the virtual load according to pipeline activity, reducing the power consumption standard deviation from 50mA to 19mA.

[0091] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A hardware-accelerated AES remote dynamic encryption method based on PCIe, characterized in that, include: S1: Generate an initial encryption key through the key management server, and transmit the initial encryption key to the local host through a secure transmission channel to obtain local key data; S2: Send the data to be encrypted to the FPGA hardware module, and encrypt the data to be encrypted through a pipeline according to the local key data to obtain encrypted output data; S3: When the pipeline performs encryption processing, it receives updated key information through a double-buffered key storage structure, and switches the key through the updated key information to obtain a dynamically updated encryption configuration; S4: Based on the anti-side channel attack protection mechanism, the timing and power consumption characteristics of the pipeline encryption process are randomly adjusted to generate an encryption execution environment; S5: Based on the encrypted execution environment and the dynamically updated encryption configuration, perform encryption processing on the encrypted output data to obtain the final output data.

2. The PCIe-based hardware-accelerated AES remote dynamic encryption method according to claim 1, characterized in that, Step S1 further includes: S11: On the key management server, a temporary key pair is generated using the elliptic curve key exchange algorithm, and the public key data in the temporary key pair is extracted. S12: Send the public key data to the local host via a TLS encrypted channel, and receive the device public key information returned by the local host; S13: Perform key negotiation calculation based on the device public key information and the private key of the key management server to generate a shared session key; S14: Encapsulate and encrypt the AES encryption key to be distributed using the shared session key to obtain the key transmission payload; S15: The key transmission payload is transmitted to the key receiving interface of the FPGA hardware module through the user-mode API, and after the key is decapsulated, it is stored in the key buffer to obtain the local key data.

3. The PCIe-based hardware-accelerated AES remote dynamic encryption method according to claim 1, characterized in that, Step S2 further includes: S21: Align and pad the data to be encrypted in the host memory according to the AES block length to generate a standardized data block sequence; S22: Construct a DMA descriptor structure, which includes a source address field, a destination address field, a data length field, and a control flag field; S23: Write the memory address of the standardized data block sequence into the source address field, write the physical address of the FPGA hardware module into the target address field, and start DMA transfer; S24: The standardized data block sequence is converted into AXI Stream data stream format by the PCIe XDMA controller, and metadata tag information is injected; S25: Input the AXI Stream data stream into the pipeline processing unit of the AES encryption core, and perform multiple rounds of cryptographic transformation operations in combination with the local key data to obtain encrypted output data.

4. The PCIe-based hardware-accelerated AES remote dynamic encryption method according to claim 3, characterized in that, The multi-round cryptographic transformation operation in step S25 further includes: S251: Extract the original key from the local key data and generate an extended key sequence through the key expansion unit; S252: Perform an XOR operation between the plaintext data block in the AXI Stream data stream and the initial round key of the extended key sequence to obtain the initial state matrix; S253: The initial state matrix is ​​sequentially fed into a multi-level pipeline encryption stage, wherein each pipeline encryption stage performs byte substitution, row shifting, column obfuscation and round key addition operations, and the final state matrix is ​​extracted from the output of the final pipeline encryption stage and sent back to the host memory as the encrypted output data.

5. The PCIe-based hardware-accelerated AES remote dynamic encryption method according to claim 1, characterized in that, Step S3 further includes: S31: Set up a first key register group and a second key register group inside the FPGA hardware module, wherein the first key register group serves as the active key storage area and the second key register group serves as the standby key storage area; S32: When the updated key information is received, the latest key data is written into the second key register group, and the first key register group is kept performing the current encryption operation; S33: Monitor the encryption completion signal of the current data block, and switch the selection state of the key selector in the next clock cycle after the encryption completion signal is valid; S34: Using the key selector, the second key register group is set as the updated active key storage area, and the original active key storage area is converted to a standby state to obtain the dynamically updated encryption configuration.

6. The PCIe-based hardware-accelerated AES remote dynamic encryption method according to claim 1, characterized in that, Step S4 further includes: S41: Generate a pseudo-random number sequence based on a linear feedback shift register, and extract the low-order bits from the pseudo-random number sequence as delay control parameters; S42: Based on the delay control parameters, insert idle states with variable clock cycles between pipeline encryption levels to make the processing time intervals of adjacent data blocks exhibit random distribution characteristics. S43: Collect the power-on initial state value of the SRAM cell inside the FPGA hardware module, perform error correction processing on the power-on initial state value through the fuzzy extractor algorithm, and generate a unique root key for the device; S44: Perform a binding operation between the device's unique root key and the local key data to bind the encryption operation to a specific hardware device; S45: Dynamically adjusts the drive strength parameters of the output drive circuit of the FPGA hardware module to keep the power consumption waveform under different data modes within the preset standard deviation range, thereby generating an encrypted execution environment.

7. A hardware-accelerated AES remote dynamic encryption system based on PCIe, characterized in that, include: A remote management terminal is used to generate and manage encryption keys, and the remote management terminal includes a key management server and a web management platform; The local host is used to receive key information issued by the remote management terminal and to execute encryption task scheduling. The local host includes PCIe drivers and user-space API libraries. An FPGA hardware module, connected to the local host via a PCIe bus, is used to perform hardware-accelerated encryption operations. The FPGA hardware module includes: The PCIe XDMA controller is used to implement PCIe protocol communication and perform DMA data transfer. The AES encryption core, employing a fully pipelined architecture, is used to perform AES-256 encryption on input data. The security module is used to generate a unique key root for the device and to implement key binding; The key memory contains a double-buffered key register set for storing the current encryption key and the key to be updated; The side-channel attack resistance module is used to randomize the timing and power consumption characteristics of the encryption process.

8. A PCIe-based hardware-accelerated AES remote dynamic encryption system according to claim 7, characterized in that, The AES encryption core includes: A key expansion unit is used to expand the original key into a multi-round key sequence; The multi-level encryption round operation unit includes a byte substitution module, a row shifting module, a column obfuscation module, and a round key addition module in each level. The levels are pipelined and separated by registers. The initial round key addition unit, located before the multi-level encryption round operation unit, is used to perform an XOR operation between the plaintext data and the initial round key; The output buffer unit is used to temporarily store the encryption results and connect to the DMA return channel.

9. A PCIe-based hardware-accelerated AES remote dynamic encryption system according to claim 7, characterized in that, The double-buffered key register group includes: The first key register array contains multiple single-bit registers for storing the first set of encryption keys; The second key register array contains multiple single-bit registers for storing the second set of encryption keys; A key selection multiplexer selects a set of keys from the first key register array and the second key register array according to the key selection signal and outputs it to the AES encryption core; A key update controller is used to detect new key write requests and switch the logical state of the key selection signal after the current data block encryption is completed.

10. A PCIe-based hardware-accelerated AES remote dynamic encryption system according to claim 7, characterized in that, The anti-side-channel attack module includes: A linear feedback shift register is used to generate a pseudo-random number sequence through XOR feedback at specific tap positions; A random delay insertion unit extracts low-order bits from the pseudo-random number sequence and inserts a random delay of multiple clock cycles between round operations of the AES encryption core; The power consumption balancing circuit, including a drive intensity dynamic adjustment module and a virtual load matching module, is used to smooth the power consumption waveform of the FPGA output port under different data modes. The power consumption monitoring unit is used to collect real-time power consumption data and calculate the standard deviation of the power consumption waveform, and feed the standard deviation back to the drive intensity dynamic adjustment module.

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