Optical module, link optimization method and system

Abstract

This invention provides an optical module, a link optimization method, and a system. The method includes: a microcontroller sending gain values ​​to a continuous-time linear equalizer (LPO) for equalization of an input voltage signal; a time processing module sampling the voltage signal output by the LPO to obtain sampled data; and the microcontroller determining the gain configuration of the LPO based on the sampled data at different gain values. Compared to existing technologies, this invention enables the module to achieve similar power consumption and latency as traditional LPOs while gaining adaptive capabilities previously only available in DSP solutions. It expands the applicable scenarios and deployment flexibility of LPO technology; simultaneously, it keeps link performance consistently near its optimal point, fundamentally avoiding the risk of continuous performance degradation leading to bit errors, and achieving intelligent maintenance of the link state.

Description

Technical Field

[0001] This invention belongs to the field of optical communication technology, specifically relating to an optical module, a link optimization method, and a system. Background Technology

[0002] In recent years, the rapid development of artificial intelligence, cloud computing, and 5G communication technologies has placed unprecedented demands on high-speed optical communication modules. In AI training clusters, ultra-large-scale data centers, and 5G fronthaul / midhaul networks, optical modules not only need to support higher speeds such as 800G / 1.6T, but also meet stringent requirements for low power consumption, low latency, and high reliability. This demand is driving optical communication technology towards higher performance and lower costs, while also posing new challenges to traditional optical module architectures.

[0003] Traditional optical modules generally employ digital signal processors (DSPs) for signal modulation, equalization, and error correction. While this ensures reliability over long distances, it also introduces significant power consumption and latency issues. For example, in an 800G optical module, the DSP chip's power consumption often exceeds 3W, resulting in an overall module power consumption of over 10W, placing immense pressure on data center cooling and power supply. Furthermore, the DSP's signal processing introduces a delay of approximately 100ns, making it difficult to meet the real-time requirements of high-speed interconnects between GPUs in AI clusters. In addition, DSP chips rely on advanced manufacturing processes, resulting in high costs and a constrained supply chain.

[0004] Therefore, to address the aforementioned technical issues, it is necessary to provide an optical module, link optimization method, and system decoupled from the DSP chip. Summary of the Invention

[0005] The purpose of this invention is to provide an optical module, a link optimization method and system, to solve the problem that the link optimization of optical modules in the prior art relies on DSP, which leads to the inability to meet the requirements in terms of power consumption, cost, latency and other aspects.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides an optical module comprising: a continuous-time linear equalizer and an adaptive engine;

[0008] The continuous-time linear equalizer is used to receive the input voltage signal and perform equalization processing on the voltage signal based on the gain value issued by the adaptive engine.

[0009] The input of the adaptive engine is connected to the output of the continuous-time linear equalizer. The adaptive engine is used to sample the output signal of the continuous-time linear equalizer and determine the gain configuration of the continuous-time linear equalizer based on the sampled data under different gain values.

[0010] In one or more embodiments of the present invention, the adaptive engine includes a time processing module and a microcontroller;

[0011] The input terminal of the time processing module is connected to the output terminal of the continuous-time linear equalizer. The time processing module is used to sample the output signal of the continuous-time linear equalizer and output the sampled data to the microcontroller.

[0012] The microcontroller's data port is connected to the time processing module, and its control port is connected to the control terminal of the continuous-time linear equalizer. The microcontroller is used to determine the gain configuration of the continuous-time linear equalizer based on the sampled data at different gain values.

[0013] In one or more embodiments of the present invention, the microcontroller sends gain values ​​to the continuous-time linear equalizer based on a preset gain sequence.

[0014] In one or more embodiments of the present invention, the gain sequence is sent by the host and stored in the microcontroller;

[0015] Alternatively, the gain sequence may be determined based on the neighborhood range of a preset gain value;

[0016] Alternatively, the gain sequence may be determined from multiple preset gain sequences based on the sampled data at the current gain value.

[0017] In one or more embodiments of the present invention, the microcontroller determines the signal quality index based on the sampled data at different gain values, and then determines the gain configuration of the continuous-time linear equalizer.

[0018] In one or more embodiments of the present invention, the time processing module further includes: a clock unit, a phase-locked loop, and a sampling module.

[0019] The clock unit is connected to the output of the continuous-time linear equalizer, and the clock unit is used to extract the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer.

[0020] The input terminal of the phase-locked loop is connected to the output terminal of the clock unit, and the phase-locked loop is used to generate a sub-clock signal based on the clock signal;

[0021] The sampling module is used to perform multiple signal acquisitions on the voltage signal output by the continuous-time linear equalizer based on the sub-clock signal to obtain the sampling data.

[0022] In one or more embodiments of the present invention, the phase-locked loop integrates a phase interpolator;

[0023] The phase interpolator is used to superimpose multiple phase-shifted signals to adjust the phase of the clock signal to obtain the sub-clock signal;

[0024] The phase-locked loop is used to lock the sub-clock signal and the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer, so that the frequency of the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer and the frequency of the sub-clock form a desired proportional relationship.

[0025] In one or more embodiments of the present invention, the phase interpolator generates a sub-clock signal for sampling by stepping multiple phase points within a preset interval of the clock signal.

[0026] In one or more embodiments of the present invention, the phase interpolator generates a sub-clock signal by stepping on multiple equally spaced phase points within a continuous preset interval of the same duration.

[0027] In one or more embodiments of the present invention, the sampling module includes an analog-to-digital converter, wherein the analog input terminal of the analog-to-digital converter is connected to the output terminal of the continuous time equalizer, the sampling clock input terminal is connected to the output terminal of the phase-locked loop, and the digital output terminal is connected to the data port of the microcontroller.

[0028] In one or more embodiments of the present invention, the sampling module includes a high-speed voltage comparator and a peak detection circuit;

[0029] The first input terminal of the high-speed voltage comparator is connected to the output terminal of the continuous-time linear equalizer to receive the voltage signal output by the continuous-time linear equalizer; the second input terminal of the high-speed voltage comparator is connected to the output terminal of the phase interpolator to receive the sub-clock signal.

[0030] The input terminal of the peak detection circuit is connected to the output terminal of the high-speed voltage comparator; the output terminal of the peak detection circuit is connected to the data port of the microcontroller.

[0031] In one or more embodiments of the present invention, the clock unit includes a clock extraction module and a clock recovery module;

[0032] The clock extraction module is used to extract the clock frequency from the voltage signal output by the continuous-time linear equalizer and output the original clock signal.

[0033] The input terminal of the clock recovery module is connected to the output terminal of the clock extraction circuit, and is used to perform phase locking and jitter filtering on the original clock signal to output the clock signal.

[0034] In one or more embodiments of the present invention, the optical module further includes a photodetector and a transimpedance amplifier connected in series;

[0035] The photodetector is used to receive optical signals and convert the optical signals into electrical signals;

[0036] The input terminal of the transimpedance amplifier is connected to the output terminal of the photodetector, and is used to convert the electrical signal into the input voltage signal and send the input voltage signal to the continuous-time linear equalizer.

[0037] Secondly, the present invention provides a link optimization method applied to the aforementioned optical module, comprising:

[0038] The microcontroller sends out a gain value so that the continuous-time linear equalizer can perform equalization processing on the input voltage signal.

[0039] The time processing module samples the voltage signal output by the continuous-time linear equalizer to obtain sampled data;

[0040] The microcontroller determines the gain configuration of the continuous-time linear equalizer based on the sampled data at different gain values.

[0041] In one or more embodiments of the present invention, the method specifically includes:

[0042] Extract the corresponding clock signal from the voltage signal output by the continuous-time linear equalizer;

[0043] Clock locking is performed on the clock signal to generate a sub-clock signal synchronized with the clock signal;

[0044] Based on the sub-clock signal, the voltage signal output by the continuous-time linear equalizer is sampled by analog-to-digital conversion to obtain sampled data.

[0045] In one or more embodiments of the present invention, the sampling data is a level value obtained by the time processing module sampling the voltage signal output by the continuous-time linear equalizer at a predetermined phase point of the sub-clock signal.

[0046] In one or more embodiments of the present invention, the method further includes:

[0047] A Cartesian coordinate system is constructed using phase and input voltage signal level values ​​as coordinate axis data;

[0048] Based on the sampled data, the signal waveform and / or eye diagram are reconstructed in the Cartesian coordinate system, and the signal quality index is calculated based on the reconstructed signal waveform and / or eye diagram.

[0049] In one or more embodiments of the present invention, the method specifically includes:

[0050] The time processing module steps through multiple phase points within a preset interval of the voltage signal output by the continuous-time linear equalizer.

[0051] At each phase point of the step, the voltage signal output by the continuous-time linear equalizer is sampled a preset number of times to obtain sampled data;

[0052] Determine the signal quality index corresponding to the sampled data, and determine the gain configuration of the continuous-time linear equalizer based on the signal quality index.

[0053] In one or more embodiments of the present invention, the preset intervals have equal period durations;

[0054] And / or the phase points based on the time processing module are evenly distributed within the preset interval.

[0055] In one or more embodiments of the present invention, extracting the corresponding clock signal from the voltage signal output by the continuous-time linear equalizer specifically includes:

[0056] The time processing module extracts the clock frequency from the voltage signal output by the continuous-time linear equalizer, and then outputs the original clock signal.

[0057] Alternatively, the original clock signal can be phase-locked and / or jitter filtered to obtain a processed clock signal.

[0058] In one or more embodiments of the present invention, the method further includes:

[0059] In response to a preset triggering condition, the microcontroller traverses a preset gain sequence and configures the continuous-time linear equalizer to a selected gain value.

[0060] The preset triggering conditions include one or more of the following: module power-on initialization, reconnection after link interruption, instructions issued based on the management interface, periodic calibration triggered by the microcontroller's internal timer, and signal quality indicators falling below a preset threshold.

[0061] In one or more embodiments of the present invention, the method further includes:

[0062] The currently determined gain value and their corresponding signal quality indicators Report to the host system;

[0063] If the currently determined gain value Greater than the gain value of the host system storage And the corresponding signal quality indicators Superior signal quality metrics compared to host system storage Then the host system increases the pre-emphasis and / or deemphasis coefficients of its transmit feedforward equalizer and updates the stored gain value to the currently determined gain value. And update the stored signal quality indicators to the corresponding signal quality indicators. ;

[0064] If the currently determined gain value Less than the stored gain value The host then reduces the pre-emphasis and / or deemphasis coefficients of the transmit feedforward equalizer and updates the stored gain value to the optimal gain value. Update the stored signal quality metrics to .

[0065] Thirdly, the present invention provides a link optimization method for an optical module, comprising:

[0066] The input signal is equalized based on the issued gain value, and sampled to obtain sampled data;

[0067] Based on the sampled data at different gain values, the gain configuration of the optical module is determined.

[0068] In one or more embodiments of the present invention, the method specifically includes:

[0069] Extract the corresponding clock signal from the input signal after equalization;

[0070] Clock locking is performed on the clock signal to generate a sub-clock signal synchronized with the clock signal;

[0071] Based on the sub-clock signal, the input signal after equalization is sampled to obtain sampled data.

[0072] In one or more embodiments of the present invention, the method further includes:

[0073] A Cartesian coordinate system is constructed using the phase and sampled values ​​of the input signal as coordinate axis data;

[0074] Based on the sampled data, a signal waveform and / or eye diagram are constructed in the Cartesian coordinate system, and a signal quality index is calculated based on the signal waveform and / or eye diagram.

[0075] In one or more embodiments of the present invention, calculating the signal quality index based on the signal waveform and / or eye diagram includes:

[0076] Based on the signal waveform and / or eye diagram, the opening degree and noise characteristics of multiple vertical eye diagrams are calculated respectively, and each vertical eye diagram corresponds to the image formed by a pair of adjacent signal levels on the signal waveform and / or eye diagram;

[0077] Based on the opening degree of each vertical eye diagram and its corresponding noise characteristics, the signal quality index corresponding to the signal waveform and / or eye diagram is determined.

[0078] In one or more embodiments of the present invention, the opening degree of multiple vertical eye diagrams is calculated, including:

[0079] The sampled data is classified according to a preset level range;

[0080] Calculate the statistical mean of the sampled data for each level interval;

[0081] The opening of the vertical eye diagram is calculated based on the difference in statistical means between adjacent level intervals constituting the vertical eye diagram.

[0082] In one or more embodiments of the present invention, the noise characteristics of multiple vertical eye diagrams are calculated, including:

[0083] The sampled data is classified according to the corresponding level range;

[0084] Calculate the standard deviation of the sampled data for each level interval;

[0085] The noise characteristics of the vertical eye diagram are calculated based on the sum of the standard deviations of adjacent level intervals constituting the vertical eye diagram.

[0086] In one or more embodiments of the present invention, the signal quality index corresponding to each vertical eye diagram is determined based on the opening degree of each vertical eye diagram and its corresponding noise characteristics, including:

[0087] Calculate the ratio of the opening to the noise characteristic of each vertical eye diagram in the signal waveform and / or eye diagram;

[0088] The signal quality index of the signal waveform and / or eye diagram is determined based on the minimum value of the ratio of the opening to the noise characteristic of each vertical eye diagram.

[0089] In one or more embodiments of the present invention, the method specifically includes:

[0090] Multiple phase points are stepped within a preset interval of the input signal after equalization processing;

[0091] At each phase point of the step, the input signal after equalization is sampled a preset number of times to obtain sampled data;

[0092] Determine the signal quality index corresponding to the sampled data, and determine the gain configuration based on the signal quality index.

[0093] In one or more embodiments of the present invention, the preset intervals have equal period durations;

[0094] The phase points, and / or the steps, are uniformly distributed within the preset interval.

[0095] In one or more embodiments of the present invention, the clock signal includes:

[0096] Extract the clock frequency from the input signal and output the original clock signal;

[0097] Alternatively, it can be a clock signal output based on phase-locked and jitter-filtered original clock signal.

[0098] Fourthly, the present invention provides a link optimization system, comprising:

[0099] The traversal module is used to perform equalization processing on the input signal based on the issued gain value and to sample and obtain sampled data;

[0100] A configuration module is used to determine the gain configuration of the optical module based on the sampled data at different gain values.

[0101] Compared with existing technologies, the optical module provided by this invention uses a microcontroller and a time processing module to replace the high-power real-time DSP processing. The time processing module can sample the output signal of the continuous-time linear equalizer, while the microcontroller can determine the gain configuration of the continuous-time linear equalizer based on the sampled data at different gain values. When channel characteristics change due to factors such as temperature drift, device aging, or changes in connection status, the optical module can promptly readjust the continuous-time linear equalizer to the optimal state, keeping the link performance near the best point. This fundamentally avoids the risk of continuous performance deterioration leading to bit errors and achieves intelligent maintenance of the link state. Attached Figure Description

[0102] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0103] Figure 1 This is a schematic diagram of the optical module architecture in one embodiment of the present invention;

[0104] Figure 2 This is a flowchart of a link optimization method in one embodiment of the present invention;

[0105] Figure 3 This is a flowchart of a link optimization method in another embodiment of the present invention;

[0106] Figure 4 This is a structural block diagram of a link optimization system according to one embodiment of the present invention;

[0107] Figure 5 This is a structural block diagram of an electronic device according to one embodiment of the present invention;

[0108] Figure 6 This is a schematic diagram of a portion of the hardware implementation in one embodiment of the present invention. Detailed Implementation

[0109] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0110] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0111] In existing technologies, a common approach to optimize signal transmission in optical module links is to integrate a digital signal processor (DSP) within the optical module. This approach relies on the powerful real-time processing capabilities of the DSP to perform complex processing on the received signal, including digital modulation and demodulation, fixed or limited adaptive digital equalization, and forward error correction. However, DSP chips themselves have high power consumption and significant processing delays. Furthermore, their algorithms are typically designed to cover worst-case channel conditions, making it difficult to perform refined, low-power real-time optimization for specific, time-varying channel environments. This results in high power consumption and cost for the entire optical module, increased signal processing delays, and an inability to meet the stringent requirements for low power consumption and low latency in applications such as artificial intelligence clusters and short-distance interconnects in data centers.

[0112] To address the shortcomings of existing technologies, the inventors of this technical solution propose a novel approach: abandoning high-power DSPs and instead employing an "optimization engine" built around a low-power microcontroller. This engine does not run continuously but is triggered when specific preset conditions are met (such as module power-on, timed triggering, or link performance degradation), entering the corresponding "optimization mode." In this mode, the optical module searches for the optimal gain configuration of the continuous-time linear equalizer through a systematic trial and evaluation process. This mechanism leverages the relatively slow changes in actual channel conditions, replacing continuous high-performance computing with periodic or event-driven optimization, thereby achieving an optimal balance between power consumption and efficiency while maintaining link performance.

[0113] To achieve the above ideas, this invention has made an innovative design in the optical module architecture: in the DSP-free optical module, an adaptive closed-loop system with a microcontroller as the core is constructed. The system senses the channel characteristics through equivalent time sampling and adjusts the gain configuration of the receiver equalizer based on the channel characteristics under different gain values. In this way, while maintaining the advantages of ultra-low power consumption and low latency, the link performance is self-optimized.

[0114] Please refer to the details. Figure 1 The diagram shows an architecture of an optical module provided by the present invention in one embodiment. This architecture specifically includes a Continuous Time Linear Equalizer (CTLE) 101 and an adaptive engine. The adaptive engine further includes a time processing module 102 and a microcontroller unit (MCU) 103.

[0115] Specifically, the continuous-time linear equalizer 101 is a type of linear analog equalization circuit that selectively boosts the high-frequency components of the signal by providing a high-pass frequency response opposite to that of the channel, thereby compensating for frequency-selective attenuation caused by the skin effect and dielectric loss, reducing inter-symbol interference (ISI), and improving eye diagram quality. In this embodiment of the invention, the parameters of the continuous-time linear equalizer 101 are adjusted in response to the calculation to obtain the gain configuration. The continuous-time linear equalizer 101 can be a programmable continuous-time linear equalizer.

[0116] In an embodiment of the present invention, a continuous-time linear equalizer 101 is embedded as an adjustable actuator in the optical module receiving link, responsible for real-time equalization of the input voltage signal. Its operation is based on a series of iteratively set gain values. By evaluating the output signal quality under each candidate gain configuration, the superiority or inferiority of the gain is determined. This process constitutes the core of link adaptive optimization; that is, the system gradually approaches the equalizer setting that can maximally compensate for channel impairments and achieve the best signal recovery effect through continuous trial and evaluation.

[0117] It should be noted that the microcontroller 103, described later, can send gain values ​​to the continuous-time linear equalizer 101 based on a preset gain sequence. This gain sequence contains multiple preset gain values; the gain value is a key adjustable parameter of the continuous-time linear equalizer 101, essentially a set of frequency-related values ​​used to describe the degree of amplification or attenuation of the signal at each frequency point, usually expressed in decibels (dB). The optimization process involves the system automatically searching for the optimal gain configuration that maximizes signal quality indicators (such as eye diagram opening and Q factor) under various channel conditions through algorithms. Therefore, the overall improvement in link performance can essentially be attributed to an adaptive process of dynamically filtering and locking the gain values ​​of the continuous-time linear equalizer 101 under the intelligent control of the microcontroller 103.

[0118] In one exemplary embodiment, the gain sequence is sent by the host and stored in the microcontroller 103; or the gain sequence is determined based on a neighborhood range of a preset gain value; or the gain sequence is determined from multiple preset gain sequences based on the sampled data at the current gain value. This embodiment of the invention does not impose any limitations on these aspects.

[0119] Based on the aforementioned architecture, in the optical module provided by this invention, the input terminal of the time processing module 102 is connected to the output terminal of the continuous-time linear equalizer 101. As an integrated signal acquisition and processing unit, its main function is to receive the frequency-compensated analog voltage signal output from the continuous-time linear equalizer (CTLE) 101, extract and / or recover the clock signal, sample the controllable phase, and output the sampled data to the microcontroller 103, providing data support for subsequent signal quality assessment and adaptive optimization. The time processing module 102 plays a crucial bridging role in the system, converting the signal from the analog domain to the digital domain; its performance directly determines the accuracy and reliability of the adaptive optimization process.

[0120] It should be noted that the time processing module 102 is flexible in its physical implementation in different embodiments of the present invention. It can be a single driver chip integrating multiple functions such as clock recovery, phase-locked loop, sampling, and data interface, or it can be composed of multiple electrically interconnected and functionally coordinated independent circuit modules. The embodiments of the present invention do not limit the specific implementation form, but focus on the completeness of its functional logic and its coordination mechanism with other parts of the system.

[0121] In one specific embodiment, the time processing module 102 can be divided into three main functional sub-modules: a clock unit, a phase-locked loop (PLL), and a sampling module. The clock unit is connected to the output of the continuous-time linear equalizer 101 and is responsible for extracting the corresponding clock signal from the input voltage signal. The input of the PLL is connected to the output of the clock unit and is used to generate a sub-clock signal based on the clock signal. The sampling module, based on the sub-clock signal, performs multiple samplings of the voltage signal output by the continuous-time linear equalizer 101 and sends the obtained sampling data to the microcontroller 103 to support subsequent signal reconstruction and quality analysis.

[0122] In one exemplary embodiment, the phase-locked loop may integrate a phase interpolator; the phase interpolator is used to superimpose multiple phase-shifted signals to adjust the phase of the clock signal to obtain the sub-clock signal; the phase-locked loop is used to lock the sub-clock signal and the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer 101, so that the frequency of the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer 101 forms a desired proportional relationship with the frequency of the sub-clock.

[0123] It should be noted that the sampling module is the core component of the time processing module 102, responsible for signal acquisition and digitization. Its design directly affects the accuracy, speed, and overall system cost of signal quality assessment. Based on different application requirements and performance trade-offs, this invention provides two optional implementation methods: implementing the sampling module function based on an analog-to-digital converter and implementing the sampling module function based on a high-speed voltage comparator and a peak detection circuit, as detailed below:

[0124] In the first implementation, the sampling module specifically includes an analog-to-digital converter (ADC). The analog input of the ADC is connected to the output of the continuous-time linear equalizer 101 to receive the equalized voltage signal; the sampling clock input is connected to the output of the phase interpolator to receive a low-frequency sampling clock (sub-clock signal) with adjustable phase and synchronized with the data clock; and the digital output is connected to the data port of the microcontroller 103 via a parallel or serial interface.

[0125] In this implementation, the system can acquire complete information on signal voltage changes over time, support software reconstruction of high-resolution eye diagrams, and calculate multiple quality indicators such as Q-factor, signal-to-noise ratio, and eye opening. Even in complex scenarios with high channel loss and severe inter-symbol interference, it can accurately evaluate the equalization effect and achieve global parameter optimization. It is suitable for long-distance or high-speed optical interconnection scenarios in data centers, or applications with complex channel conditions and extremely high requirements for signal integrity and link stability.

[0126] In the second implementation, the sampling module specifically includes a high-speed voltage comparator and a peak detection circuit. One input of the high-speed comparator is connected to the output signal of the continuous-time linear equalizer 101, and the other input is connected to a programmable reference voltage; its output is connected to the peak detection circuit, which can extract the peak voltage or average amplitude of the signal within a specific time window, convert it into amplitude information in analog or digital form, and finally output it to the microcontroller 103.

[0127] Based on this implementation method, multi-phase scanning and large-scale data acquisition are unnecessary, and the optimization process can be completed in microseconds, significantly reducing link establishment and re-optimization time. Simultaneously, it avoids high-precision ADCs and complex timing circuits, making the circuit easier to integrate and further reducing overall module cost and power consumption. It is suitable for short-distance data center interconnects or inter-board optical interconnects, as well as stable transmission environments where channel attenuation is primary and inter-symbol interference is insignificant.

[0128] On the other hand, regarding the clock unit in the time processing module 102, depending on the different requirements of the system for clock accuracy, jitter performance and cost structure, the present invention provides two optional implementation methods, including constructing the clock unit based solely on the clock extraction module; or constructing the clock unit based on both the clock extraction module and the clock recovery module.

[0129] Specifically, the clock extraction module can be used to perform clock extraction, that is, to initially capture a clock signal with the same frequency as the data rate from the incoming serial voltage signal data stream. Its goal is to find a periodic signal with the same frequency as the data rate from the data transition edges in the absence of an independent clock line. In embodiments of this invention, nonlinear processing (such as limiting, zero-crossing detection, square-law detection) or resonant circuits (such as LC resonators, SAW filters) can be used to enhance and select the implicit clock spectrum components in the data signal; this invention does not limit this. The extracted clock signal frequency is basically correct, but because the phase is not optimized, it contains a large amount of jitter from the data itself and the channel.

[0130] The clock recovery module can dynamically adjust the phase of the local oscillator based on the clock output from the clock extraction module through feedback control and other methods to eliminate errors and filter jitter, thereby recovering a clock signal with accurate frequency, phase lock, and extremely low jitter.

[0131] In the first embodiment, the clock unit only includes a clock extraction module, whose input is directly connected to the output of the continuous-time linear equalizer 101. The clock extraction module performs frequency detection and clock component extraction on the input voltage signal, and outputs a first clock signal synchronized with the data symbol rate. This architecture eliminates the need for complex clock recovery circuits, which helps reduce module complexity and hardware costs; moreover, the circuit structure is simple, and both static and dynamic power consumption are superior. It is suitable for short-distance, low-data-rate, or relatively stable channel quality optical interconnect environments, or for applications that are cost-sensitive and do not have extremely stringent clock accuracy requirements.

[0132] In the second implementation, the clock unit adds an independent clock recovery module to the clock extraction module, enabling deep shaping, jitter filtering, and phase stabilization of the clock signal. This significantly reduces clock jitter, improves the accuracy of sampling timing, and is beneficial for eye diagram reconstruction and signal quality assessment. It also provides a stable clock reference even with poor signal quality or significant channel impairments. This approach is suitable for applications with extremely high requirements for timing accuracy, jitter performance, and system stability.

[0133] Based on the aforementioned architecture, in the optical module provided by this invention, the microcontroller 103 occupies a central coordinating position. Its data port is connected to the time processing module 102 to receive raw sampled data; its control port is connected to the control terminal of the continuous-time linear equalizer 101 to generate a configuration signal based on the sampled data and send gain configuration instructions to control the iterative gain value of the continuous-time linear equalizer 101. The control method of the microcontroller 103 in this invention can be summarized as determining signal quality indicators based on the sampled data at different gain values, and then determining the gain configuration of the continuous-time linear equalizer 101. The signal quality indicators are related to at least one of Q factor, signal-to-noise ratio, eye diagram opening, and bit error rate. A detailed explanation of the control method will be provided later in the link optimization method provided by this invention.

[0134] It should also be noted that in the architecture of the optical module provided by this invention, the receiving link front end also includes key components for completing photoelectric conversion and preliminary signal conditioning: a photodetector and a transimpedance amplifier. These two components together constitute the first-level interface for the optical signal to enter the electrical domain processing, indirectly affecting the input signal quality of the subsequent adaptive optimization system.

[0135] The photodetector is typically implemented using a semiconductor photodiode. Its photosensitive surface receives the optical signal transmitted via optical fiber and linearly converts the intensity of the optical power into a corresponding weak current signal. The response speed, bandwidth, and sensitivity of this device determine the maximum data rate and receiving sensitivity that the system can support. The input of the transimpedance amplifier is directly connected to the output of the photodetector. Its core function is to convert the weak current signal output by the photodetector into a voltage signal using transimpedance gain, while providing low-noise amplification and bandwidth shaping. This amplifier not only boosts the signal amplitude but also serves as the first-stage analog conditioning circuit, partially suppressing high-frequency noise and matching the input impedance requirements of subsequent circuits. The voltage signal converted and amplified by this amplifier is the "input voltage signal" received by the continuous-time linear equalizer 101.

[0136] It should be noted that the optical module provided by this invention can be further configured with a user terminal for configuring custom parameters necessary for implementing this invention. Custom parameters may include, but are not limited to, the selection of gain values ​​in the candidate gain sequence, sampling intervals, etc., and this embodiment of the invention does not impose any limitations on these parameters. The user terminal may have computer software programs installed that match the link optimization method provided by this method; the user terminal may include, but is not limited to, portable electronic devices or wearable electronic devices such as desktop computers (PCs), smartphones, handheld computers, tablet computers, personal digital assistants (PDAs), etc., and this embodiment of the invention does not impose any limitations on the above.

[0137] Please refer to Figure 2 The diagram shown illustrates a link optimization process according to one embodiment of the present invention. This link optimization method, applied to the aforementioned optical module architecture of the present invention, specifically includes the following steps:

[0138] S201: The microcontroller sends out a gain value so that the continuous-time linear equalizer can perform equalization processing on the input voltage signal;

[0139] It is important to first clarify that, unlike traditional solutions that rely on digital signal processors (DSPs) for continuous, high-power real-time signal processing, the link optimization method proposed in this invention employs an intelligent, event-driven triggering mechanism. This method does not run continuously during module operation, but rather is activated based on preset specific conditions that reflect changes in system state or link performance, thereby achieving an optimal balance between power consumption, efficiency, and performance.

[0140] In an exemplary embodiment, the preset triggering conditions may include, but are not limited to: system state change, receiving external instructions, and internal performance detection data reaching a preset range. For system state changes, this may further include module power-on initialization and reconnection after link termination. In this scenario, the channel environment and / or channel characteristics may enter an unknown state or change. To ensure the rapid establishment of the optimal link state, the selection of a gain value can be triggered. For external instructions, there are often scenarios where users or hosts expect to actively initiate optimization training, indicating a need for system diagnosis, pre-optimization, or collaborative tuning, thus triggering the selection of a gain value. For internal performance detection data reaching a preset range, it often indicates that the link state has deteriorated and is difficult to meet the preset conditions. For example, if indicators that characterize signal quality, such as eye diagram opening and predicted bit error rate, drop to a preset threshold, link optimization needs to be triggered to dynamically re-optimize the link in order to achieve fault self-healing and performance resilience.

[0141] It is understood that in actual use cases, the triggering condition can be any one or more of the above conditions; at the same time, it can be triggered by the fulfillment of multiple conditions or by the fulfillment of any condition. This invention does not impose any restrictions on the specific selection of the triggering condition and the triggering mechanism.

[0142] A continuous-time linear equalizer, embedded as an adjustable actuator in the optical module's receiving link, performs equalization processing on the input voltage signal. Essentially, it shapes the input voltage signal in the frequency domain, providing high-frequency gain to compensate for high-frequency attenuation caused by the channel, thereby canceling inter-symbol interference and restoring clarity to the stretched and distorted digital pulse signal. In this embodiment of the invention, the equalization processing method of the continuous-time linear equalizer is not explicitly limited.

[0143] Furthermore, in this embodiment of the invention, the gain value can refer to the quantized representation of the specific frequency response curve exhibited by the continuous-time linear equalizer (CTLE) under a particular configuration. It is not a single numerical value, but rather a set of control words or register configurations used to set the internal circuit parameters of the CTLE. Each gain value corresponds to a working state of the CTLE, determining its compensation intensity for different frequency components in the input signal. The gain sequence is an ordered set of gain values, defined as a list of all CTLE configurations that the microcontroller plans to traverse and evaluate during a complete training cycle, and can be represented as:

[0144]

[0145] in, It is a gain sequence. For the first in the gain sequence Each gain value is a gain value, and the gain values ​​within the gain sequence can be updated in real time by the host.

[0146] Furthermore, the gain value issued by the microcontroller can originate from a preset gain sequence. In one embodiment, the gain sequence can be issued by the host through a corresponding management interface and stored in the microcontroller of the optical module. The gain sequence can be customized by the user terminal or generated by the host based on its own characteristics or network management strategies; this embodiment of the invention does not impose any limitations. In this embodiment, the host has a global perspective and can issue gain sequences optimized for the system, facilitating end-to-end collaborative optimization. Simultaneously, when working with a specific type of switching chip, a customized gain sequence can achieve optimal interoperability.

[0147] In another implementation, the gain sequence can be determined based on a neighborhood range of a preset gain value. For example, a center gain value for a typical channel can be preset during the module initialization phase. When training is triggered, the microcontroller uses this center gain value as a reference and generates a gain sequence within a certain positive and negative range according to a preset step size. This implementation is host-independent, has a small search range, and fast training speed, and can quickly find local optima. It is suitable for scenarios where channel characteristics are relatively stable and fluctuate only slightly around the initial value, such as internal links within a data center.

[0148] In another embodiment, the gain sequence can be determined from multiple preset gain sequences based on the sampled data at the current gain value. That is, multiple gain sequences are preset for different channel conditions. At the start of training, the microcontroller first performs a signal quality assessment under the current gain setting, and selects the most suitable preset sequence for the subsequent complete training process based on the assessment results. The signal quality assessment can refer to the calculation of signal quality indicators described below, or be evaluated based on relevant channel performance indicators; this embodiment of the invention does not limit this. This implementation is more suitable for scenarios with complex and variable channel conditions and can avoid getting trapped in local optima.

[0149] S202: The time processing module samples the voltage signal output by the continuous-time linear equalizer to obtain sampled data;

[0150] In an exemplary embodiment, this step may specifically include: extracting a corresponding clock signal from the voltage signal output by the continuous-time linear equalizer; performing phase locking on the clock signal to generate a sub-clock signal synchronized with the clock signal; and performing analog-to-digital conversion sampling on the voltage signal output by the continuous-time linear equalizer based on the sub-clock signal to obtain sampled data. The sampled data is the level value obtained by the time processing module sampling the voltage signal output by the continuous-time linear equalizer at a specific phase point of the sub-clock signal.

[0151] In one embodiment, the phase-locked loop with phase interpolation can integrate a phase interpolator in the frequency division feedback link or output terminal of the phase-locked loop. Its working process can be as follows: First, the phase-locked loop completes frequency locking, and the frequency of the output sub-clock signal is maintained at a fixed desired ratio with the frequency of the clock signal, that is, it is frequency synchronized with the clock signal extracted from the voltage signal output from the continuous-time linear equalizer.

[0152] For example, a phase-locked loop (PLL) locks the sub-clock signal and the high-frequency clock signal output by the CTLE, keeping the frequencies of the sub-clock and the high-frequency clock in a 1 / n relationship. In terms of phase, the two clock signals coincide at time t1, and after time t1+n, the phases of the two clocks coincide again.

[0153] Subsequently, the phase interpolator finely adjusts the phase of the output clock by superimposing multiple phase offset signals. Depending on the implementation scenario, the adjustment step size can reach the picosecond level. Furthermore, the phase control of the phase interpolator can be controlled by a microcontroller, enabling continuous / step phase adjustment without disrupting the frequency lock state of the PLL during the adjustment process.

[0154] It should be noted that, as described in the optical module architecture above, based on different system requirements for clock accuracy, jitter performance, and cost structure, this invention provides two optional implementation methods: constructing the clock unit using only the clock extraction module; or constructing the clock unit based on both the clock extraction module and the clock recovery module. Correspondingly, the clock signal extracted from the voltage signal output by the continuous-time linear equalizer can also be the original clock signal generated solely by the clock extraction module, or the clock signal output after phase locking and jitter filtering of the original clock signal.

[0155] It should also be noted that the process of performing phase interpolation on the clock signal to generate a sub-clock signal synchronized with the clock signal further includes the time processing module stepping through multiple phase points within a preset interval of the voltage signal output by the continuous-time linear equalizer; at each of the stepped phase points, the voltage signal output by the continuous-time linear equalizer is sampled a preset number of times to obtain sampled data. The stepped phase points are also the aforementioned specific phase points.

[0156] In one embodiment, the preset interval for interpolation can be set to have equal period durations; and / or the phase points, based on the stepping of the time processing module, can be uniformly distributed within the preset interval. Equal period durations ensure consistent time intervals for each sampling, avoiding time drift of sampling points caused by period jitter. Uniform distribution of phase points ensures that sampling points can uniformly cover the entire preset interval, preventing waveform distortion caused by uneven phase point distribution during subsequent waveform / eye diagram reconstruction. This improves the accuracy and reliability of signal quality indicator calculations and enhances the consistency and repeatability of the system.

[0157] To illustrate in more detail the implementation of data acquisition in the optical module according to the present invention, the following is a specific embodiment of the present invention, such as... Figure 6 As shown:

[0158] First, in one embodiment, a driver chip can be used to execute the functions of the time processing module. The microcontroller initializes and configures the basic function registers in the driver chip via a communication interface. These registers include power configuration registers, clock configuration registers, signal type and target indicator registers, and general setting registers. After configuration, the driver chip enters normal operating mode, and its internal voltage, clock, and signal processing links are all ready. Subsequently, the microcontroller accesses the general configuration registers and status registers to confirm that the driver chip is operating normally and that signal connections are stable and without loss.

[0159] Furthermore, the microcontroller (MCU) configures the link training register, enables the training function, and sets the number of samples for this training. After receiving the input signal, the driver chip obtains a clock synchronized with the data stream through its internal clock extraction circuit, and uses the phase discrimination and hold function to hold the signal level corresponding to each target phase at the analog output terminal (ADC_OUT), while generating an edge-triggered trigger signal on the trigger pin (ADC_TRIG).

[0160] When the microcontroller detects a trigger signal from the driver chip via its external input pin (EXT_IN), it indicates that phase-locked loop (PLL) has been completed and the signal has been stabilized. The microcontroller then initiates a rapid sampling of the signal level output by the driver chip using its internal analog-to-digital converter. Due to the strict timing requirements and high data throughput of this process, the microcontroller uses Direct Memory Access (DMA) to quickly transfer the sampled data to its internal memory for temporary storage. As the driver chip continues to generate trigger signals and corresponding levels, the microcontroller repeats the above sampling process until the number of samples reaches a preset target value, marking the completion of the data acquisition phase.

[0161] After data acquisition, the system obtains the raw signal level data corresponding to all phases. If the phase information and signal level values ​​are used as the horizontal and vertical axes of a two-dimensional coordinate system, respectively, these data points together constitute a complete raw eye diagram dataset. If visualization analysis is required, the data can be plotted on the coordinate system using host computer software to restore the intuitive eye diagram shape. If visualization is not required, all calculations are performed internally by the microcontroller: based on this dataset, key physical layer indicators such as eye height, eye width, extinction ratio, and jitter can be directly calculated, thereby deriving the signal quality indicators corresponding to the current gain value and providing a basis for adaptive equalization decisions.

[0162] S203: The microcontroller determines the gain configuration of the continuous-time linear equalizer based on the sampled data at different gain values.

[0163] It should be noted that determining the gain configuration of the continuous-time linear equalizer based on the sampled data under different gain values ​​mainly includes: determining the signal quality index corresponding to the sampled data based on the sampled data, and determining the gain configuration of the continuous-time linear equalizer based on the signal quality index.

[0164] Understandably, since the signal quality index corresponding to the calculated gain value is related to at least one of the Q factor, signal-to-noise ratio, vertical eye opening, or horizontal eye opening, the signal quality index naturally reflects the signal integrity level and transmission reliability of the current link under a specific CTLE gain setting. Therefore, the gain value with the largest signal quality index in the preset gain sequence is the optimal gain value obtained in this round of optimization.

[0165] Furthermore, in one embodiment, an eye diagram or corresponding signal waveform can be generated based on the sampled data. For example, a Cartesian coordinate system is constructed using phase and the level of the input voltage signal as coordinate axes; based on the sampled data, the signal waveform and / or eye diagram are reconstructed in the Cartesian coordinate system, and the signal quality index is calculated based on the reconstructed signal waveform and / or eye diagram. The signal quality index is positively correlated with at least one of Q-factor, signal-to-noise ratio, and eye opening; and / or the signal quality index is inversely correlated with bit error rate.

[0166] It should also be noted that, in an exemplary embodiment, the link optimization method can further be applied to the host, specifically including: setting the currently determined gain value... and their corresponding signal quality indicators Report to the host system; if the currently determined gain value Greater than the gain value of the host system storage And the corresponding signal quality indicators Superior signal quality metrics compared to host system storage Then the host system increases the pre-emphasis and / or deemphasis coefficients of its transmit feedforward equalizer and updates the stored gain value to the currently determined gain value. And update the stored signal quality indicators to the corresponding signal quality indicators. If the currently determined gain value Less than the stored gain value The host then reduces the pre-emphasis and / or deemphasis coefficients of the transmit feedforward equalizer and updates the stored gain value to the optimal gain value. Update the stored signal quality metrics to .

[0167] Based on this embodiment, by reporting the optimization results of the optical module, the host can determine the direction that the transmitter should adjust. For example, when the optical module requires higher gain ( > Furthermore, when the signal quality is better, it indicates that increasing the pre-emphasis at the transmitter (providing stronger high-frequency components) is beneficial to the overall link. This creates a positive loop for link optimization, enabling the invention to achieve synergistic optimization and better realize end-to-end global optimal performance.

[0168] Please refer to Figure 3 The diagram shown is a flowchart of a general link optimization method according to an embodiment of the present invention. This link optimization method specifically includes the following steps:

[0169] S301: Equalize the input signal based on the issued gain value and sample the signal to obtain sampled data;

[0170] It should be noted that, in an exemplary embodiment, signal quality monitoring can be implemented based on equivalent time sampling, specifically including: stepping multiple phase points within a preset interval of the input signal after equalization processing; and sampling the input signal after equalization processing a preset number of times at each of the stepped phase points to obtain sampling data.

[0171] Wherein, the preset intervals have equal period durations; and / or the stepped phase points are uniformly distributed within the preset intervals. For example, on the input voltage signal, within a single unit interval of the input voltage signal, the phase points can be selected at equal intervals along the time axis or in steps according to a preset pattern. One (e.g., 32) phase points Each phase point This represents a specific sampling moment in the data eye diagram. At each phase point... The input voltage signal is then processed using precise timing corresponding to that point. Repeated sampling to obtain One (e.g., 1024) voltage level data at that phase.

[0172] This process is equivalent to sampling the high-speed data stream using a low-frequency sampling clock synchronized with the high-speed data stream clock. Secondary sampling.

[0173] S302: Determine the gain configuration of the optical module based on the sampled data at different gain values.

[0174] Following the specific implementation method described above, at all phase points Collected from Each sample is phase-aligned in memory to reconstruct the signal waveform or eye diagram at the current CTLE gain value. Based on this waveform, a signal quality index associated with at least one of the following can be calculated: Q-factor, signal-to-noise ratio, vertical eye opening, or horizontal eye opening. The gain configuration of the optical module is then determined based on this signal quality index.

[0175] In an exemplary embodiment, calculating the signal quality index based on the signal waveform and / or eye diagram includes: calculating the opening degree and noise characteristics of a plurality of vertical eye diagrams based on the signal waveform and / or eye diagram, wherein each vertical eye diagram corresponds to an image formed by a pair of adjacent signal levels on the signal waveform and / or eye diagram; and determining the signal quality index corresponding to the signal waveform and / or eye diagram based on the opening degree of each vertical eye diagram and its corresponding noise characteristics.

[0176] Since the eye diagram's opening degree characterizes the signal waveform quality, a larger opening degree indicates better theoretical signal stability. Noise characteristics, on the other hand, characterize the signal's purity, reflecting the degree to which various random interferences cause the signal trajectory to deviate from the ideal path. This is manifested in the thickness and blurriness of the eye diagram lines; lower noise indicates stronger signal determinism. Therefore, the combination of these two quantities can overcome the limitations of a single indicator, systematically measuring signal performance. Furthermore, it more comprehensively and realistically reflects the signal's overall level in terms of tolerance and anti-interference capabilities, thus providing a reliable basis for adaptive equalization algorithms and accurately guiding the system to find the globally optimal operating point.

[0177] In one implementation, calculating the opening and noise characteristics of multiple vertical eye diagrams may include: classifying the sampled data according to preset level intervals; calculating the statistical mean and standard deviation of the sampled data for each level interval; calculating the opening of the vertical eye diagram based on the difference in the statistical means of adjacent level intervals constituting the vertical eye diagram; and calculating the noise characteristics of the vertical eye diagram based on the sum of the standard deviations of adjacent level intervals constituting the vertical eye diagram.

[0178] For example, in one specific embodiment, four-level pulse amplitude modulation (PAM-4) is used. Since PAM-4 has four levels (corresponding to symbols 00, 01, 10, and 11), a vertical eye diagram is formed between adjacent levels to distinguish adjacent symbols. The three eyes, from top to bottom, are: the upper eye corresponding to the open portion of the eye diagram between level 3 (11) and level 2 (10), which is located at the top of the eye diagram and reflects the distinction between the two highest levels; the middle eye corresponding to the open portion of the eye diagram between level 2 (10) and level 1 (01), which is located in the middle and reflects the distinction between the two middle levels; and the lower eye corresponding to the open portion of the eye diagram between level 1 (01) and level 0 (00), which is located at the bottom and reflects the distinction between the two lowest levels.

[0179] The sampling points corresponding to the three "eyes" of PAM-4 in the reconstructed waveform are classified separately. That is, the sample sets representing level 3 (11), level 2 (10), level 1 (01), and level 0 (00) are distinguished. The values ​​for each level are calculated. sample mean and standard deviation .

[0180] Furthermore, the eye height for each vertical eye diagram is calculated as follows:

[0181]

[0182]

[0183]

[0184] in, The vertical opening of the upper eyelid; The vertical opening of the middle eye; This refers to the vertical opening of the lower eyelid.

[0185] The equivalent noise for each vertical eye diagram is calculated as follows:

[0186]

[0187]

[0188]

[0189] in, The equivalent noise for the upper eyelid; This is the equivalent noise for the middle eye; This is the equivalent noise of the lower eye.

[0190] It should be noted that the method of calculating signal quality indicators based on the combination of equivalent noise and vertical eye diagram opening is not limited in the embodiments of the present invention. For example, in one implementation, the ratio of the opening of each vertical eye diagram to the noise characteristic can be calculated separately in the signal waveform and / or eye diagram; the signal quality indicator of the signal waveform and / or eye diagram is determined based on the minimum value of the ratio of the opening of each vertical eye diagram to the noise characteristic.

[0191] In other words, the bit error rate of the entire system at the current gain value is determined by the worst vertical eye diagram. This can be defined as follows: The minimum ratio of eye opening to noise in all vertical eye diagrams can be obtained based on the formula. Represented as:

[0192]

[0193] Please refer to Figure 4 As shown, based on the same inventive concept as the aforementioned link optimization method, one embodiment of the present invention provides a link optimization system 400, which includes: a traversal module 401 and a configuration module 402.

[0194] Specifically, the traversal module 401 is used to perform equalization processing on the input signal based on the issued gain value and sample to obtain sampled data; the configuration module 402 is used to determine the gain configuration of the optical module based on the sampled data under different gain values.

[0195] Please refer to Figure 5As shown, embodiments of the present invention also provide an electronic device 500, which includes at least one processor 501, a memory 502 (e.g., non-volatile memory), a main memory 503, and a communication interface 504, and the at least one processor 501, memory 502, main memory 503, and communication interface 504 are connected together via an internal bus 505. The at least one processor 501 is used to invoke at least one program instruction stored or encoded in the memory 502, so that the at least one processor 501 performs various operations and functions of the link optimization methods described in the various embodiments of this specification.

[0196] In the embodiments of this specification, electronic device 500 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile electronic device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable electronic device, consumer electronic device, etc.

[0197] This invention also provides a computer-readable medium carrying computer-executable instructions. When executed by a processor, these instructions can be used to implement various operations and functions of the link optimization methods described in the various embodiments of this specification.

[0198] The computer-readable medium in this invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0199] In this invention, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0200] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0201] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0202] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

[0203] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0204] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An optical module, characterized in that, include: Continuous-time linear equalizer and adaptive engine; The continuous-time linear equalizer is used to receive the input voltage signal and perform equalization processing on the voltage signal based on the gain value issued by the adaptive engine. The input of the adaptive engine is connected to the output of the continuous-time linear equalizer. The adaptive engine is used to sample the output signal of the continuous-time linear equalizer and determine the gain configuration of the continuous-time linear equalizer based on the sampled data under different gain values. The adaptive engine includes a time processing module and a microcontroller. The input of the time processing module is connected to the output of the continuous-time linear equalizer. The time processing module samples the output signal of the continuous-time linear equalizer and outputs the sampled data to the microcontroller. The data port of the microcontroller is connected to the time processing module, and the control port is connected to the control terminal of the continuous-time linear equalizer. The microcontroller determines the gain configuration of the continuous-time linear equalizer based on the sampled data at different gain values. The time processing module further includes a clock unit, a phase-locked loop (PLL), and a sampling module. The clock unit is connected to the output of the continuous-time linear equalizer (CTLE), and is used to extract the clock signal corresponding to the voltage signal output by the CTLE. The input of the PLL is connected to the output of the clock unit, and the PLL is used to generate a sub-clock signal based on the clock signal. The PLL locks the sub-clock signal and the clock signal of the high-frequency signal output by the CTLE as the locking objects to achieve phase coincidence. The sampling module is used to perform multiple signal acquisitions on the voltage signal output by the CTLE based on the sub-clock signal to obtain the sampling data. The sampling data is the level value obtained by the time processing module sampling the voltage signal output by the CTLE at a specific phase point of the sub-clock signal.

2. The optical module according to claim 1, characterized in that, The microcontroller sends gain values ​​to the continuous-time linear equalizer based on a preset gain sequence.

3. The optical module according to claim 1, characterized in that, The gain sequence is sent from the host and stored in the microcontroller; Alternatively, the gain sequence may be determined based on the neighborhood range of a preset gain value; Alternatively, the gain sequence may be determined from multiple preset gain sequences based on the sampled data at the current gain value.

4. The optical module according to claim 1, characterized in that, The microcontroller determines the signal quality index based on the sampled data at different gain values, and then determines the gain configuration of the continuous-time linear equalizer.

5. The optical module according to claim 1, characterized in that, The phase-locked loop integrates a phase interpolator; The phase interpolator is used to superimpose multiple phase-shifted signals to adjust the phase of the clock signal to obtain the sub-clock signal; The phase-locked loop is used to lock the sub-clock signal and the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer, so that the frequency of the clock signal corresponding to the voltage signal output by the continuous-time linear equalizer and the frequency of the sub-clock form a desired proportional relationship.

6. The optical module according to claim 5, characterized in that, The phase interpolator generates a sub-clock signal for sampling by stepping multiple phase points within a preset interval of the clock signal.

7. The optical module according to claim 6, characterized in that, The phase interpolator generates a sub-clock signal by stepping through multiple equally spaced phase points within a continuous preset interval of the same duration.

8. The optical module according to claim 5, characterized in that, The sampling module includes a high-speed voltage comparator and a peak detection circuit; The first input terminal of the high-speed voltage comparator is connected to the output terminal of the continuous-time linear equalizer to receive the voltage signal output by the continuous-time linear equalizer; the second input terminal of the high-speed voltage comparator is connected to the output terminal of the phase interpolator to receive the sub-clock signal. The input terminal of the peak detection circuit is connected to the output terminal of the high-speed voltage comparator; the output terminal of the peak detection circuit is connected to the data port of the microcontroller.

9. The optical module according to claim 1, characterized in that, The sampling module includes an analog-to-digital converter (ADC), whose analog input is connected to the output of the continuous-time linear equalizer, whose sampling clock input is connected to the output of the phase-locked loop (PLL), and whose digital output is connected to the data port of the microcontroller.

10. The optical module according to claim 1, characterized in that, The clock unit includes a clock extraction module and a clock recovery module; The clock extraction module is used to extract the clock frequency from the voltage signal output by the continuous-time linear equalizer and output the original clock signal. The input terminal of the clock recovery module is connected to the output terminal of the clock extraction circuit, and is used to perform phase locking and jitter filtering on the original clock signal to output the clock signal.

11. The optical module according to claim 1, characterized in that, The optical module also includes a photodetector and a transimpedance amplifier connected in series; The photodetector is used to receive optical signals and convert the optical signals into electrical signals; The input terminal of the transimpedance amplifier is connected to the output terminal of the photodetector, and is used to convert the electrical signal into the input voltage signal and send the input voltage signal to the continuous-time linear equalizer.

12. A link optimization method, characterized in that, include: The microcontroller sends out the gain value so that the continuous-time linear equalizer can perform equalization processing on the input voltage signal; The time processing module extracts the corresponding clock signal from the voltage signal output by the continuous-time linear equalizer. The clock signal is clock-locked to generate a sub-clock signal synchronized with the clock signal; based on the sub-clock signal, the voltage signal output by the continuous-time linear equalizer is sampled by analog-to-digital conversion to obtain sampled data; the sub-clock signal is locked with the clock signal of the high-frequency signal output by the continuous-time linear equalizer to achieve phase coincidence; wherein, the sampled data is the level value obtained by the time processing module sampling the voltage signal output by the continuous-time linear equalizer at a specific phase point of the sub-clock signal; The microcontroller determines the gain configuration of the continuous-time linear equalizer based on the sampled data at different gain values.

13. The link optimization method according to claim 12, characterized in that, The sampling data is the level value obtained by the time processing module sampling the voltage signal output by the continuous-time linear equalizer at a predetermined phase point of the sub-clock signal.

14. The link optimization method according to claim 13, characterized in that, The method further includes: A Cartesian coordinate system is constructed using phase and input voltage signal level values ​​as coordinate axis data; Based on the sampled data, the signal waveform and / or eye diagram are reconstructed in the Cartesian coordinate system, and the signal quality index is calculated based on the reconstructed signal waveform and / or eye diagram.

15. The link optimization method according to claim 12, characterized in that, The method specifically includes: The time processing module steps through multiple phase points within a preset interval of the voltage signal output by the continuous-time linear equalizer. At each phase point of the step, the voltage signal output by the continuous-time linear equalizer is sampled a preset number of times to obtain sampled data; Determine the signal quality index corresponding to the sampled data, and determine the gain configuration of the continuous-time linear equalizer based on the signal quality index.

16. The link optimization method according to claim 15, characterized in that, The preset intervals have equal periodic durations; And / or the phase points based on the time processing module are evenly distributed within the preset interval.

17. The link optimization method according to claim 12, characterized in that, Extracting the corresponding clock signal from the voltage signal output by the continuous-time linear equalizer, specifically including: The time processing module extracts the clock frequency from the voltage signal output by the continuous-time linear equalizer, and then outputs the original clock signal. Alternatively, the original clock signal can be phase-locked and / or jitter filtered to obtain a processed clock signal.

18. The link optimization method according to claim 12, characterized in that, The method further includes: In response to a preset triggering condition, the microcontroller traverses a preset gain sequence and configures the continuous-time linear equalizer to a selected gain value. The preset triggering conditions include one or more of the following: module power-on initialization, reconnection after link interruption, instructions issued based on the management interface, periodic calibration triggered by the microcontroller's internal timer, and signal quality indicators falling below a preset threshold.

19. The link optimization method according to claim 12, characterized in that, The method further includes: The currently determined gain value and their corresponding signal quality indicators Report to the host system; If the currently determined gain value Greater than the gain value of the host system storage And the corresponding signal quality indicators Superior signal quality metrics compared to host system storage Then the host system increases the pre-emphasis and / or deemphasis coefficients of its transmit feedforward equalizer and updates the stored gain value to the currently determined gain value. And update the stored signal quality indicators to the corresponding signal quality indicators. ; If the currently determined gain value Less than the stored gain value The host then reduces the pre-emphasis and / or deemphasis coefficients of the transmit feedforward equalizer and updates the stored gain value to the optimal gain value. Update the stored signal quality metrics to .

20. A link optimization method for an optical module, characterized in that, include: The input signal is equalized based on the issued gain value, and the corresponding clock signal is extracted from the equalized input signal. Clock locking is performed on the clock signal to generate a sub-clock signal synchronized with the clock signal; Based on the sub-clock signal, the input signal after equalization is sampled by analog-to-digital conversion to obtain sampled data; the sub-clock signal is locked with the clock signal of the high-frequency signal of the input signal after equalization to achieve phase coincidence; wherein, the sampled data is the level value obtained by sampling the input signal after equalization at a specific phase point of the sub-clock signal. Based on the sampled data at different gain values, the gain configuration of the optical module is determined.

21. The link optimization method according to claim 20, characterized in that, The method further includes: A Cartesian coordinate system is constructed using the phase and sampled values ​​of the input signal as coordinate axis data; Based on the sampled data, a signal waveform and / or eye diagram are constructed in the Cartesian coordinate system, and a signal quality index is calculated based on the signal waveform and / or eye diagram.

22. The link optimization method according to claim 21, characterized in that, Calculating the signal quality index based on the signal waveform and / or eye diagram includes: Based on the signal waveform and / or eye diagram, the opening degree and noise characteristics of multiple vertical eye diagrams are calculated respectively, and each vertical eye diagram corresponds to the image formed by a pair of adjacent signal levels on the signal waveform and / or eye diagram; Based on the opening degree of each vertical eye diagram and its corresponding noise characteristics, the signal quality index corresponding to the signal waveform and / or eye diagram is determined.

23. The link optimization method according to claim 22, characterized in that, Calculate the opening of multiple vertical eye diagrams separately, including: The sampled data is classified according to a preset level range; Calculate the statistical mean of the sampled data for each level interval; The opening of the vertical eye diagram is calculated based on the difference in statistical means between adjacent level intervals constituting the vertical eye diagram.

24. The link optimization method according to claim 22, characterized in that, Calculate the noise characteristics of multiple vertical eye diagrams, including: The sampled data is classified according to the corresponding level range; Calculate the standard deviation of the sampled data for each level interval; The noise characteristics of the vertical eye diagram are calculated based on the sum of the standard deviations of adjacent level intervals constituting the vertical eye diagram.

25. The link optimization method according to claim 22, characterized in that, Based on the opening degree of each vertical eye diagram and its corresponding noise characteristics, the signal quality index corresponding to the vertical eye diagram is determined, including: Calculate the ratio of the opening to the noise characteristic of each vertical eye diagram in the signal waveform and / or eye diagram; The signal quality index of the signal waveform and / or eye diagram is determined based on the minimum value of the ratio of the opening to the noise characteristic of each vertical eye diagram.

26. The link optimization method according to claim 20, characterized in that, The method specifically includes: Multiple phase points are stepped within a preset interval of the input signal after equalization processing; At each phase point of the step, the input signal after equalization is sampled a preset number of times to obtain sampled data; Determine the signal quality index corresponding to the sampled data, and determine the gain configuration based on the signal quality index.

27. The link optimization method according to claim 26, characterized in that, The preset intervals have equal periodic durations; The phase points, and / or the steps, are uniformly distributed within the preset interval.

28. The link optimization method according to claim 20, characterized in that, The clock signal includes: Extract the clock frequency from the input signal and output the original clock signal; Alternatively, it can be a clock signal output based on phase-locked and jitter-filtered original clock signal.

29. A link optimization system, applied to the link optimization method according to any one of claims 20-28, characterized in that, include: The traversal module is used to perform equalization processing on the input signal based on the issued gain value and to sample and obtain sampled data; A configuration module is used to determine the gain configuration of the optical module based on the sampled data at different gain values.

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