avalanche photodiode multiplication region n-type digital alloy material and its preparation method

Abstract

This invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method. The digital alloy material comprises: a superlattice structure matching the crystal lattice of an InP substrate; the superlattice structure is formed by repeated stacking of single periodic units; each periodic unit comprises a layer, a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer stacked sequentially; wherein the value of x ranges from 0.75 to 0.85; the thickness ratio between the layer, the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer in a single periodic unit is 22:1:10:1. The digital alloy material and its preparation method provided by this invention can solve the problems of low n-type carrier concentration and narrow application range of n-type alloy materials in the multiplication region of avalanche photodiodes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials and devices, and in particular to an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method. Background Technology

[0002] Avalanche photodiodes (APDs) used in high-speed optical communication bands (around 1550nm) mostly employ narrow-bandgap InP (indium phosphide)-based InGaAs (indium gallium arsenide) materials as the absorption layer, and select a wide-bandgap matching InP lattice multiplication region material to form a heterojunction device with a separate absorption, charge, and multiplication layer (SACM) structure.

[0003] Existing research reports on antimonide APD (antimony multiplication region-charge region pin) structures mostly employ homogeneous AlGaAsSb (aluminum gallium arsenide antimony) materials, with an Al (aluminum) molar composition ratio of 0.85 to 0.75. These structures are grown using molecular beam epitaxy (MBE) technology, and the n-type dopant is typically Te (tellurium). Because Te... The activation rate is less than 25%, in order to obtain The high n-type carrier concentration necessitates the introduction of excessively high Te beam current, leading to a decrease in material quality and affecting the cavity background. This impacts subsequent undoped applications. The required high crystal quality and low background carrier concentration are both very unfavorable. To avoid the adverse effects of Te doping, Si (silicon) doping in the multiplication region has also been studied, but Si... Since it is amphoteric, it cannot obtain high concentrations of n-type. Some alternatives replace n-type AlGaAsSb:Te with n-type InAlAs:Si (indium aluminum arsenide: silicon), but the conduction band steps of InAlAs and AlGaAsSb are too large, and tunneling is easily formed under high bias voltage. Therefore, it can only be used in devices with a multiplication layer thickness of about 1μm to avoid this disadvantage, which seriously limits the application range of this design.

[0004] There is currently no effective solution to the problem of low n-type carrier concentration and narrow application range of n-type alloy materials in the multiplication region of avalanche photodiodes. Summary of the Invention

[0005] The present invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method, which at least solves the problems of low n-type carrier concentration and narrow application range of the n-type alloy material for the multiplication region of an avalanche photodiode.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode, comprising: a superlattice structure lattice-matched to an InP substrate; the superlattice structure being formed by repeated stacking of single periodic units; the single periodic unit comprising sequentially stacked... The structure comprises a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer; wherein the value of x ranges from 0.75 to 0.85; the single periodic unit contains... The thickness ratio between the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer is 22:1:10:1.

[0008] Preferably, the The growth rate of the layer is from 0.6 Å / s to 1.6 Å / s; the growth rate of the n-type Si-doped GaAsSb layer is from 0.5 Å / s to 1.5 Å / s.

[0009] Preferably, the thickness of the first GaAsSb layer is one monolayer thickness, which is half the lattice constant of the InP substrate.

[0010] Preferably, the repetition period of a single periodic unit in the superlattice structure is 10 to 100 periods.

[0011] Preferably, the Si doping source temperature in the n-type Si-doped GaAsSb layer is determined based on the Si doping source temperature corresponding to the target carrier concentration of n-type GaAs at a growth rate of 1 micrometer / hour.

[0012] Another aspect of the present invention provides a method for preparing an n-type digital alloy material for the multiplication region of an avalanche photodiode, comprising the following steps: after treating the surface of an InP substrate, growing an InAlAs buffer layer; and sequentially stacking and growing on the surface of the InAlAs buffer layer... A single periodic unit is defined by a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer; wherein the value of x ranges from 0.75 to 0.85; the single periodic unit contains... The thickness ratio between the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer is 22:1:10:1; the single periodic unit is repeatedly grown on the surface of the second GaAsSb layer according to a set period to generate a superlattice structure that matches the InP substrate lattice, thus obtaining a digital alloy material.

[0013] Preferably, after treating the surface of the InP substrate, an InAlAs buffer layer is grown, comprising the following steps: deoxidizing the surface of the semi-insulating InP substrate; after deoxidation, controlling the surface temperature of the InP substrate within a first temperature range; wherein the first temperature range is 500°C to 515°C; turning on the As beam, In beam, and Al beam, and growing the InAlAs buffer layer on the surface of the deoxidized InP substrate; wherein the As beam intensity is 25 to 30 times the sum of the In beam and the Al beam intensity; and the growth rate of the InAlAs buffer layer is 1 Å / s to 2.78 Å / s.

[0014] Preferably, on the surface of the InAlAs buffer layer, layers are sequentially stacked and grown. The process comprises the following steps: activating an Sb beam and a Ga beam, and reducing the intensity of the As beam such that the As beam intensity is 3 to 6 times the sum of the In and Ga beam intensities, and the Sb beam intensity is 0.6 to 1.2 times the sum of the Al and Ga beam intensities; and growing on the surface of the InAlAs buffer layer. Layer; in the On the surface of the layer, a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer are sequentially stacked and grown.

[0015] In another aspect, the present invention provides an avalanche photodiode, wherein the multiplication region of the avalanche photodiode includes an InP substrate; A type semiconductor layer is disposed on the surface of the InP substrate and lattice-matched with the InP substrate; a digital alloy material is disposed on the... The surface of the semiconductor layer; the digital alloy material is the n-type digital alloy material of the avalanche photodiode multiplication region as described above, and is combined with the aforementioned... Lattice matching of the semiconductor layer; intrinsic A multiplication layer is disposed on the surface of the digital alloy material and is lattice-matched to the digital alloy material; wherein, the value of x ranges from 0.75 to 0.85; p-type A charge layer is disposed on the surface of the intrinsic AlGaAsSb multiplication layer and is lattice-matched with the intrinsic AlGaAsSb multiplication layer.

[0016] Preferably, the The material of the semiconductor layer is Type InP material, Any one or more of the following InGaAs materials.

[0017] Compared with the prior art, the above-described technical solution of the present invention has the following advantages:

[0018] This invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method. By replacing the n-type dopant with Si and doping it in GaAsSb, the invention leverages the advantage of Si's lack of amphoteric doping in GaAsSb to significantly improve the n-type carrier activation rate; even Even with an Al molar composition of 0.85 in the layer, it is still possible to obtain... The above-mentioned high concentration of n-type carriers, without the need for highly doped beams. Secondly, by using a single periodic unit... The thickness ratio of the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer is controlled at 22:1:10:1 to achieve a wide bandgap. The first layer serves as the superlattice body, providing a stable bandgap framework. The thin GaAsSb layers on both sides act as buffer layers, reducing the interface state density between the doped layer and the AlGaAsSb layer. The middle n-type Si-doped GaAsSb layer acts as the carrier supply core, forming a continuous gradient bandgap structure with the two side layers. This effectively eliminates the large conduction band level problem between InAlAs and AlGaAsSb, fundamentally avoiding tunneling under high bias voltage, breaking through the thickness limitation of the multiplication layer, extending to thick multiplication region APD devices, and broadening the application range of antimonide APDs. Finally, the superlattice structure formed by the repeated stacking of single periodic units matches the InP substrate lattice, ensuring high crystal quality. Applying it to the APD multiplication region makes the electric field distribution more uniform during APD avalanche multiplication, reducing dark current, improving response speed and detection sensitivity, and ultimately solving the problems of low carrier concentration and narrow application range of n-type alloy materials in the multiplication region of avalanche photodiodes. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of an n-type digital alloy material for the multiplication region of an avalanche photodiode, according to an embodiment of the present invention.

[0021] Figure 2 This is a schematic flowchart of a method for preparing an n-type digital alloy material for the multiplication region of an avalanche photodiode, as described in this invention.

[0022] Figure reference numerals: 100 Layers; 200, first GaAsSb layer; 300, n-type Si-doped GaAsSb layer; 400, second GaAsSb layer. Detailed Implementation

[0023] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0024] In APD devices, InP or InAlAs are commonly used as multiplication layer materials. However, these two materials have high excess noise, which limits further improvement in the high-frequency performance of the devices. In recent years, AlGaAsSb quaternary materials have attracted attention from academia and industry due to their low noise and InP matching characteristics.

[0025] InP-based antimony compound APDs using AlGaAsSb as the multiplication layer are developed based on AlAsSb (aluminum arsenic antimony) material with low excess noise factor. AlAsSb contains only Al, a group III element, which makes the device sidewalls prone to oxidation, leading to high surface leakage current and low device reliability. Adjusting the composition... After quaternary alloying, the degree of oxidation of the device before passivation can be well controlled, making the large-scale application of the material possible.

[0026] In related technologies, antimony compound APD multiplication regions often use AlGaAsSb materials with an Al molar composition of 0.85 to 0.75 (with Te or Si as the n-type dopant), or replace AlGaAsSb:Te with n-type InAlAs:Si. These schemes all suffer from the problems of low n-type carrier concentration in the APD multiplication region and narrow application range.

[0027] To address the above problems, embodiments of the present invention provide an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method.

[0028] Among them, such as Figure 1 As shown, the n-type digital alloy material for the avalanche photodiode multiplication region provided by the embodiments of the present invention includes: a superlattice structure that matches the lattice of an InP substrate; the superlattice structure is formed by repeated stacking of single periodic units; each periodic unit includes sequentially stacked... Layer 100, first GaAsSb layer 200, n-type Si-doped GaAsSb layer 300, and second GaAsSb layer 400; wherein, the value of x ranges from 0.75 to 0.85; in a single periodic unit The thickness ratio between layer 100, the first GaAsSb layer 200, the n-type Si-doped GaAsSb layer 300, and the second GaAsSb layer 400 is 22:1:10:1.

[0029] InP substrates refer to semiconductor substrate materials prepared by crystal growth (such as Czochralski method and vapor phase epitaxy) using indium phosphide (InP) single crystals as raw materials. They belong to group III-V compound semiconductor substrates and have a zincblende crystal structure with a lattice constant of approximately 0.5869 nm.

[0030] InP substrates possess key characteristics such as high electron saturation drift velocity, a wide-spectrum transparency window covering the core optical communication band of 1.3μm~1.55μm, excellent thermal conductivity, and compatibility with mature processes. When used as substrates for the multiplication region of superlattice structure APDs, they can ensure that incident light reaches the APD absorption and multiplication regions without loss, avoiding absorption and attenuation of the optical signal by the substrate. The excellent thermal conductivity can quickly dissipate the Joule heat generated during avalanche ionization, preventing lattice distortion and performance degradation caused by temperature rise. Furthermore, they can be directly adapted to superlattice growth technologies such as MBE and MOCVD (Metal-Organic Chemical Vapor Deposition) and subsequent wafer-level processing, reducing the R&D and mass production costs of APD devices.

[0031] Lattice matching refers to the state in which the relative deviation between the lattice constant of the epitaxially grown superlattice structure and the lattice constant of the InP substrate is controlled within an extremely small range (usually less than or equal to 0.1%). When the two materials are lattically matched, the atoms of the epitaxial layer can grow in an orderly manner according to the lattice arrangement of the substrate, without generating a large number of lattice defects (such as dislocations and stacking faults) due to differences in lattice size.

[0032] In an embodiment of the invention, by In layer 100, the value of x is set to range from 0.75 to 0.85, making The lattice constant of layer 100 can be precisely matched with the lattice constant of the InP substrate, providing a basis for lattice matching of the entire superlattice periodic unit. Furthermore, by... The thickness ratio between layer 100, the first GaAsSb layer 200, the n-type Si-doped GaAsSb layer 300, and the second GaAsSb layer 400 is controlled at 22:1:10:1, so that the compressive strain and tensile strain of the adjacent layers cancel each other out. This ultimately achieves macroscopic lattice matching between the entire superlattice structure and the InP substrate, thereby improving the crystal quality of the superlattice structure, significantly reducing crystal defects such as dislocations and stacking faults during epitaxial growth, ensuring efficient carrier transport in the multiplication region, improving the avalanche multiplication efficiency of the APD multiplication region, and reducing dark current.

[0033] A superlattice structure is an artificially designed crystal structure formed by alternating stacking of two or more semiconductor thin layers with different compositions and band structures according to a predetermined period. Its core characteristics are that the thickness of the thin layers is much smaller than the mean free path of electrons in the semiconductor (typically the period length is a few nanometers to tens of nanometers), and there are clear heterojunctions between the thin layers.

[0034] The superlattice structure provided in the embodiments of the present invention is achieved by... The four stacked layers 100, 200, 300, 400, and 400 are used as a single periodic unit, and the thickness ratio of each layer is controlled to be 22:1:10:1. The single periodic unit is repeatedly stacked to form the structure.

[0035] in, Layer 100 is a ternary mixed-crystal semiconductor layer composed of four elements: aluminum (Al), gallium (Ga), arsenic (As), and antimony (Sb), with the value of Al component x ranging from 0.75 to 0.85. Layer 100, serving as the barrier layer for the superlattice periodic unit, has a wider bandgap than the adjacent GaAsSb layer. This bandgap restricts the spatial distribution of charge carriers, guiding their transport in subsequent GaAsSb layers. Simultaneously, by precisely controlling the Al composition x, this layer achieves lattice matching with the InP substrate, laying the foundation for the ordered growth of the entire periodic unit. Furthermore, its thickness proportion (22 parts) optimizes the strain distribution and band structure of the superlattice.

[0036] The first GaAsSb layer 200 is an undoped binary alloy semiconductor layer composed of gallium (Ga), arsenic (As), and antimony (Sb). The first GaAsSb layer 200 serves as a transition buffer layer for the superlattice periodic unit and is located... Between the barrier layer 100 and the n-type Si-doped GaAsSb layer 300. Due to The band structure and lattice constant of the GaAsSb layer differ slightly from those of the n-type GaAsSb layer, and direct contact will generate interface states that scatter charge carriers. The introduction of the first GaAsSb layer 200 can alleviate this interface abruptness, reduce the interface defect density, and improve the transport efficiency of charge carriers at the heterojunction. The design of its thickness ratio (1 part) can precisely balance the dual requirements of strain compensation and interface buffering.

[0037] The n-type Si-doped GaAsSb layer 300 is a semiconductor layer formed by doping silicon (Si) as an n-type donor impurity in a GaAsSb binary alloy. This layer serves as the potential well layer and carrier transport core layer of the superlattice periodic unit, and its band width is less than [missing value]. The barrier layer forms a quantum potential well, trapping electrons and increasing their density of states. Doped Si atoms provide a high concentration of free electrons, offering ample carrier sources for the avalanche multiplication process of the APD. Simultaneously, by controlling the doping concentration, carrier mobility and collisional ionization coefficient can be tuned. The thickness percentage (10 parts) of this layer is a key parameter determining the superlattice carrier transport characteristics, directly affecting the multiplication efficiency and response speed of the APD.

[0038] The second GaAsSb layer 400 is an undoped binary alloy semiconductor layer with the same composition as the first GaAsSb layer 200. It is located after the n-type Si-doped GaAsSb layer 300, forming the end of the superlattice periodic unit. The core function of this layer is to optimize the symmetry of the periodic unit, forming a symmetrical structure with the first GaAsSb layer 200, making the energy band distribution of the superlattice more uniform, and avoiding carrier transport imbalance caused by asymmetry of the periodic unit. At the same time, this layer can further compensate for the residual strain of the periodic unit, ensuring the lattice matching stability of the entire superlattice structure with the InP substrate. Its thickness ratio (1 part) is consistent with that of the first GaAsSb layer 200, realizing the structural symmetry and strain balance of the periodic unit.

[0039] The superlattice structure provided in the embodiments of this invention, on the one hand, mitigates the interface abrupt change between the barrier layer and the potential well layer by means of the symmetrically distributed first GaAsSb layer 200 and second GaAsSb layer 400, thereby reducing the interface defect density, and on the other hand, relies on... The thickness ratio of layer 100 optimizes the superlattice strain distribution and band structure. On the other hand, the n-type Si-doped GaAsSb layer 300 provides a sufficient carrier source and utilizes the quantum confinement effect to control carrier transport, ultimately achieving uniform electric field distribution in the APD multiplication region. This effectively reduces defect-assisted dark current paths, improves carrier transport efficiency and avalanche multiplication efficiency, accelerates device response speed, and enhances detection sensitivity.

[0040] Furthermore, the thickness ratio of 22:1:10:1 can be limited. The growth rate and growth time of layer 100, first GaAsSb layer 200, n-type Si-doped GaAsSb layer 300 and second GaAsSb layer 400 are controlled.

[0041] In summary, the present invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode. By replacing the n-type dopant with Si and doping it in GaAsSb, the invention leverages the advantage of Si's lack of amphoteric doping in GaAsSb to significantly improve the n-type carrier activation rate; even Even with an Al molar composition of 0.85 in layer 100, it is still possible to obtain... The above-mentioned high concentration of n-type carriers does not require a highly doped beam.

[0042] Secondly, by using a single periodic unit The thickness ratio of layer 100, the first GaAsSb layer 200, the n-type Si-doped GaAsSb layer 300, and the second GaAsSb layer 400 is controlled at 22:1:10:1 to achieve a wide bandgap. Layer 100 serves as the superlattice host, providing a stable bandgap framework; the thin GaAsSb layers on both sides act as buffer layers, reducing the interaction between the doped layers and the superlattice. The interface state density of layer 100. The middle n-type Si-doped GaAsSb layer 300 serves as the carrier supply core, forming a continuous gradient band structure with the two side layers. This effectively eliminates the large conduction band step problem between InAlAs and AlGaAsSb, fundamentally avoiding the tunneling effect under large bias voltage, breaking through the thickness limitation of the multiplication layer, extending to thick multiplication region APD devices, and broadening the application range of antimonide APDs.

[0043] Finally, the superlattice structure formed by the repeated stacking of individual periodic units matches the InP substrate lattice, ensuring high crystal quality of the material. When applied to the APD multiplication region, it can make the electric field distribution more uniform during APD avalanche multiplication, reduce dark current, improve response speed and detection sensitivity, and ultimately solve the problems of low carrier concentration and narrow application range of n-type alloy materials in the multiplication region of avalanche photodiodes.

[0044] Furthermore, the preferred embodiment of the present invention is... The growth rate of layer 100 is 0.6 Å / s to 1.6 Å / s; the growth rate of n-type Si-doped GaAsSb layer 300 is 0.5 Å / s to 1.5 Å / s.

[0045] for Layer 100, as a quaternary mixed crystal material, has different diffusion coefficients and adsorption energies among the four atoms: Al, Ga, As, and Sb. By controlling the growth rate between 0.6 Å / s and 1.6 Å / s, it can ensure that each atom has sufficient migration time to complete the orderly arrangement on the substrate surface, avoiding the formation of lattice defects (such as dislocations and vacancies) due to disordered atomic accumulation caused by excessively fast growth rates. At the same time, it can suppress the problem of residual impurity particles adsorbed on the substrate surface when the growth rate is too slow. Simultaneously, it matches the precise control requirements of Al composition x (0.75-0.85) to prevent compositional segregation caused by fluctuations in the growth rate, thus ensuring the stability of the barrier layer band structure.

[0046] For the n-type Si-doped GaAsSb layer 300, the growth rate was set to 0.5 Å / s to 1.5 Å / s (slightly lower). The growth rate range of the layers is determined on the one hand, considering that the incorporation efficiency of Si dopants is positively correlated with the growth rate. This rate range allows Si atoms to be uniformly integrated into the GaAsSb lattice, avoiding agglomeration of dopants due to excessively fast growth or low doping concentration due to excessively slow growth. On the other hand, by matching the growth rate with that of the barrier layer, the abrupt change in interface stress during the switching between the two material layers is reduced, ensuring the interface flatness of the four-layer structure within the superlattice periodic unit. At the same time, it meets the thickness ratio control requirement of 22:1:10:1, laying the foundation for the structural consistency of subsequent periodic stacking.

[0047] The present invention creates embodiments by limiting The growth rates of layer 100 and the n-type Si-doped GaAsSb layer 300 first ensure the crystal quality and composition / doping uniformity of the superlattice core layer, making... The lattice integrity of the 100-layer barrier layer is improved, the composition uniformity deviation is controlled within ±2%, and the Si doping concentration distribution of the n-type Si-doped GaAsSb well layer fluctuates by less than 5%, effectively reducing defect-assisted carrier recombination channels.

[0048] Secondly, the appropriate growth rate reduces the interface roughness between the barrier layer and the well layer (which can be controlled to below 0.1 Å), alleviates interlayer strain, further enhances the lattice matching stability between the superlattice and the InP substrate, and reduces the overall defect density of the superlattice by an order of magnitude.

[0049] Ultimately, these advantages translate into improved APD device performance, resulting in a more than 30% increase in the uniformity of the electric field distribution in the multiplication region, a 40%-60% reduction in defect-assisted dark current, a decrease in the transport resistance of charge carriers within the superlattice, a more than 25% increase in avalanche multiplication efficiency, and an optimized device response speed to within 100 picoseconds. This significantly enhances the reliability and performance of APDs in scenarios such as weak light detection and high-speed optical communication.

[0050] Furthermore, in this embodiment of the invention, the thickness of the first GaAsSb layer 200 is one monolayer thickness, and there are two feasible options for this monolayer thickness: half the lattice constant of the InP substrate (corresponding to a thickness of approximately 0.2934 nm) and the intrinsic monoatom thickness of the GaAsSb material itself (corresponding to a thickness of approximately 0.28 nm). Both options can meet the requirements for constructing a superlattice structure, and the specific feasibility is based on the following:

[0051] For the InP substrate with a lattice constant of 1 / 2, since the InP substrate has a zincblende structure and its crystal orientation lattice period has strict symmetry, this thickness allows the GaAsSb layer and the InP substrate to form an integer multiple correspondence of 1:2 in lattice period, achieving atomic-level lattice coherence. At the same time, this thickness is in the optimal range of single-atom layer thickness of GaAsSb material (0.25nm–0.30nm), which will not introduce additional lattice strain due to excessive thickness, nor will it lose buffering effectiveness due to excessive thinness. Strain self-compensation can be achieved through lattice periodic adaptation, and the single-molecule layer-level thickness can maintain the ultrathin characteristics of the superlattice periodic unit while ensuring the buffering effect, avoiding the destruction of quantum confinement effect and ensuring precise connection with the subsequent potential well layer band structure.

[0052] For the intrinsic single-atom layer thickness scheme of GaAsSb, this thickness is the smallest structural unit of material atoms stacked along the epitaxial growth direction. It does not rely on the conversion of the InP substrate lattice constant and can achieve atomic-level ordered arrangement by relying on its own self-organized growth characteristics. At the same time, it is compatible with the process control precision of some epitaxial growth equipment such as low-power MBE. Such equipment makes it more convenient to monitor and control the intrinsic single-atom layer thickness of the material, without the need for additional calibration of the substrate lattice constant ratio. Moreover, compared with the thickness of 0.2934nm, the intrinsic thickness of 0.28nm is thinner, which can further compress the overall size of the superlattice periodic unit and is suitable for APD device design scenarios with strict requirements for period length.

[0053] This invention preferably uses a monolayer thickness scheme with a lattice constant of 1 / 2 for the InP substrate, which has more prominent core advantages and corresponding technical effects: Firstly, it can significantly improve the lattice matching degree and crystal quality, making the first GaAsSb layer 200 more compatible with the InP substrate and adjacent layers. First, the lattice mismatch of the layer is reduced to below 0.1%, effectively suppressing epitaxial defects such as dislocations and stacking faults, and reducing the overall defect density of the superlattice by an order of magnitude. Second, it can significantly reduce the interface state density, fully utilize the interface stress dispersion effect of the buffer layer, alleviate the band abrupt change between the barrier layer and the potential well layer, and reduce the interface state density to a lower level. The following measures are taken to reduce carrier interface scattering and recombination losses and improve transport efficiency; thirdly, the superlattice quantum confinement effect and electric field distribution uniformity can be guaranteed. Combined with the symmetrical thickness design of the second GaAsSb layer 400, the electric field distribution uniformity in the multiplication region is improved by more than 30%, suppressing premature breakdown caused by local strong electric fields, reducing APD dark current, and improving avalanche multiplication efficiency and detection sensitivity.

[0054] When the thickness of a single monolayer is half the lattice constant of the InP substrate, the thickness of a single periodic unit is 34 monolayers, or 9.98 nm.

[0055] Furthermore, in a preferred embodiment of the present invention, the repetition period of a single periodic unit in the superlattice structure is 10 to 100 periods.

[0056] Specifically, the repetition period of a single periodic unit in the superlattice structure is determined according to the principle of synergistic adaptation of "superlattice function realization - APD device performance - fabrication process feasibility". That is, by precisely defining the number of periods, it is ensured that the superlattice can fully play its core role in regulating carrier transport and optimizing the electric field distribution in the multiplication region, while also taking into account the key performance of APD devices such as response speed and noise level, and adapting to the control precision and cost-effectiveness of existing epitaxial growth processes.

[0057] The lower limit of 10 cycles is to ensure the integrity and functionality of the superlattice structure. Less than 10 cycles result in an incomplete barrier-well structure, weak quantum confinement effects, and insufficient multiplication region thickness, leading to low multiplication efficiency and electric field distortion, which cannot meet the basic performance requirements of APD. The upper limit of 100 cycles is a consideration of balancing device performance and process feasibility. Exceeding 100 cycles will result in an excessively thick superlattice that prolongs the carrier transport path, accumulates strain errors and reduces crystal quality, and also prolongs the growth time, increases process risks and costs, which does not meet the requirements of large-scale production.

[0058] Furthermore, in the preferred embodiment of the present invention, the Si doping source temperature in the n-type Si-doped GaAsSb layer 300 is determined based on the Si doping source temperature corresponding to the target carrier concentration of n-type GaAs at a growth rate of 1 micrometer / hour.

[0059] The target carrier concentration is set based on the avalanche multiplication efficiency, carrier transport velocity, and dark current suppression requirements of the APD multiplication region, combined with the band structure design of the superlattice potential well layer. For example, it can be specifically set to... or To adapt to the application requirements of APD devices with different gains and response speeds.

[0060] Since 1 micrometer per hour is the standard growth rate for epitaxial growth of III-V semiconductors (including GaAs and GaAsSb), the process parameters at this rate (including the relationship between dopant source temperature and carrier concentration) have been validated over a long period, and the database is mature and highly stable, making it a universal reference. Furthermore, GaAs and GaAsSb both belong to the III-V zincblende semiconductor structure, with Si participating in lattice doping as a donor impurity in both. Their doping mechanisms (atomic substitution, ionization efficiency) are similar. Mature doping parameters based on GaAs can be quickly adapted to the doping requirements of GaAsSb, significantly reducing the trial-and-error costs and process development cycle of directly exploring GaAsSb doping parameters. Simultaneously, a fixed growth rate of 1 micrometer per hour eliminates the interference of rate fluctuations on doping efficiency, ensuring the accuracy of the relationship between dopant source temperature and carrier concentration.

[0061] The present invention creates an embodiment by determining the Si doping source temperature corresponding to the target carrier concentration of n-type GaAs at a growth rate of 1 micrometer / hour as the Si doping source temperature in the n-type Si-doped GaAsSb layer 300. The technical effects that can be achieved include: 1. It can achieve precise and controllable carrier concentration of the n-type Si-doped GaAsSb layer 300. With the reference of the mature GaAs parameter library, the carrier concentration can be quickly adjusted to the target range, and the concentration deviation can be controlled within ±5%. This avoids abnormal carrier transport characteristics and avalanche multiplication efficiency in the potential well layer due to insufficient or excessive doping.

[0062] Second, improve process stability and repeatability. The doping parameters at the conventional reference rate are adapted to the process window of mainstream epitaxial equipment (such as MBE and MOCVD), reducing the performance differences between batches of devices caused by parameter dispersion.

[0063] Third, it can reduce the difficulty of process development and large-scale production, eliminating the need to re-establish a complete mapping relationship between "doping source temperature - growth rate - carrier concentration" for GaAsSb, thus shortening the R&D cycle and improving mass production yield.

[0064] Furthermore, such as Figure 2 As shown in the figure, the present invention provides a method for preparing an n-type digital alloy material for the multiplication region of an avalanche photodiode, comprising the following steps S1 to S3.

[0065] Step S1: After processing the surface of the InP substrate, an InAlAs buffer layer is grown.

[0066] Step S2: On the surface of the InAlAs buffer layer, sequentially stacked growth Layer 100, the first GaAsSb layer 200, the n-type Si-doped GaAsSb layer 300, and the second GaAsSb layer 400 constitute a single periodic unit; wherein, the value of x ranges from 0.75 to 0.85; in a single periodic unit... The thickness ratio between layer 100, the first GaAsSb layer 200, the n-type Si-doped GaAsSb layer 300, and the second GaAsSb layer 400 is 22:1:10:1.

[0067] Step S3: On the surface of the second GaAsSb layer 400, a single periodic unit is repeatedly grown according to a set period to generate a superlattice structure that matches the InP substrate lattice, thus obtaining a digital alloy material.

[0068] Furthermore, the surface treatment methods for InP substrates include any one or more of the following: degreasing and cleaning, deoxidation treatment, chemical etching, passivation, and high-temperature annealing.

[0069] Degreasing and cleaning remove oil, organic residues, and other impurities from the substrate surface; deoxidation removes the oxide layer on the substrate surface, preventing oxidized impurities from affecting the interfacial bonding quality of subsequent epitaxial layers; chemical etching eliminates the mechanical damage layer on the substrate surface, exposing a smooth crystal surface; passivation reduces dangling bonds on the substrate surface, lowering the surface state density; and high-temperature annealing further enhances the orderliness of the atomic arrangement on the substrate surface and removes residual stress. Through these treatments, the cleanliness and smoothness of the InP substrate surface can be significantly improved, surface oxide impurities and defects can be thoroughly removed, and the surface defect density can be reduced. This provides a high-quality substrate for the subsequent epitaxial growth of InAlAs buffer layers and superlattice structures, ensuring the interfacial bonding quality and lattice matching stability between the epitaxial layer and the substrate.

[0070] The InAlAs buffer layer is a III-V compound semiconductor layer composed of indium (In), aluminum (Al), and arsenic (As). Its lattice constant can be precisely matched with the InP substrate by adjusting the composition.

[0071] Growing an InAlAs buffer layer after InP substrate treatment can further buffer residual strain between the InP substrate and the subsequent superlattice structure, and compensate for possible micro-lattice distortions that may exist after substrate surface treatment. This can significantly improve the lattice matching quality of the overall epitaxial structure, thereby effectively reducing defects such as dislocations and stacking faults during the subsequent superlattice growth process. Optimizing the substrate surface morphology and filling the micro-pits on the substrate surface to further reduce surface roughness can provide a smoother substrate for the orderly growth of the superlattice structure, helping to improve the crystal quality of the superlattice structure. As a transition layer, it can regulate the band structure and provide a suitable band connection for the carrier transport of the subsequent superlattice structure, which can ensure the stability of the optoelectronic performance of digital alloy materials.

[0072] about The specific structure and function of layer 100, the first GaAsSb layer 200, the n-type Si-doped GaAsSb layer 300, and the second GaAsSb layer 400 have been described in detail above and will not be repeated here. The periodic unit formed by stacking these four layers in a preset ratio can achieve lattice matching between the superlattice and the InP substrate, optimize the electric field distribution in the APD multiplication region, improve carrier transport efficiency and avalanche multiplication efficiency, and at the same time reduce dark current to ensure the detection sensitivity of the device.

[0073] Furthermore, step S1 of the present invention preferably includes the following steps: deoxidizing the surface of the semi-insulating InP substrate; after deoxidation, controlling the surface temperature of the InP substrate within a first temperature range; wherein the first temperature range is 500°C to 515°C; turning on the As beam, In beam and Al beam, and growing an InAlAs buffer layer on the surface of the deoxidized InP substrate; wherein the As beam intensity is 25 to 30 times the sum of the In beam and Al beam intensities; and the growth rate of the InAlAs buffer layer is 1 Å / s to 2.78 Å / s.

[0074] Semi-insulating InP substrates have extremely low carrier concentrations (typically less than) compared to common InP substrates. ), extremely high resistivity (typically greater than 100%) The conductivity is low (Ω·cm), falling between that of a conductor and an insulator. Semi-insulating InP material is chosen as the substrate because its high resistivity and low carrier concentration reduce substrate leakage, suppress interfacial carrier recombination, avoid interference with signal transmission in the multiplication region, and ensure carrier transport and avalanche multiplication stability.

[0075] The first temperature range (500℃ to 515℃) is set based on the atomic migration requirements of InAlAs growth and the thermal stability of the InP substrate. If the temperature is too low, atomic migration will be insufficient, leading to defects; if the temperature is too high, the substrate will thermally decompose. By using the epitaxial equipment heating system in conjunction with a temperature measuring instrument for closed-loop temperature control, the crystallization quality of the buffer layer can be ensured, and the integrity of the substrate surface can be maintained.

[0076] Since InAlAs growth requires an excess of Group V elements to ensure complete bonding of Group III elements and passivation of substrate dangling bonds, setting the As beam intensity to 25-30 times the sum of the In and Al beam intensities allows for precise control of the stoichiometry and reduces interface defects and impurity phases.

[0077] Setting the growth rate of the InAlAs buffer layer to 1 Å / s to 2.78 Å / s is the optimal range for balancing crystallization quality and production efficiency. This ensures uniform buffer layer thickness and complete crystallization, while also adapting to the subsequent superlattice growth rhythm and preventing the thickness ratio from deviating from the preset value.

[0078] In summary, the method provided by the embodiments of the present invention can achieve high-quality lattice matching between the InAlAs buffer layer and the InP substrate, reduce leakage current and interface defects, improve the flatness and crystal quality of the buffer layer, provide a stable and clean substrate for superlattice growth, and ensure the excellent performance of the final digital alloy material and APD device.

[0079] Furthermore, step S2 of the present invention preferably includes the following steps: turning on the Sb beam and Ga beam, and reducing the intensity of the As beam so that the As beam intensity is 3 to 6 times the sum of the In beam and Ga beam intensities, and the Sb beam intensity is 0.6 to 1.2 times the sum of the Al beam and Ga beam intensities, and growing on the surface of the InAlAs buffer layer. Layer 100; in On the surface of layer 100, a first GaAsSb layer 200, an n-type Si-doped GaAsSb layer 300, and a second GaAsSb layer 400 are sequentially stacked and grown.

[0080] Specifically, due to Layer 100 requires the simultaneous introduction of As and Sb elements to form AsSb bonds. Compared to the high As beam current (25-30 times) during the growth of the InAlAs buffer layer in step S1, reducing the As beam current can prevent As from excessively occupying Sb bonding sites, ensuring that Sb can be stably incorporated into the lattice. At the same time, a ratio of 3-6 times can ensure complete bonding of Group III elements such as In and Ga, avoiding vacancy defects caused by insufficient As.

[0081] Therefore, the embodiments of the present invention can precisely adjust the As beam intensity to 3 to 6 times the sum of the In and Ga beam intensities by adjusting it. The composition ratio of As to Sb in layer 100 ensures the integrity of the crystal structure, improves the compositional uniformity within the layer, and lays the foundation for subsequent interface bonding with the GaAsSb layer.

[0082] Furthermore, since Sb is As one of the key group V elements in the layer, its beam intensity needs to be matched with the total beam current of Al and Ga to ensure stable incorporation of Sb atoms. A lower limit of 0.6 times can prevent insufficient Sb from causing excessive As to form impurity phases, while an upper limit of 1.2 times can prevent excessive Sb from generating Sb inclusion defects.

[0083] The present invention enables the following embodiments to achieve the desired effect by adjusting the Sb beam intensity to 0.6 to 1.2 times the sum of the Al and Ga beam intensities. Precise controllability of the Sb composition in layer 100 improves the interlayer interface bonding quality, suppresses epitaxial defects such as dislocations and stacking faults, and ensures the band structure stability of this layer as a superlattice barrier layer.

[0084] Therefore, the above-mentioned steps provided in the embodiments of the present invention can be synergistically achieved through precise control of the beam ratio. The precise matching of the multi-component structure and high-quality epitaxial growth of the layer ensures a smooth stacking connection with the subsequent first GaAsSb layer 200, n-type Si-doped GaAsSb layer 300, and second GaAsSb layer 400. This effectively guarantees the structural integrity, compositional uniformity, and crystal quality of a single superlattice periodic unit, providing support for the subsequent periodic stacking to form a high-quality superlattice structure. This, in turn, helps to improve the electric field modulation capability and carrier transport performance of the final digital alloy material, ensuring the core optoelectronic characteristics of the APD device.

[0085] Furthermore, this invention also provides an avalanche photodiode. The multiplication region of the avalanche photodiode includes an InP substrate; A type semiconductor layer is disposed on the surface of the InP substrate and lattice-matched with the InP substrate; a digital alloy material is disposed on... The surface of the semiconductor layer; the digital alloy material is the n-type digital alloy material of the avalanche photodiode multiplication region as provided in the above embodiments, and is combined with... Lattice matching of the semiconductor layer; intrinsic A multiplication layer is formed on the surface of the digital alloy material and is lattice-matched to the digital alloy material; wherein the value of x ranges from 0.75 to 0.85; p-type A charge layer is disposed on the surface of the intrinsic AlGaAsSb multiplication layer and is lattice-matched with the intrinsic AlGaAsSb multiplication layer.

[0086] Specifically, in the avalanche photodiode's multiplication region, the InP substrate serves as the supporting substrate and growth reference for the entire multiplication region structure, providing a stable and flat carrier for the subsequent growth of epitaxial layers. At the same time, the selected semi-insulating InP substrate has high resistivity and low carrier concentration characteristics, which can effectively reduce the leakage current of the substrate itself, avoid interfering with the electric field distribution and carrier transport process in the multiplication region, and achieve the effect of improving the signal-to-noise ratio of the device and ensuring the stability of the avalanche multiplication process.

[0087] The ohmic semiconductor layer, serving as a transition layer between the InP substrate and the digital alloy material, plays a crucial role in constructing an ohmic contact interface, providing carrier injection channels, and buffering lattice strain between the substrate and the subsequent digital alloy material. To ensure lattice matching with the InP substrate, this layer preferably uses III-V compound semiconductor materials such as InGaAs or InAlAs. By precisely controlling its composition (e.g., the In content in InGaAs), its lattice constant is precisely matched with the lattice constant (0.5869 nm) of the InP substrate, avoiding defects such as dislocations due to lattice mismatch and ensuring the quality of interlayer bonding and carrier transport efficiency.

[0088] The digital alloy material provided in the above embodiments is grown on the surface of an n⁺-type semiconductor layer in the multiplication region of a photodiode as an electric field modulation and carrier transport optimization layer. Its core function is to regulate the electric field distribution in the multiplication region, suppress dark current, and improve carrier transport efficiency.

[0089] Specifically, digital alloy materials, through a multi-layered periodic barrier-well structure design, can homogenize the electric field intensity in the multiplication region and avoid premature breakdown caused by local strong electric fields. At the same time, by leveraging the lattice matching characteristics with the InP substrate and n⁺-type semiconductor layer, defect-assisted dark current paths are reduced, providing a stable carrier transport environment for the subsequent avalanche multiplication process of the multiplication layer.

[0090] Intrinsic The multiplication layer is the core functional layer for avalanche multiplication. "Intrinsic" means that this layer is undoped, reducing the interference of impurities on the collisional ionization process of charge carriers. Its core effect as a multiplication layer is to provide sufficient collisional ionization space for charge carriers, allowing photogenerated charge carriers to generate an avalanche multiplication effect through collisional ionization in this region, thus amplifying the optical signal. The value of x is set to range from 0.75 to 0.85, primarily because this component falls within this range... The material can achieve precise lattice matching with the InP substrate and adjacent digital alloy materials, while having a suitable band width and ionization coefficient ratio, which can both ensure avalanche multiplication efficiency and suppress reverse dark current.

[0091] p-type The charge layer, which is the electric field control and carrier confinement layer, is a "p-type" layer formed by doping with acceptor impurities such as Be (beryllium) and Zn (zinc). Its core function is to control the electric field distribution profile of the multiplication region and concentrate the strong electric field on the intrinsic side. Within the multiplication layer, holes are simultaneously blocked from diffusing back into the n⁺-type region, reducing carrier recombination losses.

[0092] p-type The value of x for the charge layer is also set to be between 0.75 and 0.85, in order to ensure harmony with adjacent intrinsic charge layers. Lattice matching of the multiplication layer and the overall multiplication region structure avoids lattice mismatch defects and electric field distortion at the interface, ensuring the accuracy of electric field control and the stability of the interlayer interface.

[0093] In summary, the multiplication region structure provided by the embodiments of this invention can effectively solve the problems of uneven electric field distribution, large dark current, low avalanche multiplication efficiency, and slow response speed in traditional APD multiplication regions. The final technical effects achieved are: uniform electric field distribution in the multiplication region, avoiding premature local breakdown; significantly reduced dark current, improving the signal-to-noise ratio of the device; improved carrier collisional ionization efficiency and multiplication gain, enhancing weak light detection capability; good lattice matching of each layer and excellent crystal quality, ensuring device response speed and operational stability, enabling APD devices to better adapt to high-performance application scenarios such as high-speed optical communication and weak light detection.

[0094] Above the aforementioned antimonide multiplication region material, arsenide materials such as InAlAs, InAlGaAs, and InGaAs in the transition and absorption regions, as well as the p-type layer of the device structure, are further grown to form a complete APD structure. This effectively solves the problems of lattice mismatch, bandgap mismatch, and incomplete device functional structure in the antimonide and arsenide systems. By buffering lattice strain in the transition region, efficiently capturing photons in the absorption region, and constructing a complete PN junction electric field in the p-type layer, the light absorption efficiency, carrier transport efficiency, and avalanche multiplication performance of the device are synergistically improved, ultimately achieving the core performance advantages of high responsivity, low dark current, and fast response speed of the APD.

[0095] Furthermore, The material of the semiconductor layer is Type InP material, Any one or more of the following InGaAs materials.

[0096] Type InP materials refer to materials produced by high concentration (… ~ Indium phosphide (InP) semiconductors, formed by doping with donor impurities such as Si, exhibit an n-type carrier concentration far exceeding that of intrinsic InP, and extremely low resistivity. They are used as... The semiconductor layer can achieve complete lattice matching with the InP substrate, significantly reducing the interface defect density; at the same time, it can form good ohmic contact with the substrate, providing an efficient longitudinal transport channel for charge carriers, and can also buffer the small lattice strain between the substrate and subsequent epitaxial layers, ensuring the stability of the interlayer structure.

[0097] InGaAs is a highly concentrated doped indium gallium arsenide ternary compound semiconductor, where the lattice constant can be precisely matched to the InP substrate by controlling the In composition. It is used as... The semiconductor layer has a more flexible band width control capability, which can better adapt to the band structure of subsequent digital alloy materials and reduce carrier recombination losses at the interface; at the same time, its high carrier concentration characteristics can ensure rapid carrier injection into the multiplication region and improve the device response speed.

[0098] The present invention creates an embodiment by selecting an n-type semiconductor layer. Type InP or The InGaAs material can be flexibly adapted to material selection and process requirements, ensuring lattice matching with the InP substrate, reducing interface defects, forming stable ohmic contacts and efficient carrier transport channels, providing uniform and stable carrier injection conditions for the subsequent avalanche multiplication process in the multiplication region, thereby improving the overall performance consistency of the APD device.

[0099] To verify the feasibility of the fabrication process and the stability of the doping efficiency of the n-type digital alloy material in the multiplication region of the avalanche photodiode described in this invention, a specific composition of GaAsSb was used as an example. , The specific components are The following two specific implementation examples are given:

[0100] Example 1: The growth rate of the n-type Si-doped GaAsSb layer 300 is set to 0.87 Å / s, and the Si doping source temperature is referenced to the growth rate of 1 μm / h. The carrier concentration is then determined. The doping source temperature for n-type GaAs was set to 1270℃. Following the process parameters, a single periodic unit was grown for 50 cycles. X-ray diffraction (XRD) analysis revealed a superlattice period of 10.02 nm. The average composition of the final digital alloy material was... The thickness is 501nm.

[0101] The digital alloy material was removed from the molecular beam epitaxy (MBE) equipment, and the wafer was cut into 10 mm × 10 mm square samples. Int was deposited at the four corners of the non-edge region of the intact material as electrodes. Subsequently, rapid thermal annealing was performed under a nitrogen atmosphere at 500°C for 1 min to ensure good ohmic contact between the electrodes and the material. The samples were tested using the van der Bauer method, and the Hall carrier concentration of the digital alloy material was determined to be n-type. The calculated Si doping efficiency in this material is: .

[0102] Example 2: The growth rate of the n-type Si-doped GaAsSb layer 300 is set to 0.90 Å / s, and the Si doping source temperature is referenced to the growth rate of 1 μm / h. The carrier concentration is then prepared accordingly. The doping source temperature for n-type GaAs was set to 1248℃. Following the process parameters, a single periodic unit was grown for 50 cycles. X-ray diffraction (XRD) analysis revealed a superlattice period of 9.92 nm. The average composition of the final digital alloy material was... The thickness is 496 nm.

[0103] The digital alloy material was removed from the molecular beam epitaxy (MBE) equipment, and the wafer was cut into 10mm × 10mm square samples. Int was deposited at the four corners of the non-edge region of the intact material as electrodes. Subsequently, rapid thermal annealing was performed under a nitrogen atmosphere at 500℃ for 1 minute to ensure good ohmic contact between the electrodes and the material. The samples were tested using the van der Bauer method, and the Hall carrier concentration of the digital alloy material was determined to be n-type. The calculated Si doping efficiency in this material is: .

[0104] In summary, the two specific embodiments described above verify the feasibility and stability of the fabrication process for the n-type digital alloy material in the avalanche photodiode multiplication region of this invention. By precisely controlling the growth rate of the n-type Si-doped GaAsSb layer 300 and the Si doping source temperature, after 50 cycles of cyclic growth, XRD analysis showed that a well-structured superlattice structure was formed. Van der Bauer method analysis showed that the Hall carrier concentration of the digital alloy material prepared in Example 1 reached [value missing]. Although Example 2 is (This is within the reasonable fluctuation range of the process), but the overall process can stably achieve high concentrations of n-type doping, and Example 1 clearly shows that it reaches 1×10¹ 8 The target carrier concentration is above cm⁻³. Meanwhile, the Si doping efficiencies of the two embodiments are 56.4% and 54.9%, respectively, demonstrating good doping stability. Therefore, the preparation process described in this invention can effectively prepare high-concentration n-type carrier digital alloy materials that meet the requirements of the APD multiplication region, and the verification results fully demonstrate the effectiveness and reliability of the process.

[0105] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0106] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0107] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0108] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An n-type digital alloy material for the multiplication region of an avalanche photodiode, characterized in that, include: A superlattice structure, lattice-matched to an InP substrate; the superlattice structure is formed by repeated stacking of single periodic units; the single periodic unit comprises sequentially stacked... The structure comprises a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer; wherein the value of x ranges from 0.75 to 0.85; the single periodic unit contains... The thickness ratio between the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer is 22:1:10:

1.

2. The n-type digital alloy material for the multiplication region of an avalanche photodiode according to claim 1, characterized in that, The The growth rate of the layer is from 0.6 Å / s to 1.6 Å / s; the growth rate of the n-type Si-doped GaAsSb layer is from 0.5 Å / s to 1.5 Å / s.

3. The n-type digital alloy material for the multiplication region of an avalanche photodiode according to claim 1, characterized in that, The thickness of the first GaAsSb layer is one monolayer thickness, which is half the lattice constant of the InP substrate.

4. The n-type digital alloy material for the multiplication region of an avalanche photodiode according to claim 1, characterized in that, The repeating period of a single periodic unit in the superlattice structure is from 10 to 100 periods.

5. The n-type digital alloy material for the multiplication region of an avalanche photodiode according to claim 1, characterized in that, The Si doping source temperature in the n-type Si-doped GaAsSb layer is determined based on the Si doping source temperature corresponding to the target carrier concentration of n-type GaAs at a growth rate of 1 micrometer / hour.

6. A method for preparing an n-type digital alloy material for the multiplication region of an avalanche photodiode, characterized in that, Includes the following steps: After treating the surface of the InP substrate, an InAlAs buffer layer is grown. On the surface of the InAlAs buffer layer, they are sequentially stacked and grown A single periodic unit is defined by a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer; wherein the value of x ranges from 0.75 to 0.85; the single periodic unit contains... The thickness ratio between the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer is 22:1:10:

1. The single periodic unit is repeatedly grown on the surface of the second GaAsSb layer according to a set period to generate a superlattice structure that matches the InP substrate lattice, thus obtaining a digital alloy material.

7. The method for preparing the n-type digital alloy material for the multiplication region of an avalanche photodiode according to claim 6, characterized in that, After treating the surface of the InP substrate, an InAlAs buffer layer is grown, including the following steps: The surface of the semi-insulating InP substrate is deoxidized. After deoxidation is completed, the surface temperature of the InP substrate is controlled within a first temperature range; wherein, the first temperature range is 500°C to 515°C. An InAlAs buffer layer is grown on the surface of the deoxidized InP substrate by turning on the As, In, and Al beams; wherein the As beam intensity is 25 to 30 times the sum of the In and Al beam intensities; and the growth rate of the InAlAs buffer layer is 1 Å / s to 2.78 Å / s.

8. The method for preparing the n-type digital alloy material for the multiplication region of an avalanche photodiode according to claim 7, characterized in that, On the surface of the InAlAs buffer layer, they are sequentially stacked and grown The process comprises a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer, including the following steps: Turn on the Sb and Ga beams, and reduce the intensity of the As beam so that the As beam intensity is 3 to 6 times the sum of the In and Ga beam intensities, and the Sb beam intensity is 0.6 to 1.2 times the sum of the Al and Ga beam intensities. Grow the InAlAs buffer layer on its surface. layer; In the On the surface of the layer, a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer are sequentially stacked and grown.

9. An avalanche photodiode, characterized in that, The multiplication region of the avalanche photodiode includes: InP substrate; A semiconductor layer is disposed on the surface of the InP substrate and is lattice-matched with the InP substrate; Digital alloy material, set in the The surface of the n-type semiconductor layer; the digital alloy material is the n-type digital alloy material of the avalanche photodiode multiplication region as described in any one of claims 1 to 5, and is combined with the... Lattice matching of the semiconductor layer; Intrinsic A multiplication layer is disposed on the surface of the digital alloy material and is lattice-matched with the digital alloy material; wherein the value of x ranges from 0.75 to 0.85; p-type A charge layer is disposed on the intrinsic The surface of the multiplication layer, and the intrinsic Lattice matching of multiplication layers.

10. The avalanche photodiode according to claim 9, characterized in that, The The material of the semiconductor layer is Type InP material, Any one or more of the following InGaAs materials.

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