A high mobility silicon carbide n-type ldmos device

Abstract

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and to an N-type LDMOS device structure with optimized SiC interface states. Background Technology

[0002] As a leading representative of third-generation wide-bandgap semiconductors, SiC has become a key research focus in the field of high-voltage power devices due to its superior electrical properties. SiC demonstrates outstanding advantages in high-voltage power devices thanks to its bandgap width, which is three times that of Si, and its higher thermal conductivity. However, as SiC is a compound semiconductor, both carbon and silicon atoms undergo oxidation reactions during the formation of the metal-oxide-semiconductor (MOS) interface. This unique chemical composition results in a complex transition layer during oxide layer formation in SiC, introducing interface states and near-interface traps that are significantly higher than in Si-based devices. Due to the presence of these interface states and traps, when the gate voltage increases, electrons induced on the semiconductor side of the SiO2-SiC interface are trapped by these interface states and traps, preventing them from participating in conduction. Furthermore, the trapped electrons and holes in these interface states and traps generate Coulomb forces that increase Coulomb scattering of inversion layer carriers, significantly reducing their mobility and affecting the device's on-resistance. In other words, the high density of interface states at the SiC-SiO2 interface makes the channel mobility of SiC MOSFETs much lower than the bulk mobility of the SiC material itself, greatly limiting the electrical performance of the SiC material. To solve this problem, the gate of the NLDMOS is made into a trench gate. This results in different interface state densities for SiC with different crystal orientations. The interface state density of the trench gate is better than that of the lateral interface state. Furthermore, electrons do not flow from the surface, but instead flow from the source through the region near the left side of the gate to form a channel, then flow into the N-type buried layer and into the drift region, flowing along the drift region through the N-type well region and finally to the drain. At the same time, based on the charge compensation principle, the vertical N-type buried layer and the upper and lower P-type epitaxial layers together form a mutually depleted reverse PN junction, which is beneficial to improving the breakdown voltage of the device. Meanwhile, the increase in the concentration of open-state carriers by extrinsic carriers reduces the on-resistance. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to propose a high-mobility silicon carbide N-type LDMOS device that can optimize the interface state problem of SiC, reduce the on-resistance, and improve the breakdown voltage.

[0004] The technical solution of the present invention is as follows:

[0005] A high-mobility silicon carbide N-type LDMOS device includes an N-type substrate, a P-type epitaxial layer on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region and a second P-type heavily doped region connected to the source on the N-type substrate, a second N-type heavily doped region connected to the drain in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polysilicon trench gate serving as the gate of the device is provided on the P-type epitaxial layer (2) and the polysilicon trench gate extends into the P-type epitaxial layer, an N-type buried layer is provided in the P-type epitaxial layer, and one end of the N-type buried layer is connected to the channel of the device and the other end is connected to the N-type well region.

[0006] Compared with the prior art, the present invention has the following advantages:

[0007] This invention extends the polysilicon trench gate 8 into the interior of the P-type epitaxial layer 2, so that the conductive channel of the device also extends into the interior of the P-type epitaxial layer 2. This allows the N-type buried layer 3, which is connected at both ends to the N-type well region 4 and the conductive channel respectively, to sink into the interior of the P-type epitaxial layer 2. This changes the electron flow path when the device is turned on, i.e., electrons flow downward into the interior of the P-type epitaxial layer 2 and then into the N-type well region 4 through the N-type buried layer 3 located inside the P-type epitaxial layer 2. This places the electron flow path in a region with low interface state density, improves the electron mobility of the conductive channel, reduces the on-resistance, and enhances the current carrying capacity.

[0008] 1. In this invention, the gate is disposed in an NLDMOS with a (0001) crystal plane in SiC. Compared to traditional LDMOS, the crystal-faceted design changes the conductive channel of the device from the traditional (0001) crystal-faceted channel located on the surface to one that passes through the interior of the device. Crystal-plane channel. This gate configuration allows the inversion channel to be located on the sidewall of the trench, i.e., the a-plane. In traditional structures, the channel on the Si plane (0001) is charged due to the trapping of electrons or holes by the SiC-SiO2 interface states and interface traps, which greatly reduces the mobility of carriers in the inversion layer and affects the on-resistance of the device. However, for the a-plane... Gate LDMOS optimizes the interface state problem after the change of electrical neutrality in the bandgap energy level, has a lower interface state density, improves the electron mobility of the conductive channel, and obtains a lower on-resistance.

[0009] 2. The introduction of the N-type buried layer in this invention redirects the current path to flow through the (0001) crystal plane inside the device, instead of flowing through the device surface, via the N-type buried layer, thus reducing the interface state density and achieving higher electron mobility. Furthermore, increasing the concentration of the N-type buried layer does not affect the breakdown voltage, while simultaneously reducing the equivalent resistance of the drift region, thereby lowering the on-resistance of the device. It is noteworthy that the N-type buried layer concentration in this invention is the same as that in conventional structures, meaning that the reduction in on-resistance is independent of the resistance effect caused by the drift region concentration.

[0010] 3. The introduction of an N-type buried layer in the structure of this invention can improve the breakdown voltage between the N-type buried layer and the P-type epitaxial layer. The N-type buried layer in the device is at a high potential, forming an anti-polarity PN junction with the P-type epitaxial layer near the surface of the device, mutually depleting each other. Simultaneously, it forms an anti-polarity PN junction with the P-type epitaxial layer inside the device, depleting together, which is beneficial for improving the breakdown voltage of the device. This also makes the potential distribution near the N-type buried layer region more uniform, unlike the concentrated potential distribution in ordinary trench structures. Therefore, although the impurity concentration of the epitaxial layer in the structure of this invention is relatively higher, the breakdown voltage of the device does not decrease but rather slightly increases. Attached Figure Description

[0011] Figure 1 The figure shown is a three-dimensional structural diagram of the present invention.

[0012] Figure 2 The diagram shown is a cross-sectional view of the structure of this invention.

[0013] Figure 3 The diagram shows the structure of the present invention along... Figure 2 Top view of the AA' section.

[0014] Figure 4 The diagram shows the structure of the present invention along... Figure 2 Top view of the cross-section of BB'.

[0015] Figure 5 The diagram shows the connection distribution of the first metal layer (15), the second metal layer (16), and the PAD in the structure of the present invention.

[0016] Figure 6 The diagram shown illustrates the working principle of the structure of this invention.

[0017] Figure 7 The diagram shown is a cross-sectional view of the traditional structure.

[0018] Figure 8 The diagram shows the breakdown voltage and current of the structure of this invention and the conventional structure.

[0019] Figure 9The diagram shows the voltage and current during the device conduction process of the structure of this invention and the conventional structure.

[0020] Figure 10 The following are shown along... Figure 2 and Figure 7 The AA' is a plot of electron mobility in the transverse direction of the device during the device conduction process, taken from the drift region.

[0021] Figure 11 The following are shown along... Figure 2 BB' and Figure 7 The transverse electric field distribution on the surface of the device at the time of breakdown is shown in the AA' cutout.

[0022] Figure 12 The diagram shows the breakdown locations of the structure of this invention and the conventional structure during avalanche breakdown. Figure 12 a is the breakdown location of the present invention, and 12b is the breakdown location of the conventional structure. Detailed Implementation

[0023] The present invention will now be described in detail with reference to the accompanying drawings:

[0024] A high-mobility silicon carbide N-type LDMOS device includes an N-type substrate 1, a P-type epitaxial layer 2 on the N-type substrate 1, an N-type well region 4, a first heavily doped P-type region 6, a first heavily doped N-type region 7, and a second heavily doped P-type region 10 connected to the source on the N-type substrate 1. A second heavily doped N-type region 5 is located within the N-type well region 4 and connected to the drain. The first heavily doped P-type region 6, the first heavily doped N-type region 7, and the second heavily doped P-type region 10 are connected. An oxide layer 11 is provided on the surfaces of the second N-type heavily doped region 5, the N-type well region 4, the first P-type heavily doped region 6, the first N-type heavily doped region 7, the second P-type heavily doped region 10, and the P-type epitaxial layer 2. The characteristic feature is that a polysilicon trench gate 8, serving as the gate of the device, is provided on the P-type epitaxial layer 2, and the polysilicon trench gate 8 extends into the P-type epitaxial layer 2. An N-type buried layer 3 is provided within the P-type epitaxial layer 2, and one end of the N-type buried layer 3 is connected to the channel of the device, while the other end is connected to the N-type well region 4. This embodiment can also be optimized as follows:

[0025] The number of first P-type heavily doped regions, first N-type heavily doped regions, and polysilicon trench gates is at least two, and each of the first P-type heavily doped regions, first N-type heavily doped regions, and polysilicon trench gates is surrounded by a P-type epitaxial layer.

[0026] Polysilicon trench gate located at Within the crystal plane.

[0027] The polysilicon trench gate is made of polysilicon with an external gate oxide layer.

[0028] The polysilicon trench gate is embedded in the N-type buried layer region with an embedding depth greater than 0.3 μm.

[0029] The distance from the upper surface of the P-type epitaxial layer to the upper surface of the N-type buried layer is 1.3 μm, the thickness of the N-type buried layer ranges from 1 to 1.1 μm, and the injection dose ranges from 1.1 to 1.2 × 10⁻⁶. 17 cm -2 .

[0030] The implantation dose range of the first P-type heavily doped region is 8 to 9 × 10e. 16 cm -2 The injection energy range is 60–120 keV.

[0031] The concentration of the N-type well region is greater than or equal to the concentration of the N-type buried layer region and less than or equal to the concentration of the second N-type heavily doped region.

[0032] The N-type well region should overlap with the N-type buried layer region in the vertical direction, and the overlap length should be greater than 0.1 μm; the length of the N-type well region in the horizontal direction should be greater than or equal to the length of the second heavily doped N-type region. The crystal plane of the device is the Si plane (0001), and the crystal plane of the polysilicon trench gate is the a plane. Reference Figure 2 The gate metal layer is located to the right of the second P-type heavily doped region, to the left of the first N-type heavily doped region, and abuts against the boundary of the first N-type heavily doped region, and is located in the first metal layer; the first metal layer of the source is connected to the second metal layer to form a source metal field plate, and is located above the gate metal layer.

[0033] Reference Figure 6 The working principle of the structure of this invention is shown in the figure. Electrons in the device flow from the N-type buried layer region through channel 17 and finally flow to the drain through the N-type well region. This path constitutes the electron flow path 18, and its direction is shown by the arrow in the figure. Due to the introduction of the N-type buried layer, this current path flows through the (0001) crystal plane inside the device and no longer flows through the device surface. This optimizes the carrier mobility limitation caused by the interface state traps of the silicon carbide material itself, thereby obtaining a higher electron mobility, that is, low on-resistance and large saturation current.

[0034] Reference Figure 7 The diagram shows the traditional cross-sectional structure. The electron flow path is along the silicon carbide surface AA' of the device. At this time, the electrons are easily trapped by the interface traps caused by the interface states of the silicon carbide material, which affects the carrier mobility and reduces the on-resistance and saturation current.

[0035] Reference Figure 8The figure shows a comparison of the breakdown voltage of the structure of the present invention and the conventional structure. The structure of the present invention can improve the current characteristics of the device while slightly improving the breakdown voltage characteristics of the device. The breakdown voltage shown in the figure is improved by about 3%.

[0036] Reference Figure 9 The figure shows a comparison of the voltage and current of the structure of the present invention and the traditional structure during the device conduction process. In the linear region, the on-resistance of the present invention is increased by about 40%, and in the saturation region, the saturation current of the device is increased by about 26%.

[0037] refer to Figure 10 The following are the directions along... Figure 2 and Figure 7 The figure shows a comparison of the electron mobility in the lateral direction of the device within the drift region during the device conduction process, as captured by AA'. The comparison reveals that, while the total device length is almost the same, the drift region length increases due to the change in the electron flow path. Furthermore, integrating over the corresponding drift region positions shows that the total carrier mobility of this invention is higher than that of the conventional structure; that is, this invention achieves an improvement in carrier mobility.

[0038] refer to Figure 11 The following are the directions along... Figure 2 BB' and Figure 7 The AA' cutout shows the transverse electric field distribution on the surface of the device during breakdown, which is a comparison of the breakdown electric field distribution of the present invention and the traditional structure. By integrating the curve, it can be concluded that the breakdown voltage of the structure of the present invention is greater.

[0039] refer to Figure 12 The image shows a comparison of the breakdown locations of the structure of this invention and the traditional structure during avalanche breakdown. Figure 12 The penetration location of the invention in a is significantly higher than that in a. Figure 12 In section b, the breakdown location of the traditional structure is shifted downwards, which optimizes the lateral breakdown voltage of the device and increases the longitudinal breakdown voltage. This optimizes the electric field distribution of the device and increases its breakdown voltage.

[0040] The working principle of this invention is as follows:

[0041] The gate in this invention is disposed in an NLDMOS with a (0001) crystal plane in SiC. Compared to traditional LDMOS, the crystal-faceted design changes the conductive channel of the device from the traditional (0001) crystal-faceted channel located on the surface to one that passes through the interior of the device. Crystal-faceted channel. This gate design allows the inversion channel to be located on the sidewalls of the trench. Subsequently, the current path is directed through the (0001) crystal plane inside the device and no longer flows from the device surface, but rather through the N-type buried layer. It is noteworthy that the N-type buried layer of this invention has the same N-type drift region concentration as in conventional structures; that is, the reduction in on-resistance in this invention is independent of the resistance effect caused by the drift region concentration. This change in the current path optimizes the interface state problem after the bandgap energy level changes its electrical neutrality, resulting in a lower interface state density, improved electron mobility in the conductive channel, and ultimately, lower on-resistance.

[0042] Furthermore, the N-type buried layer and the P-type epitaxial layer can improve the breakdown voltage. The N-type buried layer in the device is at a high potential, forming an anti-polarity PN junction with the P-type epitaxial layer near the device surface, mutually depleting each other. Simultaneously, it forms an anti-polarity PN junction with the P-type epitaxial layer inside the device, depleting together, which helps to improve the device's breakdown voltage. This also makes the potential distribution near the N-type buried layer region more uniform, unlike the concentrated potential distribution found in conventional trench structures. Therefore, the breakdown voltage of this invention is also slightly improved.

Claims

1. A high-mobility silicon carbide N-type LDMOS device, comprising an N-type substrate (1), a P-type epitaxial layer (2) disposed on the N-type substrate (1), an N-type well region (4), a first P-type heavily doped region (6), a first N-type heavily doped region (7), and a second P-type heavily doped region (10) connected to the source on the P-type epitaxial layer (2), a second N-type heavily doped region (5) connected to the drain in the N-type well region (4), the first P-type heavily doped region (6), the first N-type heavily doped region (7), and the second P-type heavily doped region (10) being connected, and an oxide layer (11) disposed on the surface of the second N-type heavily doped region (5), the N-type well region (4), the first P-type heavily doped region (6), the first N-type heavily doped region (7), the second P-type heavily doped region (10), and the P-type epitaxial layer (2), characterized in that, A polysilicon trench gate (8) serving as the gate of the device is provided on the P-type epitaxial layer (2), and the polysilicon trench gate (8) extends into the P-type epitaxial layer (2). An N-type buried layer region (3) is provided in the P-type epitaxial layer (2), and one end of the N-type buried layer region (3) is connected to the channel of the device, and the other end is connected to the N-type well region (4).

2. The high-mobility silicon carbide N-type LDMOS device according to claim 1, characterized in that, The number of the first P-type heavily doped region (6), the first N-type heavily doped region (7) and the polysilicon trench gate (8) is at least 2. The unit structure is composed of the first P-type heavily doped region (6), the first N-type heavily doped region (7) and the polysilicon trench gate (8), and each unit structure is surrounded by a P-type epitaxial layer (2).

3. The high-mobility silicon carbide N-type LDMOS device according to claim 1 or 2, characterized in that, The polysilicon trench gate (8) is located in Within the crystal plane.

4. The high-mobility silicon carbide N-type LDMOS device according to claim 3, characterized in that, The polysilicon trench gate (8) is made of polysilicon with an external gate oxide layer (9).

5. The high-mobility silicon carbide N-type LDMOS device according to claim 1, characterized in that, The polysilicon trench gate (8) is embedded in the N-type buried layer region (3) with an embedding depth greater than 0.3 mm.

6. The high-mobility silicon carbide N-type LDMOS device according to claim 1, characterized in that, The distance from the upper surface of the P-type epitaxial layer (2) to the upper surface of the N-type buried layer region (3) is 1.3 mm, the thickness of the N-type buried layer region (3) ranges from 1 to 1.1 mm, and the injection dose ranges from 1.1 to 1.2 × 10⁻⁶. 17 cm -2 .

7. The high-mobility silicon carbide N-type LDMOS device according to claim 1, characterized in that, The implantation dose range of the first P-type heavily doped region (6) is 8~9×10e 16 cm -2 The injection energy range is 60~120keV.

8. The high-mobility silicon carbide N-type LDMOS device according to claim 1, characterized in that, The concentration of the N-type well region (4) is greater than or equal to the concentration of the N-type buried layer region (3) and less than or equal to the concentration of the second N-type heavily doped region (5).

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