Block floating point operation device and differential equation calculation system

Abstract

The application provides a block floating point operation device and a differential equation calculation system, and relates to the field of calculation devices. The differential equation calculation system manages the flow of data organized in a difference format between storage levels through a buffer controller, synchronously performs Gauss-Seidel iteration calculation optimized for the difference format based on a wavefront sequence by a processing unit array, compresses the result through a block floating point quantizer, and outputs a solution matrix through a difference reduction unit after convergence. In the processing unit array, multiple parallel processing units combine precision configuration with a block floating point input format to form a cooperatively optimized calculation mode. By sharing index compression data, dynamic precision parameters allow further control of the complexity of the mantissa during the calculation process, solving the problems of high resource occupation demand, memory access frequency and energy consumption.

Description

Technical Field

[0001] This application relates to the field of computing device technology, and in particular to a block floating-point arithmetic device and a differential equation calculation system. Background Technology

[0002] Partial differential equations can describe natural and engineering phenomena such as acoustics, heat conduction, and electromagnetism. Solving these equations requires numerical methods. The finite difference method obtains numerical solutions through discrete approximation. This process is computationally intensive and has a clear need for hardware acceleration.

[0003] Dedicated hardware accelerators are used to perform finite difference computations; these accelerators employ specific systems to process discrete grid data. In-memory processing techniques are also used to improve computational efficiency; these techniques aim to reduce latency in processor data access. The implementation of hardware acceleration impacts the performance of the solution process.

[0004] When solving partial differential equations based on the Finite Difference Method (FDM), dedicated hardware accelerators lack optimized data path design, leading to frequent memory accesses and high energy consumption. Furthermore, in-memory processing technology limits computational accuracy and grid scalability, resulting in high hardware resource consumption and storage requirements. Summary of the Invention

[0005] This application provides a block floating-point arithmetic device and a differential equation calculation system to solve the problems of high resource consumption, high memory access frequency, and high energy consumption.

[0006] In a first aspect, this application provides a block floating-point arithmetic device, comprising:

[0007] The input interface is configured to receive the first floating-point operand, the second floating-point operand, and the mantissa bit width configuration parameter.

[0008] The reconstructed data processing path, connected to the input interface, is configured to: perform operations on the first and second floating-point operands based on the mantissa bit width configuration parameters to obtain the operation result;

[0009] The output interface, connected to the reconstructed data processing path, is configured to output the calculation result.

[0010] Secondly, a differential equation computation system includes:

[0011] A buffer controller is configured to load target data in a difference format from external memory into an on-chip buffer, wherein the target data is a data block of the solution matrix and the source term matrix; the difference format is that in the target data, each element except the first column is stored as a difference value with the element of the previous column.

[0012] The processing unit array includes a plurality of parallel processing units, wherein the processing unit includes the block floating-point arithmetic device as described in any of the first aspects;

[0013] The buffer controller is further configured to send the target data in the differential format to the processing unit array according to the wavefront sequence, wherein the wavefront sequence is to group the grid points according to multiple wavefronts.

[0014] The processing unit is configured to: synchronously perform Gauss-Seidel iterative calculations based on a difference scheme on the target data within the wavefront to update the difference matrix of the solution;

[0015] A block floating-point quantizer is configured to: perform block floating-point quantization on the updated difference matrix according to the two-dimensional block size and the target mantissa bit width to output quantized data, wherein the block floating-point quantization assigns a shared exponent to multiple values ​​within the two-dimensional block; the quantized data is used in the on-chip buffer for the next iteration;

[0016] The difference restoration unit is configured to restore the difference matrix in the on-chip buffer to the solution matrix during iterative convergence.

[0017] As can be seen from the above technical solutions, this application provides a block floating-point arithmetic device and a differential equation calculation system. The differential equation calculation system includes: a buffer controller configured to load target data in a difference format from external memory into an on-chip buffer, wherein the target data is a data block of the solution matrix and the source term matrix of the equation; the difference format is that in the target data, each element except the first column is stored as the difference value with the element of the previous column; a processing unit array includes multiple parallel processing units, each processing unit including a block floating-point arithmetic device; the buffer controller also sends the target data in the difference format to the processing unit according to the wavefront order. The array, wherein the wavefront sequence groups grid points according to multiple wavefronts; the processing unit is configured to synchronously perform Gauss-Seidel iterative calculations based on a difference format on the target data within the wavefronts to update the difference matrix of the solution; a block floating-point quantizer is configured to perform block floating-point quantization on the updated difference matrix according to the two-dimensional block size and the target mantissa bit width to output quantized data, wherein the block floating-point quantization assigns a shared exponent to multiple values ​​within the two-dimensional block; the quantized data is stored in an on-chip buffer for the next iteration; a difference restoration unit is used to restore the difference matrix in the on-chip buffer to the solution matrix when the iteration converges. The differential equation calculation system reduces exponent storage overhead by sharing the same target exponent; dynamically reconstructs the data processing path based on mantissa bit width configuration parameters to improve computational efficiency and flexibility; processes the target data in a difference format in parallel based on the wavefront sequence; and combines block floating-point quantization to achieve efficient iterative solution while reducing data volume. Attached Figure Description

[0018] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the block floating-point arithmetic device provided in the embodiments of this application;

[0020] Figure 2 A schematic diagram of matrix floating-point quantization provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the adder path provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of the multiplier path provided in the embodiments of this application;

[0023] Figure 5 This is a schematic diagram of the differential equation calculation system provided in the embodiments of this application;

[0024] Figure 6 A schematic diagram illustrating the complete computational periodicity decomposition of the wavefront Gauss-Seidel method applied to a regular mesh, as provided in an embodiment of this application.

[0025] Figure 7 A schematic diagram of the iterative process of the Gauss-Seidel method provided in the embodiments of this application;

[0026] Figure 8 This is a schematic diagram of the tail number iteration provided in the embodiments of this application;

[0027] Figure 9 This is a schematic diagram of the differential equation calculation process provided in an embodiment of this application. Detailed Implementation

[0028] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following examples do not represent all embodiments consistent with this application.

[0029] Some embodiments of this application provide a block floating-point arithmetic device, such as... Figure 1 As shown, it includes:

[0030] The input interface is configured to receive the first floating-point operand, the second floating-point operand, and the mantissa bit width configuration parameter.

[0031] The first and second floating-point operands are two source data objects received by the input interface for arithmetic operations. Both operands are in block floating-point format. Block floating-point format allows multiple values ​​within a data block to share the same exponent (shared exponent), while each value has its own sign bit and mantissa. Compared to standard floating-point format, where each value has an independent exponent, block floating-point format saves bits required to store the exponent when storing a group of similar values.

[0032] The first and second floating-point operands can each be associated with a shared exponent of their respective data blocks. At the input interface, these two operands can be received in the form of a target exponent and their respective independent mantissas.

[0033] The data blocks are two-dimensional blocks, and the size of the two-dimensional blocks is configurable, for example, 2×2 or 4×4. The block size parameter is set through a programmable register, thereby flexibly balancing the compression ratio and accuracy loss according to the characteristics of the problem.

[0034] like Figure 2 As shown, the quantization of a 4×4 matrix with a block size of 2×2 is taken as an example:

[0035] The matrix is ​​divided into non-overlapping 2×2 blocks. Within each block, the largest exponent is selected as the shared exponent, and the mantissas of other data within the block are right-shifted according to their differences from the shared exponent. Finally, low-order bits exceeding the specified mantissa length are truncated, and a value of zero indicates a zero value. This process transforms the original model, where each number required 32 bits (single precision) of storage, into a group of data sharing a single exponent and multiple shortened mantissas, significantly reducing storage bandwidth and data transfer volume.

[0036] The data processing path is reconstructed and connected to the input interface. It is configured to perform operations on the first and second floating-point operands based on the mantissa bit width configuration parameters to obtain the operation result.

[0037] The path performs the specified arithmetic operation, but the specific behavior is dynamically controlled by the mantissa bit width configuration parameter. The mantissa bit width is not fixed, but can be automatically switched according to the number of iterations under a predefined strategy.

[0038] The circuit includes basic hardware units for processing floating-point numbers, such as logic for handling special values, shifters for aligning the exponent and mantissa, arithmetic logic units for performing mantissa addition, subtraction, or multiplication, and shift and rounding logic for normalizing the result. At the start of the operation, the control logic within the circuit first reads the mantissa bit width configuration parameter and, based on this parameter value, generates a series of micro-control signals to pre-configure the aforementioned hardware units. For example, it configures the input bit width selector of the mantissa processing unit to receive only the specified number of valid mantissa bits, and configures the cutoff circuit of the normalization unit to discard redundant low-order bits after the specified number of bits.

[0039] In this embodiment, the reconstructed data processing path includes an adder path and a multiplier path. The multiplier and adder are specially customized for block floating-point operations, supporting different mantissa bit widths and performing block floating-point operations.

[0040] like Figure 3 As shown, the adder path includes a first special value processing unit, a first sign bit processing unit, a first floating-point number restoration unit, an exponent alignment unit, a mantissa operation unit, a first normalization unit, and a first carry processing unit.

[0041] After the adder path is operational, the first special value processing unit checks the two operands, decodes their bit patterns, and determines whether they are denormalized numbers, zero values, or other special codes. If a special value is found, the unit will bypass subsequent complex calculations and directly output a preset standard result or identifier signal. If a normal value is found, the unit will pass it to the next stage.

[0042] Next, the first sign bit processing unit reads the sign bits of the two operands and pre-calculates the sign bit of the result according to the rules of addition. For additions with the same sign, the sign of the result is the same as that of the operands; for additions with different signs, the sign of the result depends on the sign of the operand with the larger absolute value, which may require comparing the size of the operands. This unit outputs this pre-determined sign bit, which will be combined with the finally calculated numerical part.

[0043] Subsequently, the first floating-point number restoration unit receives two block floating-point operands that share a target exponent and each has an independent mantissa. It also receives a mantissa width configuration parameter. Based on this parameter, it combines the input mantissa, adjusted relative to the shared exponent, with the shared target exponent to reconstruct two explicit floating-point numbers with independent exponents and mantissa representations. For example, the mantissa width M1 converts the block floating-point data into actual floating-point data; M1 is the mantissa width of the input addend.

[0044] Then, the exponent alignment unit compares the exponents of the two explicit floating-point numbers. If the exponents are different, the exponent difference is calculated, and an alignment control signal is generated. The alignment control signal indicates that the mantissa of the operand with the smaller exponent needs to be shifted to the right by a number of bits equal to the absolute value of the exponent difference, so that the exponents of the two operands are aligned to the larger value.

[0045] The mantissa arithmetic unit performs operations according to the alignment control signal, receiving the mantissas of the two explicit floating-point numbers and the expected result sign information from the first sign bit processing unit. Internally, the unit includes a multiplexer and a shifter, right-shifting the mantissa of the operand with the smaller exponent indicated by the alignment control signal. Then, the mantissa adder determines whether to perform addition or subtraction based on the sign bits of the two original operands and the result of a numerical comparison, and performs the corresponding arithmetic operation on the aligned mantissas to produce an unnormalized mantissa result.

[0046] The first normalization unit processes the unnormalized mantissa result. The leading zero detection circuit within the unit quickly determines the number of zeros preceding the most significant bit in the result. Then, a barrel shifter shifts the mantissa result to the left based on this number, eliminating leading zeros and transforming it into normalized form. Simultaneously with the left shift, the unit's exponent adjustment logic subtracts the number of bits shifted from the previously aligned large exponent to obtain a preliminary normalized exponent. Throughout this process, the unit strictly adheres to the input mantissa bit width configuration parameters, truncating the normalized mantissa and discarding low-order bits exceeding the specified bit width.

[0047] Finally, the first carry processing unit checks the normalized mantissa. If a carry occurred in the most significant bit of the mantissa during the normalization left shift, the unit shifts the mantissa one bit to the right and increments the initial normalization exponent by one. After this final adjustment, the final mantissa value, exponent value, and sign bit from the first sign bit processing unit are obtained. These three are combined to form the addition result, which is then sent to the output interface.

[0048] The output interface is connected to the reconstructed data processing path and is configured to output the result of the addition operation.

[0049] When a block floating-point arithmetic unit is configured to perform multiplication, its internal path is instantiated as a multiplier path. For example... Figure 4 As shown, the multiplier path includes: a second special value processing unit, a second sign bit processing unit, a second floating-point number restoration unit, an exponent processing unit, a mantissa processing unit, a second normalization processing unit, and a second carry processing unit.

[0050] The second special value processing unit is configured to process the denormalized values ​​in the first and second floating-point operands to output the third and fourth standard operands; the second sign bit processing unit is configured to determine the sign bit of the multiplication result based on the sign bit of the third and fourth standard operands.

[0051] The second floating-point number restoration unit is configured to restore the format of the third and fourth standard operands to an explicit floating-point format based on the third standard operand, the fourth standard operand, and the mantissa bit width configuration parameters, so as to obtain the third explicit operand and the fourth explicit operand; the exponent processing unit is configured to perform addition on the exponents of the third explicit operand and the fourth explicit operand to calculate the exponent sum and output the intermediate exponent.

[0052] The mantissa processing unit is configured to perform multiplication on the mantissas of the third and fourth explicit operands to obtain the mantissa product; the second normalization processing unit is configured to perform normalization shift processing on the mantissa product, truncate the mantissa according to the mantissa bit width configuration parameter, and adjust the intermediate exponent to output the second normalized mantissa and the second normalized exponent.

[0053] The second carry processing unit is configured to process the carry of the second normalized mantissa and adjust the second normalized exponent to obtain the multiplication result.

[0054] The front-end processing of the multiplier path is similar to that of the adder path. The second special value processing unit performs anomaly detection on the input operands. The second sign bit processing unit calculates the sign bit of the product directly from the sign bits of the two operands through a simple XOR gate. The second floating-point number restoration unit performs the same function as the first floating-point number restoration unit, restoring the block floating-point operands to explicit floating-point format.

[0055] Subsequently, the processing flow of the multiplier path differs from that of the adder. The exponent processing unit receives the exponents of two explicit floating-point operands, adds the two exponents together using the adder, and obtains the intermediate exponent value of the product. At the same time, the mantissa processing unit receives the mantissas of the two operands, performs binary multiplication of the two mantissas, and outputs the bit-width extended, unnormalized mantissa product.

[0056] Since the multiplication result may cause the mantissa to exceed the normalization range, the leading zero detection circuit detects the high-order bits of the product. The barrel shifter shifts the product to the left based on the detection result to normalize it. During this process, the intermediate exponent value obtained by the exponent processing unit is correspondingly subtracted by the number of bits shifted left. Similar to the addition path, the mantissa of the result is truncated according to the mantissa bit width configuration parameter. The second carry processing unit checks and processes any carry that may occur after normalization, adjusts the exponent, and combines it with the product sign bit to form the multiplication result.

[0057] The output interface is connected to the reconstructed data processing path and is configured to output the result of the multiplication operation.

[0058] The mantissa bit width configuration parameter is used in steps such as restoration, calculation, and normalization truncation, enabling the data path to flexibly adapt to different precision calculation requirements. From input restoration to output, the computing device can dynamically reduce the bit width and switching activity of the data path while ensuring the necessary calculation accuracy, thereby optimizing energy efficiency and performance.

[0059] Based on the aforementioned block floating-point arithmetic device, some embodiments of this application also provide a differential equation calculation system for solving partial differential equations discretized using the finite difference method, such as the Poisson equation. By organizing the calculation order, compressing data representation, and using dedicated hardware for calculation, the system significantly reduces the dependence on memory bandwidth and overall energy consumption while ensuring calculation accuracy.

[0060] like Figure 5 As shown, the system includes:

[0061] The buffer controller is configured to load differentially formatted target data from external memory into the on-chip buffer. The differentially formatted target data is a set of data organized according to specific rules in external memory. The target data includes the solution matrix and source term matrix obtained from the discretization of the partial differential equation to be solved. In the differential format, when storing these matrices, for each data element in a row, except for the element in the first column which stores its original value, each element in subsequent columns of that row does not directly store its original value; instead, it stores the difference between the original value of that element and the original value of its preceding adjacent element.

[0062] On-chip buffers are used to temporarily store data blocks needed directly in the current computation cycle. Their purpose is to localize data, thereby preventing the processing unit array from stalling while waiting for data. In some embodiments, on-chip buffers include current value buffers, offset buffers, and iteration buffers, which will be described in detail later.

[0063] The processing unit array includes multiple parallel processing units. Each processing unit includes a block floating-point arithmetic device as described above. In other words, the computing power of each processing unit is provided by the block floating-point arithmetic device defined in the above embodiments. Each processing unit integrates an input interface, a reconfigurable data processing path, and an output interface. It has the ability to receive block floating-point operands with shared exponents, perform dynamic precision arithmetic operations according to configuration parameters, and output the results.

[0064] The buffer controller is also configured to send the target data in differential format to the processing unit array according to the wavefront sequence, which is a grouping of grid points into multiple wavefronts. The wavefront sequence is a rule for grouping and scheduling all grid points in the computational grid. This sequence decomposes the entire update process of the computational grid into multiple sequentially executed stages, each stage being called a wavefront.

[0065] In some embodiments, the wavefront order is as follows: grid points are divided into multiple wavefronts according to the sum of their row and column indices, wherein grid points with the same sum of row and column indices belong to the same wavefront; the buffer controller is configured to send the target data corresponding to the grid points within the same wavefront to the processing unit array according to the wavefront division order; the processing unit array is configured to perform parallel update calculations on the target data corresponding to the grid points within the same wavefront.

[0066] By grouping all grid points in the same wavefront into the same wavefront, we can ensure that there are no direct data dependencies between all grid points within the same wavefront, thus allowing them to be computed in parallel.

[0067] The buffer controller distributes the data in the on-chip buffer to the processing unit array according to the wavefront order. The wavefront order is determined based on the geometry of the computational grid. For a two-dimensional computational grid with M rows and N columns, the total number of wavefronts is M+N-1. The first wavefront contains only the point at the top left corner of the grid, the second wavefront contains the two adjacent points at the bottom right corner, and so on. Each wavefront consists of all grid points along a diagonal. The buffer controller sequentially provides the data required for calculation (i.e., the difference values ​​between the point and its neighbors above, below, left, and right) for each grid point within the same wavefront to the corresponding processing unit in the processing unit array, according to the wavefront number from low to high.

[0068] The processing unit is configured to synchronously perform Gaussian-Seidel iterative calculations based on a difference scheme on the target data within the wavefront to update the difference matrix of the solution. During processing, the processing unit performs synchronous calculations. For Gaussian-Seidel iterations, the calculations of the processing unit are performed using difference values. The internal operational logic of the processing unit is designed or configured to handle these difference values, so that the calculation process is completed within the difference value domain. It is not necessary to restore the difference values ​​to the original solution values ​​in the processing unit before calculation. After each processing unit completes its calculation, it outputs the difference representation of the updated solution value for that grid point.

[0069] The core idea of ​​the wavefront Gauss-Seidel method is that there is no data dependency between all marked grid points within the same wavefront (or computation cycle), so computation can be performed simultaneously. This effectively transforms the Gauss-Seidel method from a serial process to a fine-grained parallel process, significantly improving execution efficiency on parallel computing devices while maintaining its original convergence speed.

[0070] like Figure 6 The diagram shows a complete computational periodic decomposition diagram of applying the wavefront Gauss-Seidel method to a 5×5 regular grid. The execution process is as follows:

[0071] The calculation is initialized at the top-left corner of the grid, point (1, 1). Since this point has no left or upper neighbors dependent on the new value, it is updated first in the first calculation cycle (wavefront 1). Subsequently, the calculation process is like a wavefront advancing from the top left to the bottom right. In each subsequent cycle, all grid points whose new values ​​have been calculated for their left and lower neighbors are added to the current wavefront and updated in parallel. In the second calculation cycle (wavefront 2), points (2, 1) and (1, 2) are updated in parallel; in the third calculation cycle (wavefront 3), points (3, 1), (2, 2), and (1, 3) are updated in parallel.

[0072] This process continues, as shown in the figure. The number of points that can be computed in parallel gradually increases to a peak and then decreases. The computation is finally completed at the upper right corner point (5, 5) in the ninth computation cycle (wavefront 9). In summary, for an N×N two-dimensional mesh, this method decomposes one complete iteration into 2N-1 computation cycles. Figure 6 The diagram clearly demonstrates how the nine wavefront periods systematically cover all 25 grid points within a 5×5 grid.

[0073] Taking the two-dimensional Poisson equation as an example:

[0074] ;

[0075] in, It is known, and To be solved, the finite difference method will be used to... and Convert to along and The direction has a step size Δ and Δ The grid is M×N. Therefore, the derivative can be approximated by finite difference as follows:

[0076] ;

[0077] ;

[0078] Therefore, the Poisson equation can be expressed as an M×N system of equations, as shown below:

[0079] ;

[0080] ;

[0081] The grid is uniformly distributed, and Δx and Δy are equal, from which the following formula can be derived:

[0082] (1)

[0083] All values ​​in the N×M grid are updated according to the above formula until the solution converges to the steady-state value. This is called the five-point template calculation.

[0084] In some embodiments, the processing unit determines the corresponding differential iteration calculation formula based on the position of the current grid point; based on the difference value in the difference matrix of the solution and the difference value of the source term matrix, it performs an update calculation of the differential iteration calculation formula to obtain the difference result; wherein, the operands of the differential iteration calculation formula and the difference result are both difference values.

[0085] like Figure 7As shown, the Gauss-Seidel method updates the value of the current iteration using the latest available value of u, expressed as:

[0086] (2)

[0087] However, the Gauss-Seidel method introduces data dependencies, as each update of u-value depends on the latest u-values ​​above and to the left, sacrificing computational parallelism.

[0088] The system provided in this embodiment uses [method / technology] when storing solutions, storing source terms, and iteratively calculated solutions. Alternative solution ,use Alternative solution Only the original value of the solution is stored in the first column; the values ​​in each subsequent row are the differences between that solution and the previous solution. The formula is as follows:

[0089] = - (3)

[0090] = - (4)

[0091] In solving differential equations using the finite difference grid method, the difference values ​​do not require iterative intermediate reconstruction of their corresponding values. The following is a detailed derivation:

[0092] Formula (2) has been derived above. The five-point template of the Poisson equation is calculated as follows:

[0093] ;

[0094] Next, based on formulas (2), (3), and (4), the differential iteration formula is derived, which can be divided into three cases: In some embodiments, the processing unit calls different calculation logics to update the target data based on whether the currently calculated grid point is located on the matrix boundary.

[0095] The different calculation logics include at least: a first calculation logic, a second calculation logic, and a third calculation logic; the first calculation logic is used to process the grid points of the first boundary of the matrix and calculates based on the boundary condition value; the second calculation logic is used to process the grid points within the matrix and calculates based on the difference value of adjacent grid points in different directions; the third calculation logic is used to process the grid points of the second boundary of the matrix and calculates based on the sum of the difference values ​​of multiple grid points in that row.

[0096] Specifically, for the case where j=1, refer to the following formula for calculation:

[0097] (5)

[0098] For the case where j≠1 and j≠N-1, refer to the following formula for calculation:

[0099] (6)

[0100] 3) For the case where j=N-1, refer to the following formula for calculation:

[0101] (7)

[0102] The above formulas only use difference values ​​and boundary conditions (such as...). , Iteration is performed without the need for restoration. This allows for multiple iterations.

[0103] The block floating-point quantizer is configured to perform block floating-point quantization on the updated difference matrix according to the two-dimensional block size and the target mantissa bit width to output quantized data. Here, the block floating-point quantization assigns a shared exponent to multiple values ​​within the two-dimensional block; the quantized data is buffered on-chip for the next iteration.

[0104] Specifically, the block floating-point quantizer organizes this data into two-dimensional blocks of a preset size. For each block, the quantizer finds the element with the largest value within the block, extracts the exponent of that element, and uses it as the shared exponent for the entire data block. Then, the quantizer adjusts and truncates the mantissa of each value within the block according to the target mantissa bit width configured for the current iteration stage (for example, a narrower bit width in the early stages of iteration and a wider bit width in the later stages of iteration). In this process, quantized data in block floating-point format is generated. This quantized data is written back to the specified storage area in the on-chip buffer by the buffer controller as input for the next round of iteration calculation, overwriting the old solution data.

[0105] In some embodiments, the target mantissa bit width is configured with multiple different values ​​and is set based on the iteration stage. For example, the iteration stage can be divided into a first stage, a second stage, and a third stage, with the third stage being closest to the convergence condition. The target mantissa bit width corresponding to the first stage is the first bit width, the corresponding to the second stage is the second bit width, and the corresponding to the third stage is the third bit width, wherein the value of the third bit width is greater than the value of the second bit width, and the value of the second bit width is greater than the value of the first bit width.

[0106] The target mantissa bit width determines how many binary significant bits the block floating-point quantizer retains in the mantissa of each value when converting the difference value to block floating-point format. This bit width is configured based on the iteration stage. It can be understood that the iteration stage is not just divided into three stages, but can be further divided. However, what remains unchanged is that in the early stage of iteration, a computation speed close to a low-precision fixed configuration is needed, and in the later stage of iteration, a convergence accuracy of a high-precision fixed configuration can be achieved, thus realizing the optimal balance between computational efficiency and final accuracy overall.

[0107] For example, such as Figure 8 As shown, when solving a two-dimensional Poisson equation, the following configuration strategy can be adopted: In the early stage of iteration (0-150 iterations), a 12-bit mantissa is used for fast, low-precision approximation; in the middle stage of iteration (151-900 iterations), a 16-bit mantissa is switched to improve convergence accuracy; in the later stage of iteration (901-3100 iterations), a 20-bit mantissa is further used; and in the final stage of convergence (after 3101 iterations), a 24-bit mantissa is used for final refinement to ensure reliable results. This method of dynamically configuring the target mantissa bit width based on the iteration stage, from lower to higher bit widths, can significantly reduce the computational load and energy consumption of multipliers and adders during most of the iteration time.

[0108] In some embodiments, the system further includes an error calculation unit, which is configured to: calculate the difference between the current iteration solution and the previous iteration solution, determine whether the convergence condition is met based on the difference, and output the determination result; the buffer controller is configured to: in response to the determination result that the convergence condition is not met, use the quantized data as the input for the next iteration; and in response to the determination result that the convergence condition is met, trigger the difference restoration unit to output the final solution matrix.

[0109] When the error calculation unit determines that the global error norm is less than a preset threshold, the convergence condition is met. At this point, the buffer controller will no longer start a new iteration loop, but will trigger the solution output process. Then, the difference restoration unit is activated, configured to restore the difference matrix in the on-chip buffer to the solution matrix during iteration convergence.

[0110] For each row of the solution matrix, the difference restoration unit starts from the original value stored in the first column and adds the subsequent difference values ​​to the predecessor value in turn, thereby reconstructing the complete original solution value at each grid point, i.e., the solution matrix, row by row.

[0111] The differential equation computation system provided in this embodiment manages the flow of data organized in a difference format between storage levels through a buffer controller, and the processing unit array performs Gauss-Seidel iterative computation optimized for the difference format synchronously based on the wavefront sequence. The results are then compressed by a block floating-point quantizer, and the solution matrix is ​​output through a difference restoration unit after convergence.

[0112] For the current value buffer, offset buffer, and iteration buffer, the buffer controller is configured to: load the solution matrix data block of the difference format of the current iteration into the current value buffer; load the data block of the source term matrix into the offset buffer; and write the quantized data into the iteration buffer.

[0113] The current value buffer is used to store data blocks of equation solution matrices in difference format that are about to be updated or are being read in the current iteration. These data blocks are approximate solutions for a local region in the computational grid at the current iteration step.

[0114] The offset buffer is used to store a data block of source term matrices in difference format corresponding to the current computational domain. After discretization of the partial differential equation, the source term matrix can be a known coefficient matrix or force source terms that remain unchanged during iteration. Therefore, the data in the offset buffer only needs to be loaded from external memory once in a single iteration or even throughout the entire solution process, and can then be repeatedly read and used by the processing unit array as a constant offset in the computation.

[0115] The iteration buffer is used to temporarily store new quantized data generated by the processing unit array and processed by the block floating-point quantizer. This quantized data is the result of updating the solution matrix in the current iteration, and its format is also block floating-point. The function of the iteration buffer is to receive and save the output of the current iteration, which logically becomes the input for the next iteration.

[0116] like Figure 9 As shown, the data flow method for performing one iteration of computation in this system includes the following stages in sequence: The buffer controller loads the grid data blocks required for the current iteration from external memory into the current value buffer through direct memory access, and loads the source item data blocks into the offset buffer. The buffer controller is responsible for address generation and distributing data to each memory bank of the buffer to meet the bandwidth requirements of subsequent parallel access.

[0117] The buffer controller supplies data from the on-chip buffer to the processing unit array. The processing units in the array operate in a pulsed manner, meaning that data flows in a clockwise direction within the array of processing units (PEs). This includes clock synchronization, where all PEs in the array operate simultaneously with each clock pulse. It also includes pipelined data exchange. For example, PE1 passes its calculation result after one clock pulse to PE2; PE2 receives this result, adds its own calculated result, and then passes it to PE3. Internal registers enable time-dimensional multiplexing of the input data, and dedicated interconnects facilitate the exchange of intermediate results with adjacent units, enabling spatial-dimensional multiplexing of the data.

[0118] The results generated by the processing unit array are processed by a block floating-point quantizer, which groups and quantizes the data according to the preset GS and mantissa bit width, further compressing the data bit width, and then writes it to the iterative buffer.

[0119] While calculating the new solution, the logic within the processing unit and the independent error calculation unit calculate the local difference between the new and old solutions in parallel. The buffer controller coordinates the aggregation of all local differences, and the error calculation unit calculates the global error norm. This norm is compared with a preset threshold to autonomously determine whether convergence has occurred and decide whether to continue iterating or output to the difference restoration unit.

[0120] If convergence is not achieved, the buffer controller automatically uses the current output as the input for the next iteration by swapping the logical roles of the current value buffer and the iteration buffer, and repeats the process until convergence is achieved without external intervention.

[0121] If convergence is achieved, the buffer controller will then pass the solution generated by the current array through the differential restoration unit. reduction Output the final result.

[0122] The computing system provided in this application, compared to traditional hardware accelerators, features a wavefront Gaussian-Seidel method design architecture with superior parallelism, reduced memory access frequency, and lower energy consumption. Compared to in-memory processing technologies, the scalable PE supports different mesh sizes, avoiding the limitations of fixed meshes in existing technologies. Through compression techniques such as block floating-point, dynamic mantissa, and spatial difference, bandwidth compression of the solution matrix and source term matrix is ​​achieved, improving data access efficiency. Compared to traditional single-precision data adders and multipliers, the customized multipliers and adders reduce the bit width of computational units and memory footprint.

[0123] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.

Claims

1. A block floating-point arithmetic device, characterized in that, include: The input interface is configured to receive the first floating-point operand, the second floating-point operand, and the mantissa bit width configuration parameter. The reconstructed data processing path, connected to the input interface, is configured to: perform operations on the first and second floating-point operands based on the mantissa bit width configuration parameters to obtain the operation result; The reconstructed data processing path includes an adder path and a multiplier path; the adder path is configured to perform addition operations based on the mantissa bit width configuration parameter; The multiplier path is configured to perform multiplication operations based on the mantissa bit width configuration parameter; The adder path includes: The first special value processing unit is configured to process the denormalized values ​​in the first block of floating-point operands and the second block of floating-point operands to output the first standard operand and the second standard operand. The first sign bit processing unit is configured to determine the sign bit of the addition operation result based on the sign bits of the first standard operand and the second standard operand. The first floating-point number restoration unit is configured to: restore the format of the first standard operand and the second standard operand to an explicit floating-point format based on the first standard operand, the second standard operand, and the mantissa bit width configuration parameter, so as to obtain the first explicit operand and the second explicit operand. An exponent alignment unit is configured to: compare the exponents of the first explicit operand and the second explicit operand to output an exponent difference, and output an alignment control signal based on the exponent difference; The mantissa operation unit is configured to: receive the alignment control signal, determine a target operand based on the exponent difference, wherein the target operand is an operand with a smaller exponent; perform shift alignment on the mantissa of the target operand to obtain an aligned mantissa; and perform addition on the aligned mantissa to obtain a mantissa result and a corresponding sign bit. The first normalization unit is configured to perform normalization shift processing on the mantissa result and adjust the exponent to output a first normalized mantissa and a first normalized exponent. The first carry processing unit is configured to: process the carry of the first normalized mantissa and adjust the first normalization exponent to obtain the addition result; The multiplier path includes: The second special value processing unit is configured to process the denormalized values ​​in the first and second floating-point operands to output the third and fourth standard operands. The second sign bit processing unit is configured to determine the sign bit of the multiplication result based on the sign bits of the third and fourth standard operands. The second floating-point number restoration unit is configured to: restore the format of the third standard operand and the fourth standard operand to an explicit floating-point format based on the third standard operand, the fourth standard operand and the mantissa bit width configuration parameters, so as to obtain the third explicit operand and the fourth explicit operand. The exponent processing unit is configured to perform addition on the exponents of the third and fourth explicit operands to calculate the exponent sum and output the intermediate exponent; The mantissa processing unit is configured to perform a multiplication operation on the mantissas of the third explicit operand and the fourth explicit operand to obtain a mantissa product; The second normalization processing unit is configured to: perform normalization shift processing on the mantissa product, truncate the mantissa according to the mantissa bit width configuration parameter, and adjust the intermediate exponent to output the second normalized mantissa and the second normalized exponent. The second carry processing unit is configured to process the carry of the second normalized mantissa and adjust the second normalized exponent to obtain the multiplication result. The output interface, connected to the reconstructed data processing path, is configured to output the calculation result.

2. A differential equation calculation system, characterized in that, include: A buffer controller is configured to load target data in a difference format from external memory into an on-chip buffer, wherein the target data is a data block of the solution matrix and the source term matrix; the difference format is that in the target data, each element except the first column is stored as a difference value with the element of the previous column. The processing unit array includes multiple parallel processing units, wherein the processing unit includes the block floating-point arithmetic device as described in claim 1; The buffer controller is further configured to send the target data in the differential format to the processing unit array according to the wavefront sequence, wherein the wavefront sequence is to group the grid points according to multiple wavefronts. The processing unit is configured to: synchronously perform Gauss-Seidel iterative calculations based on a difference scheme on the target data within the wavefront to update the difference matrix of the solution; A block floating-point quantizer is configured to: perform block floating-point quantization on the updated difference matrix according to the two-dimensional block size and the target mantissa bit width to output quantized data, wherein the block floating-point quantization assigns a shared exponent to multiple values ​​within the two-dimensional block; the quantized data is used in the on-chip buffer for the next iteration; The difference restoration unit is configured to restore the difference matrix of the on-chip buffer to the solution matrix during iterative convergence.

3. The differential equation calculation system according to claim 2, characterized in that, The system also includes an error calculation unit; The error calculation unit is configured to: calculate the difference between the current iteration solution and the previous iteration solution, determine whether the convergence condition is met based on the difference, and output the determination result; The buffer controller is configured to: in response to the determination result that the convergence condition is not met, use the quantized data as the input for the next iteration; In response to the judgment result being that the convergence condition is met, the differential restoration unit is triggered to output the final solution matrix.

4. The differential equation calculation system according to claim 2, characterized in that, The on-chip buffer includes a current value buffer, an offset buffer, and an iteration buffer; The buffer controller is configured to load the solution matrix data block of the difference format of the current iteration into the current value buffer; The process involves loading the data block of the source term matrix into the offset buffer and writing the quantized data into the iteration buffer.

5. The differential equation calculation system according to claim 2, characterized in that, The target mantissa bit width is configured with multiple different values, and is set based on the iteration stage; When the iteration phase is the first phase, the target mantissa width is the first bit width; When the iteration phase is the second phase, the target mantissa bit width is the second bit width; When the iteration phase is in the third phase, the target mantissa bit width is the third bit width; The third stage is an iterative stage that approaches the convergence condition, wherein the value of the third bit width is greater than the value of the second bit width, and the value of the second bit width is greater than the value of the first bit width.

6. The differential equation calculation system according to claim 2, characterized in that, The processing unit is configured to perform Gauss-Seidel iterative calculations based on a difference scheme on the target data, including: Determine the corresponding differential iteration calculation formula based on the current grid point position; Based on the difference values ​​in the difference matrix of the solution and the difference values ​​in the source term matrix, the difference iteration calculation formula is updated to obtain the difference result. In this context, both the operands and the difference results in the differential iteration calculation formula are difference values.

7. The differential equation calculation system according to claim 2, characterized in that, The wavefront order is as follows: the grid points are divided into multiple wavefronts according to the sum of the row index and the column index, wherein grid points with the same sum of row index and column index belong to the same wavefront; The buffer controller is configured to send the target data corresponding to the grid points within the same wavefront to the processing unit array according to the wavefront division order. The processing unit array is configured to perform parallel update calculations on the target data corresponding to grid points within the same wavefront.

8. The differential equation calculation system according to claim 2, characterized in that, The processing unit is further configured to update the target data by calling different calculation logics based on whether the currently calculated grid point is located on the matrix boundary; The different calculation logics include at least: a first calculation logic, a second calculation logic, and a third calculation logic; the first calculation logic is used to process the grid points of the first boundary of the matrix and calculate based on the boundary condition value; the second calculation logic is used to process the grid points within the matrix and calculate based on the difference value of adjacent grid points in different directions; the third calculation logic is used to process the grid points of the second boundary of the matrix and calculate based on the sum of the difference values ​​of multiple grid points in that row.

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