A pulse capacitor using a primary-secondary core set

Abstract

The application discloses a pulse capacitor adopting a primary and secondary core group, and relates to the technical field of pulse power. The pulse capacitor comprises a primary core control module and at least two secondary core modules. Each secondary core module comprises an energy storage capacitor unit and a switching unit connected in series with the energy storage capacitor unit. A controller of the primary core control module is connected with the control end of the switching unit of each secondary core module through a driving circuit. The primary core control module determines a target control mode in response to a discharge command. The control mode of the primary core control module comprises: an independent gating discharge mode, in which at least one secondary core module is selected based on a trigger instruction, and the energy of the secondary core module is discharged to a device; and a cooperative timing discharge mode, in which a multi-path trigger signal sequence is generated based on a high-level waveform description instruction, each secondary core module is sequentially or overlapped turned on in a specific timing sequence, and the current of the secondary core module is superimposed on the device to obtain a composite pulse. The problems of single capacitor discharge mode, low system reliability and large current impact on service life are solved.

Description

Technical Field

[0001] This invention relates to the field of pulse power technology, and more specifically, to a pulse capacitor employing a master-slave core assembly. Background Technology

[0002] Traditional single-cell large-capacity pulse capacitors have many limitations in applications: 1) They have a single discharge mode and cannot flexibly adjust the pulse waveform; 2) Once an internal fault occurs, the entire capacitor fails, resulting in low system reliability; 3) The concentrated discharge of large currents has a significant impact on switches and loads, affecting lifespan.

[0003] Existing technologies include schemes that use multiple capacitor units in parallel or series, but most of these employ simple direct electrical connections, and their control remains equivalent to a single unit. The few technologies with independent control primarily focus on redundancy and backup, lacking proactive, precise, and programmable control over discharge timing and energy combinations, thus failing to achieve complex pulse waveform synthesis and energy management. Summary of the Invention

[0004] To address the problems of existing capacitors having a single discharge mode, low system reliability, and lifespan affected by high current surges, this invention provides a pulse capacitor employing a master-slave core assembly. The pulse capacitor includes a master core control module and at least two slave core modules. Each slave core module includes an energy storage capacitor unit and a switching unit connected in series with the energy storage capacitor unit. The controller of the master core control module is connected to the control terminal of the switching unit of each slave core module via a drive circuit.

[0005] The core control module responds to the discharge command and determines the target control mode;

[0006] The control modes of the mother core control module include independent gated discharge mode and coordinated timing discharge mode;

[0007] The independent gated discharge mode is as follows: the controller receives a trigger command, selects at least one of the sub-core modules based on the trigger command to obtain a first target sub-core module, sends a trigger signal to the first switching unit of the first target sub-core module, the first switching unit starts the first target sub-core module, the switching units of non-first target sub-core modules are turned off, and the energy of the first target sub-core module is discharged to the target device.

[0008] The coordinated timing discharge mode is as follows: the controller receives a high-level waveform description instruction and generates a multi-channel trigger signal sequence containing different delay times based on the high-level waveform description instruction; the multi-channel trigger signal sequence is sent to the second switching unit of the second target sub-core module corresponding to the multi-channel trigger signal sequence, and each second target sub-core module is turned on sequentially or overlappingly according to a specific timing sequence, and the discharge current of each second target sub-core module is superimposed on the target device to obtain a composite pulse.

[0009] The independent gated discharge mode, through software commands, allows the system to select one or more sub-cores from all sub-cores for discharge. This enables the system to choose the number of energy packets to be deployed as needed, reducing energy waste and improving efficiency. It achieves stepless speed regulation of energy output, from the minimum energy of a single sub-core to the maximum energy of all sub-cores, and realizes adjustable discharge energy (from the energy of a single sub-core to the energy of all sub-cores). This breaks the traditional single-core capacitor's single-mode discharge limitation, enabling digital and discrete control of discharge energy. It transforms the centralized energy storage of traditional large single-core capacitors into distributed, independently addressable energy storage units. Because each sub-core is independently controllable, when a sub-core fails, it can be isolated (not triggered) through control algorithms, while other sub-cores can still operate normally. This allows the system to degrade even when some sub-cores fail, preventing overall failure and improving system reliability. By selecting different numbers of sub-cores to discharge, the amplitude of the discharge current can be controlled. For example, for small loads, fewer sub-cores can be selected to discharge, avoiding large current surges and extending capacitor life. Simultaneously, due to the modularity of the sub-cores, the current of each sub-core is relatively small, dispersing current stress.

[0010] The coordinated timing discharge mode controls multiple sub-cores to be triggered sequentially according to a specific timing sequence, causing their discharge currents to be superimposed on the load. This allows for the synthesis of pulse waveforms of various shapes (such as square waves, stepped waves, and sawtooth waves), achieving a fundamental shift from having fixed waveforms to defining arbitrary waveforms. The superposition of multiple sub-cores can offset the discreteness of the discharge characteristics of individual components, resulting in a more stable and ideal waveform, and enabling programmable and flexible adjustment of the pulse waveform. Employing a time-energy decoupling strategy, multiple groups of sub-cores discharge in a relay fashion, spreading and superimposing multiple short, high-current pulses along the time axis. This synthesizes ideal pulses with high power and long pulse widths without increasing the stress on individual components, solving the problem of the incompatibility between high current and long pulse width, and overcoming the physical limitations of traditional single capacitors. In coordinated timing discharge, if a sub-core fails, compensation can be made by adjusting the triggering timing and combination of other sub-cores, still synthesizing the required waveform, and the system can still operate. Furthermore, since each sub-core is independent, faults can be isolated, improving system reliability. Through timing control, a large current pulse can be decomposed into a superposition of multiple smaller current pulses, thereby reducing the current stress on each sub-core, which is beneficial to extending the sub-core life. At the same time, it also reduces the impact on the load (for example, by controlling the slope of the rising edge), solving the problem of large current impact.

[0011] Both the independent gated discharge mode and the coordinated timing discharge mode share the same hardware architecture of an independent controllable sub-core + central intelligent scheduling. The former is the foundation, while the latter is its advanced application. The former solves the problem of energy quantity, while the latter solves the problem of energy form. Together, they achieve comprehensive control over the output pulse from quantity to form. Both modes are based on distributed energy storage and have the characteristic that a single point of failure does not affect the overall operation. They improve system reliability from different dimensions and jointly subvert the traditional design paradigm of pulse capacitors as an overall uncontrollable unit. Through software-defined distributed control, they solve the problems of single discharge mode, low system reliability, and the impact of large current surges on lifespan of existing capacitors from two fundamental levels: the flexibility of energy selection and the programmability of waveform synthesis.

[0012] Furthermore, the triggering instruction includes a target energy value, a target sub-core identifier list, and a logic strategy code. The specific steps for obtaining the first target sub-core module include:

[0013] Based on the logic strategy code, the first voltage parameter of the sub-core module, and the first constraint condition, a set of several first candidate sub-core modules is obtained;

[0014] Obtain multi-dimensional features of each first candidate sub-core module in the first candidate sub-core module set, and obtain several second candidate sub-core module sets based on the multi-dimensional features. The multi-dimensional features include health value, cumulative number of working times and state of charge.

[0015] Obtain the second voltage parameter of each second candidate sub-core module in the second candidate sub-core module set, and obtain the first target sub-core module based on the second voltage parameter and the second constraint condition;

[0016] The first constraint is: the sum of the energy values ​​of all first candidate sub-core modules in the first candidate sub-core module set is not less than the target energy value;

[0017] The second constraint is: the difference between the sum of the energy values ​​of all second candidate sub-core modules in the second candidate sub-core module set and the target energy value is minimized.

[0018] First, the independent gated discharge mode selects a candidate set from all sub-cores based on energy principles. The total energy of the sub-cores in this set meets or exceeds the current requirement. Then, within this qualified candidate set, state-based rules are applied for optimal selection. For example, among several sub-core combinations that all meet the energy requirements, the combination with the lowest total historical operating frequency or the lowest average temperature is selected, and finally, the combination with the smallest difference in total energy is chosen. This mode constructs a software-programmable, pixelated, fine-grained energy management architecture, fundamentally changing the traditional attribute of the pulse capacitor as a whole, indivisible energy unit, transforming it into an array of discrete, addressable energy units, thereby achieving revolutionary controllability of energy output.

[0019] Traditional capacitor discharge is all-or-nothing, while this mode achieves digital energy selection. This mode can select the precise energy value E required by the load. need and the rated energy storage E of each sub-core unit Calculate the number of sub-cores to be activated, N = ceil(E need / E unit This energy packet-based approach enables a leap from analog, extensive discharge to digital, precise power supply. While the implementation relies on a specific hardware topology (each sub-core connected in series with an independent switch), its core value is realized through upper-level control logic (software algorithms). Users or higher-level systems can invoke different combinations of sub-core modules via programming instructions, much like calling a function, without needing to concern themselves with changes in the underlying physical connections. This approach not only precisely completes each discharge task but also significantly extends overall lifespan through intelligent scheduling, achieving a synergistic control capability that balances immediate performance with long-term reliability.

[0020] Furthermore, the coordinated timing discharge mode specifically refers to:

[0021] The controller receives the advanced waveform description instruction, which includes the waveform type and waveform parameters of the target waveform;

[0022] Based on the waveform synthesis algorithm library built into the controller, the high-level waveform description instruction is parsed and the target waveform is decomposed into multiple sub-waveform segments, including rising edge segments, flat-top segments and falling edge segments;

[0023] For the rising edge segment, the number of rising sub-core modules that are triggered simultaneously at the start time and the initial voltage of the rising sub-core modules are obtained based on the waveform synthesis algorithm library. The rising edge of the LC damped oscillation current of the rising sub-core modules is superimposed to fit the rise time of the target waveform.

[0024] For the flat-top segment, based on the waveform synthesis algorithm library, the flat-top duration of the target waveform is divided into multiple overlapping maintenance intervals. The number of flat-top sub-core modules triggered at the starting point of each maintenance interval and the triggering delay of the flat-top sub-core modules are calculated sequentially. The decaying discharge current of the flat-top sub-core modules is superimposed in time. The sum of the decaying discharge current is constant during the flat-top duration, forming a current relay.

[0025] For the falling edge segment, based on the waveform synthesis algorithm library, the last batch of discharge core modules in the discharge stage are controlled to actively shut off the discharge core modules and fit the falling time of the target waveform.

[0026] The multi-path trigger signal sequence is generated based on the rise time, the sustain interval, the trigger delay, and the fall time; the second target sub-core module is obtained based on the rising sub-core module, the flat-top sub-core module, and the electron discharge core module;

[0027] Based on the multi-path trigger signal sequence, the second switching unit of the second target sub-core module sequentially or overlappingly turns on each of the second target sub-core modules, and the discharge current of each of the second target sub-core modules is superimposed on the target device to obtain the composite pulse.

[0028] The essence of the coordinated timing discharge mode is to discretize and deconstruct the target pulse waveform in the time-energy dimension and distribute it to each sub-core for execution:

[0029] Waveform deconstruction into an energy slice sequence: The master core controller treats the desired output pulse waveform (such as a flat-top square wave, stepped wave, or sawtooth wave) as a time function I_target(t). Through discretization analysis and energy allocation of this function, it is decomposed into M (M is an integer greater than or equal to 2) time-ordered, partially overlapping, or closely connected energy slices. Each energy slice corresponds to the discharge current profile of one or a group of sub-core modules.

[0030] Sub-cores as waveform actuators: Each sub-core is no longer just an energy storage unit, but becomes a device with a specific trigger delay. And waveform pixels or strokes that may have controlled shutdown capability. Their discharge behavior (start, peak, decay) becomes a fundamental component of the synthesized target waveform.

[0031] Time-Energy Coordinated Weaving: The master core controller acts as the conductor of a symphony orchestra. Its core innovation lies in generating a set of trigger signals with high precision and programmable time delays, precisely controlling when each sub-core is engaged (turned on) and disengaged (turned off), causing them to generate current superposition on the load branch. Ultimately, it approximates the expected I_target(t), where, I total (t) Indicates time t At this moment, the total instantaneous current flowing through the load is I n () indicates the first n The inherent discharge current waveform generated after the core module begins to discharge at its local time zero point (i.e., the moment its own switch receives the trigger signal) is as follows: t Indicates time, Indicates a trigger delay. n This indicates the number of the sub-core module.

[0032] This mode moves from having waveforms to defining waveforms: users can generate waveforms ranging from sharp pulses to wide-platform square waves, or even custom complex waveforms, simply by modifying software parameters, without changing any hardware. This greatly expands the application range of the device (such as from material impact modification to particle beam injection), breaking the physical limitation that pulse capacitors can only output a single decaying waveform. By precisely arranging and stitching the energy release process of multiple discrete sub-cores on the time axis, complex pulse waveforms of arbitrary shapes can be defined and synthesized on the load in software, realizing a paradigm shift from energy release to waveform construction.

[0033] This mode solves the classic dilemma of the trade-off between high current and long pulse width: traditional single capacitors struggle to simultaneously provide extremely high current and long pulse width. This mode uses a relay-like approach, spreading the energy of multiple sub-cores over time to synthesize an ideal pulse with high power and long pulse width without significantly increasing the stress on individual components. By superimposing the currents of multiple sub-cores, the discreteness and undesirable fluctuations in the discharge characteristics of individual components can be offset, resulting in a synthesized waveform with stability and repeatability far superior to any single large capacitor, achieving a fundamental improvement in waveform quality.

[0034] Furthermore, the control mode of the mother core control module also includes a dynamic grouping alternating working mode, which is as follows:

[0035] The controller receives a grouping strategy, divides the sub-core modules into at least two logical groups based on the grouping strategy, stores the grouping information, and obtains the first operating status metadata of all the sub-core modules.

[0036] The first logic group is designated as the execution group to respond to the discharge command of the independent gating discharge mode or the cooperative timing discharge mode, while non-first logic groups are designated as rest groups, and the rest groups are in a non-discharge state.

[0037] Determine whether to switch the roles of the execution group and the rest group. If so, confirm that the discharge process of the execution group has been completed and the discharge current has returned to zero. Obtain the second operating status metadata of all the sub-core modules. Based on the second operating status metadata, obtain at least two new logical groups and store the grouping information. Within a preset switching delay time, update the logical group status mapping table of the execution group based on the new logical groups to obtain a new execution group. The new execution group responds to the next discharge command, and the execution group switches to the rest group.

[0038] The dynamic grouping and alternating working mode goes beyond the traditional simple parallel or master-slave redundancy concepts, introducing a dynamic load scheduling mechanism based on time, state, and strategy. This mechanism treats the sub-core group as a flexibly reconfigurable computing resource pool, and actively manages the system's heat accumulation and aging process through software-defined grouping and rotation strategies, thereby achieving a fundamental improvement in system-level reliability, availability, and lifespan.

[0039] Creative monitoring: The controller not only tracks the group status, but also the micro-state of each sub-core within the group, accumulating data for the next intelligent grouping; switching does not necessarily mean that the two groups simply exchange roles. Before and after each switching event, the controller will rerun the grouping algorithm based on the latest data of all sub-core states, which may result in a completely new group composition.

[0040] Meanwhile, the dynamic grouping alternating working mode (Mode C) forms an organic whole with the independent gating discharge mode (Mode A) and the cooperative timing discharge mode (Mode B):

[0041] Coordination with Modes A / B: When Group1 is assigned to perform a discharge task, the specific sub-cores used within the group and the discharge timing are determined by the algorithm of Mode A or Mode B. That is, Mode C performs macroscopic load scheduling between groups, while Modes A / B perform microscopic energy scheduling within groups.

[0042] Active thermal management and life extension: By forcibly rotating the cores, each core is regularly placed into the cooling window, reducing local hot spots and continuous thermal stress. This fundamentally delays failure processes such as electrolyte drying and film aging, shifting the system lifespan from probabilistic failure to planned maintenance.

[0043] Provides predictable maintenance windows: Maintenance personnel can know for sure when the sub-cores in the next maintenance cycle can be safely tested or replaced online, enabling planned maintenance and improving system availability.

[0044] Gradual degradation of system performance: As the sub-cores slowly age due to long-term use, the grouping and reorganization algorithm can gradually assign lighter tasks or longer rest periods to the aging sub-cores, while the younger sub-cores take on the main work. The overall system performance declines slowly and smoothly, rather than suddenly crashing.

[0045] Optimized resource utilization: Through dynamic reorganization, the best-performing sub-core cluster is always kept on the front line, achieving continuous optimization of system performance.

[0046] The dynamic grouping alternating working mode transforms grouping from a static, passive redundancy concept into a dynamic, proactive resource management and health maintenance tool. Through software-defined strategies, it deeply integrates time, status, fault events, and load requirements, directing physical sub-core units to perform orderly work and rest, thereby enabling high reliability, long lifespan, and intelligent operation and maintenance characteristics at the system level that go beyond the simple superposition of individual components.

[0047] Furthermore, based on multi-dimensional triggering conditions, it is determined whether to switch the roles of the execution group and the rest group;

[0048] The multi-dimensional triggering conditions include:

[0049] Condition 1: The fixed period ends;

[0050] Condition 2: The performance metrics of the execution group exceed the threshold;

[0051] Condition 3: Received external instructions;

[0052] Condition 4: A failure event occurs in the execution group;

[0053] When any of the multi-dimensional triggering conditions is met, the roles of the execution group and the rest group are switched.

[0054] The switching trigger is not limited to a simple time loop, but rather to a multi-condition logical OR relationship, which greatly enhances the flexibility of the capacitor.

[0055] Furthermore, the second operating status metadata includes capacity, voltage, temperature, cumulative number of operations, historical total discharge, internal resistance change rate, and physical location code. Based on the second operating status metadata and a grouping method, the at least two new logical groups are obtained, wherein the grouping method is as follows:

[0056] S1. Obtain a comprehensive health score for each sub-core module based on the second operating status metadata, and obtain optimization targets, including capacity balance, thermal load balance, aging balance and physical layout dispersion.

[0057] S2. Based on the comprehensive health score, classify the sub-core modules to obtain a first category;

[0058] S3. Based on the first classification, randomly generate an initial grouping scheme;

[0059] S4. Based on the optimization objective, obtain the first score of each first group in the initial grouping scheme, and obtain the first total score of the initial grouping scheme based on the first score;

[0060] S5. Randomly swap any two sub-core modules in any two of the first groups, or move any one sub-core module from one group to another to obtain an optimized grouping scheme. Obtain the second score of each second group in the optimized grouping scheme, and obtain the second total score of the optimized grouping scheme based on the second score.

[0061] S6. If the second total score is greater than the first total score, then return to S5, update the first group to the second group, and iterate from S5 to S6 until the termination condition is met, and obtain the new logical group based on the optimized grouping scheme; if the second total score is less than or equal to the first total score, then return to S5, update the first group to the second group based on the preset acceptance probability, and iterate from S5 to S6 until the termination condition is met, and obtain the new logical group based on the optimized grouping scheme.

[0062] Upgrade system maintenance and load scheduling from predefined fixed plans to dynamic optimization decisions based on real-time big data. This step is not a simple rotation, but a lightweight online optimization computation process embedded in each work cycle node, with the goal of ensuring that the system always operates at the optimal balance between performance, reliability, and lifespan.

[0063] Furthermore, a comprehensive health score for each sub-core module is obtained based on a scoring method, wherein the scoring method is as follows:

[0064] Status characteristics are obtained based on operational status metadata, including electrical core parameters, thermodynamic and mechanical parameters, and switch dynamic characteristic parameters;

[0065] The initial health baseline vector of each sub-core module is obtained based on the aforementioned state characteristics;

[0066] Based on preset parameters, the state characteristics are fitted to obtain the characteristic change slope of each sub-core module;

[0067] The comprehensive health score is obtained based on the initial health baseline vector and the slope of feature change.

[0068] Furthermore, if an adjustment sub-core module in the execution group is assigned to the rest group, but the current state parameters of the adjustment sub-core module do not meet the preset conditions for entering the rest group, the logical group status identifier of the adjustment sub-core module is delayed until the current state parameters of the adjustment sub-core module meet the preset conditions, and then the logical state of the adjustment sub-core module is assigned to the rest group.

[0069] By introducing a flexible execution mechanism and combining real-time data-driven, multi-objective optimization algorithms, the system acquires self-regulation and adaptive capabilities similar to those of a living organism. It no longer mechanically rotates and backs up components, but intelligently manages the lifecycle and operating rhythm of the entire sub-core group, enabling long-life and highly reliable operation of the pulse capacitor system.

[0070] Furthermore, the control mode of the mother core control module also includes a fault-tolerant mode, which is as follows:

[0071] The abnormal sub-core module and its remaining useful life are obtained based on the comprehensive health score, and the failure risk probability is obtained based on the comprehensive health score and the remaining useful life.

[0072] An early warning strategy is obtained based on the comprehensive health score and the probability of failure risk.

[0073] Providing early warnings before failures occur represents the highest level of fault tolerance. This fault-tolerant model breaks away from the traditional passive approach of triggering alarms based on fault detection thresholds and responding after the fact. Instead, it constructs a predictive health management system based on multi-dimensional state perception, trend analysis, and proactive intervention. It doesn't wait for the sub-core to completely fail; instead, it continuously monitors its sub-health state, identifying and intervening in the early stages of performance degradation, thereby eliminating faults in their nascent stages or planning an orderly retirement path.

[0074] Prevention is better than cure: Provide early warnings months or even longer before a hard fault (such as a short circuit) occurs in the sub-core, giving ample time for planned maintenance.

[0075] Extending actual service life: By reducing the usage and managing the recovery of degraded cores, it is possible to allow them to continue working safely for a long time in a sub-healthy state, extracting their remaining value within a safe range.

[0076] The fault-tolerant mode deeply integrates the advanced concepts of IoT and big data predictive maintenance into pulse capacitors, and designs a quantifiable, executable early warning system that is linked in a closed loop with the core control logic.

[0077] For sub-cores in the early warning state, the system will not immediately remove them, but will automatically initiate protective scheduling: reduce the probability of them being selected in modes A / B; in mode C, prioritize their inclusion in the recovery group and reduce their upper limit of charge and discharge current to achieve predictive fault tolerance.

[0078] Furthermore, the fault tolerance and reconfiguration mode also includes:

[0079] The controller acquires the waveform of the composite pulse, analyzes the waveform to obtain a defect region, obtains the compensation sub-core module, the compensation triggering sequence of the compensation sub-core module, and the compensation current of the compensation sub-core module based on the defect region, turns on the compensation sub-core module based on the compensation triggering sequence, and superimposes the compensation current onto the defect region to repair the waveform.

[0080] A fault-tolerant mode was designed and implemented, incorporating a microsecond-level intelligent real-time control loop nested within the millisecond-level discharge process. This control loop endows the system with muscle memory and conditioned reflex-like capabilities, enabling instantaneous and precise correction of output deviations. It is not merely a fault-tolerant mechanism, but also an adaptive optimization engine that pushes system performance to its theoretical limits, elevating system stability maintenance from open-loop, predefined parameter design to closed-loop, real-time feedback-based dynamic reshaping. It not only remedies sudden faults but also performs microsecond-level real-time correction of the synthesized waveform during each discharge process, ensuring that the quality of the output pulse is unaffected by component parameter drift, load characteristic changes, or transient disturbances. This represents a qualitative leap in the control system, moving from feedforward execution to feedback optimization. It can tolerate transient anomalies in a single discharge (such as occasional switch bounce or electromagnetic interference), minimizing their impact through immediate compensation, exhibiting impeccable stability, providing robust system performance, and also ensuring the smooth operation of modes A and B.

[0081] One or more technical solutions provided by this invention have at least the following technical effects or advantages:

[0082] 1. Independent Gated Discharge Mode: Through software commands, one or more sub-cores can be arbitrarily selected for discharge from all sub-cores. This allows the system to select the number of energy packets to be deployed as needed, reducing energy waste and improving efficiency. It achieves stepless speed regulation of energy output, from the minimum energy of a single sub-core to the maximum energy of all sub-cores, enabling adjustable discharge energy. This breaks away from the traditional single-unit capacitor's single-system discharge mode, achieving digital and discrete control of discharge energy. It transforms the centralized energy storage of traditional large single-unit capacitors into distributed, independently addressable energy storage units. Each sub-core is independently controllable, preventing overall failure and improving system reliability. By selecting different numbers of sub-cores to discharge, the amplitude of the discharge current can be controlled, avoiding large current surges and extending capacitor life. Simultaneously, due to the modular design of the sub-cores, the current of each sub-core is relatively small, distributing current stress.

[0083] 2. The cooperative timing discharge mode controls multiple sub-cores to be triggered sequentially according to a specific timing sequence, causing their discharge currents to be superimposed on the load. This allows for the synthesis of pulse waveforms of various shapes, achieving a fundamental shift from having fixed waveforms to defining arbitrary waveforms. The superposition of multiple sub-cores can offset the discreteness of the discharge characteristics of individual components, resulting in a more stable and ideal waveform. This enables programmable and flexible adjustment of the pulse waveform. A time-energy decoupling strategy is employed. By relaying discharges of multiple sets of sub-cores in time, multiple short, high-current pulses are spread out and superimposed on the time axis. Without increasing the stress on individual components, a high-power, long-pulse-width ideal pulse is synthesized, solving the problem of the incompatibility between high current and long pulse width, and overcoming the physical limitations of traditional single capacitors. In cooperative timing discharge, by adjusting the triggering timing and combination of other sub-cores for compensation, the required waveform can still be synthesized, and the system can still operate. Each sub-core is independent, and faults can be isolated, improving system reliability. Through timing control, a large current pulse can be decomposed into a superposition of multiple smaller current pulses, thereby reducing the current stress on each sub-core, which helps to extend the sub-core's lifespan. It also reduces the impact on the load and solves the problem of large current surges. Attached Figure Description

[0084] The accompanying drawings, which are provided to further illustrate embodiments of the invention and constitute a part of this invention, are not intended to limit the scope of the invention.

[0085] Figure 1 This is a schematic diagram of a pulse capacitor using a master-slave core assembly in this invention. Detailed Implementation

[0086] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, where there is no conflict, the embodiments of the present invention and the features thereof can be combined with each other.

[0087] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0088] Example 1

[0089] refer to Figure 1 This embodiment provides a pulse capacitor employing a master-slave core assembly. The pulse capacitor includes a master core control module and at least two slave core modules. Each slave core module includes an energy storage capacitor unit and a switching unit connected in series with the energy storage capacitor unit. The controller of the master core control module is connected to the control terminal of the switching unit of each slave core module through a drive line.

[0090] A storage capacitor unit refers to a capacitive component inside a core module that is specifically designed to store electrical energy and can rapidly release pulse energy to the load through the discharge main circuit after a controlled switch is turned on.

[0091] In this embodiment, the drive circuit can be an existing drive circuit, used to provide an isolated strong drive signal to control the on / off state of each switching unit; the mother core control module also includes an internal bus: connecting the output terminals of each sub-core module and the load to form a discharge circuit; and a system communication unit: realizing information interaction between the mother core control module and an external upper-level controller or human-machine interface.

[0092] For example, a capacitor system consists of a main control module and multiple sub-modules. Each sub-module includes an energy storage capacitor, switching devices (such as IGBT modules), and local detection circuitry. The main control module contains an existing microprocessor controller (such as an FPGA or high-performance MCU), multiple isolated drive circuits, power supply, and communication interfaces. The outputs of all sub-modules are connected in parallel to a common DC bus, which is connected to the load via a main switch. The installation and connection methods of the circuits, devices, equipment, and controllers mentioned above are all existing technologies.

[0093] The local detection circuit is used to directly and synchronously acquire the following data from the sub-core module via integrated sensors (such as voltage dividers and temperature sensors): terminal voltage (reflecting the state of charge (SOC)); loop current (reflecting the actual discharge energy and waveform); key point temperature (reflecting the module's thermal state); and switching status (such as drive signal feedback and fault signals). It can also be used to receive precise trigger commands (such as turning on / off at a specific time) from the parent core controller.

[0094] The core control module responds to the discharge command and determines the target control mode;

[0095] The control modes of the mother core control module include independent gated discharge mode and coordinated timing discharge mode;

[0096] In this embodiment, an existing high-impedance, high-precision voltage divider circuit or isolated voltage sensor can be connected in parallel between the positive and negative terminals of the energy storage capacitor in each sub-core module to monitor the voltage; an existing miniaturized, high-bandwidth current sensor can be connected in series in the discharge main circuit of each sub-core module (usually located between the energy storage capacitor and the switching device) to monitor the current; a digital temperature sensor (such as DS18B20, an I2C interface temperature chip) is embedded in the key heat source points (such as the surface of the capacitor core) inside the sub-core module to monitor the temperature. All of the above sensors are connected to the controller for data transmission.

[0097] The independent gated discharge mode is as follows: the controller receives a trigger command, selects at least one of the sub-core modules based on the trigger command to obtain a first target sub-core module, sends a trigger signal to the first switching unit of the first target sub-core module, the first switching unit starts the first target sub-core module, the switching units of non-first target sub-core modules are turned off, and the energy of the first target sub-core module is discharged to the target device.

[0098] For example, if a capacitor system has 10 sub-core modules, and the load only requires 30% of the total energy, the main core controller, based on energy calculations, randomly or using a polling strategy, selects three fully charged and healthy sub-core modules. The controller sends trigger pulses to the IGBTs of these three sub-cores only through the drive circuit, quickly turning them on. The IGBTs of the remaining seven sub-cores remain off. Thus, only the energy from these three sub-cores is released to the load through the bus, achieving precise on-demand energy output.

[0099] The triggering instruction includes the target energy value, the target sub-core identifier list, and the logic strategy code;

[0100] Target energy value: The total energy that needs to be released.

[0101] Target sub-core identifier list: Directly specify the sub-core number that needs to be worked.

[0102] Logic strategy code: Specifies the algorithm for selecting the sub-core (e.g., least used, highest voltage, or random selection).

[0103] The specific steps to obtain the first target sub-core module include:

[0104] Based on the logic strategy code, the first voltage parameter of the sub-core module, and the first constraint condition, a set of several first candidate sub-core modules is obtained; the voltage parameter can reflect its stored energy.

[0105] By optimizing the algorithm (such as the greedy algorithm), the multi-dimensional features of each first candidate sub-core module in the first candidate sub-core module set are obtained. Based on the multi-dimensional features, several second candidate sub-core module sets are obtained. The multi-dimensional features include health value (which can be obtained based on whether the temperature is normal and the number of historical faults), cumulative working times, and state of charge (SOC, which can be obtained based on the voltage lookup table method, such as directly defining SOC as the percentage of the current voltage to the rated charging voltage).

[0106] Obtain the second voltage parameter of each second candidate sub-core module in the second candidate sub-core module set, and obtain the first target sub-core module based on the second voltage parameter and the second constraint condition;

[0107] The first constraint is: the sum of the energy values ​​of all first candidate sub-core modules in the first candidate sub-core module set is not less than the target energy value;

[0108] The second constraint is: the difference between the sum of the energy values ​​of all second candidate sub-core modules in the second candidate sub-core module set and the target energy value is minimized.

[0109] The coordinated timing discharge mode is as follows: the controller receives a high-level waveform description instruction and generates a multi-channel trigger signal sequence containing different delay times based on the high-level waveform description instruction; the multi-channel trigger signal sequence is sent to the second switching unit of the second target sub-core module corresponding to the multi-channel trigger signal sequence, and each second target sub-core module is turned on sequentially or overlappingly according to a specific timing sequence, and the discharge current of each second target sub-core module is superimposed on the target device to obtain a composite pulse.

[0110] To generate a flat-top square wave pulse, the controller divides the available sub-core modules into three groups. The first group of sub-cores triggers simultaneously at time t0, generating the pulse leading edge. Before the current begins to decay (at time t1), the second group of sub-cores is triggered, and their discharge currents are superimposed to maintain a constant total current. Similarly, the third group of sub-cores is triggered at time t2 to extend the flat top. By precisely controlling the trigger delay and duration of each group of sub-cores, a high-quality flat-top pulse can be synthesized on the load. The energy storage capacity and trigger timing of each sub-core can be pre-programmed to match different target waveforms.

[0111] Specifically, the coordinated timing discharge mode is as follows:

[0112] The controller receives the advanced waveform description instruction, which includes the waveform type and waveform parameters of the target waveform (such as pulse width, amplitude, rise time and fall time).

[0113] Based on the waveform synthesis algorithm library built into the controller, the high-level waveform description instruction is parsed and the target waveform is decomposed into multiple sub-waveform segments, including rising edge segments, flat-top segments, and falling edge segments. In this embodiment, the waveform synthesis algorithm library may include a series of algorithms that cooperate with each other, such as existing waveform parsing algorithms, sub-core matching algorithms, timing optimization algorithms, and real-time compensation algorithms.

[0114] For the rising edge segment, based on the waveform synthesis algorithm library, the number of rising sub-core modules that are triggered simultaneously at the start time and the initial voltage of the rising sub-core modules are obtained. The rising edge of the LC damped oscillation current of the rising sub-core modules is superimposed to fit the rise time of the target waveform. The number of sub-cores and the initial voltage required to be triggered simultaneously at time t0 are calculated so that the rising edge of their LC damped oscillation can be used to fit the required rise time.

[0115] LC damped oscillating current refers to an alternating current waveform with gradually decreasing amplitude and fixed frequency generated in a series circuit consisting of an inductor and a capacitor when the initially charged capacitor discharges to the load through the inductor. This is due to the periodic energy exchange between the inductor and capacitor and the loss caused by the circuit resistance.

[0116] For the flat-top segment, based on the waveform synthesis algorithm library, the flat-top duration of the target waveform is divided into multiple overlapping maintenance intervals. The number of flat-top sub-core modules triggered at the starting point of each maintenance interval and the triggering delay of the flat-top sub-core modules are calculated sequentially. The decaying discharge current of the flat-top sub-core modules is superimposed in time. The sum of the decaying discharge current is constant during the flat-top duration, forming a current relay.

[0117] The algorithm divides the 100μs flat-top width into several overlapping maintenance intervals. Within the first interval (e.g., t1 to t1+Δt), to offset the attenuation of the first batch of sub-core currents, a second batch of sub-cores needs to be triggered at time t1. The energy magnitude and number of triggers must be calculated to ensure the sum of the currents from the two batches remains constant. The third batch of sub-cores triggers at time t2, and so on, forming a relay.

[0118] For the falling edge segment, based on the waveform synthesis algorithm library, the last batch of discharge core modules in the discharge stage are controlled to actively turn off the discharge core modules and fit the falling time of the target waveform; the last batch of discharge sub-cores are controlled to shape the required falling time by actively turning off (if IGBT is used).

[0119] Active shutdown refers to the operation of forcibly cutting off a conducting semiconductor switching device (such as IGBT or MOSFET) by actively applying a control signal, thereby immediately and actively terminating the current path.

[0120] The multi-path trigger signal sequence is generated based on the rise time, the sustain interval, the trigger delay, and the fall time; the second target sub-core module is obtained based on the rising sub-core module, the flat-top sub-core module, and the electron discharge core module;

[0121] Based on the multi-path trigger signal sequence, the second switching unit of the second target sub-core module sequentially or overlappingly turns on each of the second target sub-core modules, and the discharge current of each of the second target sub-core modules is superimposed on the target device to obtain the composite pulse.

[0122] In this embodiment, the allocation of sub-core modules can take into account not only the available energy of the sub-core, but also whether its dynamic characteristics match the role requirements, such as:

[0123] Subtasks that require a steep leading edge will be preferentially assigned to sub-core modules with small loop inductance and fast switching speed (which may be modules that are physically closer to the load).

[0124] The sub-cores responsible for maintaining the main flat top will be preferentially allocated to modules with large capacity and stable internal resistance to ensure stable current.

[0125] Allocation will prevent the same sub-core from undertaking multiple tasks in too short a time interval, in order to prevent it from overheating.

[0126] In this embodiment, the modules, devices, software, equipment, circuits and lines involved in the capacitor system, as well as the connection methods between them, are all existing technologies.

[0127] Example 2

[0128] Based on Embodiment 1, in this embodiment, the control mode of the mother core control module further includes a dynamic grouping alternating working mode, which is as follows:

[0129] The controller receives a grouping strategy, divides the sub-core modules into at least two logical groups based on the grouping strategy, stores the grouping information, and obtains the first operating status metadata of all the sub-core modules. In this embodiment, the grouping strategy can divide the available multiple sub-cores into at least two groups equally or unequally according to the known working cycle of the load. The grouping principle may include:

[0130] Capacity balancing: making the nominal total energy storage of each group approximately equal;

[0131] Balanced physical location: Consider the heat dissipation layout to avoid overheating of a certain area of ​​the sub-core due to continuous operation;

[0132] Historical workload balancing: Prioritize assigning sub-cores with shorter cumulative working time and lower recent usage frequency to the same reserve group.

[0133] The first logic group is designated as the execution group to respond to the discharge command of the independent gating discharge mode or the cooperative timing discharge mode, while non-first logic groups are designated as rest groups, and the rest groups are in a non-discharge state.

[0134] Based on multi-dimensional triggering conditions, it is determined whether to switch the roles of the execution group and the rest group; the multi-dimensional triggering conditions include:

[0135] Condition 1: When the fixed cycle ends and the current work cycle (e.g., 10 seconds) times out, a switchover is triggered.

[0136] Condition 2: If the performance indicators of the execution group exceed the threshold, such as if more than a certain percentage of the sub-core temperatures in the execution group reach the warning value, or if the average internal resistance increases by more than the set percentage, a switchover will be triggered immediately, even if the cycle has not ended.

[0137] Condition 3: Receive an external command that requires switching the working mode. For example, if a high-performance mode command is received, the system can temporarily merge all groups into one large group and output a single ultra-high energy pulse at full power, and then regroup them.

[0138] Condition 4: A failure event occurs in the execution group. A sub-core in the execution group fails and is isolated, resulting in insufficient available capacity for the group. The controller can immediately trigger a switchover and initiate the group reorganization process.

[0139] When any of the multi-dimensional triggering conditions is met, the roles of the execution group and the rest group are switched.

[0140] If so, it is confirmed that the discharge process of the execution group has been completed and the discharge current has returned to zero. The second operating status metadata of all the sub-core modules is obtained. At least two new logical groups are obtained based on the second operating status metadata, and the grouping information is stored. Within a preset switching delay time, the logical group status mapping table of the execution group is updated based on the new logical groups to obtain a new execution group. The new execution group responds to the next discharge command, and the execution group switches to the rest group.

[0141] If the system has 8 sub-cores, initially divided into two groups, A and B, with 4 sub-cores in each group, the system operates at a frequency of 10Hz. In the first 100ms cycle, group A discharges while group B charges and rests. In the second 100ms cycle, group B discharges while group A rests. This cycle repeats to balance losses. During operation, if the controller detects an abnormal temperature in a sub-core, it marks it as a fault and isolates it. Subsequently, the system logically redefines group A as a group containing 3 healthy sub-cores and compensates for the missing energy by fine-tuning the trigger energy or slightly extending the discharge time (within permissible limits). The system continues to operate without immediate shutdown.

[0142] In this embodiment, the switching does not necessarily mean that the two groups simply exchange roles. Before and after each switching event, the controller will rerun the grouping algorithm based on the latest sub-core status data, which may result in a completely new group composition.

[0143] In the previous round, Group A = [Core 1, Core 3, Core 5], and Group B = [Core 2, Core 4, Core 6]. After one round of work, Core 3 has a very high temperature, while Core 6 has historically had the least workload. After regrouping, it might become: New Group A = [Core 2, Core 4, Core 5], New Group B = [Core 1, Core 3 (under recovery), Core 6]. Core 3 is moved to the rest group and receives a longer cooldown period.

[0144] The second operating status metadata includes capacity, voltage, temperature, cumulative number of operations, total historical discharge, internal resistance change rate, and physical location code. The content of the first operating status metadata can be the same as that of the second operating status metadata.

[0145] The at least two new logical groups are obtained based on the second running status metadata and the grouping method, wherein the grouping method is:

[0146] S1. Obtain a comprehensive health score for each sub-core module based on the second operating status metadata, and obtain optimization targets, the optimization targets including:

[0147] Capacity balance: The total available energy storage of each group should be as close as possible to ensure that basic task requirements can be met when any group is called.

[0148] The heat load should be balanced, the average temperature of each group should be as close as possible, and the average temperature of the execution group should be as low as possible.

[0149] Aging should be balanced, and the average cumulative workload of each group should be as close as possible to achieve lifespan synchronization;

[0150] The physical layout should be dispersed. The sub-cores within the same group should be physically dispersed as much as possible to avoid the concentration of heat and electromagnetic interference.

[0151] S2. Based on the comprehensive health score, classify the sub-core modules to obtain a first category; for example:

[0152] Category A (High Quality): Those with an overall health score higher than the first threshold can be considered as core combatants.

[0153] Category B (Good): Overall health score is between the second and first thresholds, suitable for normal use.

[0154] Category C (Attention): Overall health score is below the second threshold, requiring observation or burden reduction.

[0155] S3. Using an improved greedy algorithm or simulated annealing algorithm, an initial grouping scheme is randomly generated based on the first classification.

[0156] S4. Based on the optimization objective, obtain the first score of each first group in the initial grouping scheme, and obtain the first total score of the initial grouping scheme based on the first score;

[0157] S5. Randomly swap any two sub-core modules in any two of the first groups, or move any one sub-core module from one group to another to obtain an optimized grouping scheme. Obtain the second score of each second group in the optimized grouping scheme, and obtain the second total score of the optimized grouping scheme based on the second score.

[0158] S6. If the second total score is greater than the first total score, return to S5, update the first group to the second group, iterate from S5 to S6 until the termination condition is met, and obtain the new logical group based on the optimized grouping scheme; if the second total score is less than or equal to the first total score, return to S5, update the first group to the second group based on the preset acceptance probability (accept with a certain probability to avoid getting trapped in local optima), iterate from S5 to S6 until the termination condition is met (such as the number of iterations or the score being greater than a threshold), and obtain the new logical group based on the optimized grouping scheme.

[0159] The comprehensive health score of each sub-core module is obtained based on a scoring method, wherein the scoring method is as follows:

[0160] State characteristics are obtained based on the state parameters, including electrical core parameters, thermodynamic and mechanical parameters, and switching dynamic characteristic parameters;

[0161] Key electrical parameters include: terminal voltage and self-discharge rate: during the rest period, monitor the voltage decay curve. An abnormal increase in self-discharge current is an early sign of electrolyte degradation or insulation deterioration; capacity decay trend: estimate the actual capacity by comparing the voltage-time integral under constant current discharge. Record its gradual decrease curve with the number of cycles.

[0162] Thermodynamic and mechanical parameters include: core temperature and temperature rise rate, monitoring the peak temperature and the rate at which it reaches the peak during each discharge process. For the same energy release, a faster temperature rise may indicate increased internal thermal resistance (e.g., aging of the thermal interface material).

[0163] Switching dynamic characteristic parameters: Off-action time jitter: Records the delay between each trigger signal and the actual current establishment time. A gradually increasing standard deviation of this delay indicates that the characteristics of the switching device or drive circuit are drifting.

[0164] Based on the state characteristics, an initial health baseline vector is obtained for each sub-core module. In the initial stage of system operation, the controller records the characteristic values ​​of each sub-core under typical operating conditions, and forms its personalized initial health baseline vector and normal fluctuation range through statistical processing, thereby realizing individualized tracking.

[0165] Based on preset parameters, the state characteristics are fitted to obtain the characteristic change slope of each sub-core module; for example, the controller uses a sliding window to perform linear or polynomial fitting on the sequence of each characteristic parameter over time or cycle number to obtain its change slope. A sharp increase in the slope of the self-discharge rate change may indicate a potential fault.

[0166] The comprehensive health score is obtained based on the initial health baseline vector and the slope of feature change. It can be calculated using the following formula:

[0167] ;

[0168] in, H i (t) Indicates the first i The individual core in time t A comprehensive health score w j The weights of each state feature are represented. F ij (t) Indicates time t , No. i The first of the sub-cores j Real-time measurements of each state characteristicB ij Indicates the first i The first of the sub-cores j The initial health baseline value of each state characteristic, Indicates the first i The first of the sub-cores j The normal range (standard deviation) of a state characteristic under healthy conditions. Indicates the trend penalty coefficient. Indicates the first i The first of the sub-cores j The slope of the feature change of each state feature t Indicates time, i and j Both represent integers greater than or equal to 1.

[0169] If an adjustment sub-core module in the execution group is assigned to the rest group, but the current state parameters of the adjustment sub-core module do not meet the preset conditions for entering the rest group, the logical group status identifier of the adjustment sub-core module is delayed until the current state parameters of the adjustment sub-core module meet the preset conditions, and then the logical state of the adjustment sub-core module is assigned to the rest group.

[0170] If some sub-cores in the original execution group are reassigned to the rest group according to the new scheme, and they happen to be in a high-temperature state after the discharge ends, the system can intelligently delay their role switch, allowing them to complete sufficient cooling within the cycle that should have been in the rest group, and then logically consider them as having switched.

[0171] Example 3

[0172] Based on the above embodiments, in this embodiment, the control mode of the mother core control module further includes a fault-tolerant and reconfiguration mode, wherein the fault-tolerant and reconfiguration mode is as follows:

[0173] Based on the comprehensive health score, the abnormal sub-core module and its remaining useful life are obtained. If the comprehensive health score exceeds a certain negative threshold, it means that the sub-core is deteriorating at an accelerated rate. Combining the current score and its decline history, a simple linear or exponential decay model is used to extrapolate and estimate the number of cycles or time required for its score to drop to the failure threshold, i.e., the remaining useful life.

[0174] The failure risk probability is obtained based on the comprehensive health score and the remaining useful life; the comprehensive health score and the remaining useful life are mapped to a failure risk probability between 0 and 1. For example, when the comprehensive health score is <60 or the remaining useful life is <1000 cycles, the failure risk probability increases sharply.

[0175] An early warning strategy is obtained based on the comprehensive health score and the probability of failure risk.

[0176] For example, observation level (70 < overall health score ≤ 85 or failure risk probability < 0.1):

[0177] As a warning, the status light for this sub-core changes from green to yellow on the controller status panel.

[0178] The control strategy is fine-tuned by slightly reducing the selection probability weight of this sub-core in the scheduling algorithm of mode A / B. During group reorganization in mode C, it is avoided from being assigned to execution groups that are about to bear high-load tasks.

[0179] Warning level (50 < Comprehensive health score ≤ 70 or 0.1 ≤ Fault risk probability < 0.3):

[0180] The system will issue an early warning, record the warning log, and report the performance degradation of the sub-core X to the superior system via the communication interface.

[0181] Control strategy intervention: In modes A / B, this sub-core will only be considered for non-critical tasks or when energy requirements are low.

[0182] In Mode C, it is forcibly assigned to the rehabilitation group. Over the next few work cycles, it will be scheduled to perform derating charging and discharging (such as reducing the upper limit of charging current and the peak value of discharging current), and its rest period may be extended, supplemented by enhanced heat dissipation.

[0183] High-risk level (overall health score ≤ 50 or failure risk probability ≥ 0.3):

[0184] The warning action will issue an audible and visual alarm or a remote alarm, suggesting planned maintenance or replacement of the sub-core X.

[0185] The control strategy enforces protection by marking it as quasi-disabled at the software level. Except for specific diagnostic tests, this sub-core will no longer be used for any routine discharge tasks.

[0186] Example 4

[0187] Based on the above embodiments, in this embodiment, the fault tolerance and reassembly mode further includes:

[0188] The controller acquires the waveform of the composite pulse, analyzes the waveform to obtain a defect region, obtains the compensation sub-core module, the compensation triggering sequence of the compensation sub-core module, and the compensation current of the compensation sub-core module based on the defect region, turns on the compensation sub-core module based on the compensation triggering sequence, and superimposes the compensation current onto the defect region to repair the waveform.

[0189] When synthesizing a flat square wave, due to the natural decay characteristics of the core discharge, even if multiple sets of cores are relayed as planned, the load current waveform may still show a slight dip or an overall decline between the two sets. The waveform of the composite pulse or the load current waveform is compared with the theoretical target waveform in real time, and the error between the two in the defect area is calculated. The algorithm immediately selects an optimal backup core from the core resource pool, the required precise trigger delay time of the backup core, and the expected trigger pulse width to ensure that its current peak can accurately fill the moment when the dip occurs.

[0190] If the characteristics of a certain sub-core switch deteriorate, causing its current leading edge to be abnormally slow, thus dragging down the overall rising edge, the algorithm can detect that the actual rising rate is lower than the target by calculating the current slope during the rising edge stage. It can then trigger a sub-core module with fast switching characteristics that was originally planned to work at a later time, and use its steep current leading edge to increase the overall rising slope.

[0191] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0192] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A pulse capacitor employing a master-slave core assembly, characterized in that, The pulse capacitor includes a master core control module and at least two sub-core modules. Each sub-core module includes an energy storage capacitor unit and a switching unit connected in series with the energy storage capacitor unit. The controller of the master core control module is connected to the control terminal of the switching unit of each sub-core module through a drive line. The core control module responds to the discharge command and determines the target control mode; The control modes of the mother core control module include independent gated discharge mode and coordinated timing discharge mode; The independent gated discharge mode is as follows: the controller receives a trigger command, selects at least one of the sub-core modules based on the trigger command to obtain a first target sub-core module, sends a trigger signal to the first switching unit of the first target sub-core module, the first switching unit starts the first target sub-core module, the switching units of non-first target sub-core modules are turned off, and the energy of the first target sub-core module is discharged to the target device. The coordinated timing discharge mode is as follows: the controller receives a high-level waveform description instruction and generates a multi-channel trigger signal sequence containing different delay times based on the high-level waveform description instruction; the multi-channel trigger signal sequence is sent to the second switching unit of the second target sub-core module corresponding to the multi-channel trigger signal sequence, and each second target sub-core module is turned on sequentially or overlappingly according to a specific timing sequence, and the discharge current of each second target sub-core module is superimposed on the target device to obtain a composite pulse; The triggering command includes a target energy value, a target sub-core identifier list, and a logical strategy code. The specific steps for obtaining the first target sub-core module include: A first set of candidate sub-core modules is obtained based on the logic strategy code, the first voltage parameter of the sub-core module, and the first constraint condition. Obtain multi-dimensional features of each first candidate sub-core module in the first candidate sub-core module set, and obtain a second candidate sub-core module set based on the multi-dimensional features. The multi-dimensional features include health value, cumulative number of working times and state of charge. Obtain the second voltage parameter of each second candidate sub-core module in the second candidate sub-core module set, and obtain the first target sub-core module based on the second voltage parameter and the second constraint condition; The first constraint is: the sum of the energy values ​​of all first candidate sub-core modules in the first candidate sub-core module set is not less than the target energy value; The second constraint is: the difference between the sum of the energy values ​​of all second candidate sub-core modules in the second candidate sub-core module set and the target energy value is minimized; The specific cooperative timing discharge mode is as follows: The controller receives the advanced waveform description instruction, which includes the waveform type and waveform parameters of the target waveform; Based on the waveform synthesis algorithm library built into the controller, the high-level waveform description instruction is parsed and the target waveform is decomposed into multiple sub-waveform segments, including rising edge segments, flat-top segments and falling edge segments; For the rising edge segment, the number of rising sub-core modules that are triggered simultaneously at the start time and the initial voltage of the rising sub-core modules are obtained based on the waveform synthesis algorithm library. The rising edge of the LC damped oscillation current of the rising sub-core modules is superimposed to fit the rise time of the target waveform. For the flat-top segment, based on the waveform synthesis algorithm library, the flat-top duration of the target waveform is divided into multiple overlapping maintenance intervals. The number of flat-top sub-core modules triggered at the starting point of each maintenance interval and the triggering delay of the flat-top sub-core modules are calculated sequentially. The decaying discharge current of the flat-top sub-core modules is superimposed in time. The sum of the decaying discharge current is constant during the flat-top duration, forming a current relay. For the falling edge segment, based on the waveform synthesis algorithm library, the last batch of discharge core modules in the discharge stage are controlled to actively shut off the discharge core modules and fit the falling time of the target waveform. The multi-path trigger signal sequence is generated based on the rise time, the sustain interval, the trigger delay, and the fall time; the second target sub-core module is obtained based on the rising sub-core module, the flat-top sub-core module, and the electron discharge core module; Based on the multi-path trigger signal sequence, the second switching unit of the second target sub-core module sequentially or overlappingly turns on each of the second target sub-core modules, and the discharge current of each of the second target sub-core modules is superimposed on the target device to obtain the composite pulse.

2. A pulse capacitor employing a master-slave core assembly according to claim 1, characterized in that, The control mode of the core control module also includes a dynamic grouping alternating working mode, which is as follows: The controller receives a grouping strategy, divides the sub-core modules into at least two logical groups based on the grouping strategy, stores the grouping information, and obtains the first operating status metadata of all the sub-core modules. The first logic group is designated as the execution group to respond to the discharge command of the independent gating discharge mode or the cooperative timing discharge mode, while non-first logic groups are designated as rest groups, and the rest groups are in a non-discharge state. Determine whether to switch the roles of the execution group and the rest group. If so, confirm that the discharge process of the execution group has been completed and the discharge current has returned to zero. Obtain the second operating status metadata of all the sub-core modules. Based on the second operating status metadata, obtain at least two new logical groups and store the grouping information. Within a preset switching delay time, update the logical group status mapping table of the execution group based on the new logical groups to obtain a new execution group. The new execution group responds to the next discharge command, and the execution group switches to the rest group.

3. A pulse capacitor employing a master-slave core assembly according to claim 2, characterized in that, Based on multi-dimensional triggering conditions, determine whether to switch the roles of the execution group and the rest group; The multi-dimensional triggering conditions include: Condition 1: The fixed period ends; Condition 2: The performance metrics of the execution group exceed the threshold; Condition 3: Received external instructions; Condition 4: A failure event occurs in the execution group; When any of the multi-dimensional triggering conditions is met, the roles of the execution group and the rest group are switched.

4. A pulse capacitor employing a master-slave core assembly according to claim 3, characterized in that, The second operating status metadata includes capacity, voltage, temperature, cumulative number of operations, historical total discharge, internal resistance change rate, and physical location code. Based on the second operating status metadata and a grouping method, at least two new logical groups are obtained, wherein the grouping method is as follows: S1. Obtain a comprehensive health score for each sub-core module based on the second operating status metadata, and obtain optimization targets, including capacity balance, thermal load balance, aging balance and physical layout dispersion. S2. Based on the comprehensive health score, classify the sub-core modules to obtain a first category; S3. Based on the first classification, randomly generate an initial grouping scheme; S4. Based on the optimization objective, obtain the first score of each first group in the initial grouping scheme, and obtain the first total score of the initial grouping scheme based on the first score; S5. Randomly swap any two sub-core modules in any two of the first groups, or move any one sub-core module from one group to another to obtain an optimized grouping scheme. Obtain the second score of each second group in the optimized grouping scheme, and obtain the second total score of the optimized grouping scheme based on the second score. S6. If the second total score is greater than the first total score, then return to S5, update the first group to the second group, iterate from S5 to S6 until the termination condition is met, and obtain the new logical group based on the optimized grouping scheme. If the second total score is less than or equal to the first total score, then return to step S5, update the first group to the second group based on the preset acceptance probability, iterate through steps S5 to S6 until the termination condition is met, and obtain the new logical group based on the optimized grouping scheme.

5. A pulse capacitor employing a master-slave core assembly according to claim 4, characterized in that, A comprehensive health score for each sub-core module is obtained based on a scoring method, wherein the scoring method is as follows: Status characteristics are obtained based on operational status metadata, including electrical core parameters, thermodynamic and mechanical parameters, and switch dynamic characteristic parameters; The initial health baseline vector of each sub-core module is obtained based on the aforementioned state characteristics; Based on preset parameters, the state characteristics are fitted to obtain the characteristic change slope of each sub-core module; The comprehensive health score is obtained based on the initial health baseline vector and the slope of feature change.

6. A pulse capacitor employing a master-slave core assembly according to claim 5, characterized in that, If an adjustment sub-core module in the execution group is assigned to the rest group, but the current state parameters of the adjustment sub-core module do not meet the preset conditions for entering the rest group, the logical group status identifier of the adjustment sub-core module is delayed until the current state parameters of the adjustment sub-core module meet the preset conditions, and then the logical state of the adjustment sub-core module is assigned to the rest group.

7. A pulse capacitor employing a master-slave core assembly according to claim 6, characterized in that, The control mode of the mother core control module also includes a fault-tolerant mode, which is as follows: The abnormal sub-core module and its remaining useful life are obtained based on the comprehensive health score, and the failure risk probability is obtained based on the comprehensive health score and the remaining useful life. An early warning strategy is obtained based on the comprehensive health score and the probability of failure risk.

8. A pulse capacitor employing a master-slave core assembly according to claim 7, characterized in that, The fault tolerance and reconfiguration mode also includes: The controller acquires the waveform of the composite pulse, analyzes the waveform to obtain a defect region, obtains the compensation sub-core module, the compensation triggering sequence of the compensation sub-core module, and the compensation current of the compensation sub-core module based on the defect region, turns on the compensation sub-core module based on the compensation triggering sequence, and superimposes the compensation current onto the defect region to repair the waveform.

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