Artificial Intelligence-Based Photonic Integrated Chip Layout Design Method and System

Abstract

This invention provides an artificial intelligence-based method and system for photonic integrated chip layout design, belonging to the field of photonic integrated chip design technology. First, it extracts requirement elements from multiple dimensions to generate a multi-domain requirement element set. Based on this set and real-time process parameters, a dynamic constraint generation mechanism is constructed to generate a dynamic constraint set. A hierarchical collaborative optimization artificial intelligence model is invoked to perform hierarchical collaborative optimization of the initial layout scheme in conjunction with the constraint set, generating an intermediate layout scheme. This intermediate scheme is then verified through cross-domain coupling control to obtain the verification results. Based on the verification results, iterative feedback is provided. If the requirements are met, the final layout design scheme is output; otherwise, it is re-optimized until the requirements are met. This invention can comprehensively consider multi-domain requirements, adapt to process changes, and improve the accuracy, reliability, and performance indicators of layout design.

Description

Technical Field

[0001] This invention relates to the field of photonic integrated chip design technology, and more specifically, to a photonic integrated chip layout design method and system based on artificial intelligence. Background Technology

[0002] With the rapid development of communication, computing and other technologies, the performance requirements for photonic integrated chips are becoming increasingly stringent. Traditional photonic integrated chip layout and design methods have many limitations.

[0003] On the one hand, traditional design methods often focus only on a single or a few aspects of requirements, such as functional implementation or signal transmission requirements, while ignoring the combined impact of multiple domain requirements, including application scenarios, manufacturing processes, and thermal management. For example, when designing chip layout, one may only focus on the functional implementation of photonic devices, without fully considering the chip's adaptability to actual application scenarios and the limitations of manufacturing processes on the layout. This can lead to problems in actual production or failure to meet the requirements of specific scenarios. On the other hand, traditional methods lack dynamic constraint mechanisms, making it difficult to flexibly adjust the layout design based on real-time changes in manufacturing process parameters. During chip manufacturing, process parameters may fluctuate due to equipment status, environmental factors, etc. Traditional fixed-constraint design methods cannot adapt to these changes, easily causing mismatches between the layout scheme and the actual manufacturing process, affecting chip quality and performance. Furthermore, traditional design processes lack effective cross-domain coupling verification and feedback iteration mechanisms. After the layout design is completed, it is difficult to comprehensively evaluate the overall performance of the layout scheme in terms of signal transmission characteristics, thermal characteristics, manufacturing process characteristics, etc., and it is impossible to optimize the layout scheme in a timely manner based on verification results, resulting in low design efficiency and chips that fail to achieve ideal performance indicators. Summary of the Invention

[0004] In view of the aforementioned problems, and in conjunction with the first aspect of the present invention, embodiments of the present invention provide a photonic integrated chip layout design method based on artificial intelligence, the method comprising:

[0005] Multi-domain requirement elements are extracted from the application scenario requirements, functional implementation requirements, signal transmission requirements, manufacturing process requirements, and thermal management requirements of photonic integrated chips to generate a multi-domain requirement element set. The multi-domain requirement element set includes scenario adaptation elements, functional implementation elements, signal attenuation control elements, process accuracy elements, and thermal distribution control elements.

[0006] Based on the set of multi-domain demand elements and the manufacturing process parameters collected in real time, a dynamic constraint generation mechanism is constructed to generate a dynamic constraint set. The dynamic constraint set includes the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints.

[0007] The pre-trained hierarchical collaborative optimization artificial intelligence model is invoked, and the initial layout scheme of the photonic integrated chip is subjected to hierarchical collaborative optimization processing in combination with the dynamic constraint set to generate an intermediate layout scheme. The intermediate layout scheme includes photonic device hierarchical arrangement information, photonic connection link hierarchical planning information, and thermal management adaptation layout information.

[0008] The intermediate layout scheme is subjected to cross-domain coupling control verification processing of layout and signal transmission characteristics, thermal characteristics and manufacturing process characteristics to obtain cross-domain coupling verification results. The cross-domain coupling verification results include characteristic adaptability control information and characteristic compliance control information.

[0009] Based on the cross-domain coupling verification results, feedback iterative processing is performed. If both the characteristic adaptability control information and the characteristic compliance control information meet the preset control requirements, the intermediate layout scheme is output as the final layout design scheme. Otherwise, the cross-domain coupling verification results are fed back to the hierarchical collaborative optimization artificial intelligence model, and the hierarchical collaborative optimization processing is re-executed until a final layout design scheme that meets the preset control requirements is generated. The final layout design scheme includes precise arrangement information of photonic devices, optimized planning information of photonic connection links, integrated layout information of thermal management, and process adaptation annotation information.

[0010] Furthermore, embodiments of the present invention also provide an artificial intelligence-based photonic integrated chip layout design system, characterized in that it includes:

[0011] A processor; a machine-readable storage medium for storing machine-executable instructions of the processor; wherein the processor is configured to execute the above-described artificial intelligence-based photonic integrated chip layout design method by executing the machine-executable instructions.

[0012] In another aspect, embodiments of the present invention also provide a computer program product, the computer program product including machine-executable instructions, the machine-executable instructions being stored in a computer-readable storage medium, the processor of the AI-based photonic integrated chip layout design system reading the machine-executable instructions from the computer-readable storage medium, the processor executing the machine-executable instructions, causing the AI-based photonic integrated chip layout design system to execute the aforementioned AI-based photonic integrated chip layout design method.

[0013] Based on the above, a multi-domain requirement element set is generated by extracting requirement elements from multiple dimensions, covering all key aspects involved in photonic integrated chip design. Then, a dynamic constraint generation mechanism is constructed based on the multi-domain requirement element set and real-time manufacturing process parameters. The generated dynamic constraint set can be flexibly adjusted according to actual needs and process changes, ensuring that the layout design is always within a reasonable constraint range, thus improving the adaptability and flexibility of the layout design. By calling a pre-trained hierarchical collaborative optimization artificial intelligence model in conjunction with the dynamic constraint set for hierarchical collaborative optimization processing, an intermediate layout scheme containing information such as the hierarchical arrangement of photonic devices, hierarchical planning of photonic connection links, and thermal management adaptation layout can be generated, achieving high efficiency and rationality in the layout design. Cross-domain coupling control verification processing is performed on the intermediate layout scheme, which can comprehensively evaluate the overall performance of the layout scheme in terms of signal transmission, thermal characteristics, and manufacturing process, obtaining accurate cross-domain coupling verification results. Based on the verification results, feedback and iterative processing can be performed to continuously optimize the layout scheme according to actual needs until a final layout design scheme that meets the preset control requirements is generated. This final layout design scheme includes detailed information such as precise arrangement of photonic devices, optimized planning of photonic connection links, integrated layout of thermal management, and process adaptation annotation, which greatly improves the accuracy, reliability and performance indicators of photonic integrated chip layout design. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the execution flow of the photonic integrated chip layout design method based on artificial intelligence provided in an embodiment of the present invention.

[0015] Figure 2 This is a schematic diagram of exemplary hardware and software components of the photonic integrated chip layout design system based on artificial intelligence provided in an embodiment of the present invention. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings. Figure 1 This is a flowchart illustrating an artificial intelligence-based photonic integrated chip layout design method according to an embodiment of the present invention. The following is a detailed description of the artificial intelligence-based photonic integrated chip layout design method.

[0017] Step S110: Extract multi-domain requirement elements from the application scenario requirements, functional implementation requirements, signal transmission requirements, manufacturing process requirements, and thermal management requirements of the photonic integrated chip, and generate a multi-domain requirement element set. The multi-domain requirement element set includes scenario adaptation elements, functional implementation elements, signal attenuation control elements, process accuracy elements, and thermal distribution control elements.

[0018] This embodiment uses the layout design of a photonic integrated chip for 5G fronthaul optical modules as a unified application scenario. This photonic integrated chip needs to support parallel transmission of multi-channel optical signals and integrate core components such as lasers, modulators, wavelength division multiplexers, and photodetectors, applied to the signal transmission link between the base station and the remote radio frequency unit. In this step, it is necessary to systematically extract quantifiable and constrained key performance indicators from different dimensions of requirements. These indicators can cover key aspects such as the chip's environmental adaptability, functional integrity, signal quality, manufacturing feasibility, and thermal stability in practical applications.

[0019] Step S111: Determine the target application scenarios, core functional modules, and performance requirements of the photonic integrated chip.

[0020] The determination of target application scenarios requires comprehensive consideration of the physical conditions, operating modes, and reliability requirements of the deployment environment. For 5G fronthaul optical modules, the deployment environment is outdoor base stations, which means that the chip needs to withstand a wide range of temperature fluctuations, possible vibrations, and electromagnetic interference. The division of core functional modules is based on signal flow and processing logic. The optical transmission subsystem is responsible for generating optical carriers, the optical modulation subsystem loads electrical signals onto the optical carriers, the wavelength division multiplexing / demultiplexing subsystem realizes the multiplexing and demultiplexing of multi-wavelength signals, and the optical receiving subsystem completes the conversion and amplification of optical signals to electrical signals. Performance requirements are a quantitative definition of the chip's functional performance. The single-channel signal rate determines the data transmission capability, the inter-channel crosstalk suppression ratio affects the signal purity, the optical power budget relates to the transmission distance, and the power consumption limit and size constraints are directly related to the installation and power supply conditions in engineering applications.

[0021] Step S112: Based on the target application scenario, analyze the environmental adaptability requirements of the scenario to the chip. The environmental adaptability requirements include temperature adaptability range, humidity adaptability range, and anti-interference capability requirements. Convert the environmental adaptability requirements of the scenario to the chip into the core indicators of the scenario adaptation elements and form the initial draft of the scenario adaptation elements.

[0022] In this embodiment, the analysis of temperature adaptability range needs to consider extreme temperature values ​​under extreme weather conditions, as well as the impact of temperature change rate on device performance. Humidity adaptability range must prevent condensation or circuit corrosion inside the chip due to excessive humidity, and electrostatic hazards caused by excessively low humidity. Interference resistance requirements include both resistance to external electromagnetic radiation and internal electromagnetic compatibility. External electromagnetic radiation may come from other equipment within the base station, while internal electromagnetic compatibility involves signal interference between different modules of the chip. When these requirements are converted into core indicators, the temperature coefficient is used to measure the sensitivity of device parameters to temperature changes, the humidity aging coefficient reflects the cumulative impact of long-term humidity environments on chip performance, and the electromagnetic sensitivity threshold characterizes the chip's tolerance limit to electromagnetic interference. These indicators together constitute the initial draft of the scenario adaptation elements.

[0023] Step S113: Based on the core functional modules, break down the implementation requirements of each functional module. The implementation requirements include the type of photonic device, the number of devices, and the functional relationship between devices corresponding to the functional module. Convert the implementation requirements of each functional module into the core indicators of the functional implementation elements to form the initial draft of the functional implementation elements.

[0024] In this embodiment, the implementation of the optical emission subsystem relies on a specific type of laser, the number of which must match the number of transmission channels, and the wavelength characteristics of the laser must meet the requirements of wavelength division multiplexing (WDM). The driving circuit must be adapted to the electro-optical characteristics of the laser. The modulator type (e.g., Mach-Zehnder modulator), modulation bandwidth, and half-wave voltage of the optical modulation subsystem must be determined based on the signal rate and driving conditions. The number of channels, insertion loss, and crosstalk level of the WDM / demultiplexing subsystem directly affect the transmission quality of multi-wavelength signals. The functional relationships between devices are manifested in the signal flow and control logic; for example, the laser output must be precisely connected to the optical input of the modulator, and the modulated signal must be correctly connected to the corresponding channel of the WDM. These implementation requirements are converted into core indicators: device type matching ensures that the selected devices can achieve the expected function; channel number matching ensures the system's parallel processing capability; and functional link integrity verifies the correctness of the connections between devices, thus forming the initial draft of the functional implementation elements.

[0025] Step S114: Based on the performance index requirements, extract the performance parameters related to signal transmission. The performance parameters include the maximum allowable signal attenuation, the minimum signal transmission rate, and the signal anti-interference level. Convert the performance parameters related to signal transmission into the core indicators of the signal attenuation control elements to form the initial draft of the signal attenuation control elements.

[0026] In this embodiment, the maximum permissible signal attenuation specifies the upper limit of power loss of the optical signal from the transmitter to the receiver, which directly relates to the transmission distance and receiver sensitivity. The minimum signal transmission rate is a basic requirement for data transmission speed and must meet the bandwidth requirements of 5G fronthaul. The signal anti-interference level involves the ability to suppress various interference factors (such as inter-channel crosstalk, polarization mode dispersion, reflection, etc.). When converting the above parameters into core indicators, the total link loss budget comprehensively considers various factors such as waveguide loss, coupling loss, and bending loss to ensure that the total attenuation does not exceed the maximum permissible value. The modulation bandwidth margin provides a guarantee for the signal transmission rate, ensuring that the modulator's bandwidth is sufficient to support the distortion-free transmission of high-speed signals. The crosstalk suppression ratio sets a clear suppression index for interference between adjacent channels or different modes to ensure the signal-to-noise ratio of the received signal. These indicators together constitute the initial draft of the signal attenuation control elements.

[0027] Step S115: Obtain the technical level of the current manufacturing process, determine the processing accuracy that the process can achieve, the processing accuracy includes the minimum device size, the minimum device spacing, and the allowable range of link processing error, convert the processing accuracy indicators that the process can achieve into the core indicators of the process accuracy elements, and form the initial draft of the process accuracy elements.

[0028] In this embodiment, obtaining the current manufacturing process level requires investigating the equipment capabilities, process maturity, and material properties of existing production lines. The minimum device size determines the precision and integration density of devices that can be integrated on the chip; the minimum device spacing affects the isolation and crosstalk levels between devices; and the allowable range of link processing errors relates to the geometric accuracy of transmission structures such as waveguides, thus affecting signal transmission characteristics. The processing accuracy achievable by the above processes is converted into core indicators. Linewidth control accuracy describes the actual processing deviation of key structural dimensions such as waveguides; alignment error tolerance ensures precise alignment between multilayer structures; and etching depth uniformity ensures the geometric consistency of the waveguide core layer and cladding. These indicators together constitute the initial draft of process accuracy elements, ensuring that the designed layout can be realized by the actual manufacturing process.

[0029] Step S116: Analyze the heat generation characteristics of the photonic device during operation, and determine the relevant parameters for heat distribution control in combination with the overall thermal management requirements of the chip. The relevant parameters for heat distribution control include the maximum allowable temperature of the device, the uniformity requirements of the overall temperature distribution of the chip, and the heat dissipation capacity requirements of the thermal management structure. Convert the relevant parameters for heat distribution control into the core indicators of heat distribution control elements to form the initial draft of heat distribution control elements.

[0030] Photonic devices inevitably generate heat during operation, especially active devices such as lasers and modulators, which have high heat density. Analyzing heat generation characteristics requires considering the device's operating current, voltage, and energy conversion efficiency to estimate the heat generation of different devices. Overall chip thermal management requirements ensure that all devices operate within their normal operating temperature range, preventing localized overheating that could lead to performance degradation or even failure. The maximum allowable temperature of a device is the upper limit of the temperature a single device can withstand; exceeding this temperature may cause irreversible changes in device parameters. Uniformity of overall chip temperature distribution requires avoiding excessive temperature gradients on the chip to reduce performance inconsistencies caused by temperature differences. The heat dissipation capacity requirements of the thermal management structure define the effectiveness of heat dissipation measures (such as microchannels and heat sinks). These parameters are converted into core indicators: the upper limit of hotspot temperature control directly limits the temperature of high-heat-generating devices; temperature gradient constraints ensure the uniformity of the chip's temperature field; and the heat dissipation efficiency coefficient measures the heat dissipation effect per unit area or volume of the heat dissipation structure. These indicators form the initial draft of thermal distribution control elements.

[0031] Step S117: Perform cross-validation on the initial drafts of scene adaptation elements, function implementation elements, signal attenuation control elements, process accuracy elements, and heat distribution control elements to identify requirement conflicts between different initial drafts.

[0032] Cross-validation aims to check for contradictions or inconsistencies between different elements. For example, the wide-temperature requirement in the scenario adaptation element may conflict with the temperature characteristics of some devices; for instance, some high-performance lasers have narrow operating temperature ranges, making it difficult to meet outdoor wide-temperature requirements. Increasing the number of devices to improve performance in the functional implementation element may lead to increased chip area, conflicting with size constraints, and may also increase power consumption, placing higher demands on the thermal management element. The low-loss link required in the signal attenuation control element may require wider waveguides or specific bending structures, which may conflict with the minimum size or spacing requirements in the process precision element. Strengthening the heat dissipation structure in the thermal distribution control element may occupy more chip area, affecting the layout of functional modules. By systematically comparing and analyzing the performance requirements and impact range of the initial drafts of each element, these potential conflicting requirements can be identified.

[0033] Step S118: Based on the preset requirement conflict resolution rules, the core indicators of the conflicting elements are automatically adjusted to eliminate conflicting content and form adjusted versions of each element. The missing core indicators in each adjusted version of each element are supplemented to ensure that the core indicators of each element cover all dimensions of the corresponding requirement. The supplemented scenario adaptation elements, function implementation elements, signal attenuation control elements, process accuracy elements, and heat distribution control elements are integrated to generate a multi-domain requirement element set.

[0034] Pre-defined rules for resolving requirement conflicts need to be formulated based on project priorities and technical feasibility. In 5G fronthaul optical module chip design, functional implementation and signal transmission performance typically have high priority. When scenario adaptation elements conflict with functional implementation elements, it may be necessary to prioritize ensuring functional integrity while meeting scenario requirements by selecting more temperature-resistant devices or adding temperature control measures. For conflicts between functional implementation and size / power consumption, it may be necessary to optimize device selection and adopt more advanced processes or architectures to reduce area and power consumption. When adjusting the core indicators of conflicting elements, a comprehensive consideration of the balance between technological maturity, cost, and performance is required. After adjustment, it is also necessary to check whether any core indicators are missing in each element version, such as whether the scenario adaptation elements consider mechanical environmental factors such as vibration and shock, and whether the thermal distribution control elements cover dynamic indicators such as thermal response time. After supplementation and improvement, all elements are integrated to form a multi-domain requirement element set.

[0035] Step S120: Based on the multi-domain demand element set and the real-time collected manufacturing process parameters, construct a dynamic constraint generation mechanism to generate a dynamic constraint set. The dynamic constraint set includes the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints.

[0036] The purpose of this step is to establish a dynamic link between demand and manufacturing capability, ensuring that the layout design not only meets multi-domain requirements but also adapts to actual manufacturing conditions. The dynamic constraint generation mechanism needs to be able to perceive and respond to changes in manufacturing processes in real time. Multi-domain demand elements provide target guidance for constraints, while real-time manufacturing process parameters determine the boundary conditions of the constraints. By constructing the above mechanism, a dynamic constraint set containing associative constraints, collaborative constraints, and process parameter adaptation constraints can be generated. Associative constraints clarify the direct limitations imposed by multi-domain demand elements on layout elements (such as device location and link routing); collaborative constraints focus on the mutual influence and coordination relationships between layout elements; and process parameter adaptation constraints ensure that the layout design matches the actual capabilities of the current manufacturing process.

[0037] Step S121: Extract scenario adaptation elements, function implementation elements, signal attenuation control elements, process accuracy elements, and heat distribution control elements from the multi-domain requirement element set. Decompose each element into element dimensions to form an element dimension decomposition list. The element dimension decomposition list includes the core indicators of the element, the scope of influence of the indicator, and the associated objects of the indicator.

[0038] In this embodiment, for each extracted element, it is necessary to deeply analyze the specific connotation of its core indicators, clarify the physical area or functional module affected by the indicator in the chip layout, and the specific devices, links, or structures associated with the indicator. For example, the temperature coefficient indicator in the scene adaptation element may cover all temperature-sensitive active devices on the chip, and the associated objects are these devices themselves and the structures used for temperature control. Through the above decomposition, macroscopic element indicators can be refined to microscopic layout elements, forming an element dimension decomposition list, which needs to record in detail the core indicator ID, spatial description of the scope of influence, and specific identifiers of associated objects for each element dimension.

[0039] Step S122: Real-time acquisition of manufacturing process parameters, including process machining accuracy parameters, process material characteristic parameters, and process environment control parameters.

[0040] In this embodiment, process precision parameters reflect the achievable geometric precision during manufacturing. For example, the uniformity of photolithography exposure dose directly affects the consistency of lines; the plasma density distribution of the etching machine affects the etching depth and sidewall perpendicularity; and the thickness uniformity of thin film deposition relates to the optical and electrical characteristics of the device. Material properties determine the intrinsic performance of the device; the resistivity distribution of the silicon substrate affects the electrical characteristics of the device; the refractive index uniformity of the silicon dioxide cladding is crucial for optical signal transmission; and the sheet resistance of the metal electrodes affects circuit losses. Environmental control parameters ensure the stability of the manufacturing process; the cleanliness level of the photolithography workshop prevents dust contamination; the temperature and concentration of the developer affect the quality of the photolithographic pattern; and the vacuum level of the coating chamber relates to the purity and adhesion of the thin film. By acquiring these parameters in real time, the current status of the manufacturing process can be monitored promptly.

[0041] Step S123: Perform correlation analysis on each element dimension in the element dimension decomposition list and the real-time collected manufacturing process parameters to determine the process parameter adaptation range corresponding to each element dimension and generate an element process correlation table.

[0042] In this embodiment, for each item in the element dimension decomposition list, it is necessary to analyze which manufacturing process parameters affect its core indicators, and within what range of variation of these process parameters can the requirements of the core indicator be met. For example, the crosstalk suppression ratio (CSRR) index in the signal attenuation control element is related to the roughness of the etched sidewalls of the waveguide and the refractive index deviation of the core layer. By using historical data and process models, a functional relationship between the CSRR and these process parameters can be established. Combined with the currently collected process parameter data, the required range of process parameters to meet a specific CSRR can be calculated. The above analysis results of all element dimensions are compiled into an element process correlation table, showing the key process parameters corresponding to each element dimension and their allowable fluctuation range.

[0043] Step S124: Construct a constraint association matrix based on the element process association table. The row dimension of the constraint association matrix is ​​the multi-domain demand element dimension, the column dimension is the manufacturing process parameter dimension, and the matrix elements are the association strength values ​​between the element dimension and the process parameter.

[0044] The constraint correlation matrix is ​​a quantitative representation of the relationship between feature dimensions and manufacturing process parameters. The rows of the matrix represent the specific dimensions extracted from multi-domain demand features, and the columns represent the manufacturing process parameters collected in real time. The correlation strength value of each matrix element is calculated using a specific algorithm (such as the mutual information algorithm). This correlation strength value reflects the degree of mutual influence between the core indicators of the feature dimension and the manufacturing process parameters. A higher correlation strength value indicates a greater impact of the process parameter on the feature dimension indicator, requiring greater attention when generating constraints.

[0045] Step S125: Perform constraint conflict resolution processing on the constraint association matrix, identify conflict terms whose association strength values ​​exceed a preset threshold, call the historical constraint resolution case library for the conflict terms, and extract resolution strategies for similar cases.

[0046] In this embodiment, a pre-set correlation strength threshold is used. When the correlation strength values ​​of a certain element dimension row and multiple process parameter columns in the constraint correlation matrix all exceed this threshold, it means that in order to meet the index requirements of that element dimension, multiple process parameters need to be strictly controlled simultaneously. However, these process parameters may be mutually restrictive and cannot simultaneously reach the ideal state, thus forming conflict terms. For example, a certain element dimension may be strongly correlated with two process parameters at the same time, but these two process parameters are difficult to optimize to the target range simultaneously under the current process conditions. At this time, the historical constraint resolution case library is called to find past cases similar to the current conflict mode through case retrieval, and the successfully applied resolution strategies are extracted, such as adjusting the device structure, optimizing the process step sequence, or adopting compensation measures.

[0047] Step S126: Based on the extracted resolution strategy and combined with the priority of the current multi-domain demand elements, perform constraint adjustment processing on the conflict items to generate the adjusted constraint correlation matrix.

[0048] When resolving conflicts, it's necessary to weigh the priorities of multiple domain requirements. Different elements have varying importance in chip design. Functional implementation elements are usually core, followed by signal attenuation control elements, then thermal distribution control elements, scenario adaptation elements, and process precision elements. Based on this priority ranking, for conflicting items, the performance requirements of higher-priority elements are prioritized. For example, when functional implementation elements conflict with process precision elements, it may be necessary to appropriately relax the parameter ranges of the process precision elements to ensure functional integrity. Based on the extracted resolution strategy, the adaptation range of process parameters involved in the conflict is adjusted, such as tightening the control range of process parameters that have a significant impact on high-priority elements and relaxing the range of process parameters that have a smaller impact on low-priority elements. After adjustment, the correlation strength values ​​in the constraint correlation matrix are recalculated, and the conflict is checked to see if it has been eliminated, until an adjusted conflict-free constraint correlation matrix is ​​generated.

[0049] Step S127: Based on the adjusted constraint correlation matrix, generate the correlation constraints between multi-domain requirement elements and layout elements. The correlation constraints include the constraints between scene adaptation elements and device arrangement density, the constraints between function implementation elements and device type adaptation, the constraints between signal attenuation control elements and link length, the constraints between process accuracy elements and device spacing, and the constraints between heat distribution control elements and device heat dissipation spacing.

[0050] The generation of correlation constraints transforms the quantized relationships in the adjusted constraint correlation matrix into specific layout rules. The temperature coefficient index in the scene adaptation element is related to the device layout density. Excessive device layout density leads to heat accumulation, making it difficult to meet wide-temperature operating requirements. Therefore, an upper limit for device layout density needs to be determined based on the temperature coefficient and heat dissipation capacity. The channel number matching index in the function implementation element requires a strict correspondence between device type and functional requirements. For example, the number of channels in a laser array must match the number of channels in a modulator array and wavelength division multiplexer; otherwise, a complete signal transmission link cannot be achieved. The total link loss budget in the signal attenuation control element directly limits the link length. Longer links result in greater losses, so the link length must be within the allowable loss range. The alignment error tolerance in the process accuracy element determines the device spacing. To ensure correct connection of multi-layer structures, the device spacing must be greater than a certain multiple of the alignment error. The upper limit for hotspot temperature control in the heat distribution control element requires a sufficiently close distance between high-heat devices and the heat dissipation structure, i.e., the device heat dissipation spacing, to ensure timely heat dissipation. These correlation constraints directly map multi-domain requirement elements to specific parameters of the layout design.

[0051] Step S128: Analyze the mutual influence relationships between layout elements and generate collaborative constraints between layout elements. The collaborative constraints include collaborative constraints between device arrangement density and link planning path, collaborative constraints between device type and process material characteristics, and collaborative constraints between link length and heat distribution control.

[0052] Complex interrelationships exist among layout elements, and synergistic constraints aim to coordinate these relationships to achieve optimal overall performance. High device density leads to limited link routing space, potentially requiring more compact link planning paths or larger bending radii. This creates a synergistic constraint between device density and link planning paths; when device density exceeds a certain value, link paths need to be adjusted accordingly to avoid overcrowding and crosstalk. Different device types have specific requirements for process materials. For example, lithium niobate modulators require lithium niobate substrates and specific electrode materials. This forms a synergistic constraint between device type and process material characteristics, ensuring that the selected device type matches the currently available process materials. Link length not only affects signal attenuation but also increases signal transmission delay. Furthermore, the link itself generates heat, especially during high-power signal transmission. Therefore, there is a synergistic constraint between link length and thermal distribution control; long links may require more optimized heat dissipation layouts or path planning to balance signal quality and thermal management.

[0053] Step S129: Convert the real-time acquired manufacturing process parameters into process parameter adaptation constraints. The process parameter adaptation constraints include layout error allowable constraints corresponding to process processing accuracy parameters, device material adaptation constraints corresponding to process material characteristic parameters, and layout environment adaptation constraints corresponding to process environment control parameters.

[0054] Real-time acquired manufacturing process parameters need to be converted into direct constraints on the layout design. The photolithography overlay error, a parameter related to process precision, determines the allowable alignment deviation between multilayer structures. Therefore, the interlayer alignment deviation of multilayer metal wiring in the layout design must be within the allowable range of the overlay error, forming a layout error constraint. The deviation between the actual and designed refractive index of the waveguide core layer, a parameter related to process material properties, needs to be compensated for by adjusting device structural parameters (such as waveguide width) to ensure the device's optical performance; this is the device material compatibility constraint. Temperature and humidity fluctuations in the photolithography workshop, a parameter related to process environment control, can affect photolithography precision. For temperature-sensitive devices, they should be placed in relatively stable temperature areas on the chip during layout to avoid excessive influence on the edges from environmental temperature and humidity fluctuations, thus forming a layout environment compatibility constraint. These constraints ensure that the layout design can adapt to actual manufacturing process conditions, improving yield.

[0055] Step S1210: Integrate the association constraints of the multi-domain demand elements and layout elements, the coordination constraints between layout elements, and the process parameter adaptation constraints to generate a dynamic constraint set.

[0056] The integration of dynamic constraint sets is a process of systematizing and standardizing the various constraints generated previously. It requires organizing associated constraints, collaborative constraints, and process parameter adaptation constraints according to a unified format, clearly defining the identifier, type, specific conditions, priority, scope of application, and validity period of each constraint. For example, an associated constraint can be described as requiring the placement density of a certain type of device within a specific region to be less than a certain value. Through integration, a dynamic constraint set is formed, which comprehensively reflects the constraints and requirements of multi-domain demand elements and manufacturing process parameters on layout design.

[0057] Step S1211: Test the executability of each constraint by simulating layout scenarios, remove unexecutable constraints, supplement the constraint items corresponding to the missing constraint scenarios, form the final dynamic constraint set, and store the final dynamic constraint set in the dynamic constraint database.

[0058] In this embodiment, a simulation environment containing virtual devices and layout areas is constructed. Each constraint in the dynamic constraint set is applied to this scenario, and it is checked whether the constraints can be satisfied under given chip area, number of devices, and process conditions. If a constraint cannot be achieved in the simulation scenario, for example, if the required device spacing is too small and cannot be arranged under given device number and area, it is determined to be an unenforceable constraint and needs to be adjusted in the previous steps. At the same time, through scenario coverage analysis, it is checked whether there are layout scenarios not covered by existing constraints, such as combinations of specific types of devices or special link routing, and corresponding constraint items are added for the missing scenarios. After testing and improvement, the final dynamic constraint set is formed and stored in the dynamic constraint database.

[0059] Step S130: Call the pre-trained hierarchical collaborative optimization artificial intelligence model, and perform hierarchical collaborative optimization processing on the initial layout scheme of the photonic integrated chip in combination with the dynamic constraint set to generate an intermediate layout scheme. The intermediate layout scheme includes photonic device hierarchical arrangement information, photonic connection link hierarchical planning information, and thermal management adaptation layout information.

[0060] In this step, the pre-trained hierarchical collaborative optimization AI model leverages existing knowledge and learning capabilities to intelligently optimize the initial layout scheme under the guidance of a dynamic constraint set. Hierarchical collaborative optimization means that the model decomposes the layout problem into different levels (such as device layer, link layer, and system layer) for processing, and performs information interaction and collaboration between these levels to achieve the optimal overall layout. The dynamic constraint set, as part of the boundary conditions and objective function of the model optimization, ensures that the optimization process always operates within a feasible range. Through the model's processing, the device arrangement, link planning, and thermal management layout in the initial layout scheme are systematically optimized and adjusted. The final intermediate layout scheme, while satisfying all constraints, should be able to achieve the chip's functional and performance goals relatively well.

[0061] Step S131: Obtain the initial layout scheme of the photonic integrated chip, wherein the initial layout scheme includes preliminary photonic device arrangement information, preliminary photonic connection link planning information, and preliminary thermal management layout information.

[0062] Step S1311: Based on the functional implementation elements in the multi-domain requirement element set, determine the types and quantities of photonic devices required for the photonic integrated chip, and generate a device list.

[0063] The functional implementation elements clearly define the core functions the chip needs to perform, such as the generation, modulation, transmission, and reception of optical signals. Based on these functions, the required types of photonic devices are determined; for example, a laser is needed to generate optical signals, a modulator is needed to modulate optical signals, and a photodetector is needed to receive optical signals. Simultaneously, considering requirements such as the number of signal channels, the quantity of each type of device is determined. For example, if four-channel signal transmission is required, four lasers, four modulators, and four photodetectors are needed, thus generating a detailed device list. This device list includes information such as the device model, functional parameters, and package type.

[0064] Step S1312: Based on the minimum device spacing and minimum device size requirements in the process accuracy elements, divide the device layout area within the chip layout area.

[0065] Minimum device spacing and minimum device size, key factors in process precision, limit the physical arrangement of devices on the chip. Based on these requirements and the overall size of the chip's layout area, the chip is divided into multiple device arrangement sub-regions. For example, based on the minimum device spacing requirement, a region for optical emitting devices is designated in the upper left corner, a region for optical receiving devices is designated in the lower right corner, and a region for modulation and wavelength division multiplexing devices is designated in the middle area. The size of each sub-region must meet the requirements for the number and spacing of devices within that region.

[0066] Step S1313: Group the photonic devices in the device list according to their functional relationships, and assign devices in the same functional group to adjacent layout areas.

[0067] Photonic devices exhibit specific functional relationships; for example, lasers and modulators need to be closely connected to reduce optical coupling losses. Therefore, functionally related devices are grouped together. For instance, lasers and their corresponding driving circuits are grouped into an optical emission functional group, and modulators and their control circuits are grouped into an optical modulation functional group. Devices within the same functional group are then assigned to adjacent layout areas to ensure close physical proximity, facilitating subsequent link connections and signal transmission.

[0068] Step S1314: Based on the link length limitation in the signal transmission characteristic requirements, plan the photonic connection link path between devices in each functional group and generate a preliminary link planning diagram.

[0069] The link length limitation in the signal transmission characteristic requirements is to ensure that signal attenuation and delay during transmission are within acceptable limits. Based on the location distribution of devices in each functional group, the path of the photonic connection link is planned according to the principle of minimizing link length. For example, the link from the optical emission functional group to the optical modulation functional group should follow a straight or minimally curved path, avoiding the device areas of other functional groups. A preliminary link planning map is generated, marking the start, end, and major turning points of the link.

[0070] Step S1315: Adjust the device arrangement position based on the device heat dissipation spacing requirements in the heat distribution control elements.

[0071] The heat dissipation spacing requirement in the thermal distribution control elements is to prevent heat accumulation between devices from affecting performance. Based on the power consumption of the devices, the initial device positions are adjusted. Devices with higher power consumption, such as lasers, require a larger heat dissipation spacing around them. They can be appropriately moved away from other high-heat devices, or their specific coordinates within the arrangement area can be adjusted to meet the heat dissipation spacing requirements and ensure that the device operating temperature remains within a safe range.

[0072] Step S1316: Integrate device layout information, link planning diagram, and heat dissipation space allocation information to generate preliminary photonic device layout information and preliminary photonic connection link planning information.

[0073] By integrating the adjusted device layout coordinates and device dimensions, preliminary photonic device layout information is formed, which details the positional parameters of each device on the chip. Simultaneously, the planned link routing, link width, bending radius, and other parameters are integrated to form preliminary photonic connection link planning information. These two pieces of information are interrelated and together constitute the main framework of the chip layout.

[0074] Step S1317: Based on thermal management requirements, plan the initial thermal management structure locations in densely populated areas and around devices whose heat generation power exceeds a preset threshold, and generate initial thermal management layout information.

[0075] Thermal management requirements aim to ensure uniform temperature distribution across the chip and prevent localized overheating. Based on preliminary photonic device layout information, densely populated areas and high-heat devices with heat output exceeding a preset threshold, such as the laser array area, are identified. The locations of thermal management structures are planned around these areas; for example, the location and orientation of microchannel heat dissipation structures are planned below the laser array, and the locations of heat sinks are planned at the chip edges. This generates preliminary thermal management layout information, which includes parameters such as the type, size, and location coordinates of the thermal management structures.

[0076] Step S1318: Integrate the preliminary photonic device layout information, the preliminary photonic connection link planning information, and the preliminary thermal management layout information to form the initial layout scheme of the photonic integrated chip.

[0077] The preliminary photonic device layout information, photonic link planning information, and thermal management layout information generated above are integrated to ensure that the three do not conflict spatially. For example, the link planning does not pass through the core area of ​​the thermal management structure, and the device layout does not occupy the space of the links and heat dissipation structure. Through integration, an initial layout scheme is formed.

[0078] Step S132: Extract the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints from the dynamic constraint set, and convert the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints into a constraint input data format that can be recognized by the hierarchical collaborative optimization artificial intelligence model.

[0079] The conversion of constraint input data format involves transforming a structured set of dynamic constraints into a numerical representation that the model can understand and process. Associative constraints, collaborative constraints, and process parameter adaptation constraints have different logical structures and parameters, requiring separate encoding. For example, the device layout density constraint within associative constraints can be encoded as a vector containing region identifiers and maximum density values. The collaborative constraint between device type and process material properties can be encoded as a matrix mapping device type IDs to material property parameter ranges. The layout error allowance constraint within process parameter adaptation constraints can be encoded as a tensor containing error type and allowable deviation values. During the conversion process, the parameters in the constraints need to be normalized, mapping them to values ​​within the model's processing range, while preserving the logical relationships and priority information of the constraints to ensure the model can accurately understand and apply these constraints.

[0080] Step S133: Convert the photonic device arrangement information, photonic connection link planning information, and thermal management layout information in the initial layout scheme into a layout input data format that can be recognized by the hierarchical collaborative optimization artificial intelligence model.

[0081] The conversion of layout input data format transforms physical layout information into a feature representation of the model. Photonic device arrangement information needs to be quantized into a tensor containing multi-dimensional features such as device type, size, location, and power consumption. Each device corresponds to a sample or feature vector within the tensor. Photonic connection link planning information requires extracting features such as link length, number of bends, and connection relationships to form a link feature tensor. Thermal management layout information includes features such as the type, size, location, and heat dissipation efficiency of the heat dissipation structure, constituting a thermal feature tensor. The extraction and quantization of these features need to consider the model's input requirements, typically requiring normalization and encoding (e.g., unique thermal encoding to represent device type) to convert physical quantities into numerical features that the model can effectively learn. The layout input data format should be compatible with the constraint input data format in terms of dimension and representation to allow for joint processing by the model.

[0082] Step S134: Simultaneously input the constraint input data format and the layout input data format into the element interaction layer of the hierarchical collaborative optimization artificial intelligence model. Perform constraint feature encoding processing on the associated constraints, collaborative constraints, and process parameter adaptation constraints in the constraint input data format to generate constraint feature tensors. Perform layout feature encoding processing on the device layout information, link planning information, and thermal management layout information in the layout input data format to generate layout feature tensors.

[0083] In this embodiment, for constraint input data, constraint feature encoding aims to transform different types of constraint information into a unified high-dimensional feature representation—a constraint feature tensor. This process may involve modeling the logical relationships between constraints, such as representing dependencies between constraints using a graph structure, or highlighting important constraints through an attention mechanism. For layout input data, layout feature encoding extracts and integrates features of layout elements such as devices, links, and thermal management to generate a layout feature tensor. During the encoding process, the model may use convolutional operations to extract local spatial features or use recurrent neural networks to process sequential link information. Through feature encoding, the original constraint and layout data are transformed into a feature tensor rich in semantic information.

[0084] Step S135: Perform cross-dimensional interactive fusion processing of constraint feature tensor and layout feature tensor to generate interactive fusion feature tensor, and input the interactive fusion feature tensor into the hierarchical optimization layer of the hierarchical collaborative optimization artificial intelligence model. The hierarchical optimization layer includes device layer optimization submodule, link layer optimization submodule and system layer optimization submodule.

[0085] In this embodiment, the constraint feature tensor and the layout feature tensor describe the constraints and current state of the problem from different perspectives. Through interactive fusion, the layout features can perceive the requirements of the constraints, and the constraint features can also be adjusted for specific layouts. The bilinear attention mechanism is an effective method for achieving this fusion. It calculates the similarity between constraint features and layout features to determine the influence weights of different constraints on different layout elements, and then integrates the constraint features into the layout features according to the weights, or vice versa. The generated interactive fusion feature tensor contains both the structural information of the layout and the requirement information of the constraints, which can more effectively guide the subsequent optimization process. The three sub-modules of the hierarchical optimization layer correspond to different levels of layout optimization: the device layer focuses on the optimization of individual devices, the link layer focuses on the optimization of connections between devices, and the system layer coordinates all parts as a whole to achieve optimal system-level performance.

[0086] Step S136: The device layer optimization submodule optimizes the photonic device arrangement information in the initial layout scheme based on the device-related features in the interactive fusion feature tensor and the device class constraints in the dynamic constraint set, and generates optimized device arrangement information. The optimization process includes device position adjustment, device type adaptation adjustment, and device spacing adjustment.

[0087] In this embodiment, the device-related features in the interactive fusion feature tensor include the device type, size, power consumption, current position, and related constraint information (such as temperature constraints and spacing constraints). The device class constraints in the dynamic constraint set specify the specific requirements for device arrangement, such as the device type must match the functional requirements, and the device spacing must meet process accuracy and heat dissipation requirements. Optimization processing satisfies various constraints and optimizes device performance by adjusting the coordinates of devices within the layout area (position adjustment), selecting device models more suitable for the current process and requirements (type adaptation adjustment), and modifying the relative distance between devices (spacing adjustment). For example, for devices with high heat generation, it may be necessary to adjust their position closer to the heat dissipation structure and increase the spacing with other devices to improve heat dissipation; for devices with high process accuracy requirements, it may be necessary to select alternative types with larger size tolerances.

[0088] Step S137: The link layer optimization submodule optimizes the photon connection link planning information in the initial layout scheme based on the link-related features in the interactive fusion feature tensor and the link class constraints in the dynamic constraint set, and generates optimized link planning information. The optimization process includes link path adjustment, link material adaptation adjustment, and link length adjustment.

[0089] The link layer optimization submodule is responsible for optimizing the connection paths between devices. Link-related features in the interactive fusion feature tensor include the current path, length, curvature, crosstalk level, and related constraint information (such as loss constraints and length constraints). Link-class constraints in the dynamic constraint set restrict the geometric parameters and material properties of the links. Link path adjustment re-plans the link's routing to avoid high crosstalk or congested areas, selecting shorter, straighter paths to reduce loss and delay. Link material adaptation adjustment selects appropriate waveguide core and cladding materials based on process material characteristics and link performance requirements to optimize refractive index distribution and loss characteristics. Link length adjustment increases or decreases the number of curved or straight segments in the path to ensure the link length meets signal attenuation control requirements while avoiding excessive length that could lead to increased delay and loss.

[0090] Step S138: The system-level optimization submodule, based on the system-related features in the interactive fusion feature tensor and combined with the system class constraints in the dynamic constraint set, performs system-level collaborative adjustment processing on the optimized device layout information and the optimized link planning information. At the same time, it optimizes the thermal management layout information in the initial layout scheme and generates system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information.

[0091] The system-level optimization submodule starts from the overall chip performance, coordinating the optimization results of the device layer and the link layer. The system-related features in the interactive fusion feature tensor reflect global information such as the chip's overall size, power distribution, temperature field, and total signal delay. The system-class constraints in the dynamic constraint set limit the chip's overall metrics such as total area, total power consumption, and maximum temperature. System-level collaborative adjustment processing may involve further adjusting device locations and link paths based on the optimization results of the device and link layers to balance resource competition and mutual influence between modules. For example, when devices and links are too densely packed in certain areas, leading to heat dissipation difficulties, system-level optimization may move some devices to other areas or adjust link routing to disperse heat. Simultaneously, the system-level optimization submodule also optimizes thermal management layout information based on the overall heat distribution, such as adjusting the distribution density of microchannels and optimizing the position and size of heat sinks to achieve the best overall heat dissipation effect.

[0092] Step S139: Input the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information into the constraint adaptation layer of the hierarchical collaborative optimization artificial intelligence model.

[0093] In this embodiment, the optimized layout information at the system level is input into the constraint adaptation layer to check whether the optimization results fully satisfy all constraints in the dynamic constraint set. The constraint adaptation layer needs to comprehensively call the dynamic constraint set, including associated constraints, cooperative constraints, and process parameter adaptation constraints, to perform a one-by-one adaptation check on the optimized device, link, and thermal management layouts. This process is similar to a final quality inspection, ensuring the feasibility and effectiveness of the optimization results.

[0094] Step S1310: The constraint adaptation layer calls all the constraint contents in the dynamic constraint set to perform adaptation control processing on the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information, and generates adaptation control results.

[0095] In this embodiment, the system-level optimization result is compared with each constraint in the dynamic constraint set to evaluate whether the optimization result meets the constraint requirements. For example, it checks whether the device layout density exceeds the limit of the associated constraint, whether the link length is within the allowable range of the signal attenuation control element, and whether the thermal management layout meets the upper limit of the hot spot temperature control. For constraints that are not met, the constraint adaptation layer will attempt to make fine adjustments, such as slightly adjusting the device position or link path, to make it meet the constraints. The adaptation adjustment result includes the degree to which the optimization result meets each constraint, as well as an indication of whether further adjustments are needed.

[0096] Step S1311: If the adaptation control results show that the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information meet all constraints, then integrate the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information to generate an intermediate layout scheme.

[0097] When the adaptability adjustment results indicate that all constraints are met, it means that the current system-level optimization result is feasible. At this point, it is necessary to integrate the optimized device layout, link planning, and thermal management layout information to form a complete intermediate layout scheme. The integration process includes converting the layout data of each part into a unified format (such as GDSII format) to ensure data consistency and integrity, and generating corresponding report files, such as constraint satisfaction reports, recording the satisfaction status of each constraint and key adjustments made during the optimization process.

[0098] Step S1312: If the adaptation control results show that the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information do not meet some constraints, then the unmet constraints are fed back to the hierarchical optimization layer, and the device layer optimization, link layer optimization, and system layer optimization steps are re-executed to adjust the optimization direction and optimization range.

[0099] When the adaptation adjustment results reveal that some constraints are not met, this information needs to be fed back to the hierarchical optimization layer to initiate a new round of optimization iterations. Unmet constraints typically have different priorities; higher-priority constraints should be prioritized during feedback. Based on the feedback constraint information, the hierarchical optimization layer adjusts the optimization direction and magnitude of each sub-module. For example, if the device spacing constraint is not met, the device layer optimization sub-module might increase the spacing adjustment step size or weight; if the link loss constraint is not met, the link layer optimization sub-module might focus more on path selection and material adaptation. Through this feedback mechanism, the model can continuously adjust its optimization strategy, gradually approaching a layout scheme that satisfies all constraints.

[0100] Step S1313: Repeat the hierarchical optimization and constraint adaptation control steps until system-level optimization information that satisfies all constraints is generated, and then integrate it into a preliminary intermediate layout scheme.

[0101] In this embodiment, due to the interrelationships between layout elements and the complexity of constraints, a single optimization iteration may not satisfy all constraints. Therefore, it is necessary to repeatedly perform hierarchical optimization (device layer, link layer, system layer) and constraint adaptation adjustment steps. In each iteration, the model adjusts based on the previous optimization results and constraint adaptation feedback, continuously optimizing the layout scheme. During the iteration process, it is necessary to monitor the changing trend of constraint satisfaction. If the constraint satisfaction does not improve significantly after several consecutive iterations, it may be necessary to adjust the model's optimization parameters or strategies, such as increasing the number of iterations or adjusting the learning rate. This continues until system-level optimization information that satisfies all constraints is generated and integrated into a preliminary intermediate layout scheme.

[0102] Step S1314: Perform optimization effect control processing on the preliminary intermediate layout scheme, and calculate the degree of satisfaction of the multi-domain requirement elements corresponding to the preliminary intermediate layout scheme. The degree of satisfaction includes the degree of satisfaction of scene adaptation, the degree of satisfaction of function implementation, the degree of satisfaction of signal attenuation control, the degree of satisfaction of process accuracy, and the degree of satisfaction of heat distribution control.

[0103] In this embodiment, calculating the satisfaction level requires comparing various performance indicators of the layout scheme with the core indicators among the multi-domain requirement elements. Scenario adaptation satisfaction assesses the chip's adaptability to the target environment, such as whether the temperature coefficient meets the standards. Functional implementation satisfaction checks whether core functional modules are fully implemented and whether the device type and quantity match the requirements. Signal attenuation control satisfaction measures the quality of signal transmission, such as whether link loss and crosstalk are within acceptable limits. Process accuracy satisfaction assesses the compatibility between the layout scheme and the manufacturing process, such as whether critical dimensions and spacing meet process requirements. Thermal distribution control satisfaction focuses on the chip's temperature distribution and heat dissipation effect. By calculating these satisfaction levels, a comprehensive understanding of the advantages and disadvantages of the initial intermediate layout scheme can be obtained.

[0104] Step S1315: If the satisfaction level reaches the preset optimization threshold, the preliminary intermediate layout scheme is determined as the intermediate layout scheme; if the satisfaction level does not reach the preset optimization threshold, the satisfaction level analysis result is fed back to the element interaction layer, and the feature encoding, cross-dimensional interaction fusion, and hierarchical optimization steps are re-executed, and the interaction fusion strategy and hierarchical optimization parameters are adjusted until an intermediate layout scheme with a satisfaction level reaching the preset optimization threshold is generated.

[0105] A preset optimization threshold is the standard for judging whether the preliminary intermediate layout scheme is qualified. It is usually set according to project requirements and experience, such as a weighted average of the satisfaction levels of each element reaching 0.9 or higher. If the satisfaction level reaches the threshold, the preliminary intermediate layout scheme is confirmed as the final intermediate layout scheme. If the threshold is not reached, the satisfaction level analysis results (which elements have low satisfaction levels and the specific reasons) need to be fed back to the element interaction layer. The element interaction layer adjusts the feature encoding method based on the feedback results, such as increasing the weight of features related to low-satisfaction elements; adjusting the cross-dimensional interaction fusion strategy, such as enhancing the interaction strength between constraint features and low-satisfaction layout elements; the hierarchical optimization layer adjusts the optimization parameters of each sub-module accordingly, such as modifying the reward function and adjusting the learning rate, to specifically improve the performance of low-satisfaction elements. Through the above methods, the optimization process is repeated until an intermediate layout scheme that meets the preset optimization threshold is generated.

[0106] Step S140: Perform cross-domain coupling control verification processing on the intermediate layout scheme to determine the layout and signal transmission characteristics, thermal characteristics, and manufacturing process characteristics, and obtain cross-domain coupling verification results. The cross-domain coupling verification results include characteristic adaptability control information and characteristic compliance control information.

[0107] While the intermediate layout scheme is optimized under constraints, in actual operation, there are complex coupling relationships between the chip's signal transmission characteristics, thermal characteristics, and manufacturing process characteristics. Optimization in one domain may lead to performance degradation in other domains. Cross-domain coupling control verification aims to simulate actual operating conditions, analyze the interactions between these characteristics, and evaluate the overall performance and robustness of the layout scheme. Characteristic adaptability control information focuses on the degree of matching between different characteristics, such as whether the impact of thermal distribution on signal transmission characteristics is within acceptable limits. Characteristic compliance control information checks whether various characteristic indicators meet the requirements of multi-domain requirements. Through this verification process, potential cross-domain problems in the layout scheme can be identified.

[0108] Step S141: Extract system-level optimized device layout information, system-level optimized link planning information, system-level optimized thermal management layout information, and process adaptation annotation information from the intermediate layout scheme.

[0109] In this embodiment, detailed parameters of the device layout information (coordinates, type, size, material, power consumption, etc.) are used to construct the physical and electrical models of the devices. Link planning information (path, size, material, bending parameters, etc.) is a key input for signal transmission characteristic simulation. Thermal management layout information (heat dissipation structure parameters, material thermal properties, etc.) is used for thermal characteristic simulation. Process adaptation annotation information (critical dimensions, overlay marks, material deposition requirements, etc.) is directly related to manufacturing process characteristic simulation. The accuracy and completeness of the above information directly affect the reliability of the verification results, therefore it needs to be accurately extracted from intermediate layout schemes.

[0110] Step S142: Based on the system-level optimized device layout information, system-level optimized link planning information, and process adaptation annotation information, construct a simulation scenario of the cross-domain characteristics of the photonic integrated chip. In the simulation scenario, restore the actual layout position of the photonic devices, the relative distance between devices, the actual direction of the connection links, and the process implementation scenario corresponding to the process adaptation annotation.

[0111] Cross-domain characteristic simulation scenarios are virtual environments for multiphysics simulations. Based on extracted device layout information, each device is precisely placed in the simulation scenario to ensure its position and relative distance match the actual layout. According to link planning information, a complete signal transmission path is constructed, including waveguide routing, bending, and coupling structures. Process adaptation annotation information is used to set process parameters in the simulation scenario, such as the deviation range of critical dimensions and the actual properties of materials, to simulate real manufacturing processes. The construction of the simulation scenario needs to consider the chip's three-dimensional structure, including the stacking of different material layers and the interactions of various physical fields (electromagnetic fields, temperature fields).

[0112] Step S143: In the cross-domain characteristic simulation scenario, construct a signal transmission characteristic simulation subsystem, a thermal characteristic simulation subsystem, and a manufacturing process characteristic simulation subsystem.

[0113] In this embodiment, the signal transmission characteristic simulation subsystem, based on electromagnetic field theory and optical principles, simulates the transmission process of optical signals in a waveguide. It needs to include a light source model, modulation model, transmission model, and detection model to calculate parameters such as signal loss, dispersion, and crosstalk. The thermal characteristic simulation subsystem, based on the heat conduction equation, simulates the heat generation, heat transfer, and heat dissipation processes during device operation. It includes a heat source model, heat conduction model, convection heat dissipation model, and radiation heat dissipation model to calculate temperature distribution and heat flux density. The manufacturing process characteristic simulation subsystem, based on a process physics model, simulates manufacturing processes such as photolithography, etching, and deposition, predicting the impact of process deviations on device structure and performance. It includes photolithography simulation models, etching simulation models, and deposition simulation models. These three subsystems need to achieve data interaction. For example, the signal transmission subsystem provides power consumption data to the thermal subsystem, the thermal subsystem provides temperature-dependent device parameters to the signal subsystem, and the process subsystem provides structural parameter deviations to the other two subsystems.

[0114] Step S144: The signal transmission characteristic simulation subsystem constructs a photonic signal transmission simulation link based on the system-level optimized link planning information, generates a photonic signal that meets the signal characteristic requirements in the multi-domain requirement element set, inputs the photonic signal into the simulation link, simulates the transmission process of the photonic signal in the link, and collects signal attenuation data, signal transmission rate data, and signal interference data during the transmission process.

[0115] The core of the signal transmission characteristic simulation subsystem is to simulate the complete transmission link of an optical signal. Based on the link planning information, modules such as the light source, modulator, waveguide, coupler, and detector are connected sequentially to construct the simulation link. The generated photonic signal must meet the signal characteristic requirements of the multi-domain requirements, such as wavelength, power, and rate. During the simulation, the subsystem solves Maxwell's equations or approximate beam propagation equations to simulate the propagation behavior of the optical signal in different devices and links. Signal attenuation data is obtained by calculating the optical power loss during transmission, including absorption loss, scattering loss, and bending loss. Signal transmission rate data is determined by analyzing parameters such as the eye diagram and bit error rate at the receiver. Signal interference data includes crosstalk between adjacent channels and mode crosstalk, which is collected by monitoring the power of the interfering signal or its impact on the main signal.

[0116] Step S145: The thermal characteristic simulation subsystem simulates the heat generation process of photonic devices, the heat conduction process within the chip, and the heat dissipation process of the thermal management structure during operation, based on the system-level optimized device layout information and the system-level optimized thermal management layout information, and collects heat distribution data, heat conduction rate data, and heat dissipation efficiency data.

[0117] For example, step S1451: Extract the type information, location information, and power consumption information of photonic devices from the system-level optimized device layout information; extract the type information, location information, and heat dissipation capacity information of thermal management structures from the system-level optimized thermal management layout information.

[0118] The system-level optimized device layout information records detailed parameters for each photonic device, from which device types, such as lasers and modulators, are extracted to determine their thermal characteristics. Position information is extracted to define the device's coordinates on the chip, used to construct a spatial model for thermal simulation. Power consumption information is extracted as the basis for calculating heat generation. Simultaneously, the system-level optimized thermal management layout information extracts the type of thermal management structure, such as microchannels and heat sinks, as different types of heat dissipation structures have different heat dissipation mechanisms. Position information is extracted to determine the layout of the heat dissipation structure on the chip. Heat dissipation capacity information, such as the heat dissipation efficiency of microchannels and the heat dissipation area of ​​heat sinks, is extracted; this information is key parameters for simulating the heat dissipation process.

[0119] Step S1452: In the cross-domain characteristic simulation scenario, a heat generation model is constructed. The heat generation model is based on the power consumption information of photonic devices, simulates the heat generation process when the devices are working, and calculates the heat generation data of each device per unit time.

[0120] The heat generation model is the foundation of thermal characteristic simulation. Based on the extracted power consumption information of photonic devices and combined with the energy conversion efficiency of the devices, the heat generated by the devices due to energy loss during operation is calculated. For example, the electrical power input of a laser is partially converted into optical power output, and the remainder is converted into heat. The heat generation per unit time can be calculated using a formula. The heat generation data of each device is input into the heat generation model. The model generates heat at the corresponding location in the simulation scene based on the device's location information, simulating the real device heating process.

[0121] Step S1453: Construct a heat conduction model. The heat conduction model is based on the heat conduction characteristic parameters of the chip substrate and the relative position information between devices to simulate the heat conduction process in the chip and calculate the heat conduction rate data from the heat-generating point of the device to the surrounding area.

[0122] The thermal conductivity parameters of the chip substrate, such as thermal conductivity, determine the rate at which heat is conducted within the substrate. Thermal conduction models, based on Fourier's law and incorporating information about the relative positions of components, calculate the rate of heat transfer from high-temperature regions (heat-generating points) to low-temperature regions. For example, given the heat output and location of a component, as well as the thermal conductivity of the substrate, a thermal conduction model can calculate the rate of temperature change at different distances from the heat-generating point—this is the conduction rate data, which reflects how quickly heat propagates within the chip.

[0123] Step S1454: Construct a heat dissipation model. The heat dissipation model is based on the type information, location information, and heat dissipation capacity information of the thermal management structure. It simulates the heat dissipation process of the thermal management structure in the chip and calculates the heat dissipation data of the thermal management structure per unit time.

[0124] Different types of thermal management structures have different heat dissipation models. For microchannel heat dissipation structures, the model is based on fluid mechanics and heat exchange principles, calculating the heat carried away by the microchannels per unit time based on parameters such as location, channel size, and coolant flow rate (if liquid cooling). For finned heat sink structures, the model is based on thermal convection and radiation principles, calculating the heat dissipated to the surrounding environment per unit time based on parameters such as location, surface area, and surface emissivity. The output of the heat dissipation model is the heat dissipation data of the thermal management structure per unit time.

[0125] Step S1455: Integrate the heat generation model, heat conduction model, and heat dissipation model to form a complete thermal characteristic simulation subsystem.

[0126] The heat generation model simulates heat generation, the heat conduction model simulates heat transfer, and the heat dissipation model simulates heat dissipation. These three models are interconnected and together constitute a complete thermal characteristic simulation subsystem. During integration, data exchange interfaces need to be established between the models. For example, the heat generation data calculated by the heat generation model serves as input to the heat conduction model, and the internal chip temperature distribution data calculated by the heat conduction model serves as input to the heat dissipation model, ensuring that the entire process of heat generation, conduction, and dissipation can be continuously and accurately simulated.

[0127] Step S1456: Start the thermal characteristic simulation subsystem, set the simulation time step, and simulate the heat generation process, heat conduction process, and heat dissipation process of the photonic device during operation according to the preset time step.

[0128] The simulation time step needs to be determined based on the dynamic characteristics of the thermal process. A step that is too small will increase the computational load, while a step that is too large may reduce simulation accuracy. After starting the thermal characteristic simulation subsystem, the system gradually simulates the heat generation of the photonic device during operation, the heat conduction within the chip, and the heat dissipation process of the thermal management structure according to the preset time step. Within each time step, the temperature data at various locations on the chip is updated, and the heat flow is recorded.

[0129] Step S1457: Set up multiple thermal monitoring points in the simulation scene. The thermal monitoring points are evenly distributed in the chip area and include device surface monitoring points, substrate internal monitoring points, and thermal management structure surface monitoring points.

[0130] To gain a comprehensive understanding of the chip's thermal distribution, multiple thermal monitoring points are set up in the simulation scenario. These monitoring points are evenly distributed across different regions and locations on the chip. For example, monitoring points are set at the center of the surface of each photonic device, monitoring points are set at different depths within the chip substrate, and monitoring points are set on the surface of the thermal management structure. These monitoring points allow for real-time acquisition of the chip's temperature data during the simulation process.

[0131] Step S1458: Collect temperature data at each time step through thermal monitoring points, integrate the temperature data of different time steps and different monitoring points, and generate thermal distribution data.

[0132] During thermal characteristic simulation, after each time step, the thermal monitoring point collects the temperature value at the corresponding location. These temperature values ​​are then organized according to time sequence and spatial location, for example, with time as the horizontal axis and the monitoring point location as the vertical axis, to construct a temperature data matrix. By processing this matrix data, a temperature field distribution image of the chip at different times can be generated, i.e., thermal distribution data. This thermal distribution data visually demonstrates the spatial and temporal variation patterns of the chip temperature.

[0133] Step S1459: Based on the heat conduction rate data output by the heat conduction model, and combined with the distance data between different monitoring points, calculate the average, maximum, and minimum values ​​of heat conduction rate in different regions, and integrate them to form heat conduction rate data.

[0134] The heat conduction rate data output by the thermal conduction model are instantaneous values ​​at specific locations and times. Combined with distance data between different thermal monitoring points, the heat conduction rate between adjacent monitoring points is calculated. Then, statistical analysis is performed on the conduction rate across the entire chip area to calculate the average conduction rate, reflecting the overall conduction level. The maximum and minimum conduction rates are identified to determine the areas with the fastest and slowest heat conduction. These statistical results are then integrated to form complete thermal conduction rate data.

[0135] Step S14510: Based on the heat dissipation data output by the heat dissipation model and the heat generation data output by the heat generation model, calculate the heat dissipation efficiency, which is the ratio of heat dissipation to heat generation. Integrate the heat dissipation efficiency values ​​at different time steps to form heat dissipation efficiency data.

[0136] Heat dissipation efficiency is a crucial indicator of the performance of a thermal management structure. Within each time step, the heat dissipation data output by the heat generation model is divided by the heat generation data output by the heat generation model to obtain the heat dissipation efficiency at that time step. For example, if the heat generation is 10W and the heat dissipation is 8W within a certain time step, the heat dissipation efficiency is 0.8. Arranging the heat dissipation efficiency values ​​at different time steps in chronological order creates heat dissipation efficiency data, which can be used to analyze the changes in the heat dissipation performance of the thermal management structure during different operating stages.

[0137] Step S14511: Perform time-series processing on the heat distribution data, heat conduction rate data, and heat dissipation efficiency data, and arrange the data in the order of the simulation time step.

[0138] To facilitate subsequent analysis and comparison, the thermal distribution data, thermal conduction rate data, and heat dissipation efficiency data need to be time-series organized. Data of the same type are arranged according to the order of the simulation time steps to form time-series data. For example, after arranging the thermal distribution data in chronological order, the trend of chip temperature change over operating time can be clearly observed; the time-series arrangement of thermal conduction rate data and heat dissipation efficiency data can be used to analyze the dynamic characteristics of heat conduction and heat dissipation processes.

[0139] Step S14512: Store the processed heat distribution data, heat conduction rate data, and heat dissipation efficiency data into the thermal characteristic database, and simultaneously send them to the thermal characteristic analysis port of the cross-domain coupling control verification process.

[0140] The processed thermal characteristic data needs to be stored in a thermal characteristic database for subsequent querying, retrieval, and analysis. Simultaneously, this data is sent in real-time to the thermal characteristic analysis port of the cross-domain coupled control and verification processing system for comparison with the thermal distribution control elements in the multi-domain demand element set, to assess whether the current thermal characteristics meet the design requirements.

[0141] Step S146: The manufacturing process characteristic simulation subsystem simulates the process flow during manufacturing based on the system-level optimized device layout information, system-level optimized link planning information, and process adaptation labeling information, and collects process processing error data, process material adaptation data, and process environment impact data.

[0142] The manufacturing process characteristic simulation subsystem aims to predict the impact of actual manufacturing processes on layout schemes. Based on the geometric information of device arrangement and link planning, combined with the requirements of process adaptation annotations, it simulates key manufacturing processes from substrate preparation to packaging. In photolithography simulation, it simulates the exposure and development processes, predicting linewidth and sidewall shape deviations, i.e., critical dimensional deviations in process processing error data. In etching simulation, it simulates the interaction between plasma and materials, predicting etching depth and sidewall roughness. Process material adaptation data is obtained by analyzing the deviations of the composition, refractive index, resistivity, etc., of the deposited material from design requirements. Process environment impact data simulates the interference of environmental factors (such as temperature, humidity, and cleanliness) on process results, such as defects caused by dust and uneven film thickness caused by temperature fluctuations.

[0143] Step S147: Compare and adjust the signal attenuation data, signal transmission rate data, and signal interference data with the signal attenuation control elements in the multi-domain demand element set to generate signal transmission characteristic adaptation results.

[0144] The comparative control process compares the simulated signal transmission characteristic data with the required indicators to evaluate their suitability. Signal attenuation data is compared with the maximum allowable attenuation in the signal attenuation control elements to calculate the attenuation margin and determine whether the transmission distance requirement is met. Signal transmission rate data is compared with the minimum transmission rate requirement, and indicators such as eye diagram parameters and bit error rate are used to assess whether the actual transmission capability meets the standard. Signal interference data is compared with indicators such as crosstalk suppression ratio to analyze the impact of interference on signal quality. The generated signal transmission characteristic adaptation results include the measured values, required values, deviations, and satisfaction status (pass / fail) for each parameter. For failures, the reasons and potential impact on system performance must be analyzed.

[0145] Step S148: Compare and adjust the heat distribution data, heat conduction rate data, and heat dissipation efficiency data with the heat distribution control elements in the multi-domain demand element set to generate thermal characteristic adaptation results.

[0146] The generation of thermal characteristic adaptation results similarly compares thermal simulation data with thermal distribution control elements. The highest temperature in the thermal distribution data is compared with the device's maximum allowable temperature, and the temperature gradient is compared with the temperature distribution uniformity requirements. Thermal conduction rate data assesses how quickly heat is conducted from the heat source to the heat dissipation structure, and whether the heat can be removed in time. Heat dissipation efficiency data is compared with heat dissipation capacity requirements to determine whether the heat dissipation structure can meet the heat dissipation needs. Through these comparisons, thermal characteristic adaptation results are generated, including measured values, required values, deviations, satisfaction status, and impact analysis of non-compliance items at each temperature point, such as potential device wavelength drift and efficiency degradation due to excessively high temperatures.

[0147] Step S149: Compare and adjust the process processing error data, process material adaptation data, process environment impact data, process accuracy elements in the multi-domain requirement element set, and real-time collected manufacturing process parameters to generate manufacturing process characteristic adaptation results.

[0148] The manufacturing process characteristic adaptation results assess the manufacturability of the layout scheme. Processing error data is compared with critical dimensions and spacing requirements in the process accuracy elements to calculate indicators such as the process capability index (CPK) and determine whether the process can stably produce chips that meet the requirements. Process material adaptation data is compared with material characteristic requirements to analyze the impact of material parameter deviations on device performance. Process environmental impact data is compared with process environmental control parameters to assess the impact of environmental factors on manufacturing yield. The generated manufacturing process characteristic adaptation results include deviations of various process parameters, process capability assessment, material matching degree, and the degree of environmental impact.

[0149] Step S1410: Perform cross-domain coupling analysis on the signal transmission characteristic adaptation results, thermal characteristic adaptation results, and manufacturing process characteristic adaptation results, analyze the mutual influence relationship between signal transmission characteristics, thermal characteristics, and manufacturing process characteristics, identify the mutual constraint or promotion relationship between characteristics, and form a description of the influence relationship between characteristics.

[0150] In this embodiment, signal transmission characteristics and thermal characteristics interact with each other. Increased temperature leads to laser wavelength drift and modulator half-wave voltage changes, thus affecting signal transmission quality. Conversely, high-power signal transmission increases device power consumption, causing further temperature increases. Between thermal characteristics and manufacturing process characteristics, process deviations (such as uneven doping concentration) result in uneven device heating; temperature changes also affect material deposition and etching rates. Between signal transmission characteristics and manufacturing process characteristics, waveguide size deviations caused by the process alter the waveguide's effective refractive index and loss, affecting signal transmission loss and dispersion. By analyzing these interactions, we can identify which relationships are limiting (e.g., increased temperature limits signal quality) and which are promoting (e.g., good heat dissipation promotes signal stability), forming a description of the inter-characteristic influence relationships and revealing the root cause of cross-domain problems.

[0151] Step S1411: Based on the signal transmission characteristic adaptation results, thermal characteristic adaptation results, manufacturing process characteristic adaptation results, and description of the influence relationship between characteristics, generate characteristic adaptation control information. The characteristic adaptation control information includes a description of the degree of adaptation of each characteristic and control suggestions for the coupling influence between characteristics.

[0152] In this embodiment, the fit description is a summary evaluation of how well the characteristics of signal transmission, heat, and manufacturing process meet the requirements, based on the preceding fit results. The control suggestions for the coupling effects between characteristics address the identified mutual constraints by proposing improvement measures. For example, if increased temperature leads to increased signal crosstalk, the control suggestions might include optimizing the heat dissipation structure layout, reducing the power consumption of high-heat-generating devices, or adjusting the link path to reduce crosstalk in temperature-sensitive areas.

[0153] Step S1412: Based on the signal transmission characteristic adaptation results, thermal characteristic adaptation results, and manufacturing process characteristic adaptation results, determine whether each characteristic meets the requirements in the multi-domain demand element set, and generate characteristic compliance control information. The characteristic compliance control information includes a description of the compliance degree of each characteristic and the adjustment direction of non-compliant characteristics.

[0154] In this embodiment, the compliance level description quantifies the degree to which each characteristic meets the requirements, such as "signal transmission characteristics meet the requirements well, and link loss is less than the maximum allowable value of 0.5dB". For characteristics that do not meet the requirements, it is necessary to analyze the specific reasons and propose clear adjustment directions. For example, if the thermal characteristics do not meet the requirements, the adjustment direction may be "increasing the number of microchannel heat dissipation structures or optimizing their size to improve heat dissipation efficiency"; if the manufacturing process characteristics do not meet the requirements, the adjustment direction may be "modifying the design of critical dimensions and relaxing the requirements for a certain process parameter to improve the process capability index".

[0155] Step S1413: Integrate the feature adaptability control information and the feature compliance control information to generate a cross-domain coupling verification result. Supplement the missing feature coupling scenario description and the uncovered compliance judgment dimension description in the cross-domain coupling verification result, and store the supplemented cross-domain coupling verification result in the cross-domain verification result database.

[0156] In this embodiment, during the integration process, it is necessary to check for any omissions in characteristic coupling scenarios, such as the failure to analyze characteristic interactions under certain specific operating conditions, or the failure to consider certain compliance judgment dimensions, such as the impact of long-term reliability on characteristics. For any missing content, supplementary descriptions are required to ensure the comprehensiveness of the cross-domain coupling verification results. The supplemented results are stored in the cross-domain verification result database.

[0157] Step S150: Based on the cross-domain coupling verification results, perform feedback iteration processing. If both the characteristic adaptability control information and the characteristic compliance control information meet the preset control requirements, output the intermediate layout scheme as the final layout design scheme. Otherwise, feed the cross-domain coupling verification results back to the hierarchical collaborative optimization artificial intelligence model and re-execute the hierarchical collaborative optimization processing until a final layout design scheme that meets the preset control requirements is generated. The final layout design scheme includes precise arrangement information of photonic devices, optimized planning information of photonic connection links, integrated layout information of thermal management, and process adaptation annotation information.

[0158] In this embodiment, the preset control requirements are the criteria for judging whether the cross-domain coupling verification results are qualified. Typically, all key characteristics must meet the requirements, and the coupling effects between characteristics must be within an acceptable range. If the preset requirements are met, the intermediate layout scheme is confirmed as the final layout design scheme. This final layout design scheme includes precisely optimized device arrangement, link planning, thermal management layout, and detailed process adaptation annotations, which can be directly used to guide chip manufacturing. If the requirements are not met, the cross-domain coupling verification results (especially the adjustment direction of non-compliant characteristics and the control suggestions for the coupling effects between characteristics) are fed back to the hierarchical collaborative optimization artificial intelligence model. The model adjusts its optimization strategy and parameters based on this feedback information, re-executes the hierarchical collaborative optimization process, generates a new intermediate layout scheme, and performs cross-domain coupling verification again. This process is repeated until a final layout design scheme that meets the preset control requirements is generated.

[0159] Furthermore, the pre-training process of the hierarchical collaborative optimization AI model requires a large amount of historical layout design data and corresponding optimization results. Through supervised learning or reinforcement learning, the model learns the rules and strategies of layout optimization. The goal of pre-training is to enable the model to converge quickly and generate high-quality optimization solutions when faced with new layout problems.

[0160] Step S211: Collect historical project data for photonic integrated chip layout design. Each historical project data includes a set of multi-domain requirement elements, a set of dynamic constraints, an initial layout scheme, an optimized layout scheme, and cross-domain coupling verification results corresponding to the project, forming the original training dataset.

[0161] Historical project data serves as the knowledge source for pre-training. The collected data needs to comprehensively cover photonic integrated chip layout design projects of different types and application scenarios to ensure the model's generalization ability. Each project dataset should include complete requirements, constraints, initial layout, optimization results, and validation results, reflecting the entire layout design process and all possible scenarios. The size and quality of the original training dataset directly affect the performance of the pre-trained model; therefore, it is necessary to collect as much high-quality data as possible.

[0162] Step S212: Remove project data from the original training dataset that are missing multi-domain requirement elements, have conflicting dynamic constraint logic, or have incomplete cross-domain coupling verification results to obtain a valid training dataset.

[0163] To ensure training quality, the original training dataset needs to be cleaned. Data lacking multi-domain requirement elements cannot provide a clear optimization objective for the model; data with conflicting dynamic constraint logic can mislead the model into learning incorrect constraint relationships; and data with incomplete cross-domain coupling validation results cannot accurately evaluate the optimization effect. By removing these unqualified data, a valid training dataset is obtained, ensuring that the training samples input to the model are reliable and effective.

[0164] Step S213: Use the set of multi-domain demand elements, the set of dynamic constraints, and the initial layout scheme in the effective training dataset as the model input data, and the optimized layout scheme as the model output label. Divide the effective training dataset into a training subset, a validation subset, and a test subset according to a preset ratio.

[0165] The dataset is partitioned to facilitate model training, validation, and testing. Model input data includes a set of multi-domain requirement elements, a set of dynamic constraints, and an initial layout scheme; these serve as the conditions and starting point for model optimization. The output label is the optimized layout scheme, i.e., the target output the model expects to learn. Preset proportions are typically determined empirically, such as a 70% training subset, a 20% validation subset, and a 10% testing subset. The training subset is used to learn model parameters, the validation subset is used to evaluate model performance and adjust hyperparameters during training, and the testing subset is used to evaluate the model's generalization ability after training is complete.

[0166] Step S214: Initialize the network structure parameters of the hierarchical collaborative optimization artificial intelligence model. The network structure parameters include the encoding weight matrix of the element interaction layer, the sub-module optimization parameters of the hierarchical optimization layer, and the adaptation control threshold of the constraint adaptation layer. The sub-module optimization parameters include the device layer optimization parameters, the link layer optimization parameters, and the system layer optimization parameters.

[0167] In this embodiment, the encoding weight matrix of the element interaction layer determines the feature encoding method and importance, and needs to be randomly initialized or pre-trained embedding weights. The sub-module optimization parameters of the hierarchical optimization layer include the neural network weights, biases, learning rates, etc., in each sub-module (device layer, link layer, system layer), which control the direction and step size of the optimization process. The adaptation control threshold of the constraint adaptation layer is used to determine whether the optimization result satisfies the constraints; the initial value can be set empirically. Reasonable parameter initialization can accelerate model convergence and improve training efficiency.

[0168] Step S215: Input the model input data of the training subset into the initialized hierarchical collaborative optimization artificial intelligence model and perform forward propagation regulation processing.

[0169] Forward propagation modulation is the process by which the model processes the input data using current parameters and generates an output. In this process, the model's feature interaction layer encodes and interacts with the input requirements, constraints, and layout data, generating an interaction-fused feature tensor. The hierarchical optimization layer then performs device, link, and system-level optimization based on this feature tensor, generating a preliminary optimized layout scheme. The constraint adaptation layer checks and fine-tunes the optimized scheme based on constraints. The output of forward propagation is the model's optimization result for the current input data.

[0170] Step S216: In the element interaction layer, feature encoding is performed on the input multi-domain demand element set, dynamic constraint set, and initial layout scheme respectively to generate demand feature tensor, constraint feature tensor, and layout feature tensor. Then, cross-dimensional interaction fusion of demand feature tensor, constraint feature tensor, and layout feature tensor is performed to generate training interaction fusion feature tensor.

[0171] In the pre-trained feature interaction layer, the feature encoding process is similar to that in real-world applications, but uses training data. The demand feature tensor, constraint feature tensor, and layout feature tensor extract features from the demand, constraint, and layout data, respectively. Cross-dimensional interaction fusion integrates the information from these three tensors, enabling the model to simultaneously consider demand, constraints, and the current layout state. The training interaction fusion feature tensor is the product of this fusion process, containing comprehensive information to guide optimization.

[0172] Step S217: In the hierarchical optimization layer, the device layer optimization submodule optimizes the device arrangement information of the initial layout scheme based on the device features in the training interactive fusion feature tensor and the device class constraints in the dynamic constraint set, generating training device optimization information; the link layer optimization submodule optimizes the link planning information of the initial layout scheme based on the link features in the training interactive fusion feature tensor and the link class constraints in the dynamic constraint set, generating training link optimization information; the system layer optimization submodule performs system-level optimization on the training device optimization information, training link optimization information, and thermal management layout information of the initial layout scheme based on the system features in the training interactive fusion feature tensor and the system class constraints in the dynamic constraint set, generating training system-level optimization information.

[0173] The hierarchical optimization layer learns optimization strategies by processing training data during the pre-training phase. The device layer, link layer, and system layer optimization submodules optimize the device, link, and system-level layouts in the training data, respectively, generating corresponding training optimization information. During this process, the model adjusts the optimization parameters of these submodules to make the generated training system-level optimization information as close as possible to the output labels (optimized layout schemes) in the training data.

[0174] Step S218: In the constraint adaptation layer, the input dynamic constraint set is called to adjust the adaptation of the training system-level optimization information and generate training adaptation results; if the training adaptation results meet the constraint requirements, the training system-level optimization information is converted into a training optimization layout scheme as the output result of the model forward propagation.

[0175] The constraint adaptation layer also plays a role in constraint checking and adjustment during pre-training. The training adaptation results evaluate whether the system-level optimization information of the training data satisfies the dynamic constraint set in the training data. If it does, it is converted into a training optimization layout scheme as output; if it does not, fine-tuning may be performed or the penalty for constraint violation may be reflected in subsequent loss calculations.

[0176] Step S219: Calculate the degree of difference between the training optimization layout scheme output by the model and the corresponding model output labels in the training subset, generate training loss value, and adjust the network structure parameters of the hierarchical collaborative optimization artificial intelligence model through backpropagation algorithm to reduce the training loss value.

[0177] The training loss is a metric that measures the difference between the model's output and the expected output (label). It is typically calculated using loss functions such as mean squared error or cross-entropy. The backpropagation algorithm, based on the training loss, calculates the gradient of the parameters layer by layer, starting from the model's output layer, and uses optimization algorithms such as gradient descent to adjust the network structure parameters, making the model's output closer to the label. This is the core process of model learning: iteratively adjusting parameters to minimize the training loss.

[0178] Step S2110: Repeat the steps of inputting the training subset into the model, generating output results through forward propagation, calculating the training loss value, and adjusting parameters through backpropagation until the training loss value is reduced to the preset training threshold.

[0179] Pre-training is an iterative process. By repeatedly inputting a training subset into the model, performing forward propagation, calculating the loss, and backpropagation to adjust the parameters, the model's parameters are gradually optimized, and the training loss value continuously decreases. When the training loss value decreases to a preset training threshold (e.g., 0.01), it indicates that the model has achieved a good fit on the training data, and training on the training subset can be stopped.

[0180] Step S2111: Input the model input data of the validation subset into the hierarchical collaborative optimization artificial intelligence model after parameter adjustment, perform forward propagation control processing, generate a validation optimization layout scheme, calculate the degree of difference between the validation optimization layout scheme and the corresponding model output labels in the validation subset, and generate a validation loss value.

[0181] The validation process monitors the model's overfitting and generalization ability. A validation subset is input into the trained model to generate an optimized validation layout, and the difference between this layout and the validation labels (validation loss) is calculated. If the validation loss increases with the number of training iterations, it indicates that the model may be overfitting, requiring adjustments to the model structure or regularization parameters.

[0182] Step S2112: If the verification loss value is higher than the preset verification threshold, the model is trained using the training subset, and the network structure parameters are adjusted; if the verification loss value is lower than the preset verification threshold, the model input data of the test subset is input into the hierarchical collaborative optimization artificial intelligence model, and forward propagation control processing is performed to generate a test optimization layout scheme.

[0183] A preset validation threshold is used to determine whether the model meets the requirements on the validation set. If the validation loss value is higher than the threshold, it indicates that the model performance still needs improvement, and further training with a subset of the training set and parameter tuning are required. If it is lower than the threshold, the model performs well on the validation set and can be tested. The testing process is similar to validation, using a subset of the test set to evaluate the model's final performance.

[0184] Step S2113: Calculate the degree of difference between the test optimization layout scheme and the corresponding model output labels in the test subset, generate the test loss value. If the test loss value is lower than the preset test threshold, the pre-training of the hierarchical collaborative optimization artificial intelligence model is completed, and the network structure parameters after pre-training are saved. If the test loss value is higher than the preset test threshold, return to the training step, increase the number of training iterations, adjust the adjustment range of the network structure parameters, and re-execute the training process until the test loss value meets the preset requirements.

[0185] The test loss value is the final evaluation metric for the model's generalization ability. If the test loss value is lower than the preset test threshold, it means the model performs well on unseen test data, pre-training is complete, and the model parameters are saved for practical applications. If the test loss value is higher than the threshold, the model's generalization ability is insufficient, and it is necessary to go back to the training step, increase the number of training iterations, or adjust parameters such as the learning rate, and retrain the model until the test loss value meets the requirements.

[0186] Furthermore, the set of dynamic constraints is not static. As manufacturing processes change, requirements are adjusted, or new problems are discovered, it needs to be updated to ensure that layout optimization is always based on the latest conditions and requirements.

[0187] For example, step S311: Real-time monitoring of changes in manufacturing process parameters. When any one of the process accuracy parameters, process material characteristic parameters, or process environment control parameters changes beyond the preset fluctuation range, dynamic constraint updates are triggered.

[0188] The preset fluctuation range is a threshold for judging whether process parameters have changed significantly, determined based on process stability and historical data. The real-time monitoring system continuously tracks various manufacturing process parameters. When the change of a parameter exceeds the preset range, such as a sudden increase in photolithography overlay error, it indicates that the manufacturing process status has changed, which may affect the manufacturability of the layout scheme. At this time, dynamic constraint updates need to be triggered.

[0189] Step S312: Based on the changed manufacturing process parameters, recalculate the process parameter adaptation range corresponding to each element dimension in the element dimension decomposition list, and update the element process association table.

[0190] The core of dynamic constraint updates is to adjust the relationship between elements and processes based on new process parameters. Based on the changed manufacturing process parameters, the sensitivity and adaptation range of each element dimension in the element dimension decomposition list to the process parameters are re-analyzed, and the adaptation range and association strength values ​​of the process parameters in the element-process association table are updated.

[0191] Step S313: Based on the updated element process association table, reconstruct the constraint association matrix, perform constraint conflict resolution processing, and generate the updated constraint association matrix.

[0192] Using the updated element process association table, the constraint association matrix is ​​reconstructed, and constraint conflict resolution is performed to ensure that there are no logical conflicts in the new constraint association matrix and that it can reflect the true relationship between elements and process parameters under the current process conditions.

[0193] Step S314: Based on the updated constraint association matrix, regenerate the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints.

[0194] Based on the updated constraint correlation matrix, various constraints are regenerated using a method similar to that used for the initial constraint generation, ensuring that the constraint conditions are adapted to the changed manufacturing process parameters.

[0195] Step S315: Integrate the association constraints of the newly generated multi-domain requirement elements and layout elements, the coordination constraints between layout elements, and the process parameter adaptation constraints, and replace the original dynamic constraint set to form an updated dynamic constraint set.

[0196] The newly generated constraints are integrated into an updated set of dynamic constraints, replacing the original set of dynamic constraints, so that subsequent layout optimization processes use the latest constraints.

[0197] Step S316: Store the updated set of dynamic constraints in the dynamic constraint database and send it to the hierarchical collaborative optimization artificial intelligence model for hierarchical collaborative optimization processing.

[0198] The updated set of dynamic constraints is stored in the database and sent to the hierarchical collaborative optimization AI model in a timely manner to ensure that the model can use the latest constraint information and adapt to changes in manufacturing processes when performing layout optimization.

[0199] In one exemplary embodiment, an AI-based photonic integrated chip layout design system is provided. This AI-based photonic integrated chip layout design system can be a terminal, server, etc., and its internal structure diagram can be as follows: Figure 2 As shown, this AI-based photonic integrated chip layout design system includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computational and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, near-field communication, or other technologies. When the computer program is executed by the processor, it implements an AI-based photonic integrated chip layout design method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device can be a touch layer covering the display screen, or a button, trackball, or touchpad set on the housing of an AI-based photonic integrated chip layout design system, or an external keyboard, touchpad, or mouse, etc.

[0200] It should be noted that, in order to simplify the description of the present invention and thus help to understand one or more embodiments of the invention, multiple features may sometimes be grouped into one embodiment, drawing or description thereof in the foregoing description of the embodiments of the present invention.

Claims

1. A photonic integrated chip layout design method based on artificial intelligence, characterized in that, The method includes: Multi-domain requirement elements are extracted from the application scenario requirements, functional implementation requirements, signal transmission requirements, manufacturing process requirements, and thermal management requirements of photonic integrated chips to generate a multi-domain requirement element set. Based on the set of multi-domain demand elements and the manufacturing process parameters collected in real time, a dynamic constraint generation mechanism is constructed to generate a dynamic constraint set. The pre-trained hierarchical collaborative optimization artificial intelligence model is invoked, and the initial layout scheme of the photonic integrated chip is subjected to hierarchical collaborative optimization processing in combination with the dynamic constraint set to generate an intermediate layout scheme. The intermediate layout scheme is subjected to cross-domain coupling control verification processing of layout and signal transmission characteristics, thermal characteristics and manufacturing process characteristics to obtain cross-domain coupling verification results; Based on the cross-domain coupling verification results, feedback iterative processing is performed. If both the characteristic adaptability control information and the characteristic compliance control information meet the preset control requirements, the intermediate layout scheme is output as the final layout design scheme. Otherwise, the cross-domain coupling verification results are fed back to the hierarchical collaborative optimization artificial intelligence model, and the hierarchical collaborative optimization processing is re-executed until a final layout design scheme that meets the preset control requirements is generated. The final layout design scheme includes precise arrangement information of photonic devices, optimized planning information of photonic connection links, integrated layout information of thermal management, and process adaptation annotation information. The step of performing feedback iteration processing based on the cross-domain coupling verification result includes: Extract characteristic adaptability control information and characteristic compliance control information from the cross-domain coupling verification results, analyze the specific content that does not meet the preset control requirements, classify the specific content that does not meet the preset control requirements, divide the problem categories according to the characteristic domains involved, the characteristic domains include signal transmission characteristic domain, thermal characteristic domain, and manufacturing process characteristic domain, and generate a problem classification list. For each specific problem in each problem category, the root cause of the problem is analyzed, and based on the root cause analysis results, the corresponding adjustment direction is determined. The adjustment direction is then converted into feedback parameters that can be recognized by the hierarchical collaborative optimization artificial intelligence model. The feedback parameters include the type of layout element to be adjusted, the suggested adjustment range, and the adjustment priority. The layout element type includes device arrangement elements, link planning elements, and thermal management layout elements. The feedback parameters are input into the parameter adjustment module of the hierarchical collaborative optimization artificial intelligence model, and the parameter adjustment module updates the optimization target weights and constraint adaptation thresholds of the model based on the feedback parameters. The hierarchical collaborative optimization artificial intelligence model with updated parameters is invoked, the dynamic constraint set and the intermediate layout scheme of the previous round are re-inputted, the hierarchical collaborative optimization process is executed, a new intermediate layout scheme is generated, and the cross-domain coupling control verification process is re-executed on the new intermediate layout scheme to obtain the new cross-domain coupling verification result. Analyze the results of the new round of cross-domain coupling verification to determine whether the characteristic adaptability control information and the characteristic compliance control information meet the preset control requirements; If the preset control requirements are met, the feedback iteration process is stopped, and the new intermediate layout scheme is determined as the final layout design scheme to be output; if the preset control requirements are not met, the steps of problem analysis, classification, root cause analysis, adjustment direction determination, feedback parameter generation, model parameter update, optimization processing, and verification processing are repeated until an intermediate layout scheme that meets the preset control requirements is generated. Record the processing of each round of feedback iteration, including feedback parameters, model parameter adjustment content, optimization results, and verification results, generate an iteration process record document, and store it in the iteration database.

2. The photonic integrated chip layout design method based on artificial intelligence according to claim 1, characterized in that, The dynamic constraint generation mechanism, based on the multi-domain demand element set and the real-time collected manufacturing process parameters, generates a dynamic constraint set, including: Extract scenario adaptation elements, function implementation elements, signal attenuation control elements, process accuracy elements, and heat distribution control elements from the multi-domain requirement element set. Decompose each element into element dimensions to form an element dimension decomposition list. The element dimension decomposition list includes the core indicators of the element, the scope of influence of the indicator, and the associated objects of the indicator. Real-time acquisition of manufacturing process parameters, including process machining accuracy parameters, process material property parameters, and process environment control parameters; The correlation analysis is performed on each element dimension in the element dimension decomposition list and the manufacturing process parameters collected in real time to determine the process parameter adaptation range corresponding to each element dimension and generate an element process correlation table. Based on the aforementioned element process association table, a constraint association matrix is ​​constructed. The row dimension of the constraint association matrix is ​​the multi-domain requirement element dimension, the column dimension is the manufacturing process parameter dimension, and the matrix elements are the association strength values ​​between the element dimension and the process parameter. The constraint association matrix is ​​subjected to constraint conflict resolution processing. Conflict terms whose association strength values ​​exceed a preset threshold are identified. For each conflict term, the historical constraint resolution case library is called to extract resolution strategies for similar cases. Based on the extracted resolution strategy and combined with the priority of the current multi-domain demand elements, constraint adjustment processing is performed on the conflict items to generate an adjusted constraint correlation matrix. Based on the adjusted constraint correlation matrix, the correlation constraints between multi-domain requirement elements and layout elements are generated. The correlation constraints include the constraints between scene adaptation elements and device arrangement density, the constraints between function implementation elements and device type adaptation, the constraints between signal attenuation control elements and link length, the constraints between process accuracy elements and device spacing, and the constraints between heat distribution control elements and device heat dissipation spacing. The interrelationships between layout elements are analyzed to generate collaborative constraints among layout elements. These collaborative constraints include collaborative constraints between device arrangement density and link planning path, collaborative constraints between device type and process material characteristics, and collaborative constraints between link length and heat distribution control. The manufacturing process parameters collected in real time are converted into process parameter adaptation constraints. The process parameter adaptation constraints include layout error allowable constraints corresponding to process processing accuracy parameters, device material adaptation constraints corresponding to process material characteristic parameters, and layout environment adaptation constraints corresponding to process environment control parameters. The association constraints between the multi-domain demand elements and layout elements, the coordination constraints between layout elements, and the process parameter adaptation constraints are integrated to generate a dynamic constraint set. The executability of each constraint is tested by simulating layout scenarios. Unexecutable constraints are removed, and constraint items corresponding to missing constraint scenarios are added to form the final dynamic constraint set. The final dynamic constraint set is then stored in the dynamic constraint database.

3. The photonic integrated chip layout design method based on artificial intelligence according to claim 1, characterized in that, The process of invoking a pre-trained hierarchical collaborative optimization artificial intelligence model, combined with the dynamic constraint set, to perform hierarchical collaborative optimization processing on the initial layout scheme of the photonic integrated chip, generates an intermediate layout scheme, including: Obtain an initial layout scheme for the photonic integrated chip, the initial layout scheme including preliminary photonic device arrangement information, preliminary photonic connection link planning information, and preliminary thermal management layout information; Extract the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints from the dynamic constraint set. Then, convert the association constraints between multi-domain demand elements and layout elements, the collaborative constraints between layout elements, and the process parameter adaptation constraints into a constraint input data format that can be recognized by the hierarchical collaborative optimization artificial intelligence model. The photonic device arrangement information, photonic connection link planning information, and thermal management layout information in the initial layout scheme are converted into a layout input data format that can be recognized by the hierarchical collaborative optimization artificial intelligence model; The constraint input data format and the layout input data format are simultaneously input into the element interaction layer of the hierarchical collaborative optimization artificial intelligence model. The associated constraints, collaborative constraints, and process parameter adaptation constraints in the constraint input data format are subjected to constraint feature encoding processing to generate constraint feature tensors. The device layout information, link planning information, and thermal management layout information in the layout input data format are subjected to layout feature encoding processing to generate layout feature tensors. Cross-dimensional interactive fusion processing of constraint feature tensor and layout feature tensor is performed to generate interactive fusion feature tensor. The interactive fusion feature tensor is then input into the hierarchical optimization layer of the hierarchical collaborative optimization artificial intelligence model. The hierarchical optimization layer includes device layer optimization submodule, link layer optimization submodule and system layer optimization submodule. The device layer optimization submodule optimizes the photonic device arrangement information in the initial layout scheme based on the device-related features in the interactive fusion feature tensor and the device class constraints in the dynamic constraint set, generating optimized device arrangement information. The optimization process includes device position adjustment, device type adaptation adjustment, and device spacing adjustment. The link layer optimization submodule optimizes the photon connection link planning information in the initial layout scheme based on the link-related features in the interactive fusion feature tensor and the link class constraints in the dynamic constraint set, generating optimized link planning information. The optimization process includes link path adjustment, link material adaptation adjustment, and link length adjustment. The system-level optimization submodule, based on system-related features in the interactive fusion feature tensor and combined with system class constraints in the dynamic constraint set, performs system-level collaborative adjustment processing on the optimized device layout information and optimized link planning information. At the same time, it optimizes the thermal management layout information in the initial layout scheme, and generates system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information. The system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information are input into the constraint adaptation layer of the hierarchical collaborative optimization artificial intelligence model. The constraint adaptation layer calls all constraint contents in the dynamic constraint set to perform adaptive adjustment processing on the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information, and generates adaptive adjustment results; If the adaptation control results show that the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information meet all constraints, then the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information will be integrated to generate an intermediate layout scheme. If the adaptation control results show that the system-level optimized device layout information, system-level optimized link planning information, and system-level optimized thermal management layout information do not meet some constraints, the unmet constraints will be fed back to the hierarchical optimization layer, and the device layer optimization, link layer optimization, and system layer optimization steps will be re-executed to adjust the optimization direction and optimization range. Repeat the hierarchical optimization and constraint adaptation control steps until system-level optimization information that satisfies all constraints is generated, and then integrate it into a preliminary intermediate layout scheme. The preliminary intermediate layout scheme is optimized and controlled. The degree of satisfaction of the multi-domain requirements corresponding to the preliminary intermediate layout scheme is calculated. The degree of satisfaction includes the degree of satisfaction of scene adaptation, the degree of satisfaction of function implementation, the degree of satisfaction of signal attenuation control, the degree of satisfaction of process accuracy, and the degree of satisfaction of heat distribution control. If the satisfaction level reaches the preset optimization threshold, the preliminary intermediate layout scheme is determined as the intermediate layout scheme; if the satisfaction level does not reach the preset optimization threshold, the satisfaction level analysis results are fed back to the element interaction layer, and the feature encoding, cross-dimensional interaction fusion, and hierarchical optimization steps are re-executed, and the interaction fusion strategy and hierarchical optimization parameters are adjusted until an intermediate layout scheme with a satisfaction level reaching the preset optimization threshold is generated.

4. The photonic integrated chip layout design method based on artificial intelligence according to claim 1, characterized in that, The cross-domain coupling control verification process for the intermediate layout scheme, involving layout and signal transmission characteristics, thermal characteristics, and manufacturing process characteristics, yields cross-domain coupling verification results, including: Extract system-level optimized device layout information, system-level optimized link planning information, system-level optimized thermal management layout information, and process adaptation annotation information from the intermediate layout scheme; Based on the system-level optimized device layout information, system-level optimized link planning information, and process adaptation annotation information, a simulation scenario of the cross-domain characteristics of photonic integrated chips is constructed. In the simulation scenario, the actual layout position of photonic devices, the relative distance between devices, the actual direction of the connection links, and the process implementation scenario corresponding to the process adaptation annotation are restored. In the cross-domain characteristic simulation scenario, a signal transmission characteristic simulation subsystem, a thermal characteristic simulation subsystem, and a manufacturing process characteristic simulation subsystem are constructed. The signal transmission characteristic simulation subsystem constructs a photonic signal transmission simulation link based on the system-level optimized link planning information, generates a photonic signal that meets the signal characteristic requirements in the multi-domain requirement element set, inputs the photonic signal into the simulation link, simulates the transmission process of the photonic signal in the link, and collects signal attenuation data, signal transmission rate data, and signal interference data during the transmission process. The thermal characteristic simulation subsystem simulates the heat generation process of photonic devices, the heat conduction process within the chip, and the heat dissipation process of the thermal management structure during operation, based on the system-level optimized device layout information and system-level optimized thermal management layout information, and collects heat distribution data, heat conduction rate data, and heat dissipation efficiency data. The manufacturing process characteristic simulation subsystem simulates the process flow during manufacturing based on system-level optimized device layout information, system-level optimized link planning information, and process adaptation labeling information, and collects process processing error data, process material adaptation data, and process environment impact data. The signal attenuation data, signal transmission rate data, and signal interference data are compared and adjusted with the signal attenuation control elements in the multi-domain demand element set to generate signal transmission characteristic adaptation results. The heat distribution data, heat conduction rate data, and heat dissipation efficiency data are compared and adjusted with the heat distribution control elements in the multi-domain demand element set to generate thermal characteristic adaptation results. The process error data, process material adaptation data, process environment impact data, process accuracy elements in the multi-domain requirement element set, and real-time collected manufacturing process parameters are compared and adjusted to generate manufacturing process characteristic adaptation results. Cross-domain coupling analysis is performed on the signal transmission characteristic adaptation results, thermal characteristic adaptation results, and manufacturing process characteristic adaptation results to analyze the mutual influence relationship between signal transmission characteristics, thermal characteristics, and manufacturing process characteristics, identify the mutual constraint or promotion relationship between characteristics, and form a description of the influence relationship between characteristics. Based on the signal transmission characteristic adaptation results, thermal characteristic adaptation results, manufacturing process characteristic adaptation results, and description of the influence relationship between characteristics, characteristic adaptation control information is generated. The characteristic adaptation control information includes a description of the degree of adaptation of each characteristic and control suggestions for the coupling influence between characteristics. Based on the signal transmission characteristic adaptation results, thermal characteristic adaptation results, and manufacturing process characteristic adaptation results, it is determined whether each characteristic meets the requirements of the multi-domain demand element set, and characteristic compliance control information is generated. The characteristic compliance control information includes a description of the compliance degree of each characteristic and the adjustment direction of non-compliant characteristics. The feature adaptability control information and the feature compliance control information are integrated to generate cross-domain coupling verification results. The missing feature coupling scenario descriptions and uncovered compliance judgment dimension descriptions in the cross-domain coupling verification results are supplemented, and the supplemented cross-domain coupling verification results are stored in the cross-domain verification result database.

5. The photonic integrated chip layout design method based on artificial intelligence according to claim 3, characterized in that, The pre-training process of the hierarchical collaborative optimization artificial intelligence model includes: Collect historical project data on the layout design of photonic integrated chips. Each historical project data includes a set of multi-domain requirement elements, a set of dynamic constraints, an initial layout scheme, an optimized layout scheme, and cross-domain coupling verification results, forming the original training dataset. By removing project data from the original training dataset that are missing multi-domain requirement elements, have conflicting dynamic constraint logic, or have incomplete cross-domain coupling verification results, an effective training dataset is obtained. The set of multi-domain demand elements, the set of dynamic constraints, and the initial layout scheme in the effective training dataset are used as the model input data, and the optimized layout scheme is used as the model output label. The effective training dataset is divided into a training subset, a validation subset, and a test subset according to a preset ratio. The network structure parameters of the hierarchical collaborative optimization artificial intelligence model are initialized. The network structure parameters include the encoding weight matrix of the element interaction layer, the sub-module optimization parameters of the hierarchical optimization layer, and the adaptation control threshold of the constraint adaptation layer. The sub-module optimization parameters include the device layer optimization parameters, the link layer optimization parameters, and the system layer optimization parameters. The model input data of the training subset is input into the initialized hierarchical collaborative optimization artificial intelligence model, and forward propagation regulation processing is performed; In the element interaction layer, the input multi-domain demand element set, dynamic constraint set, and initial layout scheme are respectively feature encoded to generate demand feature tensor, constraint feature tensor, and layout feature tensor. Then, cross-dimensional interaction fusion of demand feature tensor, constraint tensor, and layout feature tensor is performed to generate training interaction fusion feature tensor. In the hierarchical optimization layer, the device layer optimization submodule optimizes the device arrangement information of the initial layout scheme based on the device features in the training interactive fusion feature tensor and the device class constraints in the dynamic constraint set, generating training device optimization information; the link layer optimization submodule optimizes the link planning information of the initial layout scheme based on the link features in the training interactive fusion feature tensor and the link class constraints in the dynamic constraint set, generating training link optimization information; the system layer optimization submodule performs system-level optimization on the training device optimization information, training link optimization information, and thermal management layout information of the initial layout scheme based on the system features in the training interactive fusion feature tensor and the system class constraints in the dynamic constraint set, generating training system-level optimization information. In the constraint adaptation layer, the input dynamic constraint set is invoked to adapt the training system-level optimization information and generate training adaptation results. If the training adaptation results meet the constraint requirements, the training system-level optimization information is converted into a training optimization layout scheme, which is used as the output of the model forward propagation. The degree of difference between the training optimization layout scheme output by the calculation model and the corresponding model output labels in the training subset is used to generate a training loss value. Based on the training loss value, the network structure parameters of the hierarchical collaborative optimization artificial intelligence model are adjusted through the backpropagation algorithm to reduce the training loss value. Repeat the steps of inputting a training subset into the model, controlling the output results through forward propagation, calculating the training loss value, and adjusting the parameters through backpropagation until the training loss value is reduced to the preset training threshold. The model input data of the validation subset is input into the hierarchical collaborative optimization artificial intelligence model with adjusted parameters, and forward propagation control processing is performed to generate a validation optimization layout scheme. The degree of difference between the validation optimization layout scheme and the corresponding model output label in the validation subset is calculated to generate a validation loss value. If the verification loss value is higher than the preset verification threshold, the training subset is used to continue training the model and the network structure parameters are adjusted; if the verification loss value is lower than the preset verification threshold, the model input data of the test subset is input into the hierarchical collaborative optimization artificial intelligence model, forward propagation regulation processing is performed, and a test optimization layout scheme is generated. The degree of difference between the test optimization layout scheme and the corresponding model output label in the test subset is calculated, and a test loss value is generated. If the test loss value is lower than the preset test threshold, the pre-training of the hierarchical collaborative optimization artificial intelligence model is completed, and the network structure parameters after pre-training are saved. If the test loss value is higher than the preset test threshold, the process returns to the training step, the number of training iterations is increased, the adjustment range of the network structure parameters is adjusted, and the training process is re-executed until the test loss value meets the preset requirements.

6. The photonic integrated chip layout design method based on artificial intelligence according to claim 3, characterized in that, The initial layout scheme for obtaining the photonic integrated chip includes: Based on the functional implementation elements in the multi-domain requirement element set, determine the types and quantities of photonic devices required for the photonic integrated chip, and generate a device list. Based on the minimum device spacing and minimum device size requirements in the process accuracy elements, the device arrangement area is divided within the chip layout area; The photonic devices in the device list are grouped according to their functional relationships, and devices in the same functional group are assigned to adjacent layout areas; Based on the link length limitation in the signal transmission characteristics requirements, the photonic connection link routes between devices in each functional group are planned, and a preliminary link planning diagram is generated. Adjust the device arrangement position based on the device heat dissipation spacing requirements in the heat distribution control elements; By integrating device layout information, link planning diagram, and heat dissipation space allocation information, preliminary photonic device layout information and preliminary photonic connection link planning information are generated. Based on thermal management requirements, preliminary thermal management structure locations are planned in densely populated areas and around devices whose heat generation power exceeds a preset threshold, generating preliminary thermal management layout information. By integrating preliminary photonic device layout information, preliminary photonic connection link planning information, and preliminary thermal management layout information, an initial layout scheme for the photonic integrated chip is formed.

7. The photonic integrated chip layout design method based on artificial intelligence according to claim 1, characterized in that, The process involves extracting multi-domain requirement elements from the application scenario requirements, functional implementation requirements, signal transmission requirements, manufacturing process requirements, and thermal management requirements of photonic integrated chips, generating a multi-domain requirement element set, including: Determine the target application scenarios, core functional modules, and performance requirements of the photonic integrated chip; Based on the target application scenario, the environmental adaptability requirements of the scenario to the chip are analyzed. The environmental adaptability requirements include temperature adaptability range, humidity adaptability range, and anti-interference capability requirements. The environmental adaptability requirements of the scenario to the chip are converted into the core indicators of the scenario adaptation elements, forming the initial draft of the scenario adaptation elements. Based on the core functional modules, the implementation requirements of each functional module are broken down. The implementation requirements include the type of photonic device, the number of devices, and the functional relationship between devices corresponding to the functional module. The implementation requirements of each functional module are converted into the core indicators of the functional implementation elements, forming the initial draft of the functional implementation elements. Based on performance requirements, performance parameters related to signal transmission are extracted. These performance parameters include the maximum allowable signal attenuation, the minimum signal transmission rate, and the signal anti-interference level. The performance parameters related to signal transmission are converted into the core indicators of signal attenuation control elements, forming a draft of signal attenuation control elements. The technical level of the current manufacturing process is obtained, and the achievable processing accuracy of the process is determined. The processing accuracy includes the minimum device size, the minimum device spacing, and the allowable range of link processing error. The achievable processing accuracy indicators are converted into the core indicators of the process accuracy elements, forming the initial draft of the process accuracy elements. Analyze the heat generation characteristics of photonic devices during operation, and combine them with the overall thermal management requirements of the chip to determine the relevant parameters for heat distribution control. These parameters include the maximum allowable temperature of the device, the uniformity requirements of the overall temperature distribution of the chip, and the heat dissipation capacity requirements of the thermal management structure. Transform these parameters into the core indicators of the heat distribution control elements to form a draft of the heat distribution control elements. Cross-validation processing is performed on the initial drafts of scene adaptation elements, function implementation elements, signal attenuation control elements, process accuracy elements, and heat distribution control elements to identify requirement conflicts between different initial drafts. Based on the preset conflict resolution rules, the core indicators of conflicting elements are automatically adjusted to eliminate conflicting content and form adjusted versions of each element. The missing core indicators in each adjusted version of each element are supplemented to ensure that the core indicators of each element cover all dimensions of the corresponding requirement. The supplemented scenario adaptation elements, function implementation elements, signal attenuation control elements, process accuracy elements, and heat distribution control elements are integrated to generate a multi-domain requirement element set. Each element in the multi-domain requirement element set is given a priority label. The priority of each element is marked according to its criticality to the chip function implementation and its performance impact. The multi-domain requirement element set with the priority is stored in the requirement database and sent to the requirement input port of the dynamic constraint generation mechanism.

8. A photonic integrated chip layout design system based on artificial intelligence, characterized in that, include: processor; A machine-readable storage medium for storing machine-executable instructions of the processor; The processor is configured to execute the AI-based photonic integrated chip layout design method according to any one of claims 1 to 7 by executing the machine-executable instructions.

9. A computer program product, characterized in that, The computer program product includes machine-executable instructions stored in a computer-readable storage medium. The processor of the AI-based photonic integrated chip layout design system reads the machine-executable instructions from the computer-readable storage medium and executes the machine-executable instructions, causing the AI-based photonic integrated chip layout design system to perform the AI-based photonic integrated chip layout design method as described in any one of claims 1 to 7.

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