Chip-based electrical property test method, system and device

Abstract

The invention relates to the technical field of chip testing, in particular to an electrical property testing method, system and device based on a chip. According to the method, an auxiliary excitation coil is deployed around a to-be-detected chip silicon through hole array to generate a compensation magnetic field, the compensation magnetic field and an eddy current magnetic field are superposed to form an elliptically polarized magnetic field, a magnetic field sensor captures a long axis direction to extract real phase information of an original current magnetic field, and phase offset is dynamically compensated based on the phase information. And outputting the reconstructed current waveform, and finally identifying the chip defect according to the reconstructed current waveform. According to the method, the compensation magnetic field is generated by deploying the auxiliary excitation coil, the magnetic field sensor, the dynamic eddy current transfer function model and the like are combined, the current waveform is reconstructed to identify the defects, and high-precision detection and positioning of the defects such as chip micro short circuit are achieved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically, to a chip electrical testing method, system, and apparatus. Background Technology

[0002] In a three-dimensional stacked chip, when a high-frequency operating current or test current flows through a conductive structure such as a through-silicon via (TSV), according to Ampere's law, this current naturally generates a magnetic field surrounding the conductor. This magnetic field, directly generated by the current being measured, is called the primary current magnetic field. However, when a high-frequency current flows through a conductor, it induces the skin effect, causing charges to accumulate on the conductor's surface, thereby inducing closed-loop eddy currents inside the conductor. These eddy currents also generate a magnetic field, which is the primary eddy current magnetic field.

[0003] The key issue is that the original eddy current magnetic field lags behind the original current magnetic field, resulting in a significant phase difference between the two and causing severe distortion of the true waveform of the original current magnetic field. Furthermore, in the three-dimensional stacked architecture, the dense array of through-silicon vias amplifies crosstalk interference through electromagnetic induction, while interlayer parasitic effects further distort the magnetic field synchronization relationship. These factors collectively exacerbate the phase shift intensity of the original eddy current magnetic field.

[0004] When a chip has a micro-short-circuit defect (such as a local low-resistance path caused by manufacturing residues), the change in current distribution in the defect area will be reflected in the weak fluctuations of the original current magnetic field. However, due to the strong phase shift noise of the original eddy current magnetic field, the original current magnetic field is severely distorted. Traditional detection methods (such as differential methods and magnetic shielding methods) cannot accurately extract this weak signal, making it difficult to reliably identify and locate micro-short-circuit defects. Summary of the Invention

[0005] The purpose of this invention is to provide a chip electrical testing method, system and device to solve the problem of unstable detection of micro short circuit defects caused by phase shift during high-frequency current detection in three-dimensional stacked chips.

[0006] To achieve the above objectives, a chip electrical testing method is provided, comprising:

[0007] The chip under test obtains its original current magnetic field and original eddy current magnetic field under a high-frequency current environment;

[0008] An auxiliary excitation coil is deployed around the through-silicon via array of the chip under test;

[0009] Magnetic field sensor;

[0010] The steps include:

[0011] S1. A compensation magnetic field is generated based on the auxiliary excitation coil. The compensation magnetic field and the original eddy current magnetic field are superimposed to form an elliptical polarized magnetic field. The compensation magnetic field and the original eddy current magnetic field have the same frequency and a phase difference of 90°.

[0012] S2. The magnetic field sensor captures the major axis direction of the elliptical polarized magnetic field and extracts the true phase information of the original current magnetic field.

[0013] S3. Dynamically compensate for the phase offset based on the real phase information and output the reconstructed current waveform;

[0014] S4. Identify chip defects based on the reconstructed current waveform.

[0015] In the above technical solution, in step S1, a specific magnetic field environment is actively constructed to create conditions for the subsequent extraction of real phase information, so that the complex interference magnetic field is transformed into an analyzable elliptic polarization morphology.

[0016] In step S2, based on the characteristics of elliptical polarized magnetic field, its major axis direction is closely related to the true phase of the original current magnetic field. By capturing the major axis direction through a magnetic field sensor, the true phase of the original current magnetic field can be accurately extracted, and the essential characteristics of the current magnetic field can be explored from a physical perspective, laying the foundation for accurately restoring the current waveform.

[0017] In step S3, the eddy current interference component is stripped off based on the complex plane phase rotation principle, the nonlinear coupling effect between the original current magnetic field and the original eddy current magnetic field is decoupled, the electromagnetic field information is converted into an analyzable electrical signal, and the extracted phase information is converted into a reconstructed current waveform through a dynamic compensation mechanism.

[0018] In step S4, based on electrical principles, chip defects cause abnormal current distribution and conduction, which is reflected in the current waveform. Identifying defects based on the reconstructed current waveform transforms the detection at the magnetic field level into a judgment of the chip's electrical performance defects, forming a complete logical closed loop from magnetic field intervention and information extraction to defect identification.

[0019] Based on this, the dynamic compensation is achieved through a dynamic eddy current transfer function model, which is as follows: in:

[0020] H(ω,T) is the dynamic eddy current transfer function, which reflects the transfer characteristics of the eddy current magnetic field at different frequencies and temperatures;

[0021] B signal (ω,T) represents the target magnetic field component carrying the phase information of the original current magnetic field;

[0022] B meas(ω,T) represents the composite magnetic field strength measured by the magnetic field sensor, which includes the original current magnetic field component Bsignal, the original eddy current magnetic field component Beddy, the compensation magnetic field component Bcomp, and the environmental noise.

[0023] ω is the operating frequency, and T is the temperature;

[0024] The implementation of this method also requires a frequency monitoring unit and a temperature sensor, among which:

[0025] The operating frequency is collected in real time by the frequency monitoring unit, and the temperature is collected in real time by the temperature sensor.

[0026] The operating frequency and temperature parameters are input into the dynamic eddy current transfer function model to update the model parameters and correct the phase offset.

[0027] In this technical solution, considering that temperature and frequency affect the magnetic field phase during chip testing, a dynamic eddy current transfer function model is constructed. Temperature fluctuations and frequency changes during chip operation can cause drift in parameters such as material permeability and impedance, introducing additional phase shift. Traditional fixed parameter models cannot adapt to this dynamic change. By incorporating ω and T as variables into the transfer function and combining real-time temperature and frequency parameters to correct the phase shift in real time, detection errors caused by temperature drift or frequency changes can be avoided, ensuring the accuracy of current waveform reconstruction under different operating conditions.

[0028] Furthermore, the phase offset is predicted by a recurrent neural network, and the transfer function parameters are updated based on the frequency monitoring unit and the temperature sensor.

[0029] In this technical solution, since the phase prediction model based on physical formulas is difficult to capture the nonlinear phase shift under the coupling effect of temperature and frequency and random noise in complex electromagnetic environments, while recurrent neural networks can process time series data such as temperature, frequency, and historical phase shift, learn the phase change law under long time series and update it dynamically through real-time data, realize the adaptive compensation of the algorithm layer for the dynamic changes of the physical layer, and avoid the failure to detect defects due to phase prediction lag.

[0030] Furthermore, the magnetic field sensor is a tunnel magnetoresistive sensor with an array layout that matches the spatial distribution of the through-silicon via array. It is used to measure the spatial distribution of the elliptical polarized magnetic field along its major axis and to analyze the phase information of the original current magnetic field based on the angle between this direction and the current direction.

[0031] In this technical solution, the tunnel magnetoresistive sensor has high sensitivity and high magnetic field resolution, which can capture the weak magnetic field changes caused by micro short-circuit defects. The array layout can achieve spacing measurement that matches the micron-level size of the through-silicon via array. Combined with the nanocrystalline alloy shielding layer to suppress stray magnetic fields in the environment, it ensures accurate extraction of phase information. Then, based on the angle between the long axis direction and the current direction, the phase information of the original current magnetic field is analyzed, and the current density distribution is inverted to achieve micron-level positioning of defects.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] 1. In this chip electrical testing method, system and device, a compensating magnetic field with a 90° phase difference from the original eddy current magnetic field is generated by deploying an adjustable auxiliary excitation coil around the silicon via array. The superimposed elliptical polarized magnetic field carries the true phase information of the original current magnetic field along its long axis. When the tunnel magnetoresistive sensor detects that the angle between the long axis and the current direction is the smallest, it indicates that the eddy current interference is suppressed to the maximum extent. At this time, the current waveform reconstructed by combining the dynamic eddy current transfer function model and real-time temperature and frequency parameters can truly reflect the current distribution. Micro-short circuit defects will cause abnormal increments in local current. Based on this, the system can accurately identify defects and achieve micron-level precise positioning through sensor data inversion.

[0034] 2. In this chip-based electrical testing method, system, and device, temperature and operating frequency parameters are collected in real time through an embedded temperature sensor and a frequency monitoring unit. Combined with a recurrent neural network to dynamically predict the phase shift, the dynamic eddy current transfer function model can be corrected in real time in scenarios where the temperature fluctuates from 25℃ to 85℃ or in high-frequency operating scenarios of 100MHz–3.5GHz. This avoids detection errors caused by temperature drift or frequency changes and ensures the accuracy of current waveform reconstruction under different operating conditions. Attached Figure Description

[0035] Figure 1 This is a flowchart of the chip electrical testing method of the present invention;

[0036] Figure 2 This is a flowchart of the chip electrical testing system of the present invention;

[0037] Figure 3 This is a flowchart of the chip electrical testing system of the present invention;

[0038] Figure 4 This is a schematic diagram of the chip electrical testing device of the present invention;

[0039] Figure 5 This is a schematic diagram of the synchronous acquisition module of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Figure 1 A chip-based electrical testing method is shown; see [link to relevant documentation]. Figure 1 Specifically, it includes the following steps:

[0042] S1. A compensation magnetic field is generated based on the auxiliary excitation coil. The compensation magnetic field and the original eddy current magnetic field are superimposed to form an elliptical polarized magnetic field. The compensation magnetic field and the original eddy current magnetic field have the same frequency and a phase difference of 90°.

[0043] S2. The magnetic field sensor captures the major axis direction of the elliptical polarized magnetic field and extracts the true phase information of the original current magnetic field.

[0044] S3. Dynamically compensate for the phase offset based on the real phase information and output the reconstructed current waveform;

[0045] S4. Identify chip defects based on the reconstructed current waveform.

[0046] In the first embodiment, the high-frequency phase shift problem of three-dimensional stacked chips is solved by physical layer signal modulation and real-time compensation at the algorithm layer. In the physical layer implementation, based on the principle of orthogonal magnetic field interference, an adjustable auxiliary excitation coil 112 (copper wire diameter 20μm, spiral structure embedded in ceramic substrate 111) is deployed in the test device around the silicon via array to generate a compensation magnetic field (Bcomp) with the same frequency as the original eddy magnetic field (Beddy) and a phase difference locked at 90°. When the two are superimposed in space, an elliptical polarized magnetic field is formed, whose major axis carries the true phase information of the original current magnetic field (Bsignal), thereby stripping away high-frequency eddy current interference.

[0047] In the algorithm layer, a dynamic eddy current transfer function model is constructed:

[0048]

[0049] Wherein, H(ω,T) is the dynamic eddy current transfer function, which reflects the transfer characteristics of the eddy current magnetic field at different frequencies and temperatures;

[0050] B signal (ω,T) represents the target magnetic field component carrying the phase information of the original current magnetic field;

[0051] B meas(ω,T) represents the composite magnetic field strength measured by the magnetic field sensor, which includes the original current magnetic field component Bsignal, the original eddy current magnetic field component Beddy, the compensation magnetic field component Bcomp, and the environmental noise.

[0052] ω is the operating frequency, and T is the temperature.

[0053] In the data acquisition layer, a high-precision thermistor (resolution ±0.1℃) is directly embedded in the area surrounding the silicon via array of the chip under test, capturing real-time temperature data T at a specific sampling rate. At the same time, the operating frequency ω (range 100MHz–3.5GHz) is monitored by the test machine clock synchronization module, forming a dynamic parameter pair (ω,T) as the system input source.

[0054] The phase shift is then predicted using a recurrent neural network (RNN). The RNN's phase shift prediction architecture employs a two-layer cascaded gated recurrent unit (GRU), with 128 neurons deployed in each layer to address long-term temporal dependencies. The input layer receives a time-series data stream [Tt, ωt, Δφt] (containing temperature, frequency, and the original phase shift), and the output layer generates the predicted phase shift value Δφ^t+1 for the next time step. During real-time inference, the system inputs 50ms time window slices of data into the GRU network for forward propagation, strictly controlling prediction errors. During training, historical test datasets containing true temperature drift values ​​are used to optimize network weights, ensuring model generalization ability. When temperature fluctuations exceed 10℃ or frequency changes exceed 500MHz, the system automatically triggers RNN weight updates: the historical temperature drift dataset is loaded to retrain the network, and the time window is expanded from 50ms to 200ms to enhance long-term stability.

[0055] The final output is the reconstructed current waveform. The current reconstruction stage is achieved through phase compensation and magnetic field analysis. First, the RNN predicted value Δφ^ is substituted into the inverse transfer function. Then, this compensation amount is combined with the inverse operation H of the dynamic transfer function. -1 (ω,T) are combined and processed, where:

[0056]

[0057] Bmeas is the composite magnetic field measured by the tunnel magnetoresistive (TMR) sensor 114 (including the original current magnetic field component Bsignal, the original eddy current magnetic field component Beddy, the compensation magnetic field component Bcomp, and environmental noise, in Tesla). Bsignal is the ideal magnetic field of the target current, and complex domain compensation calculations are performed.

[0058]

[0059] in, For a complex exponential operator, phase rotation with an accuracy of 0.001° is achieved using the CORDIC algorithm of a digital signal processor (DSP), completely eliminating phase lag and amplitude distortion of the eddy current magnetic field. Subsequently, the real part of the compensation magnetic field is extracted. {·} Remove residual imaginary part interference and establish current mapping based on the Lorentz force law I∝∣B∣:

[0060]

[0061] The calibration coefficient k is determined by the vacuum permeability μ0, the vertical distance d from the sensor to the conductor 50 μm, and the radius r of the through silicon via (TSV) 2.5 μm, and outputs an ampere-level real current Ireal.

[0062] The reconstructed Ireal current value is input into the three-dimensional current density inversion algorithm. The data analysis module 340 divides the through-silicon via array into independent units corresponding to the coordinates of the magnetic field sensor, with each unit corresponding to the coordinate position of a tunnel magnetoresistive sensor 114. After activating the auxiliary coil in step S1, the phase difference between the compensation magnetic field Bcomp and the eddy magnetic field Beddy needs to be strictly locked at 90°±0.5° using a vector network analyzer. At the same time, the excitation current is adjusted so that |Bcomp|=0.3|Beddy| to achieve optimal elliptic polarization. By comparing the deviation between the theoretical current distribution model (generated based on the chip design layout) and the measured Ireal, when the current increment of a certain through-silicon via unit exceeds a preset threshold, the system combines the coordinate feedback of the positioning mechanism, vector analysis of the current gradient distribution, and infrared thermal imaging for verification (the micro-short-circuit region will generate a local temperature rise due to Joule heating) to lock the coordinates (x, y, z) of the defect center. For example, in the actual test of the HBM4 chip, the current value at coordinates (112μm, 58μm, Layer 5) reached 107.2% of the theoretical value, accompanied by an abnormal temperature rise of 8℃, and a current gradient Presented in the XY plane as 10 5 A / m 2 The abrupt change in magnitude can be identified as a micro-short circuit caused by residual metal in the interlayer.

[0063] Second embodiment, see Figure 2 and Figure 3 As shown, a chip-based electrical testing system is provided to implement the above-mentioned chip-based electrical testing method, including a test control module 310, an orthogonal modulation module 320, a dynamic compensation module 330, and a data analysis module 340.

[0064] The test control module 310 uses a miniature spring probe array with a gold-palladium alloy coating. It injects a precise and controllable scanning current into the power pads of the chip under test through a low-impedance path (<50mΩ). The current range covers 10mA to 100mA and is programmable and adjustable. At the same time, it integrates a phase-locked loop circuit to track the main clock signal of the test machine in real time and outputs a wide-band operating frequency ω from 100MHz to 3.5GHz with a frequency resolution of 1MHz.

[0065] The quadrature modulation module 320 generates the fundamental frequency signal of the compensation magnetic field through a direct digital frequency synthesizer (DDS). This signal is then amplified by a power amplifier to drive the spiral excitation coil on the probe card to generate Bcomp. A phase-locked loop feedback network monitors the phase relationship between Bcomp and the eddy current magnetic field Beddy in real time. A digital phase detector (phase detector) dynamically adjusts the output phase of the DDS to ensure that the phase difference between the two is strictly locked within the range of 90°±0.5°. Simultaneously, the quadrature modulation module 320 controls the operation of the tunnel magnetoresistive sensor 114 array. The differential signal output by each sensor unit is converted into a digital signal by a preamplifier (60dB gain) and a 24-bit Σ-Δ ADC. The in-phase component (I) and quadrature component (Q) are separated by a quadrature demodulation algorithm, and the coordinate rotation digital calculation (CORDIC) algorithm is used to calculate the azimuth angle θ of the major axis of the elliptical polarized magnetic field in real time, achieving an angular resolution of 0.01°.

[0066] The core of the Dynamic Compensation Module 330 is a real-time inference engine deployed on the Xilinx Versal ACAP adaptive computing platform. Its programmable logic unit runs a two-layer cascaded gated recurrent unit (GRU) network, with 128 neurons per layer. Network weights are pre-loaded via on-chip memory and support online updates. The Dynamic Compensation Module 330 receives real-time temperature T and operating frequency ω parameters transmitted from the synchronous acquisition module 150 via a PCIe Gen4×8 interface, dynamically updating the complex coefficient matrix of the dynamic eddy current transfer function H(ω,T) at 10μs intervals. The calibration unit integrates a 10Ω ±0.01% standard impedance element (temperature coefficient ±1ppm / ℃). The calibration process is automatically triggered every 24 hours, injecting a 100mA reference current into the standard impedance element, measuring the actual magnetic field Bmeas and comparing it with the theoretical model prediction Bsignal. The transfer function parameters are optimized using the least squares method, reducing model errors across the entire temperature range (-40℃ to 150℃).

[0067] The data analysis module 340 first maps the reconstructed current Ireal to the chip's through-silicon via array according to the physical coordinates of the tunnel magnetoresistive sensor 114, generating a two-dimensional current density distribution heatmap; then it calculates the spatial current gradient using the Sobel operator. When the gradient magnitude is detected to exceed the threshold (default) When the current anomaly is detected, the infrared thermal imager is triggered to collect the temperature field on the chip surface, locate the local temperature rise area (ΔT≥5℃), and combine the six-degree-of-freedom coordinate data (x,y,z,θx,θy,θz) of the multi-axis positioning platform 120 and the chip interlayer via design file (GDSII format) to map the current anomaly point to the specific functional layer (such as Layer 5 metal interconnect layer) in three-dimensional space, output the defect center coordinates and confidence score, and transmit them to the test host in real time through the gigabit Ethernet interface.

[0068] Third embodiment, see Figure 4 As shown, a chip-based electrical testing device is provided to implement the above-mentioned chip-based electrical testing method and system. The device includes an orthogonal modulation probe card 110, a multi-axis positioning platform 120, a vacuum thermal control test stand 130, and a synchronous acquisition module 150.

[0069] The orthogonal modulation probe card 110 employs a six-layer low-temperature co-fired ceramic substrate 111 stacked structure. The bottom layer features an alumina substrate to effectively dissipate the high heat flux density during chip testing. A spiral copper coil array with a wire diameter of 20 μm and a turn spacing of 5 μm is integrated on the surface to suppress high-frequency skin effect, optimize magnetic field uniformity, and control electromagnetic coupling between adjacent wires. The middle layer is a 50 μm thick Fe-Si-B-Cu nanocrystalline alloy electromagnetic shielding layer 113, providing a critical attenuation depth for electromagnetic interference. Its thermal expansion coefficient is precisely matched to the substrate to avoid interlayer delamination, attenuating environmental electromagnetic interference by more than 60 dB. The top layer is the tunnel magnetoresistive sensor 114 functional layer. The tunnel magnetoresistive sensor 114 unit arrangement matches the characteristic size of through-silicon vias and follows the spatial sampling theorem. It contains a Ta / CoFeB / MgO / CoFeB / Ta magnetic tunnel structure, which can effectively capture nanoampere-level current magnetic fields from micro-short-circuit defects. The signal conditioning circuit is directly integrated into the field-programmable gate array at the edge of the probe card, realizing integrated processing of preamplification, automatic bias compensation, I / Q demodulation and CORDIC angle calculation, and the data meets the real-time phase compensation requirements of the highest operating frequency of 3.5GHz.

[0070] The multi-axis positioning platform 120 consists of a macro-motion module 121 and a micro-motion module 122. The macro-motion module 121 uses a linear motor to drive the Z-axis lifting, with a stroke of 50 mm, a maximum speed of 100 mm / s, and a repeatability of ±1 μm. The micro-motion module 122 uses a piezoelectric ceramic six-degree-of-freedom actuator, with an X / Y displacement range of ±5 mm and a resolution of 0.1 μm, a Z-axis tilt angle adjustment range of ±5°, and a resolution of 0.01°. A laser interferometer and a capacitive displacement sensor are integrated at the platform's end, providing real-time feedback of position errors and closed-loop control to ensure that the distance between the sensor array center and the silicon via center is ≤50 μm (tolerance ±0.5 μm), and the in-plane alignment error is <±0.3 μm. The motion controller communicates with the main control system via an EtherCAT bus and supports G-code programming to implement complex scanning paths.

[0071] The vacuum thermal control test fixture 130 is made of copper-tungsten alloy with a thermal conductivity of 180 W / m·K. The bottom integrates a three-level Peltier temperature control module 131 (maximum temperature difference ΔT = 190℃), which maintains the chip temperature within the range of -40℃ to 150℃ using PID algorithm and fuzzy control, with a temperature gradient of ≤2℃ over a 2cm × 2cm area on the chip surface. The upper part of the vacuum thermal control test fixture 130 features a porous silicon carbide vacuum adsorption disk 132. A Pt1000 thin-film thermistor array 133 is embedded in the surface of the adsorption disk, enabling temperature detection using a four-wire measurement method. Temperature data is directly output via an I2C interface.

[0072] like Figure 5 As shown, the synchronous acquisition module 150 adopts a distributed architecture. The magnetic field acquisition card uses a high-resolution analog-to-digital converter and an FPGA to achieve time-division multiplexing acquisition of TMR signals. The temperature and frequency acquisition cards integrate a high-precision frequency counter and a 24-bit Σ-ΔADC temperature measurement circuit. All boards are interconnected via a backplane PCIe Gen4×8 bus. A GPS-disciplined rubidium atomic clock generates a global trigger signal, and its sub-nanosecond-level inter-channel synchronization accuracy corresponds to the phase control requirements of a 3.5GHz signal. In the composite power supply architecture, the lithium battery power supply unit suppresses power supply noise to ensure the effective extraction of femtotes-level weak magnetic signals. Finally, the synchronous acquisition module 150 sends the real-time acquired temperature, frequency, and magnetic field data to the hardware acceleration unit of the dynamic compensation module 330 via the PCIe Gen4×8 bus, where the unit performs transfer function parameter updates and phase offset compensation.

[0073] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for testing electrical properties of a chip, characterized in that, Comprise: a chip to be tested, which obtains an original current magnetic field and an original eddy current magnetic field under a high-frequency current environment; an auxiliary excitation coil arranged around a through silicon via array of the chip to be tested; a magnetic field sensor; wherein the steps comprise: S1, generating a compensation magnetic field based on the auxiliary excitation coil, the compensation magnetic field and the original eddy current magnetic field superimposed to form an elliptical polarized magnetic field; wherein the compensation magnetic field and the original eddy current magnetic field have the same frequency and a phase difference of 90°; S2, the magnetic field sensor captures the long axis direction of the elliptical polarized magnetic field, and extracts the true phase information of the original current magnetic field; S3, dynamically compensating the phase shift based on the true phase information, and outputting a reconstructed current waveform; S4, identifying a chip defect according to the reconstructed current waveform.

2. The method of claim 1, wherein: The dynamic compensation is achieved by a dynamic eddy current transfer function model, which is wherein: H(ω, T) is a dynamic eddy current transfer function, reflecting the transfer characteristics of the eddy current magnetic field under different frequencies and temperatures; B signal (ω, T) is the target magnetic field component carrying the original current magnetic field phase information; B meas (ω, T) is the complex magnetic field strength measured by the magnetic field sensor, comprising the original current magnetic field component Bsignal, the original eddy current magnetic field component Beddy, the compensation magnetic field component Bcomp, and the ambient noise; ω is the working frequency, and T is the temperature.

3. The method of claim 2, wherein: Further comprising a frequency monitoring unit and a temperature sensor, wherein: the working frequency ω is collected in real time through the frequency monitoring unit, and the temperature T is collected in real time through the temperature sensor; the working frequency ω and the temperature T parameters are input into the dynamic eddy current transfer function model, which is used to update the model parameters and correct the phase shift.

4. The method of claim 3, wherein the step of applying a voltage to the chip under test comprises applying a voltage to the chip under test using a voltage source. The phase shift is predicted by a recurrent neural network, and the parameters of the dynamic eddy current transfer function model are updated based on the frequency monitoring unit and the temperature sensor.

5. The method of claim 1, wherein: The magnetic field sensor is a tunnel magnetoresistance sensor, and is arranged in an array to match the spatial distribution of the through silicon via array, for measuring the spatial distribution of the long axis direction of the elliptical polarized magnetic field, and analyzing the phase information of the original current magnetic field based on the angle between the direction and the current direction.

6. The method of claim 1, wherein: The method for identifying the chip defect comprises the following steps: detecting an abnormal increment of the reconstructed current value relative to a theoretical current distribution; analyzing the spatial gradient distribution characteristics of the abnormal increment; locking the defect position in combination with the current gradient mutation region.

7. A test system for the chip-based electrical testing method according to any one of claims 1 to 6, characterized in that Comprise: a test control module configured to inject a scanning current into the chip to be tested and output a working frequency; a quadrature modulation module configured to drive the auxiliary excitation coil to generate a compensation magnetic field, and control the magnetic field sensor to capture the elliptical polarized magnetic field; a dynamic compensation module configured to receive the phase information output by the magnetic field sensor, and perform phase shift correction; a data analysis module configured to identify a defect region according to the reconstructed current waveform.

8. The test system of claim 7, wherein: The test control module, the quadrature modulation module, the dynamic compensation module and the data analysis module realize signal cooperation through a high-speed interconnection architecture, wherein: the test control module and the dynamic compensation module establish a real-time parameter channel to transmit frequency parameters; the quadrature modulation module keeps clock synchronization with the dynamic compensation module through a phase-locked loop network; the data analysis module integrates a spatial gradient analysis unit to detect current distribution abnormal characteristics.

9. A test apparatus for the chip-based electrical testing method according to any one of claims 1 to 6, characterized in that, Comprise: a quadrature modulation probe card, which is provided with a spiral auxiliary excitation coil, an electromagnetic shielding layer and a magnetic field sensor on a substrate; a multi-axis positioning platform configured to control the relative position of the probe card and the through silicon via array; a vacuum thermal control test seat configured to fix the chip and control the test temperature; a synchronous acquisition module configured to synchronously acquire magnetic field, temperature and frequency signals.

10. The test device of claim 9, wherein: The multi-axis positioning platform realizes automatic alignment of the magnetic field sensor array and the through silicon via with a spacing of ≤50μm. The synchronous acquisition module acquires the magnetic field, temperature and frequency signals in a synchronous triggering mode.

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