Semiconductor device and manufacturing method thereof
By forming a mask layer on the gate oxide layer and performing furnace tube annealing, the morphology of the gate oxide layer is adjusted to be thicker at the edges and thinner in the middle, which solves the problem of gate-induced drain leakage current and improves the performance and reliability of semiconductor devices.
Patent Information
- Application Number
- CN202411288580.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2026-03-17
AI Technical Summary
With the development of semiconductor technology, the electric field strength at the gate edge of MOSFET devices has increased, leading to an increase in gate-induced drain leakage current, which affects the reliability and static power consumption of the devices.
A mask layer is formed on the gate oxide layer and a furnace tube annealing process is performed to make the gate oxide layer thicker at the edges and thinner in the middle. By increasing the edge thickness, the electric field strength is reduced, thereby reducing the gate-induced drain leakage current.
By adjusting the morphology of the gate oxide layer, the electric field strength at the gate edge is reduced, which significantly reduces the gate-induced drain leakage current, improves device performance, and maintains gate control capability.
Smart Images
Figure CN121693014A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Gate-induced drain leakage current (GIDL) is the primary off-state leakage mechanism in MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). With the advancement of semiconductor technology, MOSFET dimensions are continuously shrinking, and the thickness of the polysilicon gate oxide layer is becoming increasingly thinner. Consequently, the gate-induced drain leakage current increases exponentially, severely impacting device reliability.
[0003] When the gate of a MOS transistor is turned off and the drain is connected to a voltage, the energy band near the interface of the overlapping portion of the drain impurity diffusion layer and the gate undergoes strong bending, forming an inversion layer on the surface. The depletion layer becomes particularly narrow, leading to band-to-band tunneling (BTBT) between conduction band electrons and valence band holes, resulting in drain leakage current. Solving the problem of gate-induced drain leakage current will contribute to the development and application of semiconductor devices.
[0004] In the prior art, small-size medium-voltage (MV) devices suffer from a relatively large gate-induced drain leakage current due to the strong electric field at the gate edge, which affects static power consumption. Since leakage current is an important indicator of the device, it is often a major concern. Therefore, optimizing the gate-induced drain leakage current effect is particularly important. Summary of the Invention
[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method, which improves device performance by reducing the gate-induced drain leakage current effect by reducing the electric field strength at the gate edge.
[0006] To address the aforementioned technical problems, according to a first aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the following steps:
[0007] A substrate is provided, on which a gate oxide layer and a mask material layer are sequentially formed, and the mask material layer is etched to form a mask layer, the mask layer being located in a region where a gate is to be formed;
[0008] A furnace tube annealing process is performed, causing the apex of the gate oxide layer edge located directly below the mask layer to rise above the mask layer and the bottom corner to descend and consume the substrate. This results in the gate oxide layer located directly below the mask layer having a shape that is thick at the edges and thin in the middle, where the edge of the gate oxide layer refers to the area aligned with the edge of the mask layer; and
[0009] Remove the mask layer.
[0010] Optionally, after forming the mask layer and before performing the furnace tube annealing process, the fabrication method further includes: using the mask layer as a mask, etching away the gate oxide layer exposed by the mask layer.
[0011] Optionally, after removing the mask layer, the fabrication method further includes: forming a gate material layer on the gate oxide layer; and sequentially etching the gate material layer and the gate oxide layer to form a gate structure.
[0012] Optionally, after forming the gate structure, the fabrication method further includes:
[0013] Sidewalls are formed on both sides of the gate structure;
[0014] Source / drain ion implantation is performed on the substrate to form source / drain regions.
[0015] Optionally, before forming the gate oxide layer, the fabrication method further includes: performing trap ion implantation and lightly doped ion implantation on the substrate to form a trap region and a lightly doped region.
[0016] Optionally, the thickness of the middle region of the gate oxide layer located directly below the mask layer is greater than or equal to... Less than or equal to
[0017] Optionally, the mask layer may be made of silicon nitride.
[0018] Optionally, the thickness of the mask layer is greater than or equal to Less than or equal to
[0019] Optionally, the furnace tube annealing process is wet oxygen oxidation, with an annealing temperature greater than or equal to 700℃ and less than or equal to 1000℃, and an annealing time greater than or equal to 5s and less than or equal to 400s.
[0020] To address the aforementioned technical problems, according to a second aspect of the present invention, a semiconductor device is also provided, comprising: a substrate and a gate structure located on the substrate, the gate structure comprising a gate oxide layer and a gate sequentially located on the substrate; wherein the gate oxide layer has a morphology that is thick at the edges and thin in the middle.
[0021] Compared with the prior art, the technical solution of the present invention has at least the following technical effects:
[0022] The semiconductor device fabrication method provided by this invention involves forming a mask layer in a predetermined area for forming the gate on a gate oxide layer, followed by a furnace tube annealing process. Due to the presence of the mask layer, the re-oxidation rate at the edge region of the gate oxide layer directly below the mask layer is greater than the re-oxidation rate in the middle region of the gate oxide layer. This causes the apex of the gate oxide layer edge directly below the mask layer to rise upwards, while the bottom corner consumes the substrate downwards. Consequently, the gate oxide layer directly below the mask layer exhibits a morphology that is thick at the edges and thin in the middle (which can be referred to as a "bird's beak" or "dumbbell" morphology). This invention reduces the electric field intensity at the gate edge by increasing the thickness of the gate oxide layer edge, thereby reducing the gate-induced drain leakage current and improving device performance. Simultaneously, it ensures that the thickness of the gate oxide layer in the middle meets device requirements to guarantee gate control capability.
[0023] The semiconductor device provided by the present invention has a gate oxide layer with a thick edge and a thin center (i.e., a "bird's beak" shape or a "dumbbell" shape), thereby reducing the electric field intensity at the gate edge, thereby reducing the gate-induced drain leakage current and improving device performance, while maintaining the thickness in the middle of the gate oxide layer to ensure gate control capability. Attached Figure Description
[0024] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0025] Figures 2 to 8 This is a schematic diagram of the steps in the method for fabricating a semiconductor device provided in Embodiment 1 of the present invention.
[0026] Figure 9a This is a simulation diagram of the structure after etching the gate oxide layer using a mask layer as a mask.
[0027] Figure 9b It is a simulation diagram of the structure after the furnace tube annealing process.
[0028] Figure 9c It is a simulation diagram of the semiconductor device after the source and drain regions are formed.
[0029] Figure 10a This is an electric field distribution diagram of a semiconductor device in the prior art.
[0030] Figure 10b This is an electric field distribution diagram of a semiconductor device provided in Embodiment 1 of the present invention.
[0031] Figure 11a yes Figure 10a and Figure 10bThe transverse tangent diagram of the electric field distribution.
[0032] Figure 11b yes Figure 10a and Figure 10b The longitudinal tangent diagram of the electric field distribution.
[0033] Figure 12 This is a comparison graph of the current-voltage relationship curves between existing semiconductor devices and the semiconductor device provided in Embodiment 1 of this invention.
[0034] Figures 13 to 15 This is a schematic diagram of the steps in the method for fabricating a semiconductor device provided in Embodiment 2 of the present invention.
[0035] Figure 16a This is a simulation diagram of the structure after the mask layer is formed.
[0036] Figure 16b It is a simulation diagram of the structure after the furnace tube annealing process.
[0037] Figure 16c It is a simulation diagram of the semiconductor device after the source and drain regions are formed.
[0038] Figure 17a This is an electric field distribution diagram of a semiconductor device in the prior art.
[0039] Figure 17b This is an electric field distribution diagram of a semiconductor device provided in Embodiment 2 of the present invention.
[0040] Figure 18a yes Figure 17a and Figure 17b The transverse tangent diagram of the electric field distribution.
[0041] Figure 18b yes Figure 17a and Figure 17b The longitudinal tangent diagram of the electric field distribution.
[0042] Figure 19 This is a comparison graph of the current-voltage relationship curves between semiconductor devices in the prior art and the semiconductor device provided in Embodiment 2 of the present invention.
[0043] In the attached image:
[0044] 10-Substrate; 11-Shallow trench isolation structure; 12-Patterned photoresist layer; 13-Lightly doped region; 14-Source / drain region; 20-Gate structure; 21-Gate oxide layer; 22-Mask material layer; 23-Mask layer; 24-Gate material layer; 25-Gate; 30-Sidewall; 31-First sidewall; 32-Second sidewall. Detailed Implementation
[0045] One way to address the gate-induced drain leakage current effect is to adjust the doping process to improve the interface morphology at the overlap between the drain and the gate. However, when the drain doping concentration is too high, it often leads to a high source leakage current, affecting device performance. On the other hand, when the drain doping concentration is too low, the drain depletion region will be depleted from the low-doped region to the high-doped drain region, increasing the local electric field strength and enhancing the band-band tunneling effect.
[0046] Another way to solve the gate-induced drain leakage current effect is to increase the sidewall thickness and the lateral distance between the gate and the drain, thereby reducing the electric field strength between the gate and the drain. However, growing sidewalls that are too thick will cause residues during etching, which will not only affect the ion implantation in the source and drain regions, but also affect the effectiveness of subsequent silicide processes.
[0047] Another way to solve the gate-induced drain leakage current effect is to increase the longitudinal distance between the gate and the drain by longitudinal etching of the active region, thereby reducing the electric field strength and improving leakage current. However, the existing process is not mature enough, which makes the device performance unstable.
[0048] To address the aforementioned problems, the present invention provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, sequentially forming a gate oxide layer and a mask material layer on the substrate, and etching the mask material layer to form a mask layer, wherein the mask layer is located in a predetermined region for forming a gate; performing a furnace tube annealing process, such that the apex of the edge of the gate oxide layer located directly below the mask layer is raised upwards and the bottom corner is lowered downwards to consume the substrate, thereby making the gate oxide layer located directly below the mask layer have a shape that is thick at the edges and thin in the middle, wherein the edge of the gate oxide layer refers to the region aligned with the edge of the mask layer; and removing the mask layer.
[0049] The semiconductor device fabrication method provided by this invention involves forming a mask layer in a predetermined area for forming the gate on a gate oxide layer, followed by a furnace tube annealing process. Due to the presence of the mask layer, the re-oxidation rate at the edge region of the gate oxide layer directly below the mask layer is greater than the re-oxidation rate in the middle region of the gate oxide layer. This causes the apex of the gate oxide layer edge directly below the mask layer to rise upwards, while the bottom corner consumes the substrate downwards. Consequently, the gate oxide layer directly below the mask layer exhibits a morphology that is thick at the edges and thin in the middle (which can be referred to as a "bird's beak" or "dumbbell" morphology). This invention reduces the electric field intensity at the gate edge by increasing the thickness of the gate oxide layer edge, thereby reducing the gate-induced drain leakage current and improving device performance. Simultaneously, it ensures that the thickness of the gate oxide layer in the middle meets device requirements to guarantee gate control capability.
[0050] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0051] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0052] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for fabricating a semiconductor device includes the following steps:
[0053] S1: Provide a substrate, on which a gate oxide layer and a mask material layer are sequentially formed, and the mask material layer is etched to form a mask layer, wherein the mask layer is located in a region where a gate is to be formed;
[0054] S2: Perform a furnace tube annealing process, causing the apex of the gate oxide layer edge located directly below the mask layer to rise above the mask layer and the bottom corner to descend and consume the substrate, thereby making the gate oxide layer located directly below the mask layer have a shape that is thick at the edges and thin in the middle, wherein the edge of the gate oxide layer refers to the area aligned with the edge of the mask layer; and
[0055] S3: Remove the mask layer.
[0056] The following two embodiments illustrate the method for fabricating the semiconductor device according to the present invention.
[0057] Example 1
[0058] Figures 2 to 8This is a schematic diagram illustrating the structural steps of the semiconductor device fabrication method provided in Embodiment 1 of the present invention. Next, we will combine... Figure 1 and Figures 2 to 8 The method for fabricating the semiconductor device provided in Embodiment 1 of the present invention will be described in detail.
[0059] In step S1, please refer to Figure 3 and Figure 4 As shown, a substrate 10 is provided, on which a gate oxide layer 21 and a mask material layer 22 are sequentially formed, and the mask material layer 22 is etched to form a mask layer 23, the mask layer 23 being located in a region where a gate is to be formed.
[0060] In this embodiment, the substrate 10 can be made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is a silicon substrate.
[0061] In one embodiment of the present invention, please refer to Figure 2 As shown, before forming the gate oxide layer 21 on the substrate 10, a shallow trench isolation structure 11 is first formed in the substrate 10. Then, trap ion implantation is performed on the substrate 10 to form a trap region (not shown) to adjust the threshold voltage of the device. Then, a patterned photoresist layer 12 is formed on the substrate 10. Using the patterned photoresist layer 12 as a mask, lightly doped ion implantation is performed on the substrate 10 to form a lightly doped region 13.
[0062] Next, please refer to Figure 3 As shown, a gate oxide layer 21 is formed on the substrate 10, and the gate oxide layer 21 covers the substrate 10. Exemplarily, the gate oxide layer 21 can be formed using any suitable process known to those skilled in the art, such as thermal oxidation, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The material of the gate oxide layer 21 is, for example, silicon dioxide.
[0063] Then, please continue to refer to Figure 3 As shown, a mask material layer 22 is then formed on the gate oxide layer 21, covering the gate oxide layer 21. Exemplarily, the mask material layer 22 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In this embodiment, the material of the mask material layer 22 comprises silicon nitride, but is not limited thereto.
[0064] In one embodiment of the present invention, the thickness of the mask material layer 22 is greater than or equal to... Less than or equal to However, this is not the only factor. The thickness of the mask material layer 22 (i.e., the mask layer 23 formed subsequently) is related to the size of the "beak" formed subsequently. The thinner the mask material layer 22, the larger the "beak" formed, meaning the more the top corner of the final gate oxide layer 21 is raised above the mask layer, the more the top edge bends upward, and the more the bottom corner consumes the substrate 10 downward, meaning the more the bottom edge bends downward, resulting in a larger difference between the edge thickness and the middle thickness of the final gate oxide layer 21. Conversely, the thicker the mask material layer 22, the smaller the "beak" formed, meaning the less the top corner of the final gate oxide layer 21 is raised above the mask layer, the more the top edge bends upward, the less the bottom corner consumes the substrate 10 downward, and the less the bottom edge bends downward, resulting in a smaller difference between the edge thickness and the middle thickness of the final gate oxide layer 21. The thickness of the mask material layer 22 can be selected according to actual needs.
[0065] Next, please refer to Figure 3 and Figure 4 As shown, the mask material layer 22 is etched to form a mask layer 23, which is located in the region where the gate is to be formed. For example, a photoresist layer is formed on the mask material layer 22, and the photoresist layer is subjected to processes such as exposure and development to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, the mask material layer 22 is etched to form the mask layer 23, which is located in the same position as the subsequently formed gate. The patterned photoresist layer is then removed.
[0066] In this embodiment, please refer to Figure 4 As shown, after forming the mask layer 23, the gate oxide layer 21 is etched so that the remaining gate oxide layer 21 is located only directly below the mask layer 23, that is, the edge of the remaining gate oxide layer 21 is aligned with the edge of the mask layer 23.
[0067] In one embodiment of the present invention, please refer to Figure 4 As shown, after forming a patterned photoresist layer, and using the patterned photoresist layer as a mask to etch the mask material layer 22 to form the mask layer 23, the gate oxide layer 21 is etched using the patterned photoresist layer as a mask until a portion of the substrate 10 is exposed, and then the patterned photoresist layer is removed.
[0068] In another embodiment of the present invention, please refer to Figure 4As shown, using the patterned photoresist layer as a mask, the mask material layer 22 is first etched to expose part of the surface of the gate oxide layer 21 to form a mask layer 23. Then, the patterned photoresist layer is removed. After that, using the mask layer 23 as a mask, the gate oxide layer 21 is etched to expose the surface of the substrate 10.
[0069] Optionally, in this embodiment, before forming the gate oxide layer 21 on the substrate 10, a gate oxide cleaning process can be used for pretreatment to remove the natural oxide layer and impurities on the surface of the substrate 10, ensuring the cleanliness and flatness of the surface of the substrate 10, so as to ensure that a high-quality gate oxide layer 21 is obtained subsequently.
[0070] In step S2, please refer to Figure 5 As shown, a furnace tube annealing process is performed, which causes the top corner of the edge of the gate oxide layer 21 located directly below the mask layer 23 to raise the mask layer 23 and the bottom corner to consume the substrate 10, thereby making the gate oxide layer 21 located directly below the mask layer 23 have a shape that is thick at the edges and thin in the middle. The edge of the gate oxide layer 21 refers to the area that is aligned with the edge of the mask layer 23.
[0071] In this embodiment, the gate oxide layer 21 is covered by the mask layer 23, while the sidewalls of the gate oxide layer 21 are exposed. During the furnace tube annealing process, the re-oxidation rate at the edge region of the gate oxide layer 21 is greater than that at the middle region of the gate oxide layer 21. This causes the apex of the edge of the gate oxide layer 21 to raise the mask layer 23 upwards, and the bottom corner to consume the substrate 10 downwards (i.e., the substrate 10 at the bottom corner is oxidized to form the gate oxide layer). Consequently, the apex of the edge of the gate oxide layer 21 is higher than the middle region of the gate oxide layer 21, and the bottom corner of the edge of the gate oxide layer 21 is lower than the middle region of the gate oxide layer 21. This results in the final gate oxide layer 21 having a morphology that is thick at the edges and thin in the middle (which can be called a "bird's beak" morphology or a "dumbbell" morphology. When it is regarded as a "bird's beak" morphology, the gate oxide layer 21 is composed of two opposing "bird's beaks".
[0072] When the edges of the gate oxide layer 21 are re-oxidized, the central region of the gate oxide layer 21 may also be oxidized. Alternatively, due to the relatively thick mask layer 23, the central region of the gate oxide layer 21 may not be oxidized, or may be only slightly oxidized. The final thickness of the central region of the gate oxide layer 21 needs to meet device requirements, such as the thickness required to meet gate control capabilities. In this embodiment, the thickness of the central region of the gate oxide layer 21 located directly below the mask layer 23 is greater than or equal to... Less than or equal to Of course, it's not limited to this.
[0073] It should be noted that during the re-oxidation of the gate oxide layer 21, the substrate 10 not covered by the gate oxide layer 21 is also oxidized at the same time. Therefore, after the furnace tube annealing process, the gate oxide layer 21 covers the entire substrate 10. For convenience, the gate oxide layer is still identified as 21 and is not distinguished from the gate oxide layer before the furnace tube annealing process.
[0074] After the furnace tube annealing process, the gate oxide layer 21 comprises two parts: a first part located directly below the mask layer 23 and a second part not covered by the mask layer 23. The first part of the gate oxide layer 21 has an edge that curves upwards at the top and downwards at the bottom. The gate oxide layer 21 located directly below the mask layer 23 has a shape that is thicker at the edges and thinner in the middle. Here, the edge refers to the area aligned with the edge of the mask layer 23, i.e., the edge of the first part of the gate oxide layer 21. In this embodiment, the edge of the gate oxide layer 21 mentioned after the furnace tube annealing process and before etching the gate oxide layer 21 refers to the edge of the first part. The second part of the gate oxide layer 21 is formed in this step and did not exist before the furnace tube annealing process; therefore, its thickness can be less than that of the first part. See [link to documentation] for details. Figure 5 As shown.
[0075] In this embodiment, by increasing the thickness of the gate oxide layer 21 at the edge, the electric field strength at the gate edge is reduced, thereby reducing the gate-induced drain leakage current and improving device performance. At the same time, the thickness of the middle of the gate oxide layer 21 can be guaranteed to meet the device requirements to ensure gate control capability.
[0076] In one embodiment of the present invention, after the furnace tube annealing process, the gate oxide layer 21 not covered by the mask layer 23 can be etched and removed using the mask layer 23 as a mask. In another embodiment of the present invention, after the gate material layer is subsequently formed, the gate material layer and the gate oxide layer 21 can be etched sequentially to form a gate structure.
[0077] In one embodiment of the present invention, the furnace tube annealing process is a LOCOS (Local Oxidation of Silicon) process, specifically wet oxygen oxidation, wherein the annealing temperature is greater than or equal to 700°C and less than or equal to 1000°C, and the annealing time is greater than or equal to 5s and less than or equal to 400s, but is not limited to these.
[0078] The annealing temperature and time in the furnace tube annealing process are related to the shape of the "bird's beak." For example, the higher the annealing temperature, the larger the "bird's beak," and the lower the annealing temperature, the smaller the "bird's beak." Similarly, the longer the annealing time, the larger the "bird's beak," and the shorter the annealing time, the smaller the "bird's beak." The annealing temperature and time can be determined according to actual needs.
[0079] In step S3, please refer to Figure 5 and Figure 6 As shown, the mask layer 23 is removed.
[0080] Please refer to Figure 6 As shown, after removing the mask layer 23, a gate material layer 24 is formed on the gate oxide layer 21. In one embodiment of the present invention, since the upper surface of the gate oxide layer 21 is not a flat surface, the gate material layer 24 may also not be a flat surface. Therefore, it is necessary to planarize the gate material layer 24, for example, by performing chemical mechanical polishing, so that the gate material layer 24 has a flat surface.
[0081] Then, a hard mask layer (not shown) is formed on the gate material layer 24, and a patterned photoresist layer is formed on the hard mask layer. The pattern of the patterned photoresist layer can be the same as the patterned photoresist pattern formed when the mask layer 23 is formed in step S1, that is, the same mask can be used. Next, the hard mask layer is etched using the patterned photoresist layer as a mask to form a patterned hard mask layer, and the patterned photoresist layer is removed. Then, the gate material layer 24 is etched using the patterned hard mask layer as a mask to form the gate 25.
[0082] In one embodiment of the present invention, the gate oxide layer 21 has been etched using the mask layer 23 as a mask before the mask layer 23 is removed. Therefore, after the gate 25 is formed, the patterned hard mask layer is directly removed. The gate 25 and the gate oxide layer 21 located below the gate 25 constitute a gate structure 20, as shown below. Figure 7 As shown.
[0083] In another embodiment of the present invention, the gate oxide layer 21 is not etched before the mask layer 23 is removed, such as... Figure 6 As shown, after etching the gate material layer 24 using the patterned hard mask layer as a mask to form the gate 25, the gate material layer 21 is further etched using the patterned hard mask layer as a mask to form the gate structure 20. Then, the patterned hard mask layer is removed to form the gate structure 20. Figure 7 The structure shown.
[0084] In the gate structure 20, the top of the gate oxide layer 21 is bent upward and the bottom is bent downward, and the gate oxide layer 21 has a shape that is thick at the edges and thin in the middle (which can be called a "bird's beak" shape or a "dumbbell" shape).
[0085] Please refer to Figure 8 As shown, after forming the gate structure 20, the process further includes: forming sidewalls 30 on both sides of the gate structure 20; then, using the gate structure 20 and the sidewalls 30 as masks, performing source / drain ion implantation on the substrate 10 to form source / drain regions 14. An annealing process is then performed to obtain the final semiconductor device.
[0086] The side wall 30 can be a single-layer structure or a multi-layer structure. In this embodiment, the side wall 30 is a double-layer structure. Please refer to [reference needed]. Figure 8 As shown, the sidewall 30 includes a first sidewall 31 and a second sidewall 32. The first sidewall 31 surrounds the sidewalls and top of the gate structure 20, and the second sidewall 32 covers the sidewalls of the first sidewall 31. The material of the first sidewall 31 is, for example, silicon oxide, and the material of the second sidewall 32 is, for example, silicon nitride. The distance between the source / drain region 14 and the gate structure 20 can be adjusted by the thickness of the sidewall 30.
[0087] In this embodiment, the steps described in Embodiment 1 are simulated using TCAD simulation software. Figure 9a This is a simulation diagram of the structure after etching the gate oxide layer using a mask layer. Figure 9b It is a simulation diagram of the structure after the furnace tube annealing process. Figure 9c This is a simulation diagram of the semiconductor device after the source and drain regions have been formed. Please refer to it. Figure 9a As shown, after etching the gate oxide layer 21 using the mask layer 23 as a mask, the mask layer 23 is aligned with the edge of the gate oxide layer 21. Please refer to... Figure 9b As shown, after the furnace tube annealing process, the gate oxide layer 21 includes a first portion located directly below the mask layer 23 and a second portion not covered by the mask layer 23. In the first portion, the apex of the edge of the gate oxide layer 21 raises the mask layer 23 upwards, and the bottom corners consume the substrate 10 downwards, resulting in the gate oxide layer 21 located directly below the mask layer 23 having a shape that is thick at the edges and thin in the middle. In the second portion, the thickness of the gate oxide layer 21 is less than the thickness of the gate oxide layer 21 in the first portion. Please refer to... Figure 9c As shown, after the semiconductor device is formed, the gate oxide layer 21 has a morphology that is thick at the edges and thin in the middle. The simulation results demonstrate that the semiconductor device fabrication method described in this embodiment can produce the gate oxide layer 21 with a morphology that is thick at the edges and thin in the middle.
[0088] Figure 10a This is an electric field distribution diagram of a semiconductor device in the prior art. Figure 10b This is an electric field distribution diagram of a semiconductor device provided in Embodiment 1 of the present invention. Wherein, the drain voltage Vd = Vdd (power supply voltage), and the gate voltage Vg = 0. Figure 11a yes Figure 10a and Figure 10b The transverse tangent plot of the electric field distribution diagram. Figure 11b yes Figure 10a and Figure 10b The longitudinal tangent diagram of the electric field distribution, where the transverse tangent is... Figure 10a and Figure 10b The horizontal dashed line in the image represents the surface of the semiconductor device channel, and the vertical tangent is... Figure 10a and Figure 10b The vertical dashed line in the figure represents the gate edge of a semiconductor device. Figure 11a and Figure 11b In the diagram, the smooth solid line represents a semiconductor device in the prior art (i.e., BSL in the figure), and the dotted solid line represents a semiconductor device provided in this embodiment (i.e., NEW1 in the figure). The vertical axis represents the electric field intensity. Figure 11a The horizontal axis in the graph represents the horizontal position (Position X) of the semiconductor device. Figure 11b The horizontal axis represents the vertical thickness (Depth) of the semiconductor device. From... Figure 11a and Figure 11b (i.e., the horizontal and vertical tangents of the electric field distribution diagram) It can be seen that the electric field strength at the gate edge of the semiconductor device fabricated according to the method of this embodiment is reduced compared with the semiconductor devices in the prior art.
[0089] Figure 12 This is a comparison graph of the current-voltage relationship curves between a semiconductor device in the prior art and the semiconductor device provided in Embodiment 1 of this invention. The horizontal axis represents voltage, specifically the gate voltage Vg, and the vertical axis represents current, specifically the drain current Id, with the drain voltage Vd = Vdd. The smooth solid line in the graph represents the semiconductor device in the prior art (i.e., BSL in the graph), and the dotted solid line represents the semiconductor device provided in this embodiment (i.e., NEW1 in the graph). Figure 12 It can be seen that the gate-induced drain leakage current of the semiconductor device provided in this embodiment is significantly reduced when Vg=0V, by approximately two orders of magnitude.
[0090] In summary, the semiconductor device fabrication method provided by this invention involves forming a mask layer 23 on a predetermined area for forming the gate on a gate oxide layer 21, followed by a furnace tube annealing process. Due to the presence of the mask layer 23, the re-oxidation rate at the edge region of the gate oxide layer 21 directly below the mask layer 23 is greater than the re-oxidation rate in the middle region of the gate oxide layer 21. This results in the apex of the edge of the gate oxide layer 21 directly below the mask layer 23 lifting the mask layer 23 upwards and the bottom corner consuming the substrate 10 downwards, thus giving the gate oxide layer 21 directly below the mask layer 23 a morphology that is thick at the edges and thin in the middle (which can be referred to as a "bird's beak" morphology or a "dumbbell" morphology). By increasing the thickness of the gate oxide layer 21 at the edge, this invention can reduce the electric field intensity at the gate edge, thereby reducing the gate-induced drain leakage current and improving device performance. At the same time, it can also ensure that the thickness of the middle of the gate oxide layer 21 meets the device requirements to guarantee gate control capability.
[0091]
Example 2
[0092] The difference between this implementation and Example 1 is that after etching the hard mask material layer 22 using the patterned photoresist layer as a mask to form the mask layer 23, the gate oxide layer 21 is not etched. After performing furnace tube annealing, the mask layer 23 is directly removed. After the gate material layer 24 is formed, the gate material layer 24 and the gate oxide layer 21 are etched sequentially to form the gate structure 20.
[0093] Compared with Embodiment 1, this embodiment reduces one etching process (etching of the gate oxide layer 21 before step S2), saving manufacturing costs. However, since the gate oxide layer 21 is not etched before step S2, in order to make the gate oxide layer 21 located directly below the mask layer 23 have a thick edge and thin center in the furnace tube annealing process, the degree of annealing process needs to be increased, such as increasing the annealing temperature and the annealing time.
[0094] Figures 13 to 15 This is a schematic diagram of the structural steps of the semiconductor device fabrication method provided in Embodiment 2 of the present invention. Next, we will combine... Figure 1 and Figure 2 , 3 , Figures 13 to 15 as well as Figure 7 , 8 The method for fabricating the semiconductor device provided in Embodiment 2 of the present invention will be briefly described.
[0095] In step S1, please refer to Figure 3 and Figure 13As shown, a substrate 10 is provided, on which a gate oxide layer 21 and a mask material layer 22 are sequentially formed, and the mask material layer 22 is etched to form a mask layer 23, the mask layer 23 being located in a region where a gate is to be formed.
[0096] In this embodiment, a patterned photoresist layer is formed on the mask material layer 22. Using the patterned photoresist layer as a mask, the mask material layer 22 is etched to form a mask layer 23. The mask layer 23 is located at the same position as the gate that is subsequently formed. Then, the patterned photoresist layer is removed to form a gate as shown in the image. Figure 13 The structure shown is as follows. In this embodiment, the gate oxide layer 21 is not etched, and the gate oxide layer 21 retains its original initial shape, that is, the gate oxide layer 21 includes two parts: a first part located directly below the mask layer 23 and a second part not covered by the mask layer 23.
[0097] In step S2, please refer to Figure 14 As shown, a furnace tube annealing process is performed, which causes the top corner of the edge of the gate oxide layer 21 located directly below the mask layer 23 to raise the mask layer 23 and the bottom corner to consume the substrate 10, thereby making the gate oxide layer 21 located directly below the mask layer 23 have a shape that is thick at the edges and thin in the middle. The edge of the gate oxide layer 21 refers to the area that is aligned with the edge of the mask layer 23.
[0098] In this embodiment, a portion of the gate oxide layer 21 is covered by the mask layer 23. During the furnace tube annealing process, for the first portion of the gate oxide layer 21, the re-oxidation rate at the edge region of the gate oxide layer 21 is greater than the re-oxidation rate in the middle region of the gate oxide layer 21. This causes the apex of the edge of the gate oxide layer 21 to rise above the mask layer 23, and the bottom corner to fall below the substrate 10. Consequently, the apex of the edge of the gate oxide layer 21 is higher than the middle region of the gate oxide layer 21, and the bottom corner is lower than the middle region of the gate oxide layer 21. This results in the final gate oxide layer 21 having a morphology that is thick at the edges and thin in the middle (which can be called a "bird's beak" morphology or a "dumbbell" morphology; when viewed as a "bird's beak" morphology, the gate oxide layer 21 is composed of two opposing "bird's beaks"). For the second portion of the gate oxide layer 21, the re-oxidation rate of the gate oxide layer 21 is consistent, making the second portion of the gate oxide layer 21 thicker.
[0099] For the first portion of the gate oxide layer 21, when the edges of the gate oxide layer 21 are re-oxidized, the middle region of the gate oxide layer 21 may also be oxidized. Alternatively, because the mask layer 23 is relatively thick, the middle region of the gate oxide layer 21 may not be oxidized, or may be only slightly oxidized. The final thickness of the middle region of the gate oxide layer 21 needs to meet device requirements, such as the thickness required to meet gate control capabilities. In this embodiment, the thickness of the middle region of the gate oxide layer 21 located directly below the mask layer 23 is greater than or equal to... Less than or equal to Of course, it's not limited to this.
[0100] After furnace tube annealing, the gate oxide layer 21 still comprises two parts: a first part located directly below the mask layer 23 and a second part not covered by the mask layer 23. The first part of the gate oxide layer 21 has an edge that curves upwards at the top and downwards at the bottom. The gate oxide layer 21 located directly below the mask layer 23 has a shape that is thicker at the edges and thinner in the middle. Here, the edge refers to the area aligned with the edge of the mask layer 23, i.e., the edge of the first part of the gate oxide layer 21. In this embodiment, the edge of the gate oxide layer 21 mentioned after furnace tube annealing and before etching the gate oxide layer 21 refers to the edge of the first part.
[0101] In this embodiment, by increasing the thickness of the edge of the gate oxide layer 21 directly below the mask layer 23, the electric field strength at the gate edge is reduced, thereby reducing the gate-induced drain leakage current and improving device performance. At the same time, the thickness of the middle of the gate oxide layer 21 is ensured to meet the requirements to guarantee gate control capability.
[0102] In step S3, please refer to Figure 14 and Figure 15 As shown, the mask layer 23 is removed.
[0103] Please refer to Figure 15 As shown, after removing the mask layer 23, a gate material layer 24 is formed on the gate oxide layer 21. A hard mask layer (not shown) is formed on the gate material layer 24, and a patterned photoresist layer is formed on the hard mask layer. The pattern of this patterned photoresist layer can be the same as the patterned photoresist pattern formed when the mask layer 23 was formed in step S1, that is, the same mask can be used. Then, the hard mask layer is etched using the patterned photoresist layer as a mask to form a patterned hard mask layer, and the patterned photoresist layer is removed. Then, the gate material layer 24 and the gate oxide layer 21 are etched sequentially using the patterned hard mask layer as a mask to form a gate structure 20. Then, the patterned hard mask layer is removed to form a structure as shown. Figure 7 The structure shown.
[0104] In the gate structure 20, the top of the gate oxide layer 21 is bent upward and the bottom is bent downward, and the gate oxide layer 21 has a shape that is thick at the edges and thin in the middle (which can be called a "bird's beak" shape or a "dumbbell" shape).
[0105] Please refer to Figure 8 As shown, after forming the gate structure 20, the process further includes: forming sidewalls 30 on both sides of the gate structure 20; then, using the gate structure 20 and the sidewalls 30 as masks, performing source / drain ion implantation on the substrate 10 to form source / drain regions 14. An annealing process is then performed to obtain the final semiconductor device.
[0106] In this embodiment, the steps described in Embodiment 2 are simulated using TCAD simulation software. Figure 16a This is a simulation diagram of the structure after the mask layer is formed. Figure 16b It is a simulation diagram of the structure after the furnace tube annealing process. Figure 16c This is a simulation diagram of the semiconductor device after the source and drain regions have been formed. Please refer to it. Figure 16a As shown, after the mask layer 23 is formed, the mask layer 23 is located in the region where the gate is to be formed. The gate oxide layer 21 includes a first portion located directly below the mask layer 23 and a second portion not covered by the mask layer 23. Please refer to... Figure 16b As shown, after the furnace tube annealing process, in the first part of the gate oxide layer 21, the apex corner of the edge of the gate oxide layer 21 raises the mask layer 23 upwards, and the bottom corner consumes the substrate 10 downwards, so that the gate oxide layer 21 located directly below the mask layer 23 has a morphology that is thick at the edges and thin in the middle; in the second part, the thickness of the gate oxide layer 21 is increased by re-oxidation. Please refer to... Figure 16c As shown, after the semiconductor device is formed, the gate oxide layer 21 has a morphology that is thick at the edges and thin in the middle. The simulation results demonstrate that the semiconductor device fabrication method described in this embodiment can produce the gate oxide layer 21 with a morphology that is thick at the edges and thin in the middle.
[0107] Figure 17a This is an electric field distribution diagram of a semiconductor device in the prior art. Figure 17b This is an electric field distribution diagram of the semiconductor device provided in Embodiment 2 of the present invention. Wherein, the drain voltage Vd = Vdd (power supply voltage), and the gate voltage Vg = 0. Figure 18a yes Figure 17a and Figure 17b The transverse tangent plot of the electric field distribution diagram. Figure 18b yes Figure 17a and Figure 17b The longitudinal tangent diagram of the electric field distribution, where the transverse tangent is... Figure 17a and Figure 17bThe horizontal dashed line shown represents the surface of the semiconductor device channel, and the vertical tangent is... Figure 17a and Figure 17b The vertical dashed line shown represents the gate edge of a semiconductor device. Figure 18a and Figure 18b In the diagram, the smooth solid line represents a semiconductor device in the prior art (i.e., BSL in the figure), and the solid line with line segments represents a semiconductor device provided in this embodiment (i.e., NEW2 in the figure). The vertical axis represents the electric field intensity. Figure 18a The horizontal axis in the graph represents the horizontal position (Position X) of the semiconductor device. Figure 18b The horizontal axis represents the vertical thickness (Depth) of the semiconductor device. From... Figure 18a and Figure 18b (i.e., the horizontal and vertical tangents of the electric field distribution diagram) It can be seen that the electric field strength at the gate edge of the semiconductor device fabricated according to the method of this embodiment is reduced compared with the semiconductor devices in the prior art.
[0108] Figure 19 This is a comparison graph of the current-voltage relationship curves between a semiconductor device in the prior art and the semiconductor device provided in Embodiment 2 of the present invention. The horizontal axis represents voltage, specifically the gate voltage Vg, and the vertical axis represents current, specifically the drain current Id, with the drain voltage Vd = Vdd. The smooth solid line in the graph represents the semiconductor device in the prior art (i.e., BSL in the graph), and the solid line with line segments represents the semiconductor device provided in this embodiment (i.e., NEW2 in the graph). Figure 19 It can be seen that the gate-induced drain leakage current of the semiconductor device provided in this embodiment is significantly reduced when Vg=0V, by approximately two orders of magnitude.
[0109] In summary, the semiconductor device fabrication method provided by this invention involves forming a mask layer 23 on a predetermined area for forming the gate on a gate oxide layer 21, followed by a furnace tube annealing process. Due to the presence of the mask layer 23, the re-oxidation rate at the edge region of the gate oxide layer 21 directly below the mask layer 23 is greater than the re-oxidation rate in the middle region of the gate oxide layer 21. This results in the apex of the edge of the gate oxide layer 21 directly below the mask layer 23 lifting the mask layer 23 upwards and the bottom corner consuming the substrate 10 downwards, thus giving the gate oxide layer 21 directly below the mask layer 23 a morphology that is thick at the edges and thin in the middle (which can be referred to as a "bird's beak" morphology or a "dumbbell" morphology). By increasing the thickness of the gate oxide layer 21 at the edge, this invention can reduce the electric field intensity at the gate edge, thereby reducing the gate-induced drain leakage current and improving device performance. At the same time, it can also ensure that the thickness of the middle of the gate oxide layer 21 meets the device requirements to guarantee gate control capability.
[0110] It should be noted that the embodiments in this specification are described in a progressive manner. The methods described later focus on the differences from the methods described earlier, and the similarities and similarities between the methods can be referred to each other.
[0111] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.
[0112] Please refer to Figure 8 As shown, the semiconductor device includes: a substrate 10 and a gate structure 20 located on the substrate 10. The gate structure 20 includes a gate oxide layer 21 and a gate 25 sequentially located on the substrate 10. The gate oxide layer 21 has a shape that is thick at the edges and thin in the middle.
[0113] In one embodiment of the present invention, sidewalls 30 are formed on both sides of the gate structure 20. The sidewalls 30 include a first sidewall 31 and a second sidewall 32. The first sidewall 31 covers the sidewalls and top of the gate structure 20, and the second sidewall 32 covers the first sidewall 31. The material of the first sidewall 31 is, for example, silicon oxide, and the material of the second sidewall 32 is, for example, silicon nitride.
[0114] In one embodiment of the present invention, a plurality of shallow trench isolation structures 11 are formed in the substrate 10, and a well region (not shown) is formed between the shallow trench isolation structures 11. Lightly doped regions 13 are formed in the substrate 10 on both sides of the gate structure 20, and active drain regions 14 are formed in the lightly doped regions 13 on both sides of the gate structure 20 and the sidewall 30.
[0115] The semiconductor device provided by the present invention has a gate oxide layer 21 with a thick edge and a thin center (i.e., a "bird's beak" shape or a "dumbbell" shape), thereby reducing the electric field strength at the edge of the gate 25, thereby reducing the gate-induced drain leakage current and improving device performance, while maintaining the thickness in the middle of the gate oxide layer 21 to ensure gate control capability.
[0116] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, forming a gate oxide layer and a mask material layer on the substrate in sequence, and etching the mask material layer to form a mask layer, the mask layer being located in a region where a gate is to be formed; performing a furnace tube annealing process, so that a top corner of an edge of the gate oxide layer located directly below the mask layer lifts the mask layer upward, and a bottom corner of the edge of the gate oxide layer located directly below the mask layer consumes the substrate downward, thereby making the gate oxide layer located directly below the mask layer have a profile of thick edges and thin middle; removing the mask layer. After the mask layer is formed and before the furnace tube annealing process is performed, the manufacturing method further comprises: etching and removing the gate oxide layer exposed by the mask layer with the mask layer as a mask.
2. The method of manufacturing a semiconductor device according to claim 1, wherein After the mask layer is removed, the manufacturing method further comprises: forming a gate material layer on the gate oxide layer; and etching the gate material layer and the gate oxide layer in sequence to form a gate structure.
3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein After the gate structure is formed, the manufacturing method further comprises:
4. The method of manufacturing a semiconductor device according to claim 3, wherein forming a sidewall on both sides of the gate structure; performing source-drain ion implantation on the substrate to form a source-drain region. Before the gate oxide layer is formed, the manufacturing method further comprises: performing well ion implantation and light-doped ion implantation on the substrate to form a well region and a light-doped region.
5. The method of manufacturing a semiconductor device according to claim 4, wherein The material of the mask layer comprises silicon nitride.
6. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein The thickness of the middle region of the gate oxide layer directly below the mask layer is greater than or equal to Less than or equal to 7. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein The furnace tube annealing process is wet oxygen oxidation, the annealing temperature is greater than or equal to 700 DEG C and less than or equal to 1000 DEG C, the annealing time is greater than or equal to 5 s and less than or equal to 400 s.
8. The method of manufacturing a semiconductor device according to Claim 7, wherein The thickness of the mask layer is greater than or equal to Less than or equal to 9. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein The method comprises:
10. A semiconductor device, characterized by comprising: a substrate and a gate structure located on the substrate, the gate structure comprising a gate oxide layer and a gate located on the substrate in sequence; wherein the gate oxide layer has a profile of thick edges and thin middle.
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Semiconductor device and method of manufacturing the same
CN122227657A