Fourier transform spectrometer synchronous data acquisition device and control method thereof

Abstract

The invention provides a Fourier transform spectrometer synchronous data acquisition device and a control method thereof, and the device comprises an interference signal conditioning module which is used for carrying out the synchronous amplification of a plurality of interference signals, and obtaining an amplified multi-source interference signal; the clock management module is used for performing fan-out buffering on the adjustable sampling clock signal to obtain a multi-channel ADC sampling clock signal; the multi-channel ADC sampling module is used for synchronously sampling the amplified multi-source interference signal according to a multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data; and the master control FPGA module is used for caching the multi-channel interference signal sampling data and sequentially performing adaptive filtering, zero crossing point detection, difference reconstruction, timestamp addition and data framing processing on the multi-channel interference signal sampling data to obtain framed interference data. According to the device, the reliability of data acquisition of the multi-channel Fourier transform spectrometer is improved.

Description

Technical Field

[0001] This invention relates to the field of data acquisition technology, and in particular to a synchronous data acquisition device for a Fourier transform spectrometer and its control method. Background Technology

[0002] Fourier transform spectroscopy, based on the principle of interference modulation, has advantages such as high throughput, low stray light influence, high wavenumber accuracy, large spectral range, and high spectral resolution. It has wide applications in atmospheric monitoring, meteorological research, space exploration, and airborne remote sensing.

[0003] In related technologies, traditional multi-channel Fourier transform spectrometers suffer from inconsistent paths between channels, leading to time deviations in signals from different channels and asynchronous signal sampling. Furthermore, Fourier transform spectrometers typically employ equal optical path sampling (also known as equal interval sampling), and due to factors such as noise and signal distortion, the position of the zero crossing point is often difficult to determine precisely, resulting in low reliability of data acquired by multi-channel Fourier transform spectrometers. Summary of the Invention

[0004] This invention provides a synchronous data acquisition device and control method for a Fourier transform spectrometer, which solves the defects of asynchronous signal sampling and difficulty in accurately determining the position of zero crossing point in existing multi-channel Fourier transform spectrometers. The method and system of this invention improve the reliability of data acquisition by multi-channel Fourier transform spectrometers.

[0005] This invention provides a synchronous data acquisition device for a Fourier transform spectrometer, comprising: The interference signal conditioning module is used to synchronously amplify multiple interference signals to obtain amplified multi-source interference signals. The clock management module is used to fan out and buffer the adjustable sampling clock signal to obtain the multi-channel ADC sampling clock signal; A multi-channel ADC sampling module is used to synchronously sample the amplified multi-source interference signal according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data. The main control FPGA module is used to cache the multi-channel interference signal sampling data and sequentially perform adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition and data framing on the multi-channel interference signal sampling data to obtain framed interference data; wherein, the main control FPGA module is also used to generate the adjustable sampling clock signal.

[0006] According to the present invention, a synchronous data acquisition device for a Fourier transform spectrometer includes an interferometric signal conditioning module comprising: A low-noise bias circuit is used to obtain a low-noise DC bias voltage; A current-to-voltage conversion circuit is used to convert the multi-channel interference signal into a voltage signal using the noise DC bias voltage as the common-mode input voltage; The T-type resistor feedback operational amplifier circuit is used to amplify the voltage signal with low noise using the noise DC bias voltage as the common-mode input voltage to obtain the amplified multi-source interference signal; the current-to-voltage conversion circuit and the T-type resistor feedback operational amplifier circuit are connected by RC coupling. The output voltage follower circuit features high input impedance and low output impedance.

[0007] According to the present invention, a synchronous data acquisition device for a Fourier transform spectrometer further includes: The communication module transmits the framed interference data to the host computer via at least one of network port communication or RS422 protocol communication.

[0008] According to the present invention, a synchronous data acquisition device for a Fourier transform spectrometer is provided, wherein the communication module is further used for: When transmitting data using the RS422 protocol, each frame and each byte in the framed interference data is verified.

[0009] According to the present invention, a synchronous data acquisition device for a Fourier transform spectrometer further includes: The power supply module includes a digital power supply and an analog power supply, wherein the digital power supply and the analog power supply are isolated from each other; the digital power supply supplies power to the module corresponding to the analog signal, and the analog power supply supplies power to the module corresponding to the digital signal.

[0010] According to the present invention, a synchronous data acquisition device for a Fourier transform spectrometer is provided. The multi-channel ADC sampling module adopts a three-channel architecture. Each channel consists of an input clamping circuit, a correlation dual sampler, an offset DAC, and a programmable gain amplifier. Each channel is connected to a high-performance 16-bit analog-to-digital converter (ADC) through multiplexing.

[0011] The present invention also provides a control method for a synchronous data acquisition device for a Fourier transform spectrometer, comprising: The multi-source interference signal is amplified synchronously by the interference signal conditioning module to obtain the amplified multi-source interference signal. The adjustable sampling clock signal is fanned out and buffered by the clock management module to obtain the multi-channel ADC sampling clock signal; The multi-channel ADC sampling module synchronously samples the amplified multi-source interference signal according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data. The main control FPGA module caches the multi-channel interference signal sampling data and sequentially performs adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing on the multi-channel interference signal sampling data to obtain framed interference data; wherein, the main control FPGA module is also used to generate the adjustable sampling clock signal.

[0012] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the control method of the synchronous data acquisition device for the Fourier transform spectrometer as described above.

[0013] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method of the synchronous data acquisition device for a Fourier transform spectrometer as described above.

[0014] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the control method of the synchronous data acquisition device for the Fourier transform spectrometer as described above.

[0015] The present invention provides a synchronous data acquisition device and control method for a Fourier transform spectrometer. This device amplifies multiple interference signals synchronously using an interference signal conditioning module to obtain amplified multi-source interference signals. A clock management module fans out and buffers an adjustable sampling clock signal to obtain a multi-channel ADC sampling clock signal. A multi-channel ADC sampling module then synchronously samples the amplified multi-source interference signals according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data. Finally, the main control FPGA module buffers the multi-channel interference signal sampling data and sequentially performs adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing processing on the multi-channel interference signal sampling data to obtain framed interference data. This invention enables distributed multi-channel synchronous infrared interference signal acquisition for ADCs without synchronization interfaces or timestamp functions, improving the reliability of data acquisition by a multi-channel Fourier transform spectrometer. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1This is one of the structural schematic diagrams of the synchronous data acquisition device for the Fourier transform spectrometer provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the high-precision zero-crossing sampling process provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the pipeline implementation architecture of the multi-ADC sampling data processing algorithm provided by the present invention.

[0020] Figure 4 This is a schematic diagram of the structure of the interference signal conditioning module provided by the present invention.

[0021] Figure 5 This is a schematic diagram of power distribution and layout provided by the present invention.

[0022] Figure 6 This is the second schematic diagram of the synchronous data acquisition device for the Fourier transform spectrometer provided by the present invention.

[0023] Figure 7 This is a flowchart illustrating the control method of the synchronous data acquisition device for a Fourier transform spectrometer provided by the present invention.

[0024] Figure 8 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0025] Figure label: 100: Interference signal conditioning module; 110: Low-noise bias circuit; 120: Current-to-voltage conversion circuit; 130: T-type resistor feedback operational amplifier circuit; 140: Output voltage follower circuit; 200: Clock management module; 300: Multi-channel ADC sampling module; 400: Main control FPGA module; 500: Communication module; 600: Power supply module. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0027] The following is combined Figures 1-8 The present invention describes a synchronous data acquisition device for a Fourier transform spectrometer and its control method.

[0028] Figure 1This is a schematic diagram of the structure of the synchronous data acquisition device for the Fourier transform spectrometer provided by the present invention, as shown below. Figure 1 As shown, the device includes: an interference signal conditioning module 100, a clock management module 200, a multi-channel ADC sampling module 300, and a main control FPGA module 400.

[0029] The interference signal conditioning module 100 is used to synchronously amplify multiple interference signals to obtain amplified multi-source interference signals.

[0030] In this embodiment, the multi-channel interference signal can be a signal acquired by different interference photodetectors. For example, the multi-channel interference signal includes a laser signal detected by a laser detector and infrared interference signal lamps from different channels detected by a mercury cadmium telluride detector.

[0031] In this embodiment, the interference signal conditioning module 100 completes the analog front-end processing of the interference optical signal, which includes reasonable gain and level adjustment; the purpose of signal conditioning is to make full use of the dynamic range of the ADC (Analog-to-Digital Converter).

[0032] Specifically, in order to ensure the synchronization between multiple channels, different signals in this embodiment share the same signal conditioning circuit.

[0033] It should be noted that in actual systems, the speed fluctuation of the moving mirror in the Fourier transform spectrometer leads to sampling position errors caused by equal time interval sampling. To reduce this sampling position error caused by speed fluctuations, existing technologies typically employ the following measures: First, the laser interference signal sampling pulse is obtained by pre-amplifying the detector output signal and shaping it with a comparator to obtain a zero-crossing pulse signal, which serves as the trigger signal for infrared interference signal sampling. Second, considering that the infrared interference signal is a weak signal, an anti-aliasing filter is usually added before the ADC to suppress front-end noise. Since the anti-aliasing filter has different phase frequency characteristics for different polychromatic infrared lights, different signals produce different phase lags, disrupting the synchronization between the signals of each channel. To solve this problem, in this implementation, the same path is used for each channel in the interference signal conditioning module 100, and the path consistency is maintained in the design of the corresponding PCB (Printed Circuit Board).

[0034] In this embodiment, the amplification process of the interference signal conditioning module 100 can be a two-stage amplification process, which helps to make full use of the dynamic range of the ADC while reducing noise interference and improving the signal-to-noise ratio.

[0035] The clock management module 200 is used to fan out and buffer the adjustable sampling clock signal to obtain the multi-channel ADC sampling clock signal.

[0036] In this embodiment, the adjustable sampling clock signal refers to a clock signal whose frequency can be adjusted as needed; specifically, in a Fourier transform spectrometer, the sampling frequency is closely related to the movement speed of the moving mirror, and the adjustable sampling clock signal can adapt to different moving mirror speeds, thereby achieving the best spectral resolution.

[0037] In this embodiment, the clock management module 200 copies the compliant CDS clock signal and ADC clock signal generated by the FPGA into multiple clock signals with the same frequency and phase. In multi-channel applications, using a crystal oscillator for clock signal copying increases board size and system cost. This invention generates the sampling clock using the main control FPGA, which has the advantage of flexible clock frequency adjustment.

[0038] Specifically, in this embodiment, the single-ended sampling clock is converted into a differential clock via a balun transformer and then distributed to each ADC via a clock fan-out distribution chip. The clock fan-out distribution chip has a maximum output frequency of 4.8GHz, a random jitter average of only 28fs, and 8 output channels, which can ensure the synchronization of the multi-channel sampling clock.

[0039] In addition, the clock management module 200 can enhance the driving capability of multiple ADC chips by fan-out buffering the adjustable sampling clock signal, thereby ensuring that each ADC chip can obtain a high-quality clock signal.

[0040] The multi-channel ADC sampling module 300 is used to synchronously sample the amplified multi-source interference signal according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data.

[0041] In this embodiment, the sampling clock signal is a timing signal that controls the ADC sampling process. Each clock cycle triggers one sampling, which determines the sampling frequency. The multi-channel ADC sampling module requires a synchronous multi-channel sampling clock signal to ensure that all channels are sampled at the same time, thereby achieving data synchronization.

[0042] In this embodiment, the amplified multi-source interference signal refers to the analog signal processed by the interference signal conditioning module 100. These signals come from the detector output of multiple light sources after interference and contain spectral information.

[0043] In one embodiment, the multi-channel ADC sampling module 300 adopts a three-channel architecture, with each channel consisting of an input clamping circuit, a correlated dual sampler, an offset DAC, and a programmable gain amplifier. Each channel is connected to a high-performance 16-bit analog-to-digital converter (ADC) via multiplexing.

[0044] In this embodiment, the selected analog-to-digital converter adopts a three-channel architecture design for sampling and conditioning the output of the three-line color CCD array. Each channel consists of an input clamping circuit, a correlated dual sampler (CDS), an offset DAC, and a programmable gain amplifier (PGA), and is connected to a high-performance 16-bit ADC through multiplexing. Its single-channel 16-bit maximum sampling rate can reach 12.5 MSPS, and the three-channel 16-bit maximum sampling rate can reach 15 MSPS.

[0045] The main control FPGA module 400 is used to buffer multi-channel interference signal sampling data and sequentially perform adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition and data framing on the multi-channel interference signal sampling data to obtain framed interference data; the main control FPGA module 400 is also used to generate an adjustable sampling clock signal.

[0046] In this embodiment, the main control FPGA chip integrates two ARM processors, internal memory, external memory interface, and peripherals.

[0047] In this embodiment, the interference signal sampling data after analog-to-digital conversion needs to be cached after entering the FPGA before it can be processed synchronously. This embodiment uses a DDR3 high-speed data cache chip with a single chip storage capacity of 4Gb, consisting of 16 256Mbit areas, and the data read rate can reach 1600 / 1866Mbps.

[0048] In this embodiment, the Fourier transform spectrometer synchronous data acquisition device also has two functions: high-precision zero-crossing detection and adding high-precision timestamps.

[0049] Specifically, since ADC inevitably introduces errors during the quantization process, the input signal is divided into N equally spaced levels, which may cause the sampling point to not coincide with the true zero crossing point, and the interference point data will produce sampling position error.

[0050] Figure 2 This is a schematic diagram of the high-precision zero-crossing sampling process provided by the present invention. Figure 2 In the illustrated embodiment, the linear interpolation zero-crossing method is used to approximate the line connecting two adjacent sampling data points at a high sampling rate as a straight line for calculation. The information from the two points is used to construct a linear equation to calculate the zero-crossing point of the laser interference signal. Specifically, after analog-to-digital conversion of the laser interference reference signal, the corresponding curve (e.g., ...) is obtained. Figure 2(The sine curve in the image); For infrared radiation interference signals, after analog-to-digital conversion, the number of infrared interference data points is increased due to the linear interpolation method. In order to maintain the equal interval of the data as much as possible, this embodiment uses a cubic spline interpolation method based on FPGA to supplement the data points between the existing discrete infrared interference data points. Through experiments, it was found that cubic spline interpolation is easier to achieve continuity, the data is smoother, and it is less likely to oscillate linearly.

[0051] Specifically, this embodiment uses the parallel Thomas split algorithm to solve the tridiagonal linear equations in cubic spline interpolation. By utilizing parallel computing and pipelined structure, the execution efficiency is greatly improved, resource consumption is reduced, and it is more suitable for the hardware characteristics of FPGA.

[0052] It should be noted that CCDs and dedicated ADCs for imaging front-ends typically do not have timestamp functionality or synchronization signal pins, making it impossible to use timestamps or the chip's built-in synchronization function for synchronous sampling. The multi-channel ADC data acquisition and synchronization module designed in this embodiment uses a high-precision GPS timing module, where the FPGA adds high-precision satellite time information to the acquired AD data points and adds a delay to achieve multi-channel signal synchronization.

[0053] Figure 3 This is a schematic diagram of the pipeline implementation architecture of the multi-ADC sampling data processing algorithm provided by the present invention. Figure 3 In the illustrated embodiment, the corresponding interpolation execution process, in the order of implementation, includes: taking the infrared radiation interferometric signal sampling data as input, and performing the following processing through the tridiagonal linear equation system solving module: parallel elimination, constructing a reduced tridiagonal linear equation system, solving the reduced tridiagonal linear equation system, distributing the solutions of the reduced tridiagonal linear equation system, and back-substituting to find all remaining solutions; then inputting the solution results into the coefficient cache module (which stores RAM-coefficients 1-3), and then querying through the interpolation interval query module, and outputting the corresponding interpolation results.

[0054] The Fourier transform spectrometer synchronous data acquisition device provided in this embodiment of the invention amplifies multiple interference signals synchronously through an interference signal conditioning module 100 to obtain amplified multi-source interference signals. A clock management module 200 fans out and buffers an adjustable sampling clock signal to obtain a multi-channel ADC sampling clock signal. A multi-channel ADC sampling module 300 samples the amplified multi-source interference signals synchronously according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data. Finally, a main control FPGA module 400 buffers the multi-channel interference signal sampling data and sequentially performs adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing processing on the multi-channel interference signal sampling data to obtain framed interference data. This device enables distributed multi-channel synchronous infrared interference signal acquisition for ADCs without synchronization interfaces or timestamp functions, improving the reliability of data acquisition by multi-channel Fourier transform spectrometers.

[0055] In some embodiments, the interference signal conditioning module 100 includes: a low-noise bias circuit 110 for acquiring a low-noise DC bias voltage; a current-to-voltage conversion circuit 120 for converting multiple interference signals into voltage signals using the noise DC bias voltage as a common-mode input voltage; a T-type resistor feedback operational amplifier circuit 130 for performing low-noise amplification processing on the voltage signals using the noise DC bias voltage as a common-mode input voltage to obtain amplified multi-source interference signals; the current-to-voltage conversion circuit 120 and the T-type resistor feedback operational amplifier circuit 130 are connected by RC coupling; and an output voltage follower circuit 140 with high input impedance and low output impedance.

[0056] Figure 4 This is a schematic diagram of the structure of the interference signal conditioning module provided by the present invention. Figure 4 In the illustrated embodiment, the low-noise bias circuit provides a suitable bias voltage for the normal operation of the interference photodetector (such as a mercury cadmium telluride detector). The mercury cadmium telluride detector inputs the detected interference signal to the subsequent modules for processing in sequence, and the output voltage follows the module to output the corresponding conditioned signal.

[0057] The low-noise bias circuit 110 uses active filtering bandwidth compression technology based on transistor circuits to reduce noise in the DC power supply.

[0058] In this embodiment, the output voltage follower circuit 140 can be built using an NPN transistor with low power consumption, good current characteristics and high gain. The output voltage follower circuit 140 has a high input impedance, which can reduce the loss of input signal and consume less power, thus achieving voltage following.

[0059] Since the interference infrared signal output by the detector is very weak and is affected by background noise, in order to meet the high gain requirement of the preamplifier circuit, this embodiment adopts a multi-stage amplification circuit. The first stage uses a compensated differential circuit (i.e., current-to-voltage conversion circuit 120) to complete the current-to-voltage conversion, and the second stage uses a T-type resistor feedback operational amplifier circuit 130 to achieve low-noise amplification.

[0060] Specifically, to improve circuit performance, this embodiment can select a low-noise, high-precision operational amplifier. The second-stage circuit uses a low-noise, low-temperature-drift operational amplifier. The two-stage operational amplifiers are coupled by resistors and capacitors to keep their static operating states independent of each other, while further filtering out DC signal interference.

[0061] The synchronous data acquisition device for a Fourier transform spectrometer provided in this embodiment of the invention acquires a low-noise DC bias voltage through a low-noise bias circuit 110, converts multiple interference signals into voltage signals through a current-to-voltage conversion circuit 120, and performs low-noise amplification processing on the voltage signals through a T-type resistor feedback operational amplifier circuit 130 to obtain amplified multi-source interference signals. The interference signal conditioning module 100 can provide the Fourier transform spectrometer with high-quality, low-noise, and high-amplitude analog signals. The use of the low-noise pre-interference signal conditioning module 100 improves the instrument's signal-to-noise ratio, thereby improving the accuracy and reliability of spectral analysis.

[0062] In some embodiments, the Fourier transform spectrometer synchronous data acquisition device further includes a communication module 500, which transmits the framed interference data to the host computer via at least one of Ethernet communication or RS422 protocol communication.

[0063] In this embodiment, the framed interference data refers to the data processed and packaged by the main control FPGA, which includes the sampled values ​​of the multi-channel interference signals, timestamps, and other information.

[0064] In this embodiment, Ethernet communication refers to data transmission using an Ethernet interface. Ethernet communication has advantages such as high transmission speed and high reliability, making it suitable for transmitting large amounts of data.

[0065] In this embodiment, RS422 protocol communication refers to data transmission using the RS422 interface. RS422 is a differential serial communication protocol with advantages such as strong anti-interference capability and long transmission distance.

[0066] In this embodiment, the host computer refers to the software running on a computer, which is used to receive, process, and analyze the data collected by the Fourier transform spectrometer.

[0067] This embodiment can use Ethernet communication. The main control FPGA integrates Ethernet MAC and TCP / IP protocol stacks, which can package the framed interferometric data according to the TCP protocol and send it to the host computer via the gigabit Ethernet interface. The host computer runs a TCP server to receive data from the Fourier transform spectrometer and perform analysis and processing.

[0068] The interference signals, after synchronous processing, are framed according to a protocol and sent to the host computer via a gigabit Ethernet port. The framing uses the TCP protocol and a timed transmission mechanism. Each frame contains device status information and measurement data. The device status information includes temperature and humidity measurements, moving mirror scanning speed, motor operating status, and other component status parameters, enabling the host computer to monitor the device status in real time and assisting the backend in correcting the interference data based on the device status. The measurement data frame contains multi-channel infrared interference signal sampling data, with each channel distinguished by a different channel ID number. An XMODEM checksum is added to the end of the frame. If a data error occurs during transmission, the host computer issues a command, and the main controller retrieves the corresponding interference data from the buffer and retransmits it.

[0069] The Fourier transform spectrometer synchronous data acquisition device provided in this embodiment of the invention, by setting a communication module 500 to send framed interference data to a host computer through at least one of network port communication or RS422 protocol communication, can provide stable, reliable and flexible data transmission for the Fourier transform spectrometer, and further improve the efficiency and reliability of spectral analysis.

[0070] In some embodiments, the communication module 500 is further configured to: verify each frame and each byte in the framed interferometric data when transmitting data using the RS422 protocol.

[0071] In this embodiment, the RS422 communication module 500 is used to complete the communication task between the main control FPGA chip and the host computer. In order to improve the reliability of communication, this embodiment has formulated a communication protocol between the main control chip and the host computer. Each frame of data in the communication process contains verification information, and each byte is also verified during transmission.

[0072] Specifically, assuming a data frame contains 100 bytes, each byte can be parsed, and a 16-bit CRC checksum can be added to the end of the frame. Before sending data, the main FPGA calculates the parity bit for each byte and adds it to the end of the byte. Then, it calculates the CRC checksum for the entire frame (including the parity bit) and adds it to the end of the frame. After receiving the data, the host computer first checks the parity bit of each byte. If an error is found, the byte is discarded. Then, it recalculates the CRC checksum for the entire frame and compares it with the received checksum. If the two checksums do not match, the entire frame is discarded.

[0073] The Fourier transform spectrometer synchronous data acquisition device provided in this embodiment of the invention verifies each frame and each byte of the framed interferometric data when transmitting data using the RS422 protocol. The verification mechanism can detect errors caused by noise interference, enhance the device's anti-interference capability, and thus improve the device's stability and reliability.

[0074] In some embodiments, the Fourier transform spectrometer synchronous data acquisition device further includes a power supply module 600, which includes a digital power supply and an analog power supply, and the digital power supply and the analog power supply are isolated from each other; the digital power supply supplies power to the module corresponding to the analog signal, and the digital power supply supplies power to the module corresponding to the digital signal.

[0075] In this embodiment, the digital power supply provides power to digital circuits (such as FPGAs, memories, etc.). Digital power supplies typically have lower requirements for voltage accuracy and ripple noise, but higher requirements for load transient response.

[0076] In this embodiment, the analog power supply is the power source for analog circuits (such as ADCs, operational amplifiers, etc.); the analog power supply has high requirements for voltage accuracy, ripple noise and isolation to ensure the quality of analog signals.

[0077] In this embodiment, the digital power supply and analog power supply are electrically isolated to prevent noise generated by the digital circuit from coupling to the analog circuit through the power line and affecting the quality of the analog signal. Specifically, this isolation design can be achieved through devices such as transformers and optocouplers.

[0078] It should be noted that, for mixed-signal circuits, in order to ensure normal system operation, avoid electromagnetic interference, and improve the signal-to-noise ratio and other performance characteristics of the Fourier transform spectrometer, this embodiment places the signal conditioning module and the back-end acquisition and processing module on two separate boards. The ground lines of the analog power supply and the digital power supply are bridged through inter-board connectors, so that the analog and digital power supplies have the same reference plane. The remaining circuits do not overlap, ensuring the independence of digital and analog signals and avoiding crosstalk.

[0079] In addition, the digital power supply section adopts a star connection, with all digital power supplies converging on the signal acquisition and processing board. The external 12V power supply is transformed on the board to generate various power supplies such as 3.3V, 1.5V, 1.8V, and 1.0V. Since the signal acquisition and processing board contains the analog power supply for the ADC, the digital and analog power supplies are also separated on this board. The digital chips and their power regulation devices are concentrated in the same area, while the analog power supply and analog signals are concentrated at the edge of the board to ensure their independence.

[0080] Figure 5 This is a schematic diagram of power distribution and layout provided by the present invention. Figure 5 In the illustrated embodiment, the multi-channel signal conditioning board includes multiple identical structures (AD797 op-amp, PO37 op-amp, and voltage follower). Figure 5 The electronics section is divided into three parts: a power management board, a multi-channel signal conditioning board, and a signal acquisition and processing board. The input power supply for this invention is 28V. The power management board is responsible for converting 28V to ±15V and 12V to power the multi-channel signal conditioning board and the signal acquisition and processing board, enabling independent distribution of multiple voltage outputs and integrating power protection functions to prevent hardware damage. Specifically, to avoid reverse polarity connection by the user, suppress instantaneous overvoltage and overcurrent surges in the power supply line, and mitigate the risk of circuit burnout due to excessively high or insufficient input voltage, reverse connection protection, surge protection, and over / under voltage protection are implemented after the 28V input voltage. One ±15V power supply powers the multi-channel signal conditioning board, one 12V power supply powers the signal acquisition and processing board, one 12V power supply powers the Stirling refrigerator component in the Fourier Transform Infrared Spectrometer (FTIR), and one 12V power supply powers the mercury cadmium telluride detector component in the FTIR. In the multi-channel signal conditioning board, the AD797 and OP37 act as preamplifiers, amplifying the weak infrared interference signal amplitude to match the input of the downstream AD acquisition circuit. A voltage follower acts as an isolation device to prevent interference from the downstream ADC circuit to the upstream signal. One structure (AD797 op-amp, OP37 op-amp, and voltage follower) corresponds to one infrared interference signal input, avoiding crosstalk between multiple signals. The core components of the signal acquisition and processing board are the AD9826 analog-to-digital converter and the ZYNQ main controller. One 12V supply is converted to 5V and 3.3V via LT1084 and TPS756 to power AD9826. Another 12V supply is converted to the voltage required for ZYNQ, DDR memory, crystal oscillator, and clock distribution device ADCLK948 via multiple DC-DC voltage converters such as LT1084 and TS56121.

[0081] The Fourier transform spectrometer synchronous data acquisition device provided in this embodiment of the invention includes a power supply module comprising a digital power supply and an analog power supply, with the digital power supply and analog power supply being isolated from each other; the digital power supply powers the module corresponding to the analog signal, and the analog power supply powers the module corresponding to the digital signal, thereby reducing electromagnetic interference through reasonable power supply allocation and layout.

[0082] Figure 6 This is the second schematic diagram of the structure of the synchronous data acquisition device for the Fourier transform spectrometer provided by the present invention. Figure 6 In the illustrated embodiment, the interference signal conditioning module includes multiple identical conditioning structures, such as a laser detector (for detecting laser signals), a cross-group + operational amplifier, and a two-stage amplifier; a mercury cadmium telluride detector (for infrared interference signal channel 1), a cross-group + operational amplifier, and a two-stage amplifier; and a mercury cadmium telluride detector (for infrared interference signal channel N), a cross-group + operational amplifier, and a two-stage amplifier. The data sampling module includes a high sampling rate analog-to-digital converter module with the same number of identical conditioning structures. The main control chip (corresponding to the main control FPGA) sequentially adapts the multi-channel ADC sampling clock signals output by the high sampling rate analog-to-digital converter module. The process involves filtering, high-precision zero-crossing detection, pipelined interpolation, adding timestamps, and data framing. The framed interference data is then sent to the host computer via Ethernet or RS422 communication. The adjustable sampling clock generation unit in the main control chip generates an adjustable sampling clock signal and sends the corresponding multi-channel ADC sampling clock signal to the data sampling module via clock allocation. In this embodiment, a high-precision timing module adds timestamps to the signals processed by the main control chip, and a temperature and humidity sensor provides state measurements for the signals processed by the main control chip for data framing. The raw data is then cached in an SD Card (memory card). Additionally, a stable clock signal generated by a crystal oscillator serves as the input clock source for the MMCM, ensuring that the MMCM can generate a precise clock signal at the required frequency. QSPI Flash is a non-volatile memory used to store FPGA configuration files (bitstream) and other data that needs to be stored long-term. DDR3 (Double Data Rate 3) is a type of synchronous dynamic random access memory that operates synchronously with the system clock, thereby improving data transfer speed.

[0083] The control method of the synchronous data acquisition device for a Fourier transform spectrometer provided by the present invention will be described below. The control method of the synchronous data acquisition device for a Fourier transform spectrometer described below can be referred to in correspondence with the synchronous data acquisition device for a Fourier transform spectrometer described above.

[0084] Figure 7 This is a flowchart illustrating the control method of the synchronous data acquisition device for a Fourier transform spectrometer provided by the present invention, as shown below. Figure 7As shown, the control method for the synchronous data acquisition device of the Fourier transform spectrometer includes the following steps: Step 710: The multi-channel interference signals are synchronously amplified using the interference signal conditioning module to obtain the amplified multi-source interference signal.

[0085] In this step, the multi-channel interference signal can be a signal acquired by different interference photodetectors. For example, the multi-channel interference signal includes a laser signal detected by a laser detector and infrared interference signal lamps from different channels detected by a mercury cadmium telluride detector.

[0086] In this embodiment, the interference signal conditioning module completes the analog front-end processing of the interference optical signal, which includes reasonable gain and level adjustment; the purpose of signal conditioning is to make full use of the dynamic range of the ADC (Analog-to-Digital Converter).

[0087] Specifically, in order to ensure the synchronization between multiple channels, different signals in this embodiment share the same signal conditioning circuit.

[0088] In this implementation, the same path is used for each channel in the interference signal conditioning module, and the path consistency is maintained in the design of the corresponding PCB (Printed Circuit Board).

[0089] In this embodiment, the amplification process of the interference signal conditioning module can be a two-stage amplification process, which helps to make full use of the ADC dynamic range while reducing noise interference and improving the signal-to-noise ratio.

[0090] Step 720: The adjustable sampling clock signal is fanned out and buffered through the clock management module to obtain the multi-channel ADC sampling clock signal.

[0091] In this step, the adjustable sampling clock signal refers to a clock signal whose frequency can be adjusted as needed. Specifically, in a Fourier transform spectrometer, the sampling frequency is closely related to the movement speed of the moving mirror. The adjustable sampling clock signal can adapt to different moving mirror speeds, thereby achieving the best spectral resolution.

[0092] In this embodiment, the clock management module copies the compliant CDS clock signal and ADC clock signal generated by the FPGA into multiple clock signals with the same frequency and phase. In multi-channel applications, using a crystal oscillator for clock signal copying would increase board size and system cost. This invention generates the sampling clock using the main control FPGA, which has the advantage of flexible clock frequency adjustment.

[0093] Specifically, in this embodiment, the single-ended sampling clock is converted into a differential clock via a balun transformer and then distributed to each ADC via a clock fan-out distribution chip. The clock fan-out distribution chip has a maximum output frequency of 4.8GHz, a random jitter average of only 28fs, and 8 output channels, which can ensure the synchronization of the multi-channel sampling clock.

[0094] In addition, the clock management module can enhance the driving capability of multiple ADC chips by fan-out buffering the adjustable sampling clock signal, thereby ensuring that each ADC chip can obtain a high-quality clock signal.

[0095] Step 730: The multi-channel ADC sampling module synchronously samples the amplified multi-source interference signal according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data.

[0096] In this step, the sampling clock signal is the timing signal that controls the ADC sampling process. Each clock cycle triggers one sampling, which determines the sampling frequency. The multi-channel ADC sampling module requires a synchronous multi-channel sampling clock signal to ensure that all channels are sampled at the same time, thereby achieving data synchronization.

[0097] In this embodiment, the amplified multi-source interference signal refers to the analog signal processed by the interference signal conditioning module. These signals come from the detector output after interference from multiple light sources and contain spectral information.

[0098] In one embodiment, the multi-channel ADC sampling module adopts a three-channel architecture, with each channel consisting of an input clamping circuit, a correlated dual sampler, an offset DAC, and a programmable gain amplifier. Each channel is connected to a high-performance 16-bit analog-to-digital converter (ADC) via multiplexing.

[0099] In this embodiment, the selected analog-to-digital converter adopts a three-channel architecture design for sampling and conditioning the output of the three-line color CCD array. Each channel consists of an input clamping circuit, a correlated dual sampler (CDS), an offset DAC, and a programmable gain amplifier (PGA), and is connected to a high-performance 16-bit ADC through multiplexing. Its single-channel 16-bit maximum sampling rate can reach 12.5 MSPS, and the three-channel 16-bit maximum sampling rate can reach 15 MSPS.

[0100] Step 740: The main control FPGA module caches the multi-channel interference signal sampling data and sequentially performs adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing on the multi-channel interference signal sampling data to obtain framed interference data; the main control FPGA module is also used to generate an adjustable sampling clock signal.

[0101] In this step, the main control FPGA chip integrates two ARM processors, internal memory, external memory interface and peripherals.

[0102] In this embodiment, the interference signal sampling data after analog-to-digital conversion needs to be cached after entering the FPGA before it can be processed synchronously. This embodiment uses a DDR3 high-speed data cache chip with a storage capacity of 4Gb, consisting of 16 256Mbit areas, and the data read rate can reach 1600 / 1866Mbps.

[0103] In this embodiment, the Fourier transform spectrometer synchronous data acquisition device also has two functions: high-precision zero-crossing detection and adding high-precision timestamps.

[0104] Specifically, since ADC inevitably introduces errors during the quantization process, the input signal is divided into N equally spaced levels, which may cause the sampling point to not coincide with the true zero crossing point, and the interference point data will produce sampling position error.

[0105] Based on this, this embodiment adopts the linear interpolation zero-crossing method, which approximates the line connecting two adjacent sampling data points at a high sampling rate as a straight line for calculation, and uses the information of the two points to construct a straight line equation, thereby calculating the zero-crossing point of the laser interference signal. Since the linear interpolation method increases the number of infrared interference data points, in order to maintain the equal interval of the data as much as possible, this embodiment uses a cubic spline interpolation method based on FPGA to supplement the data points between the existing discrete infrared interference data points. Through experiments, it was found that cubic spline interpolation is easier to achieve continuity, the data is smoother, and it is less prone to oscillating linearity.

[0106] Specifically, this embodiment uses the parallel Thomas split algorithm to solve the tridiagonal linear equations in cubic spline interpolation. By utilizing parallel computing and pipelined structure, the execution efficiency is greatly improved, resource consumption is reduced, and it is more suitable for the hardware characteristics of FPGA.

[0107] The multi-channel ADC data acquisition and synchronization module designed in this embodiment achieves multi-channel signal synchronization by configuring a high-precision GPS timing module, which allows the FPGA to add high-precision satellite time information to the acquired AD data points and add a delay.

[0108] The control method for the synchronous data acquisition device of the Fourier transform spectrometer provided in this invention involves amplifying multiple interference signals synchronously through an interference signal conditioning module to obtain amplified multi-source interference signals, fanning out and buffering an adjustable sampling clock signal through a clock management module to obtain a multi-channel ADC sampling clock signal, and synchronously sampling the amplified multi-source interference signals according to the multi-channel ADC sampling clock signal through a multi-channel ADC sampling module to obtain multi-channel interference signal sampling data. Finally, the multi-channel interference signal sampling data is cached by the main control FPGA module, and adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing are sequentially performed on the multi-channel interference signal sampling data to obtain framed interference data. This method enables distributed multi-channel synchronous infrared interference signal acquisition for ADCs that do not have a synchronization interface or timestamp function, thereby improving the reliability of data acquisition by the multi-channel Fourier transform spectrometer.

[0109] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 880, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 880 communicate with each other through the communications bus 840. The processor 810 can call logic instructions in the memory 880 to execute the control method of the Fourier transform spectrometer synchronous data acquisition device. The method includes: synchronously amplifying multiple interference signals through an interference signal conditioning module to obtain amplified multi-source interference signals; fanning out and buffering an adjustable sampling clock signal through a clock management module to obtain a multi-channel ADC sampling clock signal; synchronously sampling the amplified multi-source interference signals according to the multi-channel ADC sampling clock signal through a multi-channel ADC sampling module to obtain multi-channel interference signal sampling data; buffering the multi-channel interference signal sampling data through a main control FPGA module, and sequentially performing adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing processing on the multi-channel interference signal sampling data to obtain framed interference data; wherein, the main control FPGA module is also used to generate the adjustable sampling clock signal.

[0110] Furthermore, the logical instructions in the aforementioned memory 880 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0111] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the control method of the Fourier transform spectrometer synchronous data acquisition device provided by the above methods. The method includes: synchronously amplifying multiple interference signals through an interference signal conditioning module to obtain amplified multi-source interference signals; fanning out and buffering an adjustable sampling clock signal through a clock management module to obtain a multi-channel ADC sampling clock signal; synchronously sampling the amplified multi-source interference signals according to the multi-channel ADC sampling clock signal through a multi-channel ADC sampling module to obtain multi-channel interference signal sampling data; buffering the multi-channel interference signal sampling data through a main control FPGA module, and sequentially performing adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing processing on the multi-channel interference signal sampling data to obtain framed interference data; wherein, the main control FPGA module is also used to generate the adjustable sampling clock signal.

[0112] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements a control method for the synchronous data acquisition device of the Fourier transform spectrometer provided by the above methods. The method includes: synchronously amplifying multiple interference signals through an interference signal conditioning module to obtain amplified multi-source interference signals; fanning out and buffering an adjustable sampling clock signal through a clock management module to obtain a multi-channel ADC sampling clock signal; synchronously sampling the amplified multi-source interference signals according to the multi-channel ADC sampling clock signal through a multi-channel ADC sampling module to obtain multi-channel interference signal sampling data; buffering the multi-channel interference signal sampling data through a main control FPGA module, and sequentially performing adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing processing on the multi-channel interference signal sampling data to obtain framed interference data; wherein the main control FPGA module is also used to generate the adjustable sampling clock signal.

[0113] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0114] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A synchronous data acquisition device for a Fourier transform spectrometer, characterized in that, include: The interference signal conditioning module is used to synchronously amplify multiple interference signals to obtain amplified multi-source interference signals. The clock management module is used to fan out and buffer the adjustable sampling clock signal to obtain the multi-channel ADC sampling clock signal; A multi-channel ADC sampling module is used to synchronously sample the amplified multi-source interference signal according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data. The main control FPGA module is used to cache the multi-channel interference signal sampling data and sequentially perform adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition and data framing on the multi-channel interference signal sampling data to obtain framed interference data; wherein, the main control FPGA module is also used to generate the adjustable sampling clock signal.

2. The synchronous data acquisition device for a Fourier transform spectrometer according to claim 1, characterized in that, The interference signal conditioning module includes: A low-noise bias circuit is used to obtain a low-noise DC bias voltage; A current-to-voltage conversion circuit is used to convert the multi-channel interference signal into a voltage signal using the noise DC bias voltage as the common-mode input voltage; The T-type resistor feedback operational amplifier circuit is used to amplify the voltage signal with low noise using the noise DC bias voltage as the common-mode input voltage to obtain the amplified multi-source interference signal; the current-to-voltage conversion circuit and the T-type resistor feedback operational amplifier circuit are connected by RC coupling. The output voltage follower circuit features high input impedance and low output impedance.

3. The synchronous data acquisition device for a Fourier transform spectrometer according to claim 1, characterized in that, The device further includes: The communication module transmits the framed interference data to the host computer via at least one of network port communication or RS422 protocol communication.

4. The synchronous data acquisition device for a Fourier transform spectrometer according to claim 3, characterized in that, The communication module is also used for: When transmitting data using the RS422 protocol, each frame and each byte in the framed interference data is verified.

5. The synchronous data acquisition device for a Fourier transform spectrometer according to claim 1, characterized in that, The device further includes: The power supply module includes a digital power supply and an analog power supply, wherein the digital power supply and the analog power supply are isolated from each other; the digital power supply supplies power to the module corresponding to the analog signal, and the analog power supply supplies power to the module corresponding to the digital signal.

6. The synchronous data acquisition device for a Fourier transform spectrometer according to claim 1, characterized in that, The multi-channel ADC sampling module adopts a three-channel architecture. Each channel consists of an input clamping circuit, a correlated dual sampler, an offset DAC, and a programmable gain amplifier. Each channel is connected to a high-performance 16-bit analog-to-digital converter (ADC) through multiplexing.

7. A control method for a synchronous data acquisition device for a Fourier transform spectrometer, characterized in that, include: The multi-source interference signal is amplified synchronously by the interference signal conditioning module to obtain the amplified multi-source interference signal. The adjustable sampling clock signal is fanned out and buffered by the clock management module to obtain the multi-channel ADC sampling clock signal; The multi-channel ADC sampling module synchronously samples the amplified multi-source interference signal according to the multi-channel ADC sampling clock signal to obtain multi-channel interference signal sampling data. The main control FPGA module caches the multi-channel interference signal sampling data and sequentially performs adaptive filtering, zero-crossing detection, difference reconstruction, timestamp addition, and data framing on the multi-channel interference signal sampling data to obtain framed interference data; wherein, the main control FPGA module is also used to generate the adjustable sampling clock signal.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the control method of the synchronous data acquisition device for the Fourier transform spectrometer as described in claim 7.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the control method of the synchronous data acquisition device of the Fourier transform spectrometer as described in claim 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the control method of the synchronous data acquisition device of the Fourier transform spectrometer as described in claim 7.

Images