Time-to-digital converter based on magnetic track memory

Abstract

The invention relates to the technical field of time-to-digital converters, and provides a time-to-digital converter based on a magnetic track memory, comprising: a magnetic track memory array having m rows and n columns of units, each unit representing a magnetic nanowire, all units in each row sharing the same word line, all units in each column share one writing bit line and one reading bit line; an output port of the word line driver is connected with a word line input port of the magnetic track memory array; an output port of the write-in and reset controller is connected with a write bit line input port of the magnetic track memory array; the input port of the SA array is connected with the read bit line output port of the magnetic track memory array; and the storage controller is used for generating a control signal and pulse current. The time-to-digital converter has the functions of time-to-digital signal conversion and nonvolatile storage, can realize high-precision time measurement and reliable storage, and is convenient to construct a large-scale time-to-digital converter array.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time-to-digital converter, and particularly relates to a time-to-digital converter based on a magnetic racetrack memory. BACKGROUND

[0002] With the rapid development of fields such as laser radar, sensor network, medical equipment and quantum communication, the demand for high-precision measurement and reliable storage of time information is increasing. The time measurement resolution required by these fields is usually less than 1 ns, and at the same time, an economic solution with high precision, small size, low cost and commercialization is often required. In order to solve this problem, a time-to-digital converter (TDC) emerges as the times require.

[0003] The design methods of time-to-digital converter generally have technical solutions such as tapped delay line method, NUTT interpolation method, vernier delay line method and multi-chain average method. Although the time resolution of some solutions can reach very high technical indicators, there are still disadvantages such as serious nonlinearity, large resource overhead and low throughput. That is, the existing time-to-digital converter has a trade-off between power consumption and resolution, speed and complexity, and it is difficult to achieve all ideal characteristics at the same time. At the same time, the resolution of the vernier TDC depends on the delay of the inverter, so it depends on the change of the external environment, and it is difficult to have stable high resolution. These factors are not conducive to the construction of large-scale, parallel and instant time-to-digital converter. In addition, in complex application scenarios, modern TDC generally needs internal cache to temporarily store measurement data, and for long-term storage and processing of a large amount of data, TDC usually needs additional external storage circuit, which further increases the area and power consumption overhead of the circuit. SUMMARY

[0004] The present application aims at the deficiencies of the traditional time-to-digital converter (TDC), and provides a time-to-digital converter based on a magnetic racetrack memory, which has the functions of time-to-digital signal conversion and non-volatile storage, can realize high-precision time measurement and reliable storage, has the advantages of small area overhead, simple structure, strong scalability and low power consumption, so as to facilitate the construction of large-scale time-to-digital converter array at the same time.

[0005] In order to achieve the above application purpose, the embodiments of the present application provide the following technical solutions:

[0006] A time-to-digital converter based on a magnetic racetrack memory, comprising:

[0007] A magnetic racetrack memory array has m rows and n columns of units, each unit represents a magnetic nanowire, and all units in each row share the same word line, and all units in each column share a write bit line and a read bit line.

[0008] a word line driver having m output ports, each output port being connected to a word line input port of the magnetic racetrack memory array one by one;

[0009] a write and reset controller having n output ports, each output port being connected to a write bit line input port of the magnetic racetrack memory array one by one;

[0010] an SA array having n input ports, each input port being connected to a read bit line output port of the magnetic racetrack memory array one by one;

[0011] a storage controller connected to the word line driver, the SA array and the output data selector, for generating control signals and pulse currents to control the operation of the magnetic racetrack memory array;

[0012] an output data selector connected to the output ports of the SA array, for realizing serial output of data according to the control signals of the storage controller.

[0013] In the above scheme, the data is stored immediately after the time-to-digital conversion is completed by taking advantage of the non-volatility of the magnetic racetrack memory, thus eliminating the need for additional memory, saving the time for data storage and without additional area overhead.

[0014] Further, each of the magnetic nanowires includes 2 n magnetic domains, 1 write MTJ head and 1 read MTJ head.

[0015] In the above scheme, the total area of the magnetic racetrack memory array increases linearly with the number of data bits, rather than exponentially, because adding one bit only requires one additional magnetic nanowire and peripheral circuit on the bit line.

[0016] Further, the storage controller applies the same horizontal shift pulse current I Shift to each of the magnetic nanowires.

[0017] When the horizontal shift pulse current I Shift is high, the magnetic domain wall moves by the distance of one magnetic domain, and the moving direction of the magnetic domain is opposite to the direction of the horizontal shift pulse current I Shift .

[0018] When the horizontal shift pulse current I Shift is low, the storage controller applies a write pulse current I write to the write MTJ head, thereby writing data to the corresponding magnetic domain.

[0019] Further, if the storage controller applies a forward write pulse current I write to the write MTJ head., the magnetic domain at the position of the write MTJ head is magnetized downward, and the corresponding magnetic domain is written with data 0; if the storage controller applies a reverse write pulse current I write , the magnetic domain at the position of the write MTJ head is magnetized upward, and the corresponding magnetic domain is written with data 1.

[0020] Further, the storage controller applies a measurement current I read to the read MTJ head, and the SA array collects the resistance value of the read MTJ head, thereby reading the data written in the corresponding magnetic domain.

[0021] Further, if the magnetic domain at the position of the read MTJ head is magnetized in the opposite direction of the read MTJ head, the SA array collects a high resistance, and data 0 is read at this time; if the magnetic domain at the position of the read MTJ head is magnetized in the same direction as the read MTJ head, the SA array collects a low resistance, and data 1 is read at this time.

[0022] Further, the storage controller applies the same horizontal reset pulse current I reset to each magnetic nanowire, and the horizontal reset pulse current I reset is opposite to the direction of the horizontal shift pulse current I Shift , so as to move the magnetic domain wall back to the original position.

[0023] Compared with the prior art, the application has the beneficial effects:

[0024] (1) The application utilizes the non-volatile storage feature of the magnetic racetrack memory, and stores the data immediately after the time-to-digital conversion is completed, thereby eliminating the need for additional memory, saving the time for data storage without additional area overhead.

[0025] (2) The magnetic racetrack memory utilized by the application belongs to a spintronic device, which is a high-density, low-power device, so that the time-to-digital converter of the magnetic racetrack memory has the characteristics of low static power consumption and small area. At the same time, the total area of the magnetic racetrack memory array increases linearly with the number of data bits, rather than exponentially, because adding one bit only requires an additional magnetic nanowire and peripheral circuit on the bit line.

[0026] (3) The magnetic racetrack memory array structure proposed by the application is simple and small in area, and is very convenient to integrate on other circuit modules, and has strong expansibility. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0028] Figure 1 The schematic diagram of the architecture of the time-to-digital converter of the present application;

[0029] Figure 2 The schematic diagram of the structure of a magnetic nanowire and two MTJ magnetic heads respectively as read and write in the embodiment 2 of the present application;

[0030] Figure 3 The schematic diagram of the magnetic nanowire configuration process of the time-to-digital converter of the n-bit magnetic racetrack memory in the embodiment 2 of the present application;

[0031] Figure 4 The schematic diagram of the time-to-digital conversion process of the time-to-digital converter of the n-bit magnetic racetrack memory in the embodiment 2 of the present application;

[0032] Figure 5 The schematic diagram of the reset process of the time-to-digital converter of the n-bit magnetic racetrack memory in the embodiment 2 of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of the present application.

[0034] It should be noted that: similar labels and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance, or implying any such actual relationship or order between the entities or operations. In addition, the terms "connected", "connected", etc. can be direct connection between elements, components, modules, etc., or indirect connection via other elements, components, modules, etc.

[0035] Embodiment 1:

[0036] Racetrack Memory is a kind of non-volatile memory, including magnetic nanowire racetrack connected by circuit and corresponding reading device and writing device, using the movement of magnetic domain wall (DW) in magnetic material to store data, with extremely fast access speed, low power consumption, high density and other characteristics. The scheme is based on the current-induced magnetic domain wall (DW) motion in racetrack memory to design a time-to-digital converter, and proposes a time-to-digital converter (TDC) of n-bit racetrack memory.

[0037] It should be noted that the magnetic nanowire in the racetrack memory is a one-dimensional magnetic material structure, usually made of ferromagnetic metal (such as cobalt, nickel, iron alloy), with a size of nanometer scale (width and thickness of several tens of nanometers, length up to micrometer level), as a physical carrier for data storage. Magnetic domain refers to the directionally different small magnetization area divided in the process of spontaneous magnetization of magnetic material to reduce static magnetic energy, each area contains a large number of atoms, the magnetic moments of these atoms are arranged like small magnets, but the direction of atomic magnetic moment arrangement is different between adjacent different areas. The interface between each magnetic domain is called magnetic domain wall. The magnetic domains in the magnetic nanowire are arranged in an array to form a track-like track, and the magnetic domain wall can be driven to move by current, so as to realize the reading and writing of data. The magnetization direction of each magnetic domain represents a binary bit (such as "0" or "1"), and by applying a spin-polarized current, the magnetic domain wall can move along the magnetic nanowire, so that the data is oriented to be transmitted to the reading and writing head position for operation like a racing car sliding on a racetrack. This design allows high-density storage and combines the advantages of non-volatility, high speed and durability.

[0038] The application is realized by the following technical scheme, a time-to-digital converter based on racetrack memory is a time-to-digital converter structure of n-bit racetrack memory, including n same magnetic nanowires.

[0039] As shown in Figure 2 Each magnetic nanowire includes a plurality of magnetic domains separated by magnetic domain walls (DW), and the magnetization direction of each magnetic domain can be switched, and different directions represent the stored binary state. Two ferromagnetic layers with fixed magnetization direction and an oxide layer are applied on the magnetic nanowire, wherein the ferromagnetic layer forms a write magnetic tunnel junction (write MTJ) with the magnetic domain of the magnetic nanowire, and the oxide layer forms a read magnetic tunnel junction (read MTJ) with the magnetic domain of the magnetic nanowire. The write MTJ changes the magnetization direction of the magnetic domain of the magnetic nanowire by a write pulse current I write to store binary information; the read MTJ changes the magnetization direction of the magnetic domain of the magnetic nanowire by a weak measurement pulse current I readDetecting the magnetization direction of magnetic nanowire domain storage to read the stored binary information.

[0040] When a pulse current is injected from one side of the magnetic nanowire, the polarized spin current will make the domain wall move on the magnetic nanowire. The distance of the domain wall movement is proportional to the pulse current duration (pulse width) when the pulse current intensity is constant. By configuring the magnetization direction of n magnetic nanowire domains in advance through the write MTJ, the domain wall movement caused by the pulse current with equal amplitude and unchanged pulse width can be converted into different n-bit binary data in parallel. The converted data is inherently stored by using the non-volatility of the magnetic racetrack memory, eliminating the need for additional memory cells. In this way, the time information (pulse width of the pulse current) is converted into a digital signal and stored, and the time resolution is equivalent to the pulse width of the pulse current required to move the domain wall by one domain distance.

[0041] As shown in Figure 1 , the magnetic racetrack memory-based time-to-digital converter includes a word line driver, a magnetic racetrack memory array, a storage controller, a write and reset controller, an SA array (sense amplifier), and an output data selector. The magnetic racetrack memory array is connected to the word line driver, the write and reset controller, and the SA array. The storage controller is connected to the word line driver, the SA array, and the output data selector. The SA array is connected to the output data selector.

[0042] The magnetic racetrack memory array has m rows and n columns of cells, and each cell represents a magnetic nanowire. All cells in each row of the magnetic racetrack memory array share the same word line (WL), and all cells in each column share a write bit line (WBL) and a read bit line (RBL). Each row of the magnetic racetrack memory array represents an n-bit binary data, so the m-row and n-column array can store m n-bit binary data. The row number of the magnetic racetrack memory array represents the data address, and the address bit number is log2m.

[0043] The number of output ports of the word line driver is m, which is the number of rows of the magnetic racetrack memory array. That is, the output ports of the word line driver are connected to the input ports of the word lines (WL) of the magnetic racetrack memory array one by one. The word line driver is used to receive the address signal from the storage controller and then activate a certain word line in the magnetic racetrack memory array.

[0044] The output port number of the write and reset controller is n, n is the column number of the magnetic racetrack memory array, that is, the output port of the write and reset controller is connected with the write bit line (WBL) input port of the magnetic racetrack memory array one by one. The write and reset controller is used for controlling data write operation and reset operation, and transmits input signals to the magnetic racetrack memory array through the write bit line (WBL).

[0045] The storage controller generates all necessary control signals and timing pulse currents to control the whole magnetic racetrack memory array.

[0046] The input port number of the SA array is n, n is the column number of the magnetic racetrack memory array, that is, the input port of the SA array is connected with the read bit line (RBL) output port of the magnetic racetrack memory array one by one. The SA array is used for detecting and amplifying the weak signal on the read bit line (RBL) and converting it into a clear and stable digital signal.

[0047] The input end of the output data selector is connected with the output end of the SA array, and the output data selector realizes functions such as serial output of data according to the control signal of the storage controller.

[0048] Embodiment 2:

[0049] This embodiment provides a magnetic racetrack memory architecture diagram based on the above-mentioned embodiment 1, Figure 2 is a structure diagram of one magnetic nanowire and two MTJ magnetic heads for reading and writing, as Figure 2 shown, the magnetization direction of the MTJ magnetic head is fixed. One magnetic nanowire is divided into multiple magnetic domains by a domain wall (DW), and a single data bit is stored as the magnetization direction of the magnetic domain. The domain wall can move along the magnetic nanowire by an induced horizontal shift pulse current I Shift . Given a write pulse current I write on the write MTJ, the spin-polarized current will exert a torque on the magnetization direction of the magnetic domain of the magnetic nanowire, thereby changing the magnetization direction of the magnetic domain and writing data information. At the same time, the horizontal shift pulse current I Shift can make the domain wall move along the magnetic nanowire (i.e., the magnetic domain storing data moves), and the moving direction of the domain wall is opposite to the direction in which the horizontal shift pulse current I Shift is applied, and the moving distance is related to the cross-sectional area of the magnetic nanowire, the intensity of I Shift , and the pulse width of I Shift . By alternately applying the write pulse current I write and the horizontal shift pulse current I Shift , the magnetic nanowire can store a sequence of domain walls.

[0050] The magnetization of the magnetic domains beneath the MTJ head is read by measuring the resistance value of the MTJ head; this resistance value is affected by the track magnetoresistance effect. Figure 2 As shown, when the magnetization direction of the magnetic domains of the magnetic nanowire is opposite to the direction of the MTJ reading head, the resistance is high, and the data read is recorded as "0"; when the magnetization direction of the magnetic domains of the magnetic nanowire is the same as the direction of the MTJ reading head, the resistance is low, and the data read is "1". Therefore, reading the MTJ is done by applying a weak measuring current I. read This is used to measure the resistance of the MTJ, thereby reading the data stored in the magnetic domains.

[0051] Figures 3 to 5 Give all the operations required for a time-to-digital converter based on an n-bit magnetic track memory to run a complete process.

[0052] (a) Magnetic nanowire configuration.

[0053] like Figure 3 As shown, the time-to-digital converter of an n-bit magnetic track memory requires n magnetic nanowires, each magnetic nanowire consisting of 2 n One magnetic domain, one read MTJ, and one write MTJ. Each magnetic nanowire is configured differently such that the output of each magnetic nanowire (detected by the read MTJ) represents one bit of n-bit data. When a positive write pulse current I is applied to the write MTJ... write At this time, the magnetic domains below the MTJ are magnetized downwards, indicating that the data "0" is being written; a negative write pulse current I is applied. write At this time, the magnetic domains below the MTJ are magnetized upwards, indicating that the data "1" is being written. Horizontal shift pulse current I Shift The direction is applied from the right end of the magnetic nanowire, flowing towards the left end of the magnetic nanowire, I Shift The amplitude and pulse width remain constant when I Shift When I is high, the domain wall moves to the right by one domain distance. Shift When it is low, according to I write The amplitude is written as data "0" or "1". This is achieved by applying a series of alternating write pulse currents I. write and horizontal shift pulse current I Shift After 2 n After one cycle, the corresponding configuration data can be stored one after another on the magnetic nanowire, ultimately forming an n-bit magnetic track memory time-to-digital converter. For example... Figure 3 As shown, BIT0~BIT n-1 Let each represent n magnetic nanowires, and for each magnetic nanowire, let each have a bit. i Apply the corresponding write pulse current I writei, i=0,1,...,n-1; Apply the same horizontal shift pulse current I to n magnetic nanowires simultaneously. Shift ;I writei and I Shift Current pulse Figure 3 As shown. Read MTJ from right to left. The rightmost column of domains represents 0, and the leftmost column of domains represents the maximum value of an n-bit binary number (i.e., 2 in decimal). n -1).

[0054] (ii) Time-to-digital conversion.

[0055] like Figure 4 As shown, each magnetic nanowire is subjected to the same input current I. in Flowing from right to left (equivalent to a horizontal shifting pulse current I) Shift (Due to the effect of this), in this situation, the magnetic domain walls move simultaneously from left to right. This is because of the input current I0 of each magnetic nanowire. in Since the migration distance of the domain walls is the same in different magnetic nanowires, the migration distance X of the domain walls can be expressed as:

[0056]

[0057] Where v represents the velocity of the domain wall, T represents the time of the domain wall's movement, and I Shift The horizontal shift pulse current is represented by Area, the cross-sectional area of ​​the magnetic nanowire is represented by Jth, the threshold current density is represented by β, the non-adiabatic coefficient is represented by μ, the Bohr magneton is represented by p, the spin polarization of the tunneling current is represented by α, the damping constant is represented by e, and the elementary charge is represented by M. s This indicates a demagnetizing field.

[0058] Control input time - I of the digital converter in If the amplitude is a fixed value, then the domain wall movement distance X is related to I. in The pulse width is linearly related to I. in The pulse width (i.e., time information) determines the distance the domain walls in the n magnetic nanowires move. The output of the n magnetic nanowires after conversion (detected by the MTJ reader) is the binary data output by the time-to-digital converter. When there is no horizontal shift current, the domain walls of the magnetic nanowires remain stationary; therefore, this binary data is stored in the magnetic track memory and can be read out at any time via the MTJ reader. It is easy to understand that the resolution of the measurement time is equivalent to the pulse width of the pulse current signal required to move the domain wall one domain distance.

[0059] (iv) Reset operation.

[0060] like Figure 5As shown, after time-to-digital conversion, a reset needs to be performed before time-to-digital conversion can be performed again. The reset operation is similar to the inverse operation of the time-to-digital conversion process. As shown Figure 5 As shown, the horizontal reset pulse current I reset From left to right through the magnetic nanowire to cause the magnetic domain wall from right to left to move, reset detection is performed by reading the MTJ, and once it is detected that all the data read out by the magnetic nanowire is 0, it is judged that all the magnetic domains have moved back to their original positions, and then the horizontal reset pulse current I reset is cut off, indicating that the reset phase has been completed.

[0061] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A time-to-digital converter based on a magnetic track memory, characterized in that, include: The magnetic track memory array has m rows and n columns of cells. Each cell represents a magnetic nanowire. All cells in each row share the same word line, and all cells in each column share a write bit line and a read bit line. The word line driver has m output ports, each of which is connected to a word line input port of the magnetic track memory array in a one-to-one correspondence. The write and reset controller has n output ports, each of which is connected to a corresponding write bit line input port of the magnetic track memory array. The SA array has n input ports, and each input port is connected to the read bit line output port of the magnetic track memory array in a one-to-one correspondence. The memory controller, connected to the word line driver, SA array, and output data selector, generates control signals and pulse currents to control the operation of the magnetic track memory array. The output data selector, connected to the output port of the SA array, is used to serially output data according to the control signals of the storage controller.

2. The time-to-digital converter based on a magnetic track memory according to claim 1, characterized in that, Each of the magnetic nanowires comprises 2 n One magnetic domain, one write MTJ head, and one read MTJ head.

3. The time-to-digital converter based on a magnetic track memory according to claim 2, characterized in that, The storage controller applies the same horizontal shift pulse current I to each magnetic nanowire. Shift ; When the horizontal shift pulse current I Shift When the voltage is high, the domain wall moves the distance of one domain, and the direction of domain movement is the same as that of the horizontal shift pulse current I. Shift The opposite direction; When the horizontal shift pulse current I Shift When the level is low, the memory controller applies a write pulse current I to the write MTJ head. write This allows data to be written into the corresponding magnetic domains.

4. The time-to-digital converter based on a magnetic track memory according to claim 3, characterized in that, If the storage controller applies a positive write pulse current I to the write MTJ head write If the magnetic domain at the location of the write MTJ head is magnetized downwards, then the corresponding magnetic domain is written with data 0; if the memory controller applies a reverse write pulse current I to the write MTJ head... write If the magnetic domain at the location of the MTJ head is magnetized upwards, then the corresponding magnetic domain is written with data 1.

5. The time-to-digital converter based on a magnetic track memory according to claim 2, characterized in that, The storage controller applies a measuring current I to the read MTJ head. read The SA array collects the resistance value of the MTJ magnetic head, thereby reading the data written in the corresponding magnetic domain.

6. The time-to-digital converter based on a magnetic track memory according to claim 5, characterized in that, If the magnetization direction of the domains at the location of the MTJ read head is opposite to the direction of the MTJ read head, the SA array will acquire a high resistance, and the data will be read as 0. If the magnetization direction of the domains at the location of the MTJ read head is the same as the direction of the MTJ read head, the SA array will acquire a low resistance, and the data will be read as 1.

7. The time-to-digital converter based on a magnetic track memory according to claim 2, characterized in that, The memory controller applies the same horizontal reset pulse current I to each magnetic nanowire. reset Horizontal reset pulse current I reset With horizontal shift pulse current I Shift The opposite direction causes the domain walls to move back to their original positions.

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