Method and system for processing set to be long and flat, terminal and storage medium

Abstract

The invention discloses a to-be-long-flat set processing method and system, a terminal and a storage medium. The method comprises the following steps: determining a clock break point according to a synchronization relationship and an asynchronous relationship in clock constraint information; generating a first to-be-prolonged flat set for the corresponding generation clock by using the clock port of each generation clock; and combining the first to-be-long-flat set corresponding to each clock break point. According to the invention, the finally obtained second to-be-prolonged flat set can accurately, completely and briefly represent the same or related synchronization relationship in the corresponding chip, and the first to-be-prolonged flat set which is not merged into the second to-be-prolonged flat set can briefly and accurately represent relatively independent clock information in the corresponding chip. The determined clock tree structure can be as simple as possible, the comprehensive information processing amount of the clock tree can be simplified under the same input condition, and the processing result and the processing time can be optimized.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, specifically to a method and system for processing long-scale data sets, a terminal, and a storage medium. Background Technology

[0002] The complexity of digital chip clock trees mainly stems from two aspects. Firstly, completeness needs to be considered. Clock constraints themselves are formed by traversing all possible clock structures and relationships under the current circuit and functional requirements, thus making them inherently complex structures. For example, the continuous generation of clocks starting from the clock source point is itself a digital description of the actual clock waveform, even if it leads to many clock convergence points. Secondly, the input to CTS (Clock Tree Synthesis) is the clock constraints provided by the designer. Therefore, complex clock constraints will naturally be parsed into complex clock tree structures by the tool, thereby increasing the resources and time required for analysis.

[0003] On the other hand, we need to consider the behavior of tools used for clock signal processing. In the default tool behavior, the clock tree path from the clock source point to all the clock ports of its registers is analyzable, even though it may involve multiple generated clocks. In other words, when the tool analyzes the clock path delay of the last-level generated clock, it can still trace back from the generated clock path to the clock source point in the clock tree structure. However, it lacks sufficient information and behavioral basis to break the integrity of the entire clock tree at the clock source of a particular generated clock. Furthermore, based on the aforementioned underlying logic, the default tool behavior treats each source clock as a working set for skewing. This working set can be called the skew group, meaning that all generated clocks in the skew group are under their most source clock. Therefore, this set is characterized by a large number of registers and a greater number of clock delay path combinations that need to be traversed and analyzed, thus requiring a significant amount of work to skew.

[0004] Based on the above two points, there are generally two common methods for processing clock tree information in existing digital chip physical implementations. One method is to simplify clock constraints. This includes changing the structure of source clock (clock source), generated clock (clock source), ... up to the last generated clock layer, according to actual design needs, to a directly defined structure of source clock, source clock, ..., source clock. It also simplifies the constraint that a single clock port has multiple source clocks or generated clocks to one or a few, and applies this simplified SDC (Synopsys Design Constraint) separately to the tool's CTS, thereby simplifying the clock tree structure seen by the tool. The other method is to maintain a single set of clock constraints throughout the entire process, but use existing tool parameters to allow the tool to automatically identify synchronous / asynchronous relationships and exceptions within the clock constraints, thereby simplifying the clock tree structure generated by the tool.

[0005] The inventors researched the aforementioned clock tree information processing scheme and found that the method for simplifying clock constraints requires designers to provide two sets of clock constraint data, which poses risks of maintenance and data misalignment. Furthermore, as the complexity of digital chips increases, so does the complexity of clock constraints. In addition, complex clock constraints are usually integrated collaboratively by multiple people, making the simplification of clock constraints itself a difficult and complex operation. Moreover, the simplified clock constraints may not achieve the expected results and may even require multiple iterations, impacting project progress. With the iterative updates of CTS tools, some tools now offer options to simplify the generation of unnecessary clock trees based on clock synchronization / asynchronous relationships, exception relationships, etc., enabling CTS operations under a single set of clock constraints. However, on the one hand, the synchronous and asynchronous relationships, and exceptional relationships in clock structures are inherently intertwined and complex. On the other hand, corresponding tools often struggle to obtain sufficient information from clock constraint inputs to simplify complex constraints in a way that meets design requirements. For example, when clock A generates clocks that are synchronous with both clocks B and C, but B and C are asynchronous, the tool can only merge these relationships, essentially assuming a synchronous relationship between B and C. Given the current complexity of clock constraints, relying solely on automated analysis using tools is insufficient to achieve true simplification based on design requirements. Consequently, the clock constraint information obtained in this way still suffers from high complexity. Summary of the Invention

[0006] In view of this, this application provides a method and system for processing a set of data to be processed, a terminal, and a storage medium to simplify the clock constraint information of the resulting set of data to be processed.

[0007] This application provides a method for processing long-distance sets, including the following steps: The clock segmentation point is determined based on the synchronization and asynchronous relationships in the clock constraint information; A first set of long-term flat data is generated with the clock port of each generated clock as the corresponding generated clock. Merge the first set of clock segments corresponding to each clock segmentation point.

[0008] Optionally, determining the clock segmentation point based on the synchronization and asynchronous relationships in the clock constraint information includes: generating an initial segmentation point set based on the clock definition points; generating a clock list corresponding to each generated clock; traversing each generated clock in the clock list according to each synchronization relationship to find the clock definition points of all clock names within each synchronization relationship, and determining the found clock definition points as target segmentation points; deleting the generated clocks traversed when determining each target segmentation point from the initial segmentation point set to obtain a target segmentation point set including at least one clock segmentation point.

[0009] Optionally, the process of generating the clock list includes: traversing the clock source of the generated clock to trace back the clock definition points at each level in turn; and sequentially assigning the generated clock upwards to the clock list of the clock definition points at each level to obtain the clock list of the generated clock.

[0010] Optionally, generating a first set of pending long-term flatnesses for each generated clock with its corresponding clock port includes: obtaining an initial set of pending long-term flatnesses for each generated clock; removing the clock port of each generated clock from the initial set of pending long-term flatnesses for each clock source above the corresponding generated clock to obtain each first set of pending long-term flatnesses.

[0011] Optionally, merging the first set of clock segments corresponding to each clock segmentation point includes: identifying the generation clocks at each level downward from each clock segmentation point, merging the first sets of clock segments corresponding to each level of generation clock, and obtaining a second set of clock segments.

[0012] Optionally, the method for processing the set to be leveled further includes: deleting the first set to be leveled that was incorporated into the second set to be leveled determination process.

[0013] Optionally, the method for processing the set to be scaled further includes: determining a clock tree structure based on the second set to be scaled.

[0014] This application also provides a system for processing sets of objects to be processed, including: The determination module is used to determine the clock segmentation point based on the synchronization and asynchronous relationships in the clock constraint information; The generation module is used to generate a first set of long flat lines to be generated, with the clock port of each generated clock as the corresponding generated clock. The merging module is used to merge the first set of clock segments corresponding to each clock segmentation point.

[0015] This application also provides a terminal, including: a memory and a processor, wherein the memory stores a program for processing a set of data to be processed, and when the program for processing a set of data to be processed is executed by the processor, it implements the steps of any of the above methods for processing a set of data to be processed.

[0016] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above methods for processing long-length sets.

[0017] The above-mentioned method, system, terminal, and storage medium for processing clock sets to be scaled up in this application determine clock segmentation points based on the synchronous and asynchronous relationships in the clock constraint information. The clock segmentation points are used to segment asynchronous clock ports and avoid being located on any synchronous clock path. A first set to be scaled up is generated with the clock port of each generated clock as the corresponding generated clock. The first sets to be scaled up corresponding to each clock segmentation point are merged to obtain a second set to be scaled up. The second set to be scaled up includes clock endpoints corresponding to the same or related synchronous relationships. In this way, the second set to be scaled up can accurately, completely, and concisely represent the same or related synchronous relationships within the corresponding chip. The first set to be scaled up that is not merged into the second set to be scaled up can concisely and accurately represent the relatively independent clock information within the corresponding chip. The clock tree structure determined in this way can be as concise as possible, simplifying the information processing volume of clock tree synthesis under the same input conditions, and optimizing the processing results and processing time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the clock tree structure during the research process; Figure 2 This is a schematic flowchart of a method for processing a set of objects to be processed according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a long-scale collection processing system according to an embodiment of this application; Figure 4 This is a schematic diagram of a terminal structure according to an embodiment of this application. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0021] Inventor based on Figure 1 The clock tree structure shown further investigates the chip clock tree information processing scheme. The tool used to process clock information, through CTS (Clock Tree Synthesis), first generates a clock tree and a set to be lengthened based on clock constraints. Then, using the clock tree and the set to be lengthened as new constraints, it performs a lengthening operation on the clock tree. Figure 1 The clock tree structure shown defines a source clock CLK A at the clock source point, with clock ports connected to registers. Then, at the definition point BUF A, a generated clock CLK B is defined using source clock A as the clock source, with clock ports connected to registers. Further, at the definition point BUF B, generated clocks CLK C, CLK D, and CLK E are defined using generated clock B as the clock source, each with its own clock ports connected to registers. This clock tree, generated by the tool, is structurally a single entity. For each clock port connected to a register of the generated clock CLK C, the path in the clock tree is all paths from that port to BUF B, then to BUF A, and finally to the clock source point. Considering all traversable paths including PB / P-B1 / P-B2 and PA / P-A1 / P-A2, a total of 3*3=9 paths can be found. Therefore, when performing CTS, the tool needs to perform delay analysis on all 9 paths for the ports of all registers connected to the generated clock C, and control the delay of all register clock ports within a certain range of difference values ​​on these paths. On the other hand, under the default tool behavior, the above clock constraints will only generate a set of clocks to be flattened based on the source clock CLK A. This set includes the register clock ports connected to the source clock CLK A and all the generated clocks (CLK B, CLK C, CLK D, CLK E, etc.) under it. That is, the tool needs to control all the delay values ​​of all the register clock ports to be within the same range of difference values.

[0022] Based on the above research, the first aspect of this application provides a method for processing a set of data to be processed. This method is applied in the clock tree synthesis of digital chips and can be executed by a terminal such as a chip that needs to process clock signals. The terminal is pre-configured with tools for processing clock information. The tools for processing clock information can refer to clock tree synthesis tools, such as Innovus / FC / ICC2, which may include tools for converting the corresponding chip from a logic design to a physical implementation design.

[0023] Specifically, refer to Figure 2 As shown, the method for processing the set of long flat objects includes the following steps S110 to S130.

[0024] S110, determine the clock split point based on the synchronization and asynchronous relationships in the clock constraint information.

[0025] Clock constraint information can be obtained by tools used to process clock information. This information may include synchronization and asynchronous relationships. Optionally, the synchronization relationship includes which registers or other clock ports are clock-synchronized, and the asynchronous relationship includes which registers or other clock ports are clock-asynchronous.

[0026] Optionally, the clock split point is used to split the clock ports of asynchronous relationships and / or aggregate the clock endpoints corresponding to at least one synchronous relationship; wherein the clock endpoints include a generated clock, a clock definition point, and / or a clock port. Step S110 may first determine the clock definition point corresponding to the asynchronous relationship as the initial split point, and at the first split point, delete the split points within the same synchronous relationship to determine the final clock split point.

[0027] Specifically, this step, based on the synchronous and asynchronous relationships in the clock constraint information, for all generated clocks under a certain source clock, if the generated clock and its clock source are asynchronous, then the definition point of the generated clock can be used as the dividing point to split the same clock tree in which the generated clock and the source clock reside by default, forming two new clock tree structures. For example, refer to... Figure 1 As stated above, when the clock constraint between the generated clock CLK B and its clock source (CLK A) is asynchronous, the definition point BUF A of the generated clock B can be used as the dividing point to split the original default single clock tree structure into two independent segments: the clock source point to BUF A and the segment below BUF A. Under this structure, when the tool performs clock tree synthesis on the generated clock CLK B, the segment of the clock tree from the definition point BUF A of the generated clock CLK B is used as the common path. The number of paths within it does not need to be multiplied by the number of paths below BUF A for traversal analysis, thereby reducing the number of traversals required for tool analysis.

[0028] On the other hand, assuming that generating clocks CLK C and CLK B are asynchronous, and generating clocks CLK C and CLK G are synchronous, if BUF B is defined as the split point due to the asynchronous relationship between CLK B and CLK C, the synchronous relationship between CLK C and CLK G will be incompletely analyzed because the clock tree is split at this point. Therefore, it is necessary to correct the split point determined directly based on the asynchronous relationship according to the synchronous relationship, so that the obtained clock split point has the following characteristics: a. The clock split point is used to split the clock tree between asynchronous clocks, and it usually contains one or more synchronous relationship groups. b. The clock split point cannot exist inside synchronous relationship clocks, and cannot exist inside synchronous relationship clocks of any operating mode. c. The clock split point can be the definition point of the generating clock, or other location points on the relevant common path. d. From the perspective of the clock tree structure, the candidate list of clock split points (such as a list or set of initial split points) usually comes from the common path points of each synchronous relationship group, that is, these split points in the candidate list all contain all clock paths within their corresponding synchronous relationship group. e. For the split points in the candidate list, the one with the fewest synchronization relationship groups is usually selected as the clock split point. f. The traversal path from the clock split point to any clock in its corresponding synchronization relationship cannot contain any split point.

[0029] S120, generate a first set of clock ports to be generated for each generated clock, so that the first set of clock ports to be generated includes the clock ports under the corresponding generated clock.

[0030] Specifically, step S120 can establish an initial set of clock ports to be long-term pulsed under the corresponding generated clock, and remove the register clock ports under the generated clock from the initial set of clock ports to be long-term pulsed under each level of clock source during the clock source traversal process, so as to obtain an independent first set of clock ports to be long-term pulsed under each generated clock, so as to avoid the first set of clock ports to be long-term pulsed under as much as possible from including duplicate clock ports.

[0031] S130, merge the first set of clock segments corresponding to each clock segmentation point.

[0032] Step S130 can, for each clock synchronization relationship, take its corresponding clock segmentation point as the source point, merge the first set of synchronization relationships to be extended into a second set of synchronization relationships, so that each second set of synchronization relationships contains a set of synchronization relationships in its specific working mode.

[0033] The above-described method for processing clock sets to be extended determines clock segmentation points based on the synchronous and asynchronous relationships in the clock constraint information. These clock segmentation points are used to segment asynchronous clock ports and avoid being located on any synchronous clock path. A first set to be extended is generated with the clock port of each generated clock as the corresponding generated clock. The first sets to be extended corresponding to each clock segmentation point are merged to obtain a second set to be extended. The second set to be extended includes clock endpoints corresponding to the same or related synchronous relationships. In this way, the second set to be extended can accurately, completely, and concisely represent the same or related synchronous relationships within the corresponding chip. The first set to be extended that is not merged into the second set to be extended can concisely and accurately represent the relatively independent clock information within the corresponding chip. The clock tree structure determined in this way can be as concise as possible, simplifying the information processing volume of clock tree synthesis under the same input conditions and optimizing the processing results and processing time.

[0034] In some embodiments, determining the clock split point based on the synchronization and asynchronous relationships in the clock constraint information includes steps S111 to S114.

[0035] S111, generate an initial set of segmentation points based on the clock definition points. Specifically, step S111 can include all clock definition points that generate clocks in the initial set of segmentation points, such as including BUF A, BUF B, BUF C, etc. in the initial set of segmentation points.

[0036] S112, Generate a clock list corresponding to each of the generated clocks.

[0037] In some examples, the process of generating a clock list corresponding to a generated clock includes: traversing the clock source of the generated clock to trace the clock definition points at each level in turn; and sequentially adding the generated clock upwards to the clock list of each level of clock definition points to obtain the clock list of the generated clock.

[0038] Specifically, this example can represent the clock list using arrays or similar methods. For instance, an array can be used to collect the clock definition points contained under each generated clock definition point, resulting in a list of clock names. Specifically, a clock source traversal operation can be performed on each generated clock. For example, for generated clock CLK C, the list of clock names contained under its definition point BUF B is generated clock CLK C. Then, based on generated clock CLK C, a clock source traversal can be performed, tracing back to definition points BUF B and BUF A. Therefore, generated clock C is assigned to the clock name list under BUF B and BUF A. The method for assigning other generated clocks is similar, and the clock list corresponding to each generated clock can be obtained from the beginning. It should be noted that in various embodiments of this application, the lower level or below of the generated clock includes, for example, the following. Figure 1As shown, the various clock definition points, generation clocks, and / or clock ports, etc., are determined using this generated clock as the source clock; the superior or superior levels of the generated clock include, for example, Figure 1 As shown, the clock definition point of the generated clock and / or the source clock corresponding to the clock definition point are determined, etc.

[0039] S113, according to each synchronization relationship, the source clock is traced sequentially in the clock list. Based on the generated clock list information contained in each clock definition point, the first definition point containing at least all clocks in the same synchronization relationship is traced, and the first definition point is determined as the target split point.

[0040] S114, delete the generated clocks that were traversed when determining each target segmentation point from the initial segmentation point set to obtain a target segmentation point set including at least one clock segmentation point. You can also delete all clock definition points encountered on the tracing path from the target segmentation point set to satisfy the condition constraint that no clock segmentation point appears on the synchronization relationship clock path.

[0041] Specifically, this embodiment can traverse all operating modes and all synchronization relationship groups under them in the chip design. For a certain synchronization relationship group, the clock source traversal operation described above is performed on each clock contained within it until the first generated clock definition point containing the names of all clocks in the synchronization relationship group is found. This point is defined as the segmentation point related to the synchronization relationship group, and all other generated clock definition points that appear during the traversal are deleted from the initial segmentation point set. For example, for the synchronization relationship group related to generated clocks CLK C and CLK G, clock source traversal is performed on generated clocks CLK C and CLK G in sequence until the generated clock definition point BUF A is found to contain these two clocks for the first time. Therefore, it is confirmed as the segmentation point related to the synchronization relationship group, and BUF B and BUF C that appear during the traversal are deleted from the initial segmentation point set, thus obtaining the target segmentation point set. The segmentation points included in the target segmentation point set are the final obtained clock segmentation points.

[0042] In some embodiments, all generated clocks can be merged into the set of clocks to be scaled up related to the source clock. However, after simplifying the clock tree path through clock split points, some generated clocks are already independent from the set of clocks to be scaled up related to the source clock. But this independence only includes some generated clocks, and this independence may not be located in its own set of clocks to be scaled up, but rather in the set of clocks to be scaled up related to previous clock sources. For example, since BUF A is included in the split point but BUF B is not, the completely independent asynchronous generated clock E is still not included in the set of clocks to be scaled up related to generated clock CLK E itself, but is located in the set of clocks to be scaled up related to its clock source B. Therefore, the set of clocks to be scaled up does not meet design expectations in some scenarios.

[0043] To address the above issues, in some embodiments, the step of generating a first set of long-term flat data with the clock port of each generated clock as the corresponding generated clock includes steps S121 and S122.

[0044] S121, obtain the initial set of clocks to be generated for each of the generated clocks.

[0045] Step S121 can establish an independent set of clocks to be leveled based on their own clock definition point for each generated clock. Alternatively, by default, the corresponding tool can place the clock port of each generated clock into the set of clocks to be leveled for all generated clocks traced back to the source clock and the set of clocks to be leveled for the source clock, thereby obtaining the initial set of clocks to be leveled for that generated clock.

[0046] S122, remove the clock port under each generated clock from the initial set of clock sources above the corresponding generated clock to obtain each first set of clocks to be generated, so that each first set of clocks to be generated avoids including duplicate clock ports.

[0047] Specifically, as Figure 1Taking the generated clock CLK C as an example, the process of determining the first set of clocks to be leveled is further explained. For the generated clock CLK C, the related register clock port list L(C) is first included in the set of clocks to be leveled with the definition point of the generated clock CLK C as the source, so as to obtain the initial set of clocks to be leveled for the generated clock CLK C. By tracing back along the clock source B of the generated clock CLK C, all clock ports in L(C) are removed from the set of clocks to be leveled starting from the definition point of clock source B. Then, the clock source A of the generated clock CLK B is found, and all clock ports in L(C) are removed from the set of clocks to be leveled starting from the definition point of clock source A. This process is repeated, tracing back along the clock source until the final source clock A is reached. The clock ports of L(C) are then removed from all the sets of clocks to be leveled related to these traced source clocks. Finally, L(C) is independently located in the set of clocks to be leveled starting from the definition point of the generated clock CLK C. This set is the first set of clocks to be leveled for the generated clock CLK C. The clock source tracing method for other generated clocks is similar, ultimately ensuring that the register clock port list for each generated clock is independently located in the first set of clocks to be leveled starting from the definition point of its related generated clock.

[0048] This embodiment adopts the method of traversing the generated clock sources. All generated clocks are traversed in turn. First, an initial set of clocks to be leveled is established for each generated clock. Then, the register clock port under the generated clock is removed from the set of clocks to be leveled of each level clock source during the clock source traversal process. Finally, an independent set of clocks to be leveled is obtained for each generated clock.

[0049] In step S110, for each synchronization relationship group, its related split point is obtained. In order to ensure that all clock ports within the synchronization relationship have the same or similar clock delay, these clock ports can be put into a unified set to be leveled. That is, the independent generated clocks can be merged into the first set to be leveled according to the synchronization relationship.

[0050] Based on this, in some embodiments, merging the first set of clock segments corresponding to each clock segmentation point includes: identifying the generation clocks at each level downwards from each clock segmentation point, merging the first sets of clocks to be merged at each level to obtain a second set of clocks to be merged. Wherein, the clock segmentation point determined in step S110 does not include clock endpoints within a synchronization relationship; it can be the definition point or source point of multiple clock endpoints with a synchronization relationship. Therefore, merging the generation clocks at each level downwards from the clock segmentation point allows clock endpoints corresponding to the same or related synchronization relationships to be merged into the same set of clocks to be merged (i.e., the second set of clocks to be merged).

[0051] Specifically, from the perspective of each synchronization relationship group, there is a corresponding clock split point. One split point may correspond to multiple synchronization relationship groups. In this embodiment, the clock split point can be determined first. Starting from each synchronization relationship in each working mode, the corresponding first set to be merged is identified according to its related clock split point. Then, the first set to be merged corresponding to each clock split point is merged to obtain the second set to be merged.

[0052] This embodiment merges the first set of items to be merged based on clock segmentation points and synchronization relationships. Specifically, the first set of items to be merged under each generated clock is processed according to the synchronization relationship, and its relevant segmentation point is defined as the source point of the merged second set of items to be merged. Figure 1 Based on the constraints of the synchronization relationship, the first sets of clocks to be synchronized corresponding to the generated clock CLK C and the generated clock CLK G can be merged. The register clock port lists in the two sets are then incorporated into the same set of clocks to be synchronized. A new set of clocks to be synchronized needs to be established. The source point of this set is the segmentation point BUF-A related to the corresponding synchronization relationship group obtained in step S110. The clock port list in the first set of clocks to be synchronized is the merging of L(C) and L(G) to obtain the second set of clocks to be synchronized. This approach achieves the synchronous and asynchronous correspondence of the sets to be leveled, while also resolving some complex clock constraint issues. For example, when the deviation value is set to 200, if the generation clocks CLK C and CLK G are synchronous, and CLK C and CLK D are synchronous, but CLK G and CLK D are asynchronous, then the merged second set to be leveled will contain generation clocks CLK C / G and CLK C / D respectively. The deviation constraint between CLK C / G and CLK C / D is 200, and the deviation constraint between CLK G / D can be between 200 and 200*2.

[0053] As one of the constraints of clock tree synthesis, the number of pending long-term sets and the complexity of the clock paths they contain affect the computational load of the tool for this calculation. Therefore, the existence of the first independent pending long-term set after merging is no longer very meaningful and can be considered for deletion to simplify the pending long-term set constraints. Ultimately, this also achieves the required effect of synchronous merging and asynchronous independence as equivalent design constraints.

[0054] Therefore, in some examples, the method for processing the set to be flattened further includes: deleting the first set to be flattened that was incorporated into the second set to be flattened determination process, in order to simplify the constraints of the set to be flattened. For example... Figure 1As shown, after L(C) and L(G) are incorporated into the new second set of pending clocks, the constraints of the two original independent first sets of pending clocks, which were respectively derived from the definition points of the generating clocks CLK C and CLK G, overlap with the merged second set of pending clocks. Therefore, these two independent first sets of pending clocks can be deleted. Ultimately, the generating clocks under synchronous relationships are located in the corresponding merged set of pending clocks, while the generating clocks under asynchronous relationships are located in their respective independent sets of pending clocks.

[0055] In some embodiments, the method for processing the set to be scaled further includes: determining a clock tree structure based on the second set to be scaled, so that the obtained clock tree structure is as simple as possible, thereby improving the effect and efficiency of subsequent clock signal processing based on the clock tree structure.

[0056] The above method for processing the set of clock trees to be split into two parts is to determine the clock splitting point based on the synchronous and asynchronous relationships in the clock constraint information. This allows for the priority of splitting the clock tree structure through the clock splitting point, which simplifies the algorithm resources required for traversal analysis. The clock splitting point of the synchronous relationship group is determined by generating the generation level corresponding to the clock, so as to maximize the simplification of the clock tree structure while meeting the clock constraint requirements. An independent first set of clock trees to be split into two parts is established, and traversal deletion based on the clock source achieves a completely independent effect. Under synchronous relationships, the shared first set of clock trees to be split into two parts is merged to achieve the constraint relaxation effect in the cross-synchronization relationship. This simplifies the complex clock tree structure, reduces the resources and time required for analysis, and removes redundant constraints under the default conditions, thereby enhancing the implementation effect of CTS.

[0057] A second aspect of this application provides a system for processing clock signals, which can be installed in a terminal such as a chip that requires clock signal processing. (Reference) Figure 3 As shown, the above-mentioned long-scale collection processing system includes: The determining module 110 is used to determine the clock segmentation point based on the synchronization and asynchronous relationships in the clock constraint information; Generation module 120 is used to generate a first set of long flat lines to be generated, with the clock port of each generated clock as the corresponding generated clock. The merging module 130 is used to merge the first set of clock segments corresponding to each clock segmentation point.

[0058] Specific limitations regarding the system for processing sets to be scaled can be found in the limitations of the method for processing sets to be scaled above, and will not be repeated here. Each module in the above-mentioned system for processing sets to be scaled can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the computational modules in the relevant computer equipment, or stored in software in the memory of the computer equipment, so that the computational modules can call and execute the operations corresponding to each of the above units.

[0059] This application also provides a terminal, for reference. Figure 4 As shown, the terminal may include: a memory and a processor, wherein the memory stores a program for processing the set to be flattened, and when the program for processing the set to be flattened is executed by the processor, it implements the steps of the method for processing the set to be flattened as described in any of the above embodiments.

[0060] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for processing the set of objects to be processed as described in any of the above embodiments.

[0061] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0062] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0063] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0064] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A method for processing sets of objects to be processed, characterized in that, The method for processing the set to be flattened includes: The clock segmentation point is determined based on the synchronization and asynchronous relationships in the clock constraint information; A first set of long-term flat data is generated with the clock port of each generated clock as the corresponding generated clock. Merge the first set of clock segments corresponding to each clock segmentation point.

2. The method for processing sets of objects to be processed according to claim 1, characterized in that, The step of determining the clock segmentation point based on the synchronization and asynchronous relationships in the clock constraint information includes: Generate an initial set of segmentation points based on the clock definition point; Generate a clock list corresponding to each of the generated clocks; According to each synchronization relationship, the source clock is traced sequentially in the clock list. Based on the generated clock list information contained in each clock definition point, the first definition point containing at least all clocks in the same synchronization relationship is traced, and the first definition point is determined as the target split point. Remove the generated clocks that were traversed when determining each target segmentation point from the initial segmentation point set to obtain a target segmentation point set that includes at least one clock segmentation point.

3. The method for processing sets of objects to be processed according to claim 2, characterized in that, The process of generating the clock list includes: The generated clock is traversed through the clock source to trace the definition points of each level of clock sequentially; The generated clocks are sequentially assigned to clock lists at each level of clock definition point to obtain the generated clock list.

4. The method for processing sets of objects to be processed according to claim 1, characterized in that, The step of generating a first set of long-term flat data for each generated clock as its corresponding clock port includes: Obtain the initial set of clocks to be generated for each of the generated clocks; Remove the clock port under each generated clock from the initial set of clock sources above the corresponding generated clock to obtain each first set of clock sources.

5. The method for processing sets of objects to be processed according to claim 1, characterized in that, The merging of the first set of clock segments corresponding to each clock segmentation point includes: Identify the generation clocks at each of the clock segmentation points downwards, merge the first set of clocks to be leveled down corresponding to each generation clock, and obtain the second set of clocks to be leveled down.

6. The method for processing sets of objects to be processed according to claim 5, characterized in that, The method for processing the set to be flattened also includes: Delete the first set of long-term flat objects that was incorporated into the second set of long-term flat objects determination process.

7. The method for processing sets of objects to be processed according to claim 1, characterized in that, The method for processing the set to be flattened also includes: The clock tree structure is determined based on the second set of pending long-term flattening.

8. A system for processing sets of objects to be processed, characterized in that, include: The determination module is used to determine the clock segmentation point based on the synchronization and asynchronous relationships in the clock constraint information; The generation module is used to generate a first set of long flat lines to be generated, with the clock port of each generated clock as the corresponding generated clock. The merging module is used to merge the first set of clock segments corresponding to each clock segmentation point.

9. A terminal, characterized in that, The terminal may include: a memory and a processor, wherein the memory stores a program for processing the set to be flattened, and when the program for processing the set to be flattened is executed by the processor, it implements the steps of the method for processing the set to be flattened as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for processing a set of objects to be processed as described in any one of claims 1 to 7.

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