Global process corner model and extraction method thereof
By introducing the LOD correction function into the global process corner model and using SA and SB correction terms to correct the device electrical parameters, the impact of shallow trench dielectric isolation technology on device performance is resolved, achieving more accurate process corner model fitting and more reasonable layout design.
Patent Information
- Application Number
- CN202511232152.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2026-03-20
AI Technical Summary
Existing global process corner models fail to effectively consider the mechanical stress effects of shallow trench dielectric isolation technology on device performance, resulting in inaccurate changes in device electrical parameters, which affects the design window and device performance.
A LOD correction function is introduced into the global process corner model. The electrical parameters of the device are corrected by SA and SB correction terms, and power function terms and channel parameter terms are used for correction to improve the model fitting accuracy.
The fitting accuracy of the process corner model has been improved, which can more accurately reflect the impact of process changes on device performance, thereby enabling the design of a more reasonable layout.
Smart Images
Figure CN121706706A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a global process corner model. This invention also relates to a method for extracting the global process corner model. Background Technology
[0002] Process variations (including doping concentration, diffusion depth, etching degree, etc.) occur in semiconductor manufacturing, leading to differences in the electrical characteristics of devices of the same size between different batches (lots), different wafers within the same batch, and different dies within the same wafer. Process corner models are used to characterize these variations. Process variation is a stochastic process and can be divided into global and local variations. Global variations include die-to-die, wafer-to-wafer, and lot-to-lot. Local variations refer to local mismatches. The semiconductor industry has mature manufacturing processes and data monitoring flows, allowing for the generation of process corners through test data analysis. This provides designers with a design window. As designs become increasingly complex and the design window shrinks, process corner analysis becomes indispensable. Using process corner models allows designers to easily understand the impact of process variations on device performance, facilitating the determination of design scope and performance improvement. As design complexity continues to increase, understanding device performance and manufacturing variations using process corner model analysis becomes increasingly important.
[0003] In advanced integrated circuits, the impact of device size on electrical characteristics is receiving increasing attention, especially at advanced process nodes. Shallow Trench Isolation (STI) has now replaced Localized Silicon Oxide (LOCOS) isolation as the mainstream isolation technology in integrated circuit manufacturing. As MOSFET device sizes continue to shrink, the mechanical stress generated by STI has become increasingly severe and can no longer be ignored. The mechanical stress generated by STI causes a series of changes in physical parameters such as carrier mobility, impurity diffusion coefficient, and effective carrier mass. This leads to changes in electrical parameters such as threshold voltage and drain saturation current with the length of the active region (LOD). This change in electrical parameters caused by LOD is known as the LOD effect. LOD is typically represented by the distance from the device gate to the STI, with the distances from the two sides of the device gate to the STI being SA and SB, respectively. The global variation of process deviation differs under different SA and SB conditions. The existing global process angle model does not consider the LOD effect. If parameters related to SA and SB can be introduced into the global process angle model, it can better reflect the global process angle model under LOD. Summary of the Invention
[0004] The technical problem this invention aims to solve is to provide a global process corner model that improves the fitting accuracy of the process corner model, more accurately reflects the impact of process changes on device performance, and ultimately enables the design of a more reasonable layout. To this end, this invention also provides a method for extracting the global process corner model.
[0005] To address the aforementioned technical problems, the present invention provides a global process angle model. In this global process angle model architecture, the global process angle of the electrical parameters of a semiconductor device is the TTG process angle of the electrical parameters plus the standard deviation of the electrical parameters after correction using the LOD correction function.
[0006] The LOD correction function includes an SA correction term, an SB correction term, and a first constant term.
[0007] The SA correction term is a correction term formed by multiplying the power function term of SA by the first channel parameter term.
[0008] The SB correction term is a correction term formed by multiplying the power function term of SB by the second channel parameter term.
[0009] The first channel parameter term and the second channel parameter term have the same structure, including at least a second constant term, a power function term of L, a power function term of W, and a power function term of WL.
[0010] The first constant term, the power function term of SA, the power function term of SB, the second constant term, the power function term of L, the power function term of W, and the power function term of WL all have fitting parameters determined by fitting.
[0011] SA represents the distance between the first side of the gate structure of the semiconductor device and the adjacent shallow trench isolation; SB represents the distance between the second side of the gate structure and the adjacent shallow trench isolation; L represents the length of the channel region of the semiconductor device; and W represents the width of the channel region of the semiconductor device.
[0012] A further improvement is that the semiconductor device is formed on a semiconductor substrate.
[0013] The shallow trench isolation is formed on the semiconductor substrate.
[0014] A further improvement is that the semiconductor device also includes a source region and a drain region.
[0015] The source region is formed between the first side of the gate structure and the adjacent shallow trench isolation.
[0016] The drain region is formed between the second side of the gate structure and the adjacent shallow trench isolation.
[0017] The channel region is located between the source region and the drain region and is covered by the gate structure.
[0018] A further improvement is that the electrical parameters include the linear threshold voltage, saturation threshold voltage, linear drain current, and saturation drain current of the semiconductor device.
[0019] A further improvement is that, in the global process corner model architecture, the global process corner model formulas for the linear threshold voltage, the saturation threshold voltage, the linear drain current, and the saturation drain current are as follows:
[0020] Vtlin corner =Vtlin ttg +ΔVtlin*f(SA,SB);
[0021] Vtsat corner =Vtsat ttg +ΔVtsat*f(SA,SB);
[0022] Idlin corner =Idlin ttg +ΔIdlin*f(SA,SB);
[0023] Idsat corner =Idsat ttg +ΔIdsat*f(SA,SB);
[0024] Vtlin corner Vtsat represents the global process angle of the linear threshold voltage. corner This represents the global process angle representing the saturation threshold voltage; Idlin corner Indicates the global process corner of the linear drain current; Idsat corner This represents the global process corner of the saturated drain current.
[0025] Vtlin ttg The TTG process angle representing the linear threshold voltage; Vtsat ttg The TTG process corner representing the saturation threshold voltage; Idlin ttg The TTG process corner representing the linear drain current; Idsat ttg The TTG process angle represents the saturated drain current; f() represents the LOD correction function; SA represents the distance between the first side of the gate of the semiconductor device and the adjacent shallow trench isolation; SB represents the distance between the second side of the gate of the semiconductor device and the adjacent shallow trench isolation.
[0026] ΔVtlin represents the standard deviation of the linear threshold voltage before correction, ΔVtsat represents the standard deviation of the saturation threshold voltage before correction, ΔIdlin represents the standard deviation of the linear drain current before correction, and ΔIdsat represents the standard deviation of the saturation drain current before correction.
[0027] A further improvement is that the global process angle and the TTG process angle of each of the electrical parameters are obtained by measuring and calculating multiple semiconductor devices with different SA or SB.
[0028] A further improvement is that the LOD correction function is expressed by the formula:
[0029]
[0030] Here, pwr() represents the power function.
[0031] γ1, α1, A1, B1, b1, C1, c1, D1, d1, γ2, α2, A2, B2, b2, C2, c2, D2, d, and E are all fitting coefficients. To solve the above technical problems, the global process angle model extraction method provided by this invention includes the following steps:
[0032] Step 1: Design and fabricate semiconductor devices with multiple different active region lengths.
[0033] Step 2: Measure the electrical parameters of each semiconductor device.
[0034] Step 3: Calculate the standard deviation of the electrical parameters and obtain the corresponding global process angle.
[0035] Step 4: Establish and modify the global process angle model. In the global process angle model architecture, the global process angle of the electrical parameters of the semiconductor device is the TTG process angle of the electrical parameters plus the standard deviation of the electrical parameters after correction using the LOD correction function.
[0036] The LOD correction function includes an SA correction term, an SB correction term, and a first constant term.
[0037] The SA correction term is a correction term formed by multiplying the power function term of SA by the first channel parameter term.
[0038] The SB correction term is a correction term formed by multiplying the power function term of SB by the second channel parameter term.
[0039] The first channel parameter term and the second channel parameter term have the same structure, including at least a second constant term, a power function term of L, a power function term of W, and a power function term of WL.
[0040] SA represents the distance between the first side of the gate structure of the semiconductor device and the adjacent shallow trench isolation, SB represents the distance between the second side of the gate structure and the adjacent shallow trench isolation, SA and SB are set by the length of the active region; L represents the length of the channel region of the semiconductor device, and W represents the width of the channel region of the semiconductor device.
[0041] Step 5: Perform parameter fitting on the global process angle model based on the calculated global process angle, and determine the fitting parameters in the first constant term, the power function term of SA, the power function term of SB, the second constant term, the power function term of L, the power function term of W, and the power function term of WL through parameter fitting.
[0042] A further improvement is that, in step five, if the result of the parameter fitting does not meet the requirements, the process returns to step four to modify the global process angle model, and then performs the parameter fitting in step five again, until the result of the parameter fitting meets the requirements.
[0043] A further improvement includes the following steps:
[0044] Step 6: Verify the global process corner model.
[0045] A further improvement is that the semiconductor device is formed on a semiconductor substrate.
[0046] The shallow trench isolation is formed on the semiconductor substrate.
[0047] A further improvement is that the semiconductor device also includes a source region and a drain region.
[0048] The source region is formed between the first side of the gate structure and the adjacent shallow trench isolation.
[0049] The drain region is formed between the second side of the gate structure and the adjacent shallow trench isolation.
[0050] The channel region is located between the source region and the drain region and is covered by the gate structure.
[0051] A further improvement is that the electrical parameters include the linear threshold voltage, saturation threshold voltage, linear drain current, and saturation drain current of the semiconductor device.
[0052] A further improvement is that, in the global process corner model architecture, the global process corner model formulas for the linear threshold voltage, the saturation threshold voltage, the linear drain current, and the saturation drain current are as follows:
[0053] Vtlin corner =Vtlinttg +ΔVtlin*f(SA,SB);
[0054] Vtsat corner =Vtsat ttg +ΔVtsat*f(SA,SB);
[0055] Idlin corner =Idlin ttg +ΔIdlin*f(SA,SB);
[0056] Idsat corner =Idsat ttg +ΔIdsat*f(SA,SB);
[0057] Vtlin corner Vtsat represents the global process angle of the linear threshold voltage. corner This represents the global process angle representing the saturation threshold voltage; Idlin corner Indicates the global process corner of the linear drain current; Idsat corner This represents the global process corner of the saturated drain current.
[0058] Vtlin ttg The TTG process angle representing the linear threshold voltage; Vtsat ttg The TTG process corner representing the saturation threshold voltage; Idlin ttg The TTG process corner representing the linear drain current; Idsat ttg The TTG process angle represents the saturated drain current; f() represents the LOD correction function; SA represents the distance between the first side of the gate of the semiconductor device and the adjacent shallow trench isolation; SB represents the distance between the second side of the gate of the semiconductor device and the adjacent shallow trench isolation.
[0059] ΔVtlin represents the standard deviation of the linear threshold voltage before correction, ΔVtsat represents the standard deviation of the saturation threshold voltage before correction, ΔIdlin represents the standard deviation of the linear drain current before correction, and ΔIdsat represents the standard deviation of the saturation drain current before correction.
[0060] A further improvement is that the global process angle and the TTG process angle of each of the electrical parameters are obtained by measuring and calculating multiple semiconductor devices with different SA or SB.
[0061] A further improvement is that the LOD correction function is expressed by the formula:
[0062]
[0063] Here, pwr() represents the power function.
[0064] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d and E are all fitting coefficients.
[0065] This invention employs a LOD correction function in the global process corner model. The LOD correction function can effectively correct the impact of LOD effect on the global process corner. Therefore, this invention can improve the fitting accuracy of the process corner model and more accurately reflect the impact of process changes on device performance. Due to the high fitting accuracy of the process corner model, a more reasonable layout can be designed in the end. Attached Figure Description
[0066] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0067] Figure 1 This refers to the layout structure of semiconductor devices in the global process corner model of this invention embodiment;
[0068] Figure 2 This is an architecture diagram of the global process corner model in an embodiment of the present invention;
[0069] Figure 3A This is the fitting curve of the linear threshold voltage in the global process angle model of this invention embodiment;
[0070] Figure 3B This is the fitted curve of the saturation threshold voltage in the global process angle model of this invention embodiment;
[0071] Figure 3C This is the fitted curve of the linear drain current in the global process corner model of this invention embodiment;
[0072] Figure 3D This is the fitted curve of the saturated drain current in the global process corner model of this invention embodiment;
[0073] Figure 4 This is a flowchart of the method for extracting the global process angle model according to an embodiment of the present invention. Detailed Implementation
[0074] like Figure 1 The diagram shows the layout structure of a semiconductor device in the global process corner model of an embodiment of the present invention; as shown... Figure 2 The diagram shown is an architecture diagram of the global process angle model according to an embodiment of the present invention. In the global process angle model architecture 201 of the present invention, the global process angle of the electrical parameters of the semiconductor device is the TTG process angle of the electrical parameters plus the standard deviation of the electrical parameters after being corrected by the LOD correction function.
[0075] The LOD correction function includes an SA correction term, an SB correction term, and a first constant term.
[0076] The SA correction term is a correction term formed by multiplying the power function term of SA by the first channel parameter term.
[0077] The SB correction term is a correction term formed by multiplying the power function term of SB by the second channel parameter term.
[0078] The first channel parameter term and the second channel parameter term have the same structure, including at least a second constant term, a power function term of L, a power function term of W, and a power function term of WL.
[0079] The first constant term, the power function term of SA, the power function term of SB, the second constant term, the power function term of L, the power function term of W, and the power function term of WL all have fitting parameters determined by fitting.
[0080] SA represents the distance between the first side of the gate structure 102 of the semiconductor device and the adjacent shallow trench isolation; SB represents the distance between the second side of the gate structure 102 and the adjacent shallow trench isolation; L represents the length of the channel region of the semiconductor device; and W represents the width of the channel region of the semiconductor device. The semiconductor device is formed on a semiconductor substrate, and the shallow trench isolation is formed on the semiconductor substrate. Figure 1 In the active region 101, the semiconductor device is formed in the active region 101, and the shallow trench isolation is formed on the periphery of the active region 101, that is, the active region 101 is composed of a semiconductor substrate with the shallow trench isolation surrounding region.
[0081] The semiconductor device also includes a source region and a drain region.
[0082] The source region is formed between the first side of the gate structure 102 and the adjacent shallow trench isolation.
[0083] The drain region is formed between the second side of the gate structure and the adjacent shallow trench isolation.
[0084] The channel region is located between the source region and the drain region and is covered by the gate structure 102.
[0085] It can be seen that the length of the entire active region 101 is the sum of SA, SB, and L. Given a fixed L, the values of SA and SB can be adjusted by regulating the length of the active region 101. The tops of both the source region and the drain region are led out through corresponding contact holes 103.
[0086] In this embodiment of the invention, the electrical parameters include the linear threshold voltage, saturation threshold voltage, linear leakage current, and saturation leakage current of the semiconductor device.
[0087] like Figure 2 As shown, in the global process corner model architecture 201, the global process corner model formulas for the linear threshold voltage, the saturation threshold voltage, the linear leakage current, and the saturation leakage current are:
[0088] Vtlin corner =Vtlin ttg +ΔVtlin*f(SA,SB);
[0089] Vtsat corner =Vtsat ttg +ΔVtsat*f(SA,SB);
[0090] Idlin corner =Idlin ttg +ΔIdlin*f(SA,SB);
[0091] Idsat corner =Idsat ttg +ΔIdsat*f(SA,SB);
[0092] Vtlin corner This represents the global process angle of the linear threshold voltage; please also refer to the formula. Figure 2 As shown in the dashed box 202 in the image; Vtsat corner This represents the global process angle of the saturation threshold voltage; please also refer to the formula. Figure 2 As shown in the dashed box 203 in the image; Idlin corner This represents the global process corner of the linear drain current; please also refer to the formula. Figure 2 As shown in the dashed box 204; Idsat corner This represents the global process corner of the saturated drain current; please also refer to the formula. Figure 2 As shown in the dashed box 205 in the figure.
[0093] Vtlin ttg The TTG process angle representing the linear threshold voltage; Vtsat ttg The TTG process corner representing the saturation threshold voltage; Idlin ttg The TTG process corner representing the linear drain current; Idsat ttgThe TTG process angle represents the saturated drain current; f() represents the LOD correction function. SA represents the distance between the first side of the gate of the semiconductor device and the adjacent shallow trench isolation, and SB represents the distance between the second side of the gate of the semiconductor device and the adjacent shallow trench isolation.
[0094] ΔVtlin represents the standard deviation of the linear threshold voltage before correction, ΔVtsat represents the standard deviation of the saturation threshold voltage before correction, ΔIdlin represents the standard deviation of the linear drain current before correction, and ΔIdsat represents the standard deviation of the saturation drain current before correction.
[0095] The global process angle and the TTG process angle of each of the aforementioned electrical parameters are obtained by measuring and calculating multiple semiconductor devices with different SA or SB values. ΔVtlin, ΔVtsat, ΔIdlin, and ΔIdsat can be calculated based on the measurement results.
[0096] In some embodiments, the LOD correction function is expressed by the formula:
[0097]
[0098] Where pwr() represents the power function. Please also refer to the formula for the LOD correction function. Figure 2 The dashed box 206 in the figure is shown.
[0099] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d and E are all fitting coefficients.
[0100] in, This is an SA correction term; SB is the correction term; E is the first constant term. For the power function term of SA, This is the first channel parameter item. For SB, the power function term, Second channel parameter item.
[0101] like Figure 3A The figure shows the fitting curve of the linear threshold voltage in the global process angle model of this invention; the vertical axis sigma represents the standard deviation, and the horizontal axis is SA. Figure 3A In this context, sigma(Vtlin) represents the standard deviation of the linear threshold voltage. Figure 3AEach point in the diagram represents a target value, which can be obtained through actual measurement. The fitted line is obtained by fitting the target value using the formula shown in the dashed box 202 of this embodiment, and is calculated using ΔVtlin*f(SA, SB). It can be seen that the fitting result matches the target value.
[0102] like Figure 3B The figure shows the fitting curve of the saturation threshold voltage in the global process angle model of this invention; it can also be seen that the fitting result is consistent with the target value.
[0103] like Figure 3C The figure shows the fitting curve of the linear drain current in the global process corner model of this invention; it can also be seen that the fitting result is consistent with the target value.
[0104] like Figure 3D The figure shows the fitting curve of the saturated drain current in the global process corner model of this invention; it can also be seen that the fitting result is consistent with the target value.
[0105] Therefore, the embodiments of the present invention can improve the fitting accuracy of the process corner model.
[0106] In this embodiment of the invention, a Level of Degrees (LOD) correction function is used in the global process corner model. The LOD correction function can effectively correct the impact of LOD effect on the global process corner. Therefore, this embodiment of the invention can improve the fitting accuracy of the process corner model and more accurately reflect the impact of process changes on device performance. Due to the high fitting accuracy of the process corner model, a more reasonable layout can be designed. That is, based on the process corner simulation results of this embodiment of the invention, the layout design can be determined, thereby designing a more reasonable layout.
[0107] like Figure 4 As shown, the method for extracting the global process corner model in this embodiment of the invention includes the following steps:
[0108] Step 1: Design and fabricate a semiconductor device with multiple active regions 101 of different lengths. In this embodiment of the invention, the semiconductor device is formed on a semiconductor substrate, and shallow trench isolation is formed on the semiconductor substrate. Figure 1 In the active region 101, the semiconductor device is formed in the active region 101, and the shallow trench isolation is formed on the periphery of the active region 101, that is, the active region 101 is composed of a semiconductor substrate with the shallow trench isolation surrounding region.
[0109] The semiconductor device also includes a source region and a drain region.
[0110] The source region is formed between the first side of the gate structure 102 and the adjacent shallow trench isolation.
[0111] The drain region is formed between the second side of the gate structure and the adjacent shallow trench isolation.
[0112] The channel region is located between the source region and the drain region and is covered by the gate structure 102.
[0113] The following SA represents the distance between the first side of the gate structure 102 of the semiconductor device and the adjacent shallow trench isolation, SB represents the distance between the second side of the gate structure 102 and the adjacent shallow trench isolation; L represents the length of the channel region of the semiconductor device, and W represents the width of the channel region of the semiconductor device.
[0114] It can be seen that the length of the entire active region 101 is the sum of SA, SB, and L. With L fixed, the values of SA and SB can be adjusted by changing the length of the active region 101. The tops of both the source region and the drain region are led out through corresponding contact holes 103. That is, in the method of this embodiment, SA and SB can be adjusted by changing the length of the active region 101, while W and L of the channel region remain fixed. In other embodiments, W and L of the channel region can also be changed as needed.
[0115] Step 1 corresponds to Figure 4 Step S101: Design device structures with different active region lengths.
[0116] Step 2: Measure the electrical parameters of each semiconductor device. Step 2 corresponds to... Figure 4 Step S102, measuring device data.
[0117] Step 3: Calculate the standard deviation of the electrical parameters and obtain the corresponding global process angle. Step 3 corresponds to... Figure 4 In step S103, the standard deviation of the data is calculated to obtain the global process angle under different SA and SB.
[0118] Step 4: Establish and modify the global process angle model. In the global process angle model architecture 201, the global process angle of the electrical parameters of the semiconductor device is the TTG process angle of the electrical parameters plus the standard deviation of the electrical parameters after correction using the LOD correction function.
[0119] The LOD correction function includes an SA correction term, an SB correction term, and a first constant term.
[0120] The SA correction term is a correction term formed by multiplying the power function term of SA by the first channel parameter term.
[0121] The SB correction term is a correction term formed by multiplying the power function term of SB by the second channel parameter term.
[0122] The first channel parameter term and the second channel parameter term have the same structure, including at least a second constant term, a power function term of L, a power function term of W, and a power function term of WL.
[0123] In the method of this invention embodiment, the electrical parameters include the linear threshold voltage, saturation threshold voltage, linear leakage current, and saturation leakage current of the semiconductor device.
[0124] In the global process corner model architecture 201, the global process corner model formulas for the linear threshold voltage, the saturation threshold voltage, the linear leakage current, and the saturation leakage current are as follows:
[0125] Vtlin corner =Vtlin ttg +ΔVtlin*f(SA,SB);
[0126] Vtsat corner =Vtsat ttg +ΔVtsat*f(SA,SB);
[0127] Idlin corner =Idlin ttg +ΔIdlin*f(SA,SB);
[0128] Idsat corner =Idsat ttg +ΔIdsat*f(SA,SB);
[0129] Vtlin corner Vtsat represents the global process angle of the linear threshold voltage. corner This represents the global process angle representing the saturation threshold voltage; Idlin corner Indicates the global process corner of the linear drain current; Idsat corner This represents the global process corner of the saturated drain current.
[0130] Vtlin ttg The TTG process angle representing the linear threshold voltage; Vtsat ttg The TTG process corner representing the saturation threshold voltage; Idlin ttg The TTG process corner representing the linear drain current; Idsat ttg The TTG process angle represents the saturated drain current; f() represents the LOD correction function. SA represents the distance between the first side of the gate of the semiconductor device and the adjacent shallow trench isolation, and SB represents the distance between the second side of the gate of the semiconductor device and the adjacent shallow trench isolation.
[0131] ΔVtlin represents the standard deviation of the linear threshold voltage before correction, ΔVtsat represents the standard deviation of the saturation threshold voltage before correction, ΔIdlin represents the standard deviation of the linear drain current before correction, and ΔIdsat represents the standard deviation of the saturation drain current before correction.
[0132] In some embodiments, the LOD correction function is expressed by the formula:
[0133]
[0134] Here, pwr() represents the power function.
[0135] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d and E are all fitting coefficients.
[0136] in, This is an SA correction term; SB is the correction term; E is the first constant term. For the power function term of SA, This is the first channel parameter item. For SB, the power function term, Second channel parameter item.
[0137] The global process angle and the TTG process angle of each of the electrical parameters are obtained by measuring and calculating multiple semiconductor devices with different SA or SB, i.e., through the preceding step three. ΔVtlin, ΔVtsat, ΔIdlin, and ΔIdsat can be calculated based on the measurement results.
[0138] Step four corresponds to Figure 4 Step S104: Establish and modify the global process angle model related to different active area environments.
[0139] Step 5: Perform parameter fitting on the global process angle model based on the calculated global process angle, and determine the fitting parameters in the first constant term, the power function term of SA, the power function term of SB, the second constant term, the power function term of L, the power function term of W, and the power function term of WL through parameter fitting.
[0140] In step five, if the result of the parameter fitting does not meet the requirements, return to step four to modify the global process angle model, and then perform the parameter fitting in step five again until the result of the parameter fitting meets the requirements.
[0141] Step five corresponds to Figure 4Step S105: Fitting the curve of the active region length correlation model.
[0142] It also includes the following steps:
[0143] Step Six: Verify the global process corner model. Step Six corresponds to... Figure 4 Step S106: Verification of the device LOD global process corner model.
[0144] The method of this invention can improve the fitting accuracy of the process corner model and design a more reasonable layout; by introducing a function related to the LOD size (SA,SB), it can more accurately reflect the impact of process changes on device performance and better reflect the characteristics of the device in actual circuits.
[0145] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A global process angle model, characterized in that, In the global process angle model architecture, the global process angle of the electrical parameters of a semiconductor device is the TTG process angle of the electrical parameters plus the standard deviation of the electrical parameters after correction using the LOD correction function; The LOD correction function includes an SA correction term, an SB correction term, and a first constant term; The SA correction term is a correction term formed by multiplying the power function term of SA by the first channel parameter term; The SB correction term is a correction term formed by multiplying the power function term of SB by the second channel parameter term; The first channel parameter term and the second channel parameter term have the same structure, including at least a second constant term, a power function term of L, a power function term of W, and a power function term of WL; The first constant term, the power function term of SA, the power function term of SB, the second constant term, the power function term of L, the power function term of W, and the power function term of WL all have fitting parameters determined by fitting. SA represents the distance between the first side of the gate structure of the semiconductor device and the adjacent shallow trench isolation; SB represents the distance between the second side of the gate structure and the adjacent shallow trench isolation; L represents the length of the channel region of the semiconductor device; and W represents the width of the channel region of the semiconductor device.
2. The global process corner model as described in claim 1, characterized in that: The semiconductor device is formed on a semiconductor substrate; The shallow trench isolation is formed on the semiconductor substrate.
3. The global process corner model as described in claim 2, characterized in that: The semiconductor device further includes a source region and a drain region; The source region is formed between the first side of the gate structure and the adjacent shallow trench isolation; The drain region is formed between the second side of the gate structure and the adjacent shallow trench isolation; The channel region is located between the source region and the drain region and is covered by the gate structure.
4. The global process corner model as described in claim 1, characterized in that: The electrical parameters include the linear threshold voltage, saturation threshold voltage, linear drain current, and saturation drain current of the semiconductor device.
5. The global process corner model as described in claim 4, characterized in that: In the global process corner model architecture, the global process corner model formulas for the linear threshold voltage, the saturation threshold voltage, the linear drain current, and the saturation drain current are as follows: Vtlin corner =Vtlin ttg +ΔVtlin*f(SA,SB); Vtsat corner =Vtsat ttg +ΔVtsat*f(SA,SB); Idlin corner =Idlin ttg +ΔIdlin*f(SA,SB); Idsat corner =Idsat ttg +ΔIdsat*f(SA,SB); Vtlin corner Vtsat represents the global process angle of the linear threshold voltage. corner This represents the global process angle representing the saturation threshold voltage; Idlin corner Indicates the global process corner of the linear drain current; Idsat corner This represents the global process corner of the saturated drain current; Vtlin ttg The TTG process angle representing the linear threshold voltage; Vtsat tt The TTG process corner representing the saturation threshold voltage; Idlin ttg The TTG process corner representing the linear drain current; Idsat ttg The TTG process angle represents the saturated drain current; f() represents the LOD correction function; ΔVtlin represents the standard deviation of the linear threshold voltage before correction, ΔVtsat represents the standard deviation of the saturation threshold voltage before correction, ΔIdlin represents the standard deviation of the linear drain current before correction, and ΔIdsat represents the standard deviation of the saturation drain current before correction.
6. The global process corner model as described in claim 5, characterized in that: The global process angle and the TTG process angle of each of the electrical parameters are obtained by measuring and calculating multiple semiconductor devices with different SA or SB.
7. The global process corner model as described in claim 5, characterized in that: The LOD correction function is expressed by the following formula: Where pwr() represents the power function; γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d and E are all fitting coefficients.
8. A method for extracting a global process corner model, characterized in that, Includes the following steps: Step 1: Design and fabricate semiconductor devices with multiple different active region lengths; Step 2: Measure the electrical parameters of each semiconductor device. Step 3: Calculate the standard deviation of the electrical parameters and obtain the corresponding global process angle; Step 4: Establish and modify the global process angle model. In the global process angle model architecture, the global process angle of the electrical parameters of the semiconductor device is the TTG process angle of the electrical parameters plus the standard deviation of the electrical parameters after correction using the LOD correction function. The LOD correction function includes an SA correction term, an SB correction term, and a first constant term; The SA correction term is a correction term formed by multiplying the power function term of SA by the first channel parameter term; The SB correction term is a correction term formed by multiplying the power function term of SB by the second channel parameter term; The first channel parameter term and the second channel parameter term have the same structure, including at least a second constant term, a power function term of L, a power function term of W, and a power function term of WL; SA represents the distance between the first side of the gate structure of the semiconductor device and the adjacent shallow trench isolation, SB represents the distance between the second side of the gate structure and the adjacent shallow trench isolation, SA and SB are set by the length of the active region; L represents the length of the channel region of the semiconductor device, and W represents the width of the channel region of the semiconductor device. Step 5: Perform parameter fitting on the global process angle model based on the calculated global process angle, and determine the fitting parameters in the first constant term, the power function term of SA, the power function term of SB, the second constant term, the power function term of L, the power function term of W, and the power function term of WL through parameter fitting.
9. The method for extracting the global process corner model as described in claim 8, characterized in that: In step five, if the result of the parameter fitting does not meet the requirements, return to step four to modify the global process angle model, and then perform the parameter fitting in step five again until the result of the parameter fitting meets the requirements.
10. The method for extracting the global process angle model as described in claim 9, characterized in that, It also includes the following steps: Step 6: Verify the global process corner model.
11. The method for extracting the global process corner model as described in claim 8, characterized in that: The semiconductor device is formed on a semiconductor substrate; The shallow trench isolation is formed on the semiconductor substrate.
12. The method for extracting the global process corner model as described in claim 11, characterized in that: The semiconductor device further includes a source region and a drain region; The source region is formed between the first side of the gate structure and the adjacent shallow trench isolation; The drain region is formed between the second side of the gate structure and the adjacent shallow trench isolation; The channel region is located between the source region and the drain region and is covered by the gate structure.
13. The method for extracting the global process corner model as described in claim 8, characterized in that: The electrical parameters include the linear threshold voltage, saturation threshold voltage, linear drain current, and saturation drain current of the semiconductor device.
14. The method for extracting the global process angle model as described in claim 13, characterized in that: In the global process corner model architecture, the global process corner model formulas for the linear threshold voltage, the saturation threshold voltage, the linear drain current, and the saturation drain current are as follows: Vtlin corner =Vtlin ttg +ΔVtlin*f(SA,SB); Vtsat corner =Vtsat ttg +ΔVtsat*f(SA,SB); Idlin corner =Idlin ttg +ΔIdlin*f(SA,SB); Idsat corner =Idsat ttg +ΔIdsat*f(SA,SB); Vtlin corner Vtsat represents the global process angle of the linear threshold voltage. corner This represents the global process angle representing the saturation threshold voltage; Idlin corner Indicates the global process corner of the linear drain current; Idsat corner This represents the global process corner of the saturated drain current; Vtlin ttg The TTG process angle representing the linear threshold voltage; Vtsat ttg The TTG process corner representing the saturation threshold voltage; Idlin ttg The TTG process corner representing the linear drain current; Idsat ttg The TTG process angle represents the saturated drain current; f() represents the LOD correction function; ΔVtlin represents the standard deviation of the linear threshold voltage before correction, ΔVtsat represents the standard deviation of the saturation threshold voltage before correction, ΔIdlin represents the standard deviation of the linear drain current before correction, and ΔIdsat represents the standard deviation of the saturation drain current before correction.
15. The method for extracting the global process corner model as described in claim 14, characterized in that: The global process angle and the TTG process angle of each of the electrical parameters are obtained by measuring and calculating multiple semiconductor devices with different SA or SB.
16. The method for extracting the global process corner model as described in claim 14, characterized in that: The LOD correction function is expressed by the following formula: Where pwr() represents the power function; γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d and E are all fitting coefficients.