An instruction buffer and a control method thereof, a network processor and a chip

Abstract

This application relates to an instruction buffer and its control method, a network processor, and a chip. It includes at least a storage module, a read pointer address management module, and a controller. The storage module comprises contiguously addressed memory cells, each storing an entry containing a valid flag, a thread identifier, and instruction data. The controller reads the instruction according to the read pointer address and sends it to the back-end pipeline, simultaneously invalidating the entry flag. The read pointer address management module manages the read pointer. After each read, it searches backward within a preset range from the current address for the first valid flag memory cell. If found, the read pointer is updated to that address; otherwise, it is updated to the address following the end of the range. The instruction buffer of this application only needs to update the read pointer address after reading the instruction, without physically shifting data. Furthermore, the read pointer address can skip invalid instructions, thereby reducing power consumption and minimizing invalid instructions entering the pipeline.

Description

Technical Field

[0001] This application relates to the field of instruction buffer technology, specifically to an instruction buffer and its control method, a network processor, and a chip. Background Technology

[0002] The current instruction buffer is typically implemented using a shift buffer to create a FIFO-like structure. For example, ... Figure 1 As shown, the instruction buffer is a register-based storage structure with 32 entries. Each entry caches the contents of one instruction. Whenever a thread returns fetch data, the instruction buffer pointer is filled. The instruction buffer pointer defaults to 0. The pointer is incremented by N every N instructions filled. The pointer is decremented by 1 every time an instruction is issued. The pointer is used to determine whether all returned instructions from the thread can be received. If the instruction buffer cannot receive all returned instructions, the thread will be blocked from initiating an instruction fetch request to ensure that the instruction buffer does not overflow. As long as the instruction buffer pointer is not 0 and the backend pipeline's issuance requirements are met, an instruction needs to be issued to ensure that the instructions cached in the instruction buffer can be emptied. When an instruction is issued, the instruction buffer removes Entry 0, then shifts the contents of Entry 1 to Entry 0, and so on. The contents of other Entries are also shifted to their corresponding previous Entry.

[0003] The above Figure 1 The instruction buffer scheme has the following problems:

[0004] Because every instruction issue shifts all Entries within the instruction buffer pointer to the previous Entry, register updates occur every issue cycle, significantly wasting processor power. Furthermore, the back-end pipeline flushes instructions from various threads, invalidating all instructions cached in the instruction buffer for the corresponding thread. However, instructions are flushed from Entry 0, which may contain invalid ones. Therefore, issuing an invalid instruction is considered a "bubble," and the back-end pipeline's handling of invalid instructions wastes pipeline resources. Figure 1 As shown, both Entry1 and Entry2 are invalid instructions, which will generate two bubbles.

[0005] Therefore, there is an urgent need for a technical solution that can reduce the power consumption of register flipping and reduce invalid instructions entering the instruction buffer of the back-end pipeline. Summary of the Invention

[0006] The purpose of this application is to propose an instruction buffer and its control method, network processor and chip, which can reduce register toggling power consumption and reduce invalid instructions entering the back-end pipeline.

[0007] To achieve the above objectives, according to the first aspect of this application, an instruction buffer is proposed, comprising a storage module, a read pointer address management module, and a controller;

[0008] The storage module includes multiple contiguously addressed storage units. Each storage unit is used to store an entry. Each entry includes a valid flag field, a thread identifier field, and a data field. The data field is used to store the prefetched instruction. The thread identifier field is used to store the thread identifier corresponding to the instruction. The valid flag field is used to store a flag indicating whether the instruction is valid.

[0009] The read pointer address management module is used to manage the read pointer address, which is the address of the storage unit for the next read instruction;

[0010] The controller is used to read the instruction from the data field of the memory unit corresponding to the read pointer address and send it to the back-end pipeline, and update the flag in the valid flag field of the memory unit corresponding to the read pointer address to invalid;

[0011] The read pointer address management module is also used to, whenever an instruction is read, start from the read pointer address and search backward within a preset search range for the first valid flag storage unit. If the first valid flag storage unit is found, the read pointer address is updated to the address of the first valid flag storage unit. If no valid flag storage unit is found, the read pointer address is updated to the address of the next storage unit after the end of the preset search range.

[0012] In some embodiments, a write pointer address management module is further included, which is used to manage write pointer addresses, the write pointer addresses pointing to the next storage unit for write instructions;

[0013] The controller is also used to receive n instructions and their thread identifiers. If the storage module currently has n available storage units, the controller writes the n instructions and their thread identifiers into n consecutive storage units starting from the write pointer address, and updates the flags in the valid flag field of the n storage units to be valid; where n is greater than or equal to 1.

[0014] In some embodiments, the plurality of contiguously addressed memory cells are divided into a plurality of memory cell groups according to the addressing order, and the plurality of memory cell groups include the same number of memory cells;

[0015] The read pointer address includes a first group address and a first group address. The first group address is the address of the storage unit group of the next read instruction, and the first group address is the address within the corresponding storage unit group of the storage unit of the next read instruction.

[0016] The write pointer address includes a second group address and a second group internal address. The second group address is the address of the storage unit group of the next write instruction, and the second group internal address is the internal address of the storage unit of the next write instruction within the corresponding storage unit group.

[0017] In some embodiments, the preset search range is determined according to the following method:

[0018] When the read pointer address is less than the write pointer address, and the read pointer address and the write pointer address are located in the same memory cell group, the preset search range is the memory cells between the addresses in the first group and the addresses in the second group.

[0019] When the read pointer address is greater than the write pointer address, and the read pointer address and the write pointer address are located in the same storage unit group, the preset search range is the storage units between the address in the first group and the last storage unit in the group;

[0020] When the read pointer address and the write pointer address are located in different memory cell groups, the preset search range is the memory cell between the address in the first group and the last memory cell in the group.

[0021] In some embodiments, the controller is further configured to receive a flushing signal, determine a target thread identifier based on the flushing signal, query the storage module based on the target thread identifier to determine at least one target storage unit, and update all flags in the valid flag field of the at least one target storage unit to invalid.

[0022] In some embodiments, the read pointer address management module is further configured to manage a read flip flag, which flips when the read pointer address wraps around.

[0023] The write pointer address management module is also used to manage the write flip flag, which flips when the write pointer address wraps around.

[0024] Specifically, the controller is used to determine whether the storage module currently has n available storage units when it receives the n instructions, based on the write pointer address, the read pointer address, the write pointer address toggling flag, and the read pointer address toggling flag.

[0025] According to a second aspect of this application, a control method based on the instruction buffer described in the first aspect is proposed, the method comprising:

[0026] The controller receives a read instruction command, reads the read pointer address according to the read instruction command, reads the instruction from the data field of the memory unit corresponding to the read pointer address and sends it to the back-end pipeline, and updates the flag in the valid flag field of the memory unit corresponding to the read pointer address to invalid.

[0027] After each instruction is read, the read pointer address management module starts from the read pointer address and searches backward within a preset search range for the first valid flag storage unit. If the first valid flag storage unit is found, the read pointer address is updated to the address of the first valid flag storage unit. If no valid flag storage unit is found, the read pointer address is updated to the address of the next storage unit after the end of the preset search range.

[0028] According to a third aspect of this application, a network processor is proposed, including the instruction buffer described in the first aspect of this application.

[0029] According to a fourth aspect of this application, a chip is proposed that includes the instruction buffer described in the first aspect of this application.

[0030] According to a fifth aspect of this application, a computer program product is provided, comprising computer program instructions that instruct a computer device to perform an operation corresponding to the method described in the above embodiments.

[0031] The instruction buffer and its control method, network processor, and chip disclosed in this application have the following beneficial effects:

[0032] This application's instruction buffer introduces a read pointer address management module. After each instruction is read, only the read pointer address is updated, without physically shifting other entries in the memory module. This avoids invalid flipping of a large amount of register data in the memory cell, thus significantly reducing processor power consumption. After each instruction is read, a lookup operation is triggered, searching backwards (in the addressing increment direction) for the first valid flag memory cell. If found, the read pointer address is directly updated to the address of that first valid flag memory cell. This mechanism allows the read pointer address to automatically skip invalid entries (such as invalid instructions left by flushing), reducing the number of invalid instructions sent to the back-end pipeline, thereby reducing the generation of pipeline bubbles and improving pipeline utilization. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a structural diagram of an instruction buffer disclosed in the background art.

[0035] Figure 2 This is a structural diagram of an instruction buffer in an embodiment of this application.

[0036] Figure 3 This is a schematic diagram of an entry in an embodiment of this application.

[0037] Figure 4 This is an example diagram of a preset search range in an embodiment of this application.

[0038] Figure 5 This is another example diagram of the preset search range in the embodiments of this application.

[0039] Marked in the image:

[0040] 1-Storage module, 2-Write pointer management module, 3-Read pointer management module, 4-Controller. Detailed Implementation

[0041] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0042] See Figure 2 One embodiment of this application provides an instruction buffer, including a storage module, a read pointer address management module, and a controller.

[0043] The storage module includes multiple contiguously addressed storage units, each of which stores one entry, such as... Figure 3 As shown, each entry includes a valid flag field, a thread identifier field, and a data field. The data field is used to store the prefetched instruction, the thread identifier field is used to store the thread identifier corresponding to the instruction, and the valid flag field is used to store a flag indicating whether the instruction is valid.

[0044] The term "multiple consecutively addressed memory units" refers to multiple memory units arranged in sequence, each with a unique and consecutive address (similar to 0, 1, 2, 3...), which facilitates the search for instructions using pointers, since a pointer is essentially a record of an address number.

[0045] The valid flag field is used to mark whether the instruction in this entry is available. For example, vld=1 indicates that it is valid and vld=0 indicates that it is invalid. If it is valid, it means that there is a valid instruction waiting to be executed. If it is invalid, it means that the position is empty or the instruction in it has been invalidated, such as being flushed out by the pipeline or already read. This is the basis for implementing the function of skipping invalid instructions when reading pointer address, so that the buffer can identify which are bubbles and which are valid instructions.

[0046] In a multithreaded processor, multiple threads may share the same instruction buffer. The thread identifier field is used to record which thread the current instruction belongs to, so that when scheduling instructions, the processor knows which thread to dispatch the instruction to for execution.

[0047] The data field stores the instruction itself (the instruction's opcode, operands, and other binary code) prefetched from memory, which is the part that will eventually be sent to the backend pipeline for execution.

[0048] The read pointer address management module is used to manage the read pointer address, which is the address of the storage unit of the next read instruction. In the instruction buffer, the read pointer address can be stored in a register.

[0049] The controller is used to read the instruction from the data field of the memory cell corresponding to the read pointer address and send it to the back-end pipeline, and update the flag in the valid flag field of the memory cell corresponding to the read pointer address to invalid. Specifically, the controller performs the instruction issuance operation. When it receives a read instruction command, the controller locates the corresponding memory cell according to the read pointer address, extracts the instruction from the data field of the memory cell and sends it to the back-end pipeline for processing. Then, the controller updates the flag in the valid flag field of the memory cell to invalid. This action indicates that the memory cell has been cleared and the instruction is no longer available. Thus, the instruction reading and release process is completed by logical flags rather than physical data shifting.

[0050] The read pointer address management module is also used to, after each instruction is read, start from the read pointer address and search backward within a preset search range for the first valid flag storage unit. If the first valid flag storage unit is found, the read pointer address is updated to the address of the first valid flag storage unit; if no valid flag storage unit is found, the read pointer address is updated to the address of the next storage unit after the end of the preset search range. Specifically, after each instruction is read, the read pointer address management module immediately starts the pointer update mechanism, that is, starting from the current read pointer address, it searches forward (in the addressing increment direction) within the set preset search range, aiming to locate the first storage unit containing a valid flag entry. Once a search is successful, the read pointer address management module will directly jump to update the read pointer address to the address of the first storage unit containing a valid flag entry, ensuring that the next read operation directly points to a valid instruction, thus skipping invalid data in the middle. Therefore, the read pointer address does not simply increment by 1 each time, which can eliminate some popped bubbles to a certain extent. Conversely, if no storage unit with a valid flag entry is found within the entire preset search range, the read pointer address management module will update the read pointer address to the address of the next storage unit after the end of the search range. This logic maintains the continuity of the pointer and the normal progress of subsequent operations, achieving efficient management that can intelligently skip invalid instruction bubbles without physical shifting.

[0051] It should be noted that the preset search range can be set based on technical requirements. For example, a full-range search based on the total buffer capacity can be used. For instance, if the instruction buffer has 32 memory units, the preset search range can be set to start from the current read pointer address and traverse to the last address of the buffer (e.g., Entry 31). This method ensures that as long as there are still unissued instructions in the buffer, they can be found regardless of the distance. However, the disadvantage is that the search path is the longest, which may increase the latency and power consumption of the search circuit. Another example is a dynamic range search based on the current fill depth. For instance, by maintaining a write pointer, the preset search range is set to the interval between the current read pointer and the last valid unit pointed to by the write pointer. If the write pointer indicates that the data has only filled up to Entry 10, then the search range only extends to Entry 10. Up to 10, this method can avoid scanning unused blank areas and improve search efficiency; another example is fixed window search based on timing constraints. According to the strict requirements of the processor pipeline on the launch delay, the preset search range is limited to a fixed N entries (such as searching forward 8 or 16 entries). If no valid instruction is found in these N entries, it is directly judged as launch failure or paused, and no further search is performed to ensure the stability of the high frequency processor's main frequency.

[0052] As described in the above embodiments, the instruction buffer in this embodiment introduces a read pointer address management module. After each instruction is read, only the read pointer address is updated, without physically shifting other entries in the memory module. This avoids invalid flipping of a large amount of register data in the memory unit, thereby significantly reducing the processor's power consumption. After each instruction is read, a lookup operation is triggered, searching backwards (in the address increment direction) for the first valid flag memory unit. If found, the read pointer address is directly updated to the address of the first valid flag memory unit. This mechanism allows the read pointer address to automatically skip invalid entries (such as invalid instructions left by flushing), reducing the number of invalid instructions sent to the back-end pipeline, thereby reducing the generation of pipeline bubbles and improving pipeline utilization.

[0053] In some embodiments, a write pointer address management module is also included. The write pointer address management module is used to manage write pointer addresses, which point to the next storage unit for write instructions. When the validity flag of an entry in the storage unit is invalid, it indicates that the storage unit is in an idle state and new data can be written.

[0054] The controller is also used to receive n instructions and their thread identifiers. If the storage module currently has n available storage units, the controller writes the n instructions and their thread identifiers into n consecutive storage units starting from the write pointer address, and updates the flags in the valid flag field of the n storage units to be valid; where n is greater than or equal to 1. Specifically, when modern processors fetch instructions from memory or cache, they usually do not fetch them one by one, but rather fetch one instruction block (e.g., one cache line) at a time via the bus. A line (or line) is an instruction block that typically contains m instructions (e.g., 4 or 8 instructions). When storing instructions into the instruction buffer, all instructions in the instruction block can be stored in the instruction buffer at once to improve write efficiency. Alternatively, the instruction block can be preprocessed, discarding some useless instructions before storing them into the instruction buffer. Since not all prefetched instructions will necessarily be executed, this saves buffer resources. Therefore, the instruction buffer is designed to support writing a maximum of m instructions in one instruction block at a time, which can directly adapt to this bus width without splitting the processing. When the controller receives n instructions and their thread identifiers, if it detects that there is enough available space in the storage module, it writes the corresponding instruction data and thread identifiers into n consecutive storage units starting from the write pointer address, and simultaneously updates the valid flag fields of these n storage units to the valid state, thereby completing the ordered cache filling of instructions and ensuring that subsequent read operations can recognize and process the newly written instructions.

[0055] In some embodiments, the plurality of contiguously addressed storage units are divided into a plurality of storage unit groups according to the addressing order, and the plurality of storage unit groups include the same number of storage units; specifically, this embodiment structurally divides the originally linear and contiguous storage space into a plurality of storage unit groups of the same size. Through this modular physical organization, group addressing and easy updating of pointer addresses are achieved.

[0056] The read pointer address includes a first set of addresses and addresses within the first set. The first set of addresses is the address of the storage unit group of the next read instruction, and the addresses within the first set are the addresses within the corresponding storage unit group of the next read instruction. Specifically, the read pointer address uses grouped addressing logic and is composed of the first set of addresses and addresses within the first set. The first set of addresses is used to locate the specific storage unit group where the target instruction is located, and the addresses within the first set are used to accurately locate the specific position of the target instruction within the specific storage unit group, thereby achieving fast and accurate indexing of the next instruction to be read.

[0057] The write pointer address includes a second set of addresses and a second set of internal addresses. The second set of addresses is the address of the memory cell group of the next write instruction, and the second set of internal addresses is the address within the corresponding memory cell group of the next write instruction. Specifically, the write pointer address also adopts the corresponding grouped addressing structure, which includes a second set of addresses and a second set of internal addresses. The second set of addresses is used to locate the specific memory cell group where the write position is located, and the second set of internal addresses is used to accurately locate the specific position of the write position within the specific memory cell group, ensuring that the write operation can be accurately and orderly placed.

[0058] Taking 32 Entries as an example, the storage units are divided into four groups based on the address of the Entries: Entry 0 to Entry 7 is Group 0, Entry 8 to Entry 15 is Group 1, Entry 16 to Entry 23 is Group 2, and Entry 24 to Entry 31 is Group 3. The write pointer address (popPtr) and the read pointer address (popPtr) are both 5 bits. Bits [4:3] are used to represent the first group address and the second group address, and bits [2:0] are used to represent the address within the first group and the address within the second group. The addresses 0 to 3 (2 bits) of the first group address and the address within the second group address can be used to address the Group, and the addresses 0 to 7 (3 bits) of the first group address and the address within the second group address can be used to address the Entries in the Group. Each Group has 8 Entries.

[0059] In some embodiments, the preset search range is determined according to the following method:

[0060] When the read pointer address is less than the write pointer address, and the read pointer address and the write pointer address are located in the same memory cell group, such as Figure 4 As shown, the preset search range is the storage unit between the first group address and the second group address; specifically, when the read pointer address is less than the write pointer address and both are in the same storage unit group, it indicates that the ring buffer has not wrapped around, and the data in the middle is a valid instruction stream that has been written and is waiting to be read. At this time, the preset search range is set to the storage unit between the current first group address and the second group address, that is, the scan is restricted to the currently filled data area.

[0061] When the read pointer address is greater than the write pointer address, and the read pointer address and the write pointer address are located in the same memory cell group, the preset search range is the memory cell between the address in the first group and the last memory cell in the group. Specifically, when the read pointer address is greater than the write pointer address, and the two are in the same memory cell group, it indicates that the ring buffer has wrapped around. The area from the current read pointer address to the end of the group may contain old valid data that has not yet been covered. Since the read pointer address needs to be updated within one clock cycle, the preset search range is set to start from the current address in the first group and continue to the last memory cell in the corresponding memory cell group to ensure that the read pointer update module can complete the read pointer update within one clock cycle.

[0062] When the read pointer address and the write pointer address are located in different memory cell groups, such as Figure 5 As shown, the preset search range is the storage units between the address in the first group and the last storage unit in the group; specifically, when the read pointer address and the write pointer address are located in different storage unit groups, similarly, the read pointer address needs to be updated within one clock cycle. The search range only considers the current storage unit group and does not consider cross-storage unit group queries. At this time, the preset search range is set to start from the current address in the first group and continue to the last storage unit in the corresponding storage unit group, ensuring that the read pointer update module can complete the read pointer update within one clock cycle.

[0063] In some embodiments, the controller is further configured to receive a flushing signal, determine a target thread identifier based on the flushing signal, query the storage module based on the target thread identifier to determine at least one target storage unit, and update all flags in the valid flag field of the at least one target storage unit to invalid.

[0064] Specifically, the flushing signal carries a target thread identifier. The target thread identifier is extracted from the flushing signal, and the storage module is queried based on the target thread identifier to find all target storage units whose thread identifier field contains the target thread identifier. The flags in the valid flag field of all target storage units are updated to vld=0 without updating the data field of all target storage units, which simplifies the logic. By modifying vld, non-sequential instruction output can be achieved, effectively eliminating the bubble problem in instruction output.

[0065] In some embodiments, the write pointer address management module is further configured to manage a write wrap-around flag (wrapFlagW). The write pointer address wrap-around flag is toggled when the write pointer address wraps around, i.e., 0 is toggled to 1 and 1 is toggled to 0. Specifically, the write pointer address management module includes a write pointer address update unit, a write pointer address storage unit, and a write wrap-around flag storage unit. The write pointer address storage unit stores the write pointer address, and the write pointer address update unit updates the write pointer address, which points to the next storage unit for the write instruction. The write wrap-around flag storage unit stores the write pointer address wrap-around flag, and the write pointer address update unit updates the write pointer address wrap-around flag when the write pointer address wraps around, i.e., 0 is changed to 1 or 1 is changed to 0.

[0066] The read pointer address management module is also used to manage the read wrap-up flag (wrapFlagR), which is flipped when the read pointer address wraps around. Specifically, the read pointer address management module includes a read pointer address update unit, a read pointer address storage unit, and a read wrap-up flag storage unit. The read pointer address storage unit stores the read pointer address, and the read pointer address update unit updates the read pointer address, which points to the next storage unit used for the read instruction. The read wrap-up flag storage unit stores the read pointer address wrap-up flag, and the read pointer address update unit updates the read pointer address wrap-up flag when the read pointer address wraps around, i.e., 0 changes to 1 or 1 changes to 0.

[0067] Specifically, the controller, upon receiving the n instructions, determines whether the storage module 1 currently has n available storage units based on the write pointer address, the read pointer address, the write pointer address toggling flag, and the read pointer address toggling flag. Specifically, when wrapFlagW is not equal to wrapFlagR, instructions are not allowed to be received; when wrapFlagW is equal to wrapFlagR, the available storage units (i.e., entries with vld=0) are calculated based on the read pointer address and the write pointer address. If the available storage units are greater than or equal to n, the n instructions can be written; otherwise, the write request for the n instructions is not responded to.

[0068] Another embodiment of this application proposes a control method for the instruction buffer based on the above embodiments, the method comprising:

[0069] The controller receives a read instruction command, reads the read pointer address according to the read instruction command, reads the instruction from the data field of the memory unit corresponding to the read pointer address and sends it to the back-end pipeline, and updates the flag in the valid flag field of the memory unit corresponding to the read pointer address to invalid.

[0070] After each instruction is read, the read pointer address management module starts from the read pointer address and searches backward within a preset search range for the first valid flag storage unit. If the first valid flag storage unit is found, the read pointer address is updated to the address of the first valid flag storage unit. If no valid flag storage unit is found, the read pointer address is updated to the address of the next storage unit after the end of the preset search range.

[0071] Another embodiment of this application provides a network processor that includes the instruction buffer described in the above embodiments of this application.

[0072] Another embodiment of this application provides a chip including the network processor or instruction buffer described in the above embodiments of this application.

[0073] Another embodiment of this application provides a computer program product including computer program instructions that instruct a computer device to perform operations corresponding to the methods described in the above embodiments of this application.

[0074] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the methods described in the above embodiments. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the methods of the above embodiments.

[0075] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or market improvements of the embodiments, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An instruction buffer, characterized by It includes a storage module, a read pointer address management module, and a controller; The storage module includes multiple contiguously addressed storage units. Each storage unit is used to store an entry. Each entry includes a valid flag field, a thread identifier field, and a data field. The data field is used to store the prefetched instruction. The thread identifier field is used to store the thread identifier corresponding to the instruction. The valid flag field is used to store a flag indicating whether the instruction is valid. The read pointer address management module is used to manage the read pointer address, which is the address of the storage unit for the next read instruction; The controller is used to read the instruction from the data field of the memory unit corresponding to the read pointer address and send it to the back-end pipeline, and update the flag in the valid flag field of the memory unit corresponding to the read pointer address to invalid; The read pointer address management module is also used to, whenever an instruction is read, start from the read pointer address and search backward within a preset search range for the first valid flag storage unit. If the first valid flag storage unit is found, the read pointer address is updated to the address of the first valid flag storage unit. If no valid flag storage unit is found, the read pointer address is updated to the address of the next storage unit after the end of the preset search range.

2. The instruction buffer of claim 1, wherein, It also includes a write pointer address management module, which manages write pointer addresses, which point to the next storage unit used for write instructions; The controller is also used to receive n instructions and their thread identifiers. If the storage module currently has n available storage units, the controller writes the n instructions and their thread identifiers into n consecutive storage units starting from the write pointer address, and updates the flags in the valid flag field of the n storage units to be valid; where n is greater than or equal to 1.

3. The instruction buffer according to claim 2, characterized in that, The plurality of consecutively addressed storage units are divided into a plurality of storage unit groups according to the addressing order, and the plurality of storage unit groups include the same number of storage units; The read pointer address includes a first group address and a first group address. The first group address is the address of the storage unit group of the next read instruction, and the first group address is the address within the corresponding storage unit group of the storage unit of the next read instruction. The write pointer address includes a second group address and a second group internal address. The second group address is the address of the storage unit group of the next write instruction, and the second group internal address is the internal address of the storage unit of the next write instruction within the corresponding storage unit group.

4. The instruction buffer of claim 3, wherein, The preset search range is determined according to the following method: When the read pointer address is less than the write pointer address, and the read pointer address and the write pointer address are located in the same memory cell group, the preset search range is the memory cells between the addresses in the first group and the addresses in the second group. When the read pointer address is greater than the write pointer address, and the read pointer address and the write pointer address are located in the same storage unit group, the preset search range is the storage units between the address in the first group and the last storage unit in the group; When the read pointer address and the write pointer address are located in different memory cell groups, the preset search range is the memory cell between the address in the first group and the last memory cell in the group.

5. The instruction buffer of any one of claims 1 to 4, wherein, The controller is also configured to receive a flushing signal, determine a target thread identifier based on the flushing signal, query the storage module based on the target thread identifier to determine at least one target storage unit, and update all flags in the valid flag field of the at least one target storage unit to invalid.

6. The instruction buffer of any one of claims 2-4, wherein, The read pointer address management module is also used to manage the read flip flag, which flips when the read pointer address wraps around. The write pointer address management module is also used to manage the write flip flag, which flips when the write pointer address wraps around. Specifically, the controller is used to determine whether the storage module currently has n available storage units when it receives the n instructions, based on the write pointer address, the read pointer address, the write pointer address toggling flag, and the read pointer address toggling flag.

7. A control method of an instruction buffer according to any one of claims 1 to 6, characterized by, The method includes: The controller receives a read instruction command, reads the read pointer address according to the read instruction command, reads the instruction from the data field of the memory unit corresponding to the read pointer address and sends it to the back-end pipeline, and updates the flag in the valid flag field of the memory unit corresponding to the read pointer address to invalid. After each instruction is read, the read pointer address management module starts from the read pointer address and searches backward within a preset search range for the first valid flag storage unit. If the first valid flag storage unit is found, the read pointer address is updated to the address of the first valid flag storage unit. If no valid flag storage unit is found, the read pointer address is updated to the address of the next storage unit after the end of the preset search range.

8. A network processor, comprising: Includes the instruction buffer as described in any one of claims 1 to 6.

9. A chip, characterized in that, Includes the instruction buffer as described in any one of claims 1 to 6.

10. A computer program product comprising computer program instructions that instruct a computer device to perform an operation corresponding to the method of claim 7.

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