Doherty power amplifier with harmonic frequency resonant circuit

Abstract

The invention relates to a Doherty power amplifier with a harmonic frequency resonant circuit. A Doherty power amplifier includes a combining node that combines amplified output signals from first and second amplifiers. A reconfigurable impedance inverter circuit is coupled between a first amplifier and the combining node. The impedance inverter circuit includes an inductive element coupled between a first node and a second node, and a switching circuit coupled between the first node and the second node. A fundamental frequency tuning circuit and a harmonic frequency resonant circuit are coupled between the switching circuit and a ground reference node. When the switching circuit is configured to be in a first state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to a first node and a second node through the switching circuit. When the switching circuit is configured to be in a second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first node and the second node.

Description

TECHNICAL FIELD

[0001] Embodiments of the subject matter described herein generally relate to Doherty power amplifiers. BACKGROUND

[0002] For many years, Doherty power amplifiers have been one of the most popular amplifiers for cellular infrastructure applications, provided that the Doherty power amplifier is capable of providing high efficiency and linear amplification of high peak-to-average power ratio (PAPR) signals. A well-designed conventional Doherty power amplifier exhibits linear signal amplification over a range of average output power levels, where high efficiency amplification can be achieved in the high power operating region. Furthermore, compared to balanced amplifiers, Doherty power amplifiers can exhibit better efficiency when the output power is backed off from saturation.

[0003] To achieve high efficiency operation, Doherty power amplifiers are attempted to be designed such that the power dissipated within the amplifier is minimized. A well-designed Doherty power amplifier is configured to most efficiently amplify signal energy of a radio frequency (RF) signal centered at a particular operating fundamental frequency. However, due to nonlinearities and impedance mismatches within the amplifier, signal energy at harmonic frequencies (e.g., second and higher order harmonic frequencies) can be added to the RF signal amplified by the Doherty power amplifier. The presence of harmonic signal energy can degrade the efficiency and linearity of the Doherty power amplifier. Accordingly, some Doherty power amplifier designs include harmonic termination circuits at the input and / or output of the carrier amplifier and the peaking amplifier.

[0004] A remaining challenge is that in some types of Doherty power amplifiers, the harmonic termination circuitry at the input and / or output of the carrier amplifier and the peaking amplifier can undesirably limit the bandwidth of the amplifier. Specifically, the dispersive nature of the load impedance (Zmod) at the backoff power of the operating fundamental frequency in some Doherty power amplifiers (e.g., 90 / 0 Doherty power amplifiers) can preclude the inclusion of conventional harmonic frequency resonant circuits in such amplifiers. However, the absence of harmonic termination circuitry limits the performance of the Doherty power amplifier. Accordingly, there is a need to provide Doherty power amplifier designs that provide good harmonic frequency termination without unduly limiting the bandwidth of the amplifier. SUMMARY

[0005] According to a first aspect of the present invention, there is provided a Doherty power amplifier, comprising:

[0006] a first amplifier having a first amplifier output, wherein the first amplifier is configured to produce an amplified first output signal;

[0007] a second amplifier having a second amplifier output, wherein the second amplifier is configured to produce an amplified second output signal;

[0008] a combining node configured to combine the amplified first output signal and the amplified second output signal;

[0009] a reconfigurable impedance inverter circuit coupled between the first amplifier output and the combining node, wherein the reconfigurable impedance inverter circuit comprises

[0010] a first node coupled to the first amplifier output,

[0011] a second node coupled to the second amplifier output,

[0012] a first inductive element having a first end coupled to the first node and a second end coupled to the second node,

[0013] a switching circuit having a first switching circuit end coupled to the first node and a second switching circuit end coupled to the second node, wherein the switching circuit is configured to be controlled to a first state and a second state,

[0014] a fundamental frequency tuning circuit coupled between the switching circuit and a ground reference node, wherein the fundamental frequency tuning circuit is configured to resonate at or near an operating fundamental frequency,

[0015] a harmonic frequency resonance circuit coupled between the switching circuit and the ground reference node, wherein the harmonic frequency resonance circuit is configured to resonate at or near a second harmonic frequency of the operating fundamental frequency, and

[0016] wherein, when the switching circuit is configured to be in the first state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically coupled to the first node and the second node through the switching circuit, and when the switching circuit is configured to be in the second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first node and the second node.

[0017] In one or more embodiments, the reconfigurable impedance inverter circuit additionally comprises:

[0018] a second inductive element coupled between the first node and the ground reference node.

[0019] In one or more embodiments, the harmonic frequency resonance circuit is primarily characterized by a capacitance at the operating fundamental frequency, and

[0020] the fundamental frequency tuning circuit is primarily characterized by an inductance at the operating fundamental frequency, and

[0021] when the switch circuit is configured to be in the first state, the inductance of the fundamental frequency tuning circuit cancels the capacitance of the harmonic frequency resonance circuit.

[0022] In one or more embodiments, the reconfigurable impedance inverter circuit additionally includes:

[0023] a first transmission line section coupled between the first amplifier output and the first node, wherein the first transmission line section is characterized by a first electrical length and a first characteristic impedance;

[0024] a second transmission line section coupled between the second amplifier output and the second node, wherein the second transmission line section is characterized by a second electrical length and a second characteristic impedance;

[0025] a third transmission line section coupled between the first node and the first terminal of the switch circuit, wherein the third transmission line section is characterized by a third electrical length and a third characteristic impedance; and

[0026] a fourth transmission line section coupled between the second node and the second terminal of the switch circuit, wherein the fourth transmission line section is characterized by a fourth electrical length and a fourth characteristic impedance.

[0027] In one or more embodiments, the fundamental frequency tuning circuit includes a second inductive element and a first capacitor coupled in series between the switch circuit and the ground reference node; and

[0028] the harmonic frequency resonance circuit includes a third inductive element and a second capacitor coupled in series between the switch circuit and the ground reference node.

[0029] In one or more embodiments, the fundamental frequency tuning circuit includes a first shunt stub; and

[0030] the harmonic frequency resonance circuit includes a second shunt stub.

[0031] In one or more embodiments, the Doherty power amplifier additionally includes:

[0032] a first DC blocking capacitor coupled between the first amplifier output and the first node; and

[0033] a second DC blocking capacitor coupled between the second amplifier output and the second node.

[0034] In one or more embodiments, the Doherty power amplifier additionally includes:

[0035] an amplifier controller coupled to the switching circuit, wherein

[0036] the amplifier controller is configured to receive a signal indicative of a full power state and, in response, provide a first control signal to the switching circuit to set the switching circuit to the first state, and

[0037] the amplifier controller is configured to receive a signal indicative of a reduced power state and, in response, provide a second control signal to the switching circuit to set the switching circuit to the second state.

[0038] In one or more embodiments, the switching circuit comprises:

[0039] a first switching element coupled between the first switching circuit terminal and an intermediate node; and

[0040] a second switching element coupled between the intermediate node and the second switching circuit terminal, and

[0041] wherein the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are each coupled between the intermediate node and the ground reference node,

[0042] when the switching circuit is configured to be in the first state, the first switching element and the second switching element are configured to be in a closed state, and

[0043] when the switching circuit is configured to be in the second state, the first switching element and the second switching element are configured to be in an open state.

[0044] In one or more embodiments, the switching circuit comprises:

[0045] a first switching element coupled between the first switching circuit terminal and an intermediate node; and

[0046] a second switching element coupled between the intermediate node and the second switching circuit terminal, and

[0047] wherein the fundamental frequency tuning circuit is coupled between the intermediate node and the ground reference node,

[0048] the harmonic frequency resonant circuit is coupled between the second switching circuit terminal and the ground reference node,

[0049] when the switching circuit is configured to be in the first state, the first switching element and the second switching element are configured to be in a closed state, and

[0050] when the switch circuit is configured to be in the second state, the first switch element and the second switch element are configured to be in an open state.

[0051] In one or more embodiments, the first amplifier output is characterized by a first amplifier output capacitance;

[0052] the second amplifier output is characterized by a second amplifier output capacitance;

[0053] the combination node is characterized by a combination node impedance; and

[0054] wherein the Doherty power amplifier additionally includes

[0055] a reconfigurable carrier output capacitance circuit coupled to the first amplifier output, wherein the reconfigurable carrier output capacitance circuit and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance,

[0056] a reconfigurable peaking output capacitance circuit coupled to the second amplifier output and the combination node, wherein the reconfigurable peaking output capacitance circuit and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance, and

[0057] an output impedance transformer coupled between the combination node and an output of the Doherty power amplifier, wherein the output impedance transformer is configured to establish the combination node impedance.

[0058] In one or more embodiments, the reconfigurable carrier output capacitance circuit includes a first bypass switch having a first terminal and a second terminal, a first capacitor and a second inductive element coupled in series between the first amplifier output and the first terminal of the first bypass switch, and a third inductive element coupled between the first terminal of the first bypass switch and the ground reference node, wherein the second terminal of the first bypass switch is coupled to the ground reference node;

[0059] the reconfigurable peaking output capacitance circuit includes a second bypass switch having a first terminal and a second terminal, a second capacitor and a fourth inductive element coupled in series between the second amplifier output and the first terminal of the second bypass switch, and a fifth inductive element coupled between the first terminal of the second bypass switch and the ground reference node, wherein the second terminal of the second bypass switch is coupled to the ground reference node; and

[0060] The output impedance transformer includes a transmission line section having a first end coupled to the combining node and a second end coupled to an output of the Doherty power amplifier, a third capacitor coupled between the first end and the ground reference node, and a reconfigurable inductor-capacitor circuit coupled between the second end and the ground reference node, wherein the reconfigurable inductor-capacitor circuit includes a third shunt switch having a first terminal and a second terminal, a fourth capacitor coupled between the second end and the first terminal of the third shunt switch, and a sixth inductive element coupled between the first terminal of the third shunt switch and the ground reference node, wherein the second terminal of the third shunt switch is coupled to the ground reference node,

[0061] when the switch circuit is configured to be in the first state, the first, second, and third shunt switches are configured to be in an open state, and

[0062] when the switch circuit is configured to be in the second state, the first, second, and third shunt switches are configured to be in a closed state.

[0063] In one or more embodiments, the first amplifier includes a first power transistor having a first drain terminal and a first source terminal, wherein the first drain terminal corresponds to the first amplifier output;

[0064] the first amplifier output capacitance is a first drain-source capacitance between the first drain terminal and the first source terminal;

[0065] the second amplifier includes a second power transistor having a second drain terminal and a second source terminal, wherein the second drain terminal corresponds to the second amplifier output; and

[0066] the second amplifier output capacitance is a second drain-source capacitance between the second drain terminal and the second source terminal.

[0067] In one or more embodiments, the Doherty power amplifier additionally includes:

[0068] an amplifier input; and

[0069] a power divider having a power divider input coupled to the amplifier input, a first power divider output coupled to a first amplifier input of the first amplifier, and a second power divider output coupled to a second amplifier output of the second amplifier.

[0070] In one or more embodiments, the first amplifier is a carrier amplifier; and

[0071] The second amplifier is a peaking amplifier.

[0072] According to a second aspect of the application, there is provided a method of operating a Doherty power amplifier, comprising:

[0073] generating, by a first amplifier, an amplified first output signal at a first amplifier output;

[0074] generating, by a second amplifier, an amplified second output signal at a second amplifier output;

[0075] communicating the amplified first output signal to a combining node by a reconfigurable impedance inverter circuit coupled between the first amplifier output and the combining node, wherein the reconfigurable impedance inverter circuit comprises

[0076] a first node coupled to the first amplifier output,

[0077] a second node coupled to the second amplifier output,

[0078] a first inductive element having a first end coupled to the first node and a second end coupled to the second node,

[0079] a switching circuit having a first switching circuit end coupled to the first node and a second switching circuit end coupled to the second node, wherein the switching circuit is configured to be controlled to a first state and a second state,

[0080] a fundamental frequency tuning circuit coupled between the switching circuit and a ground reference node, wherein the fundamental frequency tuning circuit is configured to resonate at or near an operating fundamental frequency,

[0081] a harmonic frequency resonance circuit coupled between the switching circuit and the ground reference node, wherein the harmonic frequency resonance circuit is configured to resonate at or near a second harmonic frequency of the operating fundamental frequency, and

[0082] wherein, when the switching circuit is configured to be in the first state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically coupled to the first node and the second node through the switching circuit, and when the switching circuit is configured to be in the second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first node and the second node;

[0083] communicating the amplified second output signal to the combining node;

[0084] combining the amplified first and second output signals at the combining node to generate an amplified combined output signal; and

[0085] The amplified combined output signal is delivered through an output impedance transformer coupled between the combined node and an output of the Doherty power amplifier.

[0086] In one or more embodiments, the method further comprises:

[0087] configuring the switch circuit to the first state in which the base frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first node and the second node through the switch circuit.

[0088] In one or more embodiments, the method further comprises:

[0089] configuring the switch circuit to the second state in which the base frequency tuning circuit and the harmonic frequency resonant circuit are electrically disconnected from the first node and the second node.

[0090] In one or more embodiments, the first amplifier output is characterized by a first amplifier output capacitance;

[0091] the second amplifier output is characterized by a second amplifier output capacitance;

[0092] the combined node is characterized by a combined node impedance; and

[0093] wherein the Doherty power amplifier further comprises

[0094] a reconfigurable carrier output capacitance circuit coupled to the first amplifier output, wherein the reconfigurable carrier output capacitance circuit and the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance,

[0095] a reconfigurable peaking output capacitance circuit coupled to the second amplifier output and the combined node, wherein the reconfigurable impedance inverter circuit and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance, and

[0096] the output impedance transformer coupled between the combined node and the output of the Doherty power amplifier, wherein the output impedance transformer is configured to establish the combined node impedance.

[0097] In one or more embodiments, the method further comprises configuring the Doherty power amplifier by:

[0098] configuring the switch circuit to be in the first state, in which the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first node and the second node through the switch circuit;

[0099] configuring the reconfigurable carrier output capacitance circuit to modify the first amplifier effective output capacitance while the switch circuit is configured to be in the first state;

[0100] configuring the reconfigurable peaking output capacitance circuit to modify the second amplifier effective output capacitance while the switch circuit is configured to be in the first state; and

[0101] configuring the output impedance circuit to modify the combined node impedance while the switch circuit is configured to be in the first state.

[0102] These and other aspects of the application will become apparent from the embodiments described below, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0103] A more complete understanding of the subject matter can be obtained by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein like reference numerals indicate like elements throughout the figures.

[0104] Figure 1 is a simplified block diagram of an example communications device in which embodiments of a Doherty power amplifier can be incorporated;

[0105] Figure 2 is a graph showing theoretical efficiency performance as a function of full output power level and reduced output power level for embodiments of a Doherty power amplifier;

[0106] Figure 3 is a schematic diagram of a Doherty power amplifier in a full power state according to an example embodiment, in which the Doherty power amplifier includes a harmonic frequency resonant circuit and a fundamental frequency tuning circuit electrically coupled to a reconfigurable impedance inverter circuit;

[0107] Figure 4 is a schematic diagram of a Doherty power amplifier in a reduced power state according to an example embodiment, in which the harmonic frequency resonant circuit and the fundamental frequency tuning circuit are electrically disconnected from the reconfigurable impedance inverter circuit; Figure 3

[0108] Figure 5 is a schematic diagram of a reconfigurable impedance inverter circuit according to another example embodiment;

[0109] Figure 6 ​is a schematic diagram of a reconfigurable impedance inverter circuit according to yet another example embodiment; and

[0110] Figure 7 is a flowchart of a method of operating a Doherty power amplifier according to an example embodiment. DETAILED DESCRIPTION

[0111] A conventional Doherty amplifier includes an amplifier input for receiving a radio frequency (RF) signal, a power divider, a carrier amplifier, a peaking amplifier, an output circuit, and an amplifier output, among other things. The output circuit includes a combining node coupled to outputs of both the carrier amplifier and the peaking amplifier and corresponding to a circuit node of a combined amplified carrier signal and peaking signal. The output of the carrier amplifier is coupled to the combining node through a fixed impedance inverter. The combining node is coupled to the amplifier output through an output transformer.

[0112] According to one or more embodiments, the combining node is coupled to the output of the carrier amplifier through a reconfigurable impedance inversion and phase shift circuit (also referred to herein as a "reconfigurable impedance inverter circuit" or "tunable quasi-line"). A first inductor-capacitor (LC) network configured to resonate at or near a second harmonic frequency (2fo) is attached to the reconfigurable impedance inverter circuit. Additionally, a second LC network tuned for impedance at an operating fundamental frequency (fo) is also attached to the reconfigurable impedance inverter circuit. The values of the inductive elements and capacitors of the first and second LC networks, as well as the locations of the first and second LC networks along the reconfigurable impedance inverter circuit, can be carefully selected to optimize the impedance at 2fo and fo. With this approach, the efficiency of a Doherty power amplifier embodiment can be significantly improved while maintaining the same bandwidth. Moreover, as described in detail below, the proposed reconfigurable impedance inverter circuit can be combined with various other reconfigurable circuits to provide efficiency enhancement based on traffic load conditions (e.g., traffic tracking).

[0113] As will be discussed in detail below, embodiments of the reconfigurable impedance inverter circuit include a series of phase shifting elements (e.g., a series of transmission line segments) configured to provide impedance inversion and impart a phase delay to an amplified RF signal that is communicated between the output of the carrier amplifier and the combining node. Other embodiments of the reconfigurable impedance inverter circuit include a fundamental frequency tuning circuit and a harmonic frequency resonant circuit, both of which are coupled to the reconfigurable impedance inverter circuit through a switching circuit. The fundamental frequency tuning circuit is configured to optimize the impedance at the operating fundamental frequency of the Doherty power amplifier and is configured to resonate at or near the fundamental frequency (e.g., where "at or near" means exactly at the fundamental frequency fo, or at a frequency between about 90% and about 110% of fo). The harmonic frequency resonant circuit is configured to resonate at or near the second harmonic frequency (e.g., where "at or near" means exactly at the second harmonic frequency 2fo, or at a frequency between about 90% and about 110% of 2fo). Thus, during operation of the Doherty power amplifier, the harmonic frequency resonant circuit is used to remove signal energy at or near the second harmonic frequency from the amplified carrier signal.

[0114] Other embodiments of the Doherty power amplifier include additional tuning circuits coupled to the output transformer and to the output terminals (e.g., intrinsic drain terminals) of the carrier amplifier and peaking amplifier. These additional tuning circuits are also reconfigurable, which enables the correct and proper impedance to be established at the carrier and peaking output terminals for a plurality of average output power levels, thus enabling high efficiency signal amplification at full average output power levels and reduced average output power levels.

[0115] As used herein, the reconfigurable impedance inverter circuit (including the harmonic frequency resonant circuit and the fundamental frequency tuning circuit) and the "additional tuning circuits" can be collectively referred to as "reconfigurable output circuits." Furthermore, because the Doherty power amplifiers described herein have "reconfigurable output circuits," such Doherty power amplifier embodiments can be referred to herein as "reconfigurable Doherty power amplifiers."

[0116] As used herein, in the context of a circuit, the term "reconfigurable" means that the state (e.g., electrical characteristics, electrical connections, electrical states, and / or values) of components, nodes, and / or sub-circuits within the reconfigurable circuit can be selectively changed during operation. According to one or more embodiments, the reconfigurable output circuits can be selectively configured into any of a plurality of different states. Two particular states are discussed in detail herein (specifically, a "full power state" and a "reduced power state"). Based on the description herein, one of skill in the art will appreciate that the embodiments of the reconfigurable output circuits discussed herein can also be configured into other states.

[0117] As will be described in detail later, embodiments of the reconfigurable Doherty power amplifier described herein are capable of being dynamically reconfigured to different amplifier states. For example, in some embodiments, the reconfigurable Doherty power amplifier can be electronically controlled to different amplifier states based on actual or expected traffic load (e.g., based on how many users are communicating on or expected to communicate on the system). For example, when a communication device including the reconfigurable Doherty power amplifier is handling (or is expected to handle) high traffic (e.g., between 75% and 100% traffic load), the system can determine that the reconfigurable Doherty power amplifier should be configured (or reconfigured) to a "full power state," in which the amplifier should be effectively operating at a full average output power level. Conversely, when the amplifier system is handling (or is expected to handle) lower traffic (e.g., less than 75% traffic load), the system can determine that the reconfigurable Doherty power amplifier should be configured (or reconfigured) to a "reduced power state," in which the amplifier should be effectively operating at a reduced average output power level. Either way, the system can generate a control signal that causes the reconfigurable Doherty power amplifier to be reconfigured to either the full power state or the reduced power state. In other words, according to some embodiments, traffic tracking can be performed on traffic being handled by the amplifier system, and a selected amplifier state can be determined based on the instantaneous measured traffic load. In other embodiments, relative traffic loads during various time ranges can be anticipated (rather than measured instantaneously), and an amplifier state can be selected based on the time information (e.g., the current time of day, the current day of the week, or based on some other time information). Yet in other embodiments, an amplifier state can be selected based on other factors.

[0118] To provide context, Figure 1 is a simplified block diagram of an example communication device 100 in which embodiments of the reconfigurable Doherty power amplifier (e.g., the amplifier 112) can be incorporated. For example, the communication device 100 can be implemented in a base station (not shown) of a cellular communication system (or in another device associated with a cellular or other type of communication system). The communication device 100 includes a baseband and intermediate frequency (IF) processing subsystem 101, a base station controller 103, a radio frequency (RF) transceiver 106, and an antenna 190.

[0119] The base station controller 103 includes hardware and associated software that is generally responsible for controlling the operation of the communication device 100, including managing radio channels (e.g., allocating channels and optimizing utilization of available resources), performing mobile device handovers, and performing call setup, among other operations.

[0120] According to one or more embodiments, the base station controller 103 can periodically or continuously perform traffic load measurements (traffic tracking) and can provide control signals 104 to the RF transceiver 106 based on the traffic load measurements. Based on the control signals 104 from the base station controller 103, the RF transceiver 106 (and more specifically, the amplifier controller 114) can reconfigure the output circuit of the amplifier 112 to one of a plurality of amplifier states (e.g., a full power state or a reduced power state), as will be discussed in greater detail later.

[0121] The base station controller 103 can periodically or continuously measure or determine the instantaneous traffic load condition of the system and can compare the instantaneous traffic load condition to one or more thresholds to determine a traffic load range into which the instantaneous traffic load condition falls. Each traffic load range can correspond to one amplifier state. The base station controller 103 can then provide a control signal (e.g., control signal 104) to the transmitter 107 indicating the amplifier state corresponding to the current traffic load. As will be described in detail below, the transmitter 107 then configures (or reconfigures) the amplifier (e.g., amplifier 112) in response to the control signal.

[0122] According to one or more other example embodiments, the base station controller 103 can maintain a lookup table relating time-of-day ranges to power levels (and / or amplifier states). For example, the base station controller 103 can determine a time-of-day range into which the current time-of-day falls. Each time-of-day range can correspond to one of a plurality of amplifier states. The base station controller 103 can then provide a control signal (e.g., control signal 104) to the transmitter 107 indicating the amplifier state corresponding to the current time-of-day. As will be described in detail below, the transmitter 107 then configures (or reconfigures) the amplifier (e.g., amplifier 112) in response to the control signal.

[0123] Referring again to Figure 1 , the baseband and IF processing subsystem 101 includes a transmit signal processor 102 and a receive signal processor 188. According to one or more embodiments, the transceiver 106 includes a transmitter 107, a circulator 180, an RF switch 184, and a receiver 186.

[0124] In a transmit mode of operation of the system 100, the transmit signal processor 102 of the baseband and IF processing subsystem 101 performs baseband and IF processing to produce an RF transmit signal 105. The transmitter 107 receives and amplifies the RF transmit signal 105 and produces an amplified RF transmit signal 113 that will ultimately be transmitted over the air by the antenna 190.

[0125] According to one or more embodiments, transmitter 107 includes an RF signal input 108, a control signal input 109, a power amplifier 112, an amplifier controller 114, and an RF signal output 110. Through the RF signal input 108, power amplifier 112 receives an RF transmission signal 105 from transmit signal processor 102. According to one or more embodiments, power amplifier 112 is a relatively high-gain amplifier that amplifies the RF transmission signal 105 and generates an amplified RF transmission signal 113 at RF signal output 110.

[0126] According to various embodiments, the power amplifier 112 may have a reconfigurable output circuit (e.g., Figure 3 , 4 The reconfigurable Dougherty power amplifier (e.g., output circuit 390) of the output circuit 390) Figure 3 , 4 Amplifier 300). As will be described in detail later, a reconfigurable output circuit configuration is established based on control signal 104 received from base station controller 103. As indicated above, control signal 104 may indicate amplifier state (e.g., state 1 or state 2). According to one or more embodiments, amplifier controller 114 receives control signal 104 from base station controller 103 via control signal input 109 (e.g., a serial peripheral input (SPI) port or another suitable control signal interface). Based on control signal 104, amplifier controller 114 may determine additional control signals (e.g., via...). Figure 1 , 3 The switching control signal of the switching control line 116 of the 4th generation (and the additional control signal) is provided to the power amplifier 112, which allows the power amplifier 112 to reconfigure its output circuitry (e.g., Figure 3 , 4 The output circuitry of power amplifier 112 (390) enables it to amplify the RF transmit signal 105 in a linear and efficient manner over a wide range of average power levels and service load conditions, as will be described in more detail later.

[0127] The amplified RF transmit signal 113 generated at the RF output 110 of transmitter 107 is transmitted to circulator 180. Circulator 180 includes a transmitter port 181, an antenna port 182, and a receiver port 183. The amplified RF transmit signal 113 is received at transmitter port 181 of circulator 180. Circulator 180 can then transmit the amplified RF transmit signal 113 to antenna port 182, which is coupled to antenna 190. Antenna 180 is configured to radiate the amplified RF transmit signal 113 through an air interface.

[0128] The circulator 180 is characterized by signal conduction directionality indicated by the arrows within the drawing of the circulator 180. Essentially, RF signals are conveyed between the circulator ports 181-183 in the indicated direction (counterclockwise) but not in the opposite direction (clockwise). Thus, during normal operation, signals can be conveyed through the circulator 180 from the transmitter port 181 to the antenna port 182 and from the antenna port 182 to the receiver port 183, but not directly from the transmitter port 181 to the receiver port 183 or from the receiver port 183 to the antenna port 182.

[0129] In the receive mode of operation, the antenna 190 can receive RF signals over the air interface and can provide the RF receive signals to the antenna port 182 of the circulator 180. The circulator 180 can then convey the RF receive signals to the receiver port 183 of the circulator 180. The receiver port 183 of the circulator 180 can be coupled to the receiver 186 through the RF switch 184. The receiver 186 includes a receive amplifier 187 (e.g., a low noise amplifier) that amplifies the RF receive signals and provides the amplified RF receive signals to a receive signal processor 188 of the baseband and IF processing subsystem 101.

[0130] The RF switch 184 is optional, but desirably included to ensure good isolation for the receiver 186. In particular, in some cases, when the transceiver 106 is in the transmit mode of operation, the circulator 180 can not be able to convey signal energy received through the transmitter port 181 through the antenna port 182 to the antenna 190. For example, the antenna 190 can be disconnected from the antenna port 182, or can otherwise be in a very high impedance state. In such cases, the circulator 180 can convey signal energy from the transmitter 107 (i.e., signal energy received through the transmitter port 181) through the antenna port 182 to the receiver port 183. To avoid conveying transmitter signal energy into the receiver 186 when the transceiver 106 is in the transmit mode, the RF switch 184 can operate as a fail-safe switch that couples any transmitter signal energy to a ground reference node (not shown) when the transceiver 106 is in the transmit mode.

[0131] Figure 1 The configuration of the communication device 100 shown in FIG. 1 is provided for contextual and illustrative purposes. In other embodiments, the circulator 180 can not be included, and an RF switch can instead be used to establish a signal path between the antenna 190 and the transmitter 107 or receiver 186 in a half-duplex fashion. Other modifications to the communication device 100 can also be made.

[0132] To better explain how power amplifier 112 can be reconfigured to provide linear and efficient amplification over a wide range of average output power levels, refer now to Figure 2 Figure 200 shows two power efficiency curves 210 and 220. Power efficiency curve 210 is associated with a first amplifier state (state 1 or "full power") corresponding to the full average output power condition, and power efficiency curve 220 is associated with a second amplifier state (state 2 or "reduced power") corresponding to the reduced power condition. The horizontal axis of Figure 200 corresponds to the output power (in dBm), and the vertical axis of Figure 200 corresponds to the drain efficiency (in percentage).

[0133] In the terminology used for the Dougherty power amplifiers in this article, "saturated output power" P SAT This refers to the output power level of the Dougherty power amplifier when it enters saturation, and the "back-off output power" P. BO This refers to the lower output power level (e.g., typically below P) along the same power efficiency curve as when the peaked amplifier of a Dougherty power amplifier begins to conduct. SAT (Approximately 6dB to approximately 10dB). Each amplifier state allows for reconfigurable Dougherty power amplifier efficiency characterized by different saturated output power P. SAT and different back-off output power P BO Therefore, each power efficiency curve 210 and 220 is characterized by different saturation output power PSAT and different back-off output power PBO.

[0134] As used in this article, the "fully" saturated output power P SAT-F This refers to the theoretically highest saturated output power, which is associated with an embodiment of a reconfigurable Dougherty power amplifier configured to be in full-power mode (state 1). Similarly, as used herein, the "full" back-off output power P BO-F This means that the amplifier is configured to operate at full power (e.g., below the fully saturated output power P). SAT-F The first efficiency peak occurs at P (approximately 6 dB to approximately 10 dB). SAT-F The following power levels.

[0135] Conversely, the "reduced" saturated output power P SAT-R This refers to the saturated output power below the full saturated output power, and is associated with an embodiment of the Dougherty power amplifier configured in a reduced power state (state 2). Therefore, the "reduced" back-off output power P BO-R This means that when the amplifier is configured to operate in reduced power mode, the first efficiency peak occurs below P. SAT-R The power level.

[0136] The reconfigurable Dougherty power amplifier embodiments discussed herein are configured to support full-power mode (corresponding to P...). SAT-F and P BO-F ) and at least one reduced power state. In such embodiments, P can be used SAT-R and P BO-R Indicates a specific power reduction state.

[0137] refer to Figure 2 Power efficiency curve 210 corresponds to the full-power state (e.g., state 1). As indicated by curve 210, when the embodiment of the reconfigurable Dougherty power amplifier is configured to be in the full-power state, the fully saturated output power P SAT-F It is approximately 47 dBm, as indicated by circle 211, and the full back-off output power P BO-F It is approximately 38 dBm, as indicated by circle 212 (e.g., below the fully saturated output power 211P). SAT-F (Approximately 9 dB). Depending on various characteristics of the reconfigurable Dougherty power amplifier (e.g., operating frequency, circuit topology, and other characteristics), the full-saturation output power and full-back output power may have higher or lower values ​​than those given above.

[0138] Power efficiency curve 220 corresponds to a reduced power state (e.g., state 2). As indicated by curve 220, when an embodiment of the reconfigurable Dougherty power amplifier is configured to be in a reduced power state, the reduced saturated output power P SAT-R It is approximately 47 dBm, as indicated by circle 221, and the backoff output power P is reduced. BO-R It is approximately 36 dBm, as indicated by circle 222 (e.g., below the reduced saturation output power 221P). SAT-R (Approximately 11 dBm). Similarly, depending on the various characteristics of the reconfigurable Dougherty power amplifier, the reduced saturation output power and reduced back-off output power can have values ​​higher or lower than those given above.

[0139] During operation of an embodiment of the reconfigurable Doherty power amplifier, the amplifier can be configured to operate at a relatively high P-value when high traffic load conditions are present. SAT And the corresponding P that is relatively high BO The amplifier's power efficiency curve (e.g., curve 210) indicates the amplifier's state (e.g., full power state) to support amplification at high average output power levels. Conversely, the amplifier can be configured to operate in a state characterized by relatively low P values ​​when lower traffic load conditions are present. SAT and the relatively low corresponding P BOof the power efficiency curve (e.g., curve 220) of the power amplifier (e.g., to a reduced power state) in order to support amplification at lower average output power levels. Reconfiguring the Doherty power amplifier to a reduced P SAT and a reduced corresponding P BO operated capability has the potential advantage (e.g., when traffic load is relatively low) of enabling efficient processing of signals at lower average output power levels, thus enabling overall power savings.

[0140] Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figure 3 , 4 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figure 3 , 4 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figure 3 , 4 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figure 3 , 4 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figures 3-6 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110).

[0141] Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figures 3-6 Figures 3-6 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figures 3-6 Figures 3-6 Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110).

[0142] Embodiments of the reconfigurable Doherty power amplifier described herein include a reconfigurable output circuit (e.g., output circuit 390) coupled between the output of the carrier amplifier and peaking amplifier (e.g., amplifiers 331, 371) and an RF signal output (e.g., output 110). Figure 3 , 4 ​​reconfigurable peaking output capacitance circuit (e.g., a peaking output capacitance circuit 334) coupled between the peaking amplifier output and the combination node, and a reconfigurable carrier output capacitance circuit (e.g., a carrier output capacitance circuit 374) coupled between the carrier amplifier output and the combination node. The reconfigurable peaking output capacitance circuit and the reconfigurable carrier output capacitance circuit can be selectively configured to modify the drain-source capacitances C Figure 3 , 4

[0143] The effective values of C EFF_C and C EFF_P . Figure 3 4 An additional embodiment of a reconfigurable Doherty power amplifier can include a reconfigurable output impedance transformer (e.g., a transformer 382) coupled between the combination node and an amplifier output (e.g., an RF output 110). The reconfigurable output impedance transformer can be configured to modify the impedance at the combination node. Figure 3 4 As used herein, "reconfigurable" means that individual elements in a circuit can be controlled (e.g., switched into or out of the circuit) to configure the Doherty power amplifier into any one of a plurality of amplifier states. Each amplifier state can be structured such that the amplifier achieves peak efficiency (e.g., 60% or higher) at full output power and at reduced output power.

[0144] For example, some embodiments of a reconfigurable Doherty power amplifier include a reconfigurable output circuit that can be selectively configured into either of two amplifier states, with the first amplifier state desirably selected for full average output power (e.g., 39.5 dBm or some other value) and the second amplifier state desirably selected for a single reduced average output power level (e.g., 38.0 dBm or some other value).

[0145] For example, some embodiments of a reconfigurable Doherty power amplifier include a reconfigurable output circuit that can be selectively configured into either of two amplifier states, with the first amplifier state desirably selected for full average output power (e.g., 39.5 dBm or some other value) and the second amplifier state desirably selected for a single reduced average output power level (e.g., 38.0 dBm or some other value).

[0146] For purposes of illustration only and not limitation, the example Doherty power amplifier embodiments discussed in detail below have a 2: 1 asymmetry ratio and include a reconfigurable 0 degrees / 90 degrees (0 / 90) output circuit (i.e., an electrical length of approximately 0 degrees couples the peaking amplifier intrinsic drain terminal and the combination node, and an electrical length of approximately 90 degrees couples the carrier amplifier intrinsic drain terminal and the combination node). With a 2: 1 asymmetry ratio, the size and power handling capability P peaking of the peaking amplifier is twice the size and power handling capability P carrier ​​​about two times. Other embodiments can include reconfigurable output circuits implemented in symmetric Doherty power amplifiers or implemented in asymmetric Doherty power amplifiers having different asymmetry ratios. Further, other embodiments can include reconfigurable output circuits having different electrical lengths (e.g., 90 / 180, 180 / 270, etc.) between the carrier eigen-leakage end and the peaking eigen-leakage end and the combining node. In addition, the Doherty power amplifier embodiments discussed herein correspond to a "non-inverted" configuration in which the peaking input RF signal (at the input of peaking amplifier 371) is delayed from the carrier input RF signal (at the input of carrier amplifier 331) by about 90 degrees in order to compensate for the about 90 degree phase delay imposed to the amplified carrier output RF signal between carrier amplifier output 332 and the combining node 380. Alternative embodiments can include an "inverted" Doherty power amplifier configuration in which the carrier input RF signal (at the input of carrier amplifier 331) is delayed from the peaking input RF signal (at the input of peaking amplifier 371) by about 90 degrees in order to compensate for the about 90 degree phase delay imposed to the amplified peaking output RF signal between peaking amplifier output 372 and the combining node 380. In the inverted Doherty power amplifier configuration, the reconfigurable impedance inverter circuit (e.g., circuit 340, 340', 340") would exist between peaking amplifier output 372 and the combining node 380 instead of between carrier amplifier output 332 and the combining node 380. Figures 3-6

[0147] The example component values provided below correspond to a 2: 1 asymmetric Doherty power amplifier having a full saturated output power P SAT-F of about 47 dBm, a full average output power level of about 39.5 dBm, and a first efficiency peak at a full back-off output power P SAT-F of about 38 dBm (i.e., about 9 dB below P BO-F It should be understood that embodiments of Doherty power amplifiers can be designed to have different asymmetry ratios (including symmetric Doherty power amplifiers), different full saturated output powers, different full average output power levels, and / or efficiency peaks at different full back-off output powers, and such Doherty power amplifier embodiments can have different component values than the example component values provided herein.

[0148] ​Furthermore, although embodiments of the asymmetric Dougherty power amplifier are described in detail herein, it should be understood that other embodiments of the reconfigurable Dougherty power amplifier may have a symmetrical configuration (e.g., the relative size and power handling capability of the carrier amplifier and peaking amplifier are equal). As used herein, when referring to the physical characteristics of a power amplifier or power transistor, the term “size” refers to the peripheral or power handling capability of the transistor associated with said amplifier or transistor. When referring to the relative size and power handling capability of the carrier amplifier and peaking amplifier, the term “symmetric” means that the cumulative size of the power transistors forming the carrier amplifier is substantially equal to (i.e., within 5%) the cumulative size of the power transistors forming the peaking amplifier. Conversely, the term “asymmetric” means that the cumulative size of the power transistors forming the peaking amplifier is 25% to 200% (e.g., 100%) larger than the cumulative size of the power transistors forming the carrier amplifier. Therefore, for example, when the ratio of the peaking amplifier size to the carrier amplifier size (or "peaking-carrier ratio") is expressed as x:y (where x corresponds to the relevant peaking amplifier size and y corresponds to the relevant carrier amplifier size), according to the above definition, a 1:1 ratio corresponds to a symmetrical amplifier, while a 2:1 ratio corresponds to an asymmetrical amplifier. Furthermore, as used herein, the term "shunt" means electrically coupled between a circuit node and a ground reference (or other DC voltage reference).

[0149] The following are embodiments of reconfigurable Dougherty power amplifiers (e.g., Figure 1 The amplifier 112) provides additional details, stating that the reconfigurable Dougherty power amplifier can be dynamically configured to different states to modify the impedance at 2f0 and f0 and to achieve multiple power efficiency curves (e.g., Figure 2 The power efficiency curves 210 and 220 are shown. As previously mentioned, the reconfigurable Dougherty power amplifier embodiment includes first and second LC networks selectively attachable to a reconfigurable impedance inverter circuit via a switching circuit. When the Dougherty power amplifier operates in full-power mode, the switches of the switching circuit are controlled to be closed to achieve the desired impedance of the inverter circuit. In this state, the switching circuit electrically couples the first and second LC networks to the reconfigurable impedance inverter circuit to provide harmonic termination at the output of the carrier amplifier, thereby improving the full-power baseline performance. When the Dougherty power amplifier operates in a reduced-power mode, the switches are controlled to be open to achieve a different desired impedance of the inverter circuit (e.g., an impedance higher than that in full-power mode). Therefore, the first and second LC networks are disconnected from the reconfigurable impedance inverter circuit. In this case, the parasitic capacitance of each “off” state switch, together with the rest of the inverter circuit system, provides the desired load impedance to the carrier amplifier to achieve optimal performance at the reduced power level.

[0150] According to one or more embodiments, and as will be discussed in detail below, a first LC network is configured to resonate at or near the second harmonic frequency 2f0, and a second LC network is configured to resonate at or near the fundamental frequency f0. The values ​​of the first and second LC networks, as well as their positions along a reconfigurable guideline, can be carefully selected to optimize the impedance at 2f0 and f0. Using this method, the efficiency of the Dougherty power amplifier embodiment can be significantly improved while maintaining the same bandwidth.

[0151] Figure 3 and 4 This is a schematic diagram of a reconfigurable Dougherty power amplifier 300 with a reconfigurable output circuit 390 according to an example embodiment, the reconfigurable output circuit 390 being selectively configured at least to a "full power state" ( Figure 3 ) and "reduce power state" Figure 4 More specifically, Figure 3 A reconfigurable Dougherty power amplifier 300 in full power mode is depicted, wherein the aforementioned first LC network and second LC network (hereinafter referred to as harmonic frequency resonant circuit 359 (or "2f0 notch filter") and fundamental frequency tuning circuit 356 (or "f0 notch filter"), respectively) are electrically coupled (through switching circuit 349) to reconfigurable impedance inverter circuit 340. Figure 4 A reconfigurable Dougherty power amplifier 300 in a reduced power state is depicted, wherein the aforementioned first and second LC networks (using switching circuitry 349) are decoupled from a reconfigurable impedance inverter circuitry 340. For the context, the reconfigurable Dougherty power amplifier 300 can be used as a power amplifier forming part of an RF circuitry system in a communication system (e.g., Figure 1 In amplifier 112).

[0152] The Doherty power amplifier 300 includes an RF input 108, an RF output 110, a power divider 320, a carrier amplification path 330 with a carrier amplifier 331, a peaking amplification path 370 with a peaking amplifier 371, a reconfigurable output circuitry 390 with a combination node 380, and a reconfigurable output impedance transformer 382. In an embodiment, an antenna 388 (or other type of load) is coupled to the RF output 110 (e.g., via a circulator). Figure 1 (Circuit 180), RF switch or other circuitry). Although not shown, a DC blocking capacitor may also be coupled between the combination node 380 and the RF output 110.

[0153] The Doherty power amplifier 300 is considered a "bidirectional" Doherty power amplifier, which includes a carrier amplification path 330 and a peaking amplification path 370. Essentially, a carrier amplifier 331 provides RF signal amplification along the carrier amplification path 330, and a peaking amplifier 371 provides RF signal amplification along the peaking amplification path 370. The amplified carrier and peaking RF signals are then delivered through a reconfigurable output circuit 390, and combined at a combining node 380, before being provided to the RF output 110 through a reconfigurable output impedance transformer 382.

[0154] The power divider 320 is configured to receive an input RF signal from the RF input 108 at a power divider input 322. The power divider 320 is additionally configured to divide the power of the input RF signal into a carrier input RF signal and a peaking input RF signal produced at power divider outputs 324, 326, respectively. In this way, the power divider 320 is configured to provide the carrier input RF signal to the carrier amplification path 330, and to provide the peaking input RF signal to the peaking amplification path 370. In the Doherty power amplifier 300, the power divider 320 is configured such that, at a center operating frequency fo of the amplifier 300, the input signal supplied to the peaking amplification path 370 is delayed relative to the input signal supplied to the carrier amplification path 330 by some input phase offset (e.g., about 90 degrees).

[0155] The power divider 320 can have any of a variety of configurations, including a Wilkinson-type divider, a hybrid-quadrature divider, and the like. The power divider 320 divides the power of the input RF signal according to a carrier-to-peaking size ratio. For example, when the Doherty power amplifier 300 has a symmetric Doherty power amplifier configuration in which the sizes of the carrier amplifier 331 and the peaking amplifier 371 are substantially equal, the power divider 320 can divide the power such that about half of the input signal power is provided to the carrier amplification path 330, and about half of the input signal power is provided to the peaking amplification path 370. Conversely, when the Doherty power amplifier 300 has an asymmetric Doherty power amplifier configuration, the power divider 320 can divide the power unequally. For example, when the Doherty power amplifier 300 has a 2: 1 peaking-to-carrier size ratio, the power divider 320 can divide the input signal power such that about one-third of the input signal power is provided to the carrier amplification path 330, and about two-thirds of the input signal power is provided to the peaking amplification path 370.

[0156] According to one or more embodiments, the carrier amplification path 330 includes a carrier input matching network (IMN) 327, a carrier amplifier 331, a reconfigurable carrier output capacitance circuit 334, and a reconfigurable impedance inverter circuit 340. Similarly, the peaking amplification path 370 includes a peaking IMN 328, a peaking amplifier 371, and a reconfigurable peaking output capacitance circuit 374. It can be noted here that the term "circuit" as used herein is analogous to "electronic circuit," "circuitry," and "network."

[0157] The carrier IMN 327 and the peaking IMN 328 are coupled between the power divider output 324 and the carrier amplifier 331 and between the power divider output 326 and the peaking amplifier 371, respectively. The carrier IMN 327 and the peaking IMN 328 can each include, for example, a low-pass or band-pass circuit configured as a T- or pi-type impedance matching network, although other matching network topologies are contemplated. Regardless of the configuration, the IMNs 327, 328 incrementally increase the circuit impedance toward the source impedance.

[0158] The carrier amplifier 331 and the peaking amplifier 371 can each be implemented as a power transistor (or series of power transistors). Thus, each of the carrier amplifier 331 and the peaking amplifier 371 has a control input (e.g., a gate terminal) and two current-carrying terminals (e.g., a drain terminal and a source terminal). A first one of the current-carrying terminals (e.g., the drain terminal) of the amplifiers 331, 371 acts as an output 332, 372 of the carrier amplifier 332 and the peaking amplifier 371, with the amplified RF signal being produced by the amplifiers 331, 371. A second one of the current-carrying terminals (e.g., the source terminal) of the amplifiers 331, 371 can be coupled to a ground reference node.

[0159] According to embodiments, the first current-carrying terminal (e.g., the drain terminal) of each amplifier 331, 371 corresponds to an intrinsic current generator (e.g., an intrinsic drain) of each amplifier 331, 371. The capacitors 333, 373 represent parasitic output capacitances (e.g., drain-source capacitances) present at the outputs of the carrier amplifier 331 and the peaking amplifier 371 (e.g., at the drain terminals of the carrier and peaking power transistors). In other words, the carrier amplifier output 332 is characterized by a drain-source capacitance 333 (or carrier amplifier output capacitance) between the drain terminal and the source terminal of the carrier amplifier 331. Similarly, the peaking amplifier output 372 is characterized by a drain-source capacitance 373 (or peaking amplifier output capacitance) between the drain terminal and the source terminal of the peaking amplifier 371. Although the capacitances 333, 373 are not discrete physical components (e.g., discrete capacitors), they are nonetheless represented as discrete components in the figures for ease of illustration. Figure 3 and 4The parasitic capacitances 333, 373 are depicted to help later discussion of how the reconfigurable output capacitance circuits 334, 374 can contribute to the effective output capacitances C of the carrier amplifier 331 and peaking amplifier 371 EFF_C and C EFF_P According to embodiments, the parasitic capacitances 333, 373 each have a capacitance value in a range of about 0.25 picofarads (pF) to about 20 pF, although the capacitance value can be lower or higher.

[0160] The carrier amplifier 331 and peaking amplifier 371 each include one or more power transistors (e.g., field effect transistors) embodied in a semiconductor die. In some embodiments, the semiconductor die that includes the carrier amplifier 331 and peaking amplifier 371 can be packaged in a power amplifier device or power amplifier module along with all or portions of the carrier IMN 327 and peaking IMN 328 and the reconfigurable output circuits 334, 340, 374.

[0161] According to embodiments, the carrier amplifier 331 and peaking amplifier 371 each include a single-stage amplifier (i.e., an amplifier having a single amplification stage or power transistor). In other embodiments, the carrier amplifier 331 is a two-stage amplifier that includes a relatively low-power driver amplifier (not shown) and a relatively high-power final amplifier (not shown) connected in a cascaded (or series) arrangement between a carrier amplifier input and a carrier amplifier output. Similarly, the peaking amplifier 371 can include a two-stage amplifier that includes a relatively low-power driver amplifier (not shown) and a relatively high-power final amplifier (not shown) connected in a cascaded arrangement between a peaking amplifier input and a peaking amplifier output.

[0162] Various DC bias circuits are coupled to the inputs and outputs of the carrier amplifier 331 and peaking amplifier 371 in order to deliver DC bias voltages that will ensure proper operation of the Doherty power amplifier 300. Figure 3 Gate bias circuits are not shown, but carrier drain bias circuit 392 and peaking drain bias circuit 394 are shown, respectively. More specifically, during operation of the Doherty power amplifier 300, the carrier amplifier 331 is biased to operate in an AB class mode or a deep AB class mode, and the peaking amplifier 371 is biased to operate in a C class mode or a deep C class or J class mode. In some configurations, the peaking amplifier 371 can be biased to operate in a B class mode.

[0163] For example, output DC bias circuits 392, 394 can be coupled to the outputs (e.g., drain terminals) of the carrier amplifier 331 and peaking amplifier 371, respectively, and the output DC bias circuits 392, 394 are configured to deliver drain bias voltages V DDC and V DDPoutputs (e.g., drain terminals) to the carrier amplifier 331 and the peaking amplifier 371. According to one or more embodiments, each output DC bias circuit 392, 394 can include a bias inductor 393, 395. The bias inductors 393, 395 can affect the effective output capacitances C EFF_C and C EFF_P When the amplifier 300 is a symmetric Doherty power amplifier having substantially equal parasitic output capacitances 333, 373, the bias inductors 393, 395 can have substantially equal inductance values. Conversely, when the amplifier 300 is an asymmetric Doherty power amplifier having unequal parasitic output capacitances 333, 373 (e.g., for a 2: 1 Doherty power amplifier, the parasitic output capacitance 373 of the peaking amplifier 371 can be about twice the parasitic output capacitance 333 of the carrier amplifier 331), the bias inductors 393, 395 can have unequal inductance values, which causes the effective output capacitances C EFF_C and C EFF_P of the carrier amplifier 331 and the peaking amplifier 371, respectively, to be equal.

[0164] The carrier amplifier 331 is configured to amplify a carrier input RF signal produced at the distributor output 324 and produce an amplified carrier output RF signal at a carrier amplifier output 332 (e.g., a carrier amplifier intrinsic drain terminal). Similarly, the peaking amplifier 371 is configured to amplify a peaking input RF signal produced at the distributor output 326 and produce an amplified peaking output RF signal at a peaking amplifier output 372 (e.g., a peaking amplifier intrinsic drain terminal).

[0165] The carrier amplifier output 332 and the peaking amplifier output 372 are coupled to the RF output 110 through the reconfigurable output circuit 390 and, in some embodiments, through the reconfigurable output impedance transformer 382. According to one or more embodiments, the reconfigurable output circuit 390 includes a combining node 380, a reconfigurable carrier output capacitance circuit 334 coupled to the carrier amplifier output 332, a reconfigurable impedance inverter circuit 340 (or a reconfigurable quasi- line) coupled between the carrier amplifier output 332 and the combining node 380, and a reconfigurable peaking output capacitance circuit 374 coupled to the peaking amplifier output 372 and the combining node 380.

[0166] The reconfigurable circuits 334, 340, 374 are configured to act as an impedance inverter. Generally, and as will be described in greater detail below, the impedance inverter includes a first shunt capacitance (e.g., the carrier drain-source capacitance 333 as modified by the reconfigurable carrier output capacitance circuit 334), a series inductance (the reconfigurable impedance inverter circuit 340), and a second shunt capacitance (e.g., the peaking drain-source capacitance 373 as modified by the reconfigurable peaking output capacitance circuit 374). In other words, the circuit formed by the reconfigurable circuits 334, 340, and 374 is a PI network consisting of a shunt C (parasitic capacitance 333 and circuit 334), a series L (circuit 340), and a shunt C (parasitic capacitance 373 and circuit 374). In theory, when the shunt C circuits have substantially equal capacitance values (i.e., C EFF_C = C EFF_P ), optimal performance (e.g., optimal bandwidth) of the amplifier 300 can be achieved. As will also be described in greater detail below, during operation of the amplifier 300, the reconfigurable circuits 334, 340, 374 are controlled in synchronization to set up the impedance inverter configuration that will achieve the desired peak efficiency power level. The reconfigurability of the reconfigurable circuits 334, 340, 374 enables setting up the correct / appropriate impedances at the carrier amplifier output 332 and the peaking amplifier output 372 (i.e., the drain terminals of the amplifiers 331, 371), which can ensure optimal signal amplification and later combining at full average output power levels and reduced average output power levels.

[0167] As mentioned above, each of the carrier amplifier 331 and the peaking amplifier 371 is characterized by a parasitic drain-source capacitance 333, 373. According to one or more embodiments, the reconfigurable carrier output capacitance circuit 334 is used to modify the parasitic drain-source capacitance 333 of the carrier amplifier 331 to produce an effective output capacitance C EFF_C at the carrier amplifier output 332 that is different from (e.g., lower than) the parasitic drain-source capacitance 333. Similarly, the reconfigurable peaking output capacitance circuit 374 is used to modify the parasitic drain-source capacitance 373 of the peaking amplifier 371 to produce an effective output capacitance C EFF_P at the peaking amplifier output 372 that is different from (e.g., lower than) the parasitic drain-source capacitance 373.

[0168] During operation, the shunt inductances provided by the reconfigurable carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 are used to resonate out some of the parasitic drain-source capacitances 333, 373. In other words, the carrier amplifier effective output capacitance C EFF_CThe carrier amplifier parasitic drain-source capacitance 333 (or the first shunt capacitance of the impedance inverter) is defined by a reconfigurable carrier output capacitance circuit 334 modification, and the peaking amplifier effective output capacitance C EFF_P The peaking amplifier parasitic drain-source capacitance 373 (or the second shunt capacitance of the impedance inverter) is defined by a reconfigurable peaking output capacitance circuit 374 modification. It can be noted here that the peaking amplifier effective output capacitance C EFF_P It can also be affected by the capacitance value of the reconfigurable output impedance transformer 382, described later.

[0169] According to one or more embodiments, to achieve optimal performance, the effective output capacitances C EFF_C and C EFF_P are controlled to be equal or approximately equal to each other, regardless of whether the Doherty power amplifier 300 is a symmetric or asymmetric Doherty power amplifier. In other embodiments, the effective output capacitances C EFF_C and C EFF_P may be controlled to be different from each other, while still achieving at least some of the benefits described herein.

[0170] In the embodiments shown in Figure 3 and 4 , the reconfigurable carrier output capacitance circuit 334 includes a reconfigurable shunt circuit coupled between the carrier amplifier output 332 and a ground reference node. Similarly, the reconfigurable peaking output capacitance circuit 374 includes a reconfigurable shunt circuit coupled between the peaking amplifier output 372 and a ground reference node.

[0171] Each reconfigurable carrier and peaking output capacitance circuit 334, 374 includes a dc blocking capacitor 335, 375 coupled in series with a first inductive element 336, 376 between the carrier amplifier output 332 or the peaking amplifier output 372 and an intermediate node (not numbered). Additionally, each reconfigurable carrier output capacitance circuit 334 and peaking output capacitance circuit 374 includes a second inductive element 337, 377 coupled in parallel with a bypass switch element 338, 378 between the intermediate node and a ground reference node. More specifically, a first end of each capacitor 335, 375 is coupled to the carrier amplifier output 332 or the peaking amplifier output 372, and a second end of each capacitor 335, 375 is coupled to a first end of the first inductive element 336, 376, and a second end of each first inductive element 336, 376 is coupled to the intermediate node. Additionally, a first end of each second inductive element 337, 377 and a first end of each bypass switch element 338, 378 is coupled to the intermediate node, and a second end of each second inductive element 337, 377 and a second end of each bypass switch element 338, 378 is coupled to the ground reference node.

[0172] In the full power state, when the switch element 338, 378 is open, as shown in Figure 3 the series inductance provided by the inductive elements 336+337 and 376+377 is used to resonate out a portion of the parasitic drain-source capacitance 333, 373, thus reducing C EFF_C and C EFF_P respectively, in the full power state. In the reduced power state, when the switch element 338, 378 is closed, as shown in Figure 4 the inductive elements 337 and 377 are bypassed by the switch element 338, 378, and only the series inductance provided by the inductive elements 336 and 376 is used to resonate out a smaller portion of the parasitic drain-source capacitance 333, 373, thus reducing C EFF_C and C EFF_P respectively, by a smaller amount.

[0173] The capacitance and inductance values selected for the capacitors 335, 375 and the inductive elements 336, 337, 376, 377 can be based on an operating fundamental frequency fo of the amplifier 300. For example, fo can be in a range from about 800 megahertz (MHz) to about 7 gigahertz (GHz), although fo can be lower or higher. According to one or more embodiments, each of the capacitors 335, 375 has a capacitance value in a range from about 3 pF to about 22 pF, and each of the inductive elements 336, 337, 376, 377 has an inductance value in a range from about 0.25 nanohenry (nH) to about 12 nH, although the capacitance and / or inductance values can be lower or higher.

[0174] According to one or more embodiments, the reconfigurable carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 can have similar or identical circuit topologies. For example, in embodiments where the Doherty power amplifier 300 is a symmetric amplifier, corresponding capacitors in the reconfigurable carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 can have equal capacitance values (e.g., capacitors 335, 375 can have equal capacitance values), corresponding first and second inductive elements in the reconfigurable carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 can have equal inductance values (e.g., inductive elements 336, 376 can have equal inductance values, and inductive elements 337, 377 can have equal inductance values). Conversely, in embodiments where the Doherty power amplifier 300 is an asymmetric amplifier, corresponding capacitors in the reconfigurable carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 can have unequal but scaled capacitance values (e.g., for a 2: 1 peaking-to-carrier ratio, capacitor 375 can have twice the capacitance value of capacitor 335). Moreover, corresponding first and second inductive elements in the reconfigurable carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 can have unequal but scaled inductance values (e.g., for a 2: 1 peaking-to-carrier ratio, inductive elements 376 and 377 can have twice the inductance values of inductive elements 336 and 337, respectively).

[0175] Capacitor 339 is coupled between the carrier amplifier output 332 (and the reconfigurable carrier output capacitance circuit 334) and the reconfigurable impedance inverter circuit 340, and capacitor 369 is coupled between the peaking amplifier output 372 (and the reconfigurable peaking output capacitance circuit 374) and the combining node 380. Capacitors 339, 369 act as dc-blocking capacitors and also help with impedance matching between the carrier amplifier output 332 and the peaking amplifier output 372 and the combining node 380.

[0176] As shown in FIG. 3, the reconfigurable carrier output capacitance circuit 334 includes a first inductive element 336 coupled in series with a second inductive element 337, which are in turn coupled in parallel with a capacitor 335. The reconfigurable peaking output capacitance circuit 374 includes a first inductive element 376 coupled in series with a second inductive element 377, which are in turn coupled in parallel with a capacitor 375. The first inductive elements 336, 376 and the second inductive elements 337, 377 can be implemented as inductors, and the capacitors 335, 375 can be implemented as capacitors. Figure 3 and 4 As shown in FIG. 3, the reconfigurable carrier output capacitance circuit 334 includes a first inductive element 336 coupled in series with a second inductive element 337, which are in turn coupled in parallel with a capacitor 335. The reconfigurable peaking output capacitance circuit 374 includes a first inductive element 376 coupled in series with a second inductive element 377, which are in turn coupled in parallel with a capacitor 375. The first inductive elements 336, 376 and the second inductive elements 337, 377 can be implemented as inductors, and the capacitors 335, 375 can be implemented as capacitors.

[0177] More specifically, the series circuit of the reconfigurable impedance inverter circuit 340 includes an input node 341 coupled in series between the carrier amplifier output 332 and a combination node 380, a first transmission line section 342, a first intermediate node 343, a first inductive element 344, a second intermediate node 345, and a second transmission line section 346. More specifically, the input node 341 is coupled to the carrier amplifier output 332 through a dc blocking capacitor 339. A first end of the first transmission line section 342 is coupled to the input node 341, and a second end of the first transmission line section 342 is coupled to the first intermediate node 343. A first end of the first inductive element 344 is coupled to the first intermediate node 343, and a second end of the first inductive element 344 is coupled to the second intermediate node 345. A first end of the second transmission line section 346 is coupled to the second intermediate node 345, and a second end of the second transmission line section 346 is coupled to the combination node 380.

[0178] The inductive element 344 can include, for example, a discrete inductor. In other embodiments, the inductive element 344 can be a transmission line section (e.g., transmission line section 344' shown to the left of the inductive element 344). Either way, the inductive element 344 (or transmission line section 344') is characterized by an electrical length and a characteristic impedance, referred to herein as Z 344 .

[0179] The shunt circuit of the reconfigurable impedance inverter circuit 340 includes a third transmission line section 347, a fourth transmission line section 348, a switching circuit 349, a second inductive element 355, a fundamental frequency tuning circuit 356, and a harmonic frequency resonant circuit 359. More specifically, the third transmission line section 347 has a first end coupled to the first intermediate node 343 and a second end coupled to a first switching circuit end 350 of the switching circuit 349. The fourth transmission line section 348 has a first end coupled to the second intermediate node 345 and a second end coupled to a second switching circuit end 351 of the switching circuit 349.

[0180] The third transmission line section 347 and the second inductive element 355 are coupled in series between the first intermediate node 343 and a ground reference node. The series combination of the third transmission line section 347 and the second inductive element 355 forms a shunt circuit that helps match / transform the impedance between the carrier amplifier output 332 and the combination node 380. According to one or more embodiments, the second inductive element 355 (e.g., a discrete inductor, a transmission line section, or a set of bond wires) has an inductance value in the range of about 3 nH to about 9 nH, although the inductance value can be lower or higher.

[0181] In Figure 3 and 4In this embodiment, the switching circuit 349 includes a first switching circuit terminal 350, a second switching circuit terminal 351, a first switching element 352 coupled between the first switching circuit terminal 350 and the intermediate node 354, and a second switching element 353 coupled between the intermediate node 354 and the second switching circuit terminal 351. The fundamental frequency tuning circuit 356 and the harmonic frequency resonant circuit 359 are both coupled between the intermediate node 354 and the ground reference node.

[0182] Brief reference Figure 5 In the reconfigurable impedance inverter circuit 340' (which can replace Figure 3 , 4 In an alternative embodiment of circuit 340), switching circuit 349' includes a first switching circuit terminal 350, a second switching circuit terminal 351, a first switching element 352 coupled between the first switching circuit terminal 350 and intermediate node 354, and a second switching element 353 coupled between intermediate node 354 and second switching circuit terminal 351. However, with Figure 3 and 4 In contrast to the embodiments, Figure 5 In one embodiment, the harmonic frequency resonant circuit 359 is coupled between the second switch circuit terminal 351 and the ground reference node, and the fundamental frequency tuning circuit 356 is coupled between the intermediate node 354 and the ground reference node.

[0183] exist Figures 3-5 In all embodiments, and according to one or more embodiments, the harmonic frequency resonant circuit 359 includes an LC network comprising an inductor 360 (e.g., a discrete inductor, a transmission line segment, or a set of bonded wires) and a capacitor 361 series coupled between an intermediate node 354 and a ground reference node. Figure 3 , 4 As shown, the first end of inductor 360 is coupled to intermediate node 354, and the second end of inductor 360 is coupled to the first end of capacitor 361. The second end of capacitor 361 is coupled to ground reference node. It should be noted that the series order of inductor 360 and capacitor 361 in circuit 359 may differ from that of inductor 360 and capacitor 361 in... Figure 3 and 4 The order shown is reversed. (Brief reference) Figure 6 In an alternative embodiment of the reconfigurable impedance inverter circuit 340", Figures 3-5 The harmonic frequency resonant circuit 359 is replaced by the first branch line 359' (also known as the harmonic frequency resonant circuit 359').

[0184] Regardless of the approach, the harmonic frequency resonant circuit 359, 359' is configured to resonate at or near the second harmonic frequency of the operating fundamental frequency fo of the amplifier 300, or at 2fo (e.g., where“at or near” means exactly at the second harmonic frequency 2fo, or at a frequency between about 90% and about 110% of 2fo). According to one or more embodiments, the inductive element 360 has an inductance value in a range of about 0.5 nH to about 1.0 nH, and the capacitor 361 has a capacitance value in a range of about 0.3 pF to about 1.0 pF, although the inductance and / or capacitance values can be lower or higher.

[0185] According to one or more embodiments, the shunt circuit of the reconfigurable impedance inverter circuit 340, 340' further includes the above-described fundamental frequency tuning circuit 356 coupled between the intermediate node 354 of the switching circuit 349 and the ground reference node. More specifically, the fundamental frequency tuning circuit 356 can be an LC network including an inductive element 357 (e.g., a discrete inductor, a section of transmission line, or a set of bond wires) and a capacitor 358 coupled in series between the intermediate node 354 and the ground reference node. As shown in Figure 3 、 4 The first end of the inductive element 357 is coupled to the intermediate node 354, and the second end of the inductive element 357 is coupled to the first end of the capacitor 358. The second end of the capacitor 358 is coupled to the ground reference node. It should be noted that the series order of the inductive element 357 and the capacitor 358 in the circuit 356 can be reversed from the order shown in Figure 3 and 4 Briefly referring again to Figure 6 , in an alternative embodiment of the reconfigurable impedance inverter circuit 340", the fundamental frequency tuning circuit 356 of Figures 3-5 is replaced with a second shunt stub 356' (also referred to as a fundamental frequency tuning circuit 356').

[0186] The harmonic frequency resonance circuit 359, 359' is substantially capacitive at the fundamental frequency f0, and the resonance network of the fundamental frequency tuning circuit 356, 356' (i.e., the inductive element 357 and the capacitor 358 or the second shunt stub 356') functions to cancel the capacitive nature of the harmonic frequency resonance circuit 359, 359' at f0 by behaving like a shunt inductance in parallel with the capacitive harmonic frequency resonance circuit 359. In other words, the harmonic frequency resonance circuit 359, 359' is primarily characterized by capacitance at f0, and the fundamental frequency tuning circuit 356, 356' is primarily characterized by inductance at f0. Thus, when the switching circuit 349 (or 349') is configured to be in the full power state, the inductance of the fundamental frequency tuning circuit 356, 356' cancels the capacitance of the harmonic frequency resonance circuit 359, 359'. According to one or more embodiments, the fundamental frequency tuning circuit 356, 356' is configured to resonate at or near the operating fundamental frequency f0 of the amplifier 300 (e.g., where "at or near" means exactly at the fundamental frequency f0, or at a frequency between about 90% and about 110% of f0).

[0187] As an explanation, the fundamental frequency tuning circuit 356, 356' (or "f0 trap") and the harmonic frequency resonance circuit 359, 359' (or "2f0 trap") are both positioned along the reconfigurable impedance inverter circuit 340 (i.e., along the reconfigurable stub), and the positions of the fundamental frequency tuning circuit 356, 356' and the harmonic frequency resonance circuit 359, 359' can be designed to be relatively electrically close to the combination node 380 and the peaking amplifier 371. Thus, according to one or more embodiments, 2f0 (short) will be transmitted as a short 2f0 through the 90-degree (referring to f0) stub to the carrier amplifier output 332 (e.g., the drain terminal). Conversely, short f0 will be transmitted as an open circuit through the reconfigurable impedance inverter circuit 340 (i.e., through the reconfigurable stub) to the carrier amplifier output 332. Thus, these f0 and 2f0 traps along the reconfigurable impedance inverter circuit 340 collectively form a 2f0 termination and an open circuit at f0 to ensure that the f0 / 2f0 network will not affect the basic matching of the Doherty power amplifier 300. Depending on the positions of the 2f0 / f0 traps along the reconfigurable impedance inverter circuit 340 (i.e., along the reconfigurable stub), there is a certain frequency range for both the 2f0 and f0 trap resonance frequencies. According to one or more embodiments, to achieve the desired resonance, the inductive element 355 has an inductance value in the range of about 1 nH to about 3.0 nH, and the capacitor 358 has a capacitance value in the range of about 1.0 pF to about 2.0 pF, although the inductance and / or capacitance values can also be lower or higher.

[0188] As mentioned above, the inductive element 344 (or transmission line section 344') is characterized by an electrical length and a characteristic impedance Z 344Furthermore, each of the first, second, third, and fourth transmission line segments is characterized by an electrical length β and a characteristic impedance Z. As used herein, the characteristic impedance of the transmission line segments 342, 346, 347, 348 can be referred to as Z 342 , Z 346 , Z 347 , Z 348 The electrical lengths of the transmission line segments 342, 346, 347, 348 can be equal or unequal, and the characteristic impedances of the transmission line segments 342, 346, 347, 348 can be equal or unequal.

[0189] The total impedance value Z TOT of the reconfigurable impedance inverter circuit 340, 340', 340" depends on the state of the switching circuit 349, 349', and more specifically on whether the harmonic frequency resonant circuit 359, 359' and the base frequency tuned circuit 356, 356' are coupled to the reconfigurable impedance inverter circuit 340, 340', 340" through the switching circuit 349, 349'.

[0190] Embodiments of the reconfigurable impedance inverter circuit 340, 340', 340" can be designed to implement an impedance inverter that is characterized by the same phase but different characteristic impedances in a full power state and a reduced power state. Typically, the total impedance value Z TOT of the reconfigurable impedance inverter circuit 340, 340', 340" between the carrier amplifier output 332 and the combination node 380 is higher when the reconfigurable impedance inverter circuit 340, 340', 340" is configured to be in the reduced power state than when the reconfigurable impedance inverter circuit 340, 340', 340" is configured to be in the full power state. As an illustrative approximation, if the amplifier 300 is configured such that the reduced power state is x dB back from the full power state, then the ratio of the reduced power state Z TOT ("Z TOT _red") to the full power state Z TOT ("Z TOT _full") can be approximately 10^(x / 10). For example, if the reduced power state is 3 dB back from the full power state, then Z TOT _red = 2 * Z TOT _full.

[0191] The impedance values and electrical lengths selected for the transmission line sections 342, 346, 347, 348 can be based on an operating fundamental frequency fo (e.g., about 800 MHz to about 7 GHz) of the amplifier 300. According to one or more embodiments, each of the parallel transmission line sections 342, 346, 347, 348 has an impedance value in a range of about 20 ohms to about 100 ohms, although the impedance value can also be lower or higher. Further, according to one or more embodiments, each of the transmission line sections 342, 346, 347, 348 has an electrical length in a range of about 10 degrees to about 40 degrees, although the electrical length can also be lower or higher. According to one or more embodiments, the electrical lengths of the transmission line sections 342, 346, 347, 348 are selected such that the total electrical length between the output 332 of the carrier amplifier 332 and the combining node 380 is about 90 degrees for signal energy at the operating fundamental frequency fo. Additionally, according to one or more embodiments, the electrical lengths of the transmission line sections 347, 348 (and switches 352, 353) are designed such that the total electrical length of these series-coupled components is approximately equal to the electrical length of the inductive element 344 (or transmission line section 344'). In various embodiments, the characteristic impedances of the inductive element 344 and the transmission line sections 347, 348 (and switches 352, 353) can be the same or different.

[0192] As previously mentioned, the switch elements 338, 352, 353, 378, 387 are not ideal components, and each switch element is characterized by some degree of loss. According to one or more embodiments, each of the switch elements 338, 352, 353, 378, 387 can be implemented as an active switching device (e.g., a field effect transistor (FET)) having a control terminal (e.g., a gate terminal) and current conduction terminals (e.g., drain and source terminals). For example, the switch elements 338, 352, 353, 378, 387 can include a metal-oxide-semiconductor FET (MOSFET), a high electron mobility transistor (HEMT), a metal-semiconductor field effect transistor (MESFET), a laterally diffused metal-oxide-semiconductor (LDMOS) FET, an enhancement-mode MOSFET (EMOSFET), and / or a junction gate FET (JFET), to name a few.

[0193] During operation of the Doherty power amplifier 300, the state of the reconfigurable impedance inverter circuit 340, 340', 340" can be controlled to be in a full-power state (State 1) or a reduced-power state (State 2) by controlling the switch elements 352, 353 of the switch circuit 349, 349'. Figure 3 Figures 4-6 ​State 2). According to one or more embodiments, the switching elements 352, 353 are controlled synchronously. In other words, to set up the full-power state or the reduced-power state configuration of the amplifier 300, the states of the switching elements 352, 353 are controlled by the amplifier controller 114 in a synchronous manner. Based on the switching control signals provided to the control terminals of the switching elements, each of the switching elements 352, 353 can be“turned off’ or“open” (e.g., placed in a high-impedance state between the drain terminal and the source terminal), or“turned on” or“closed” (e.g., placed in a low-impedance state between the drain terminal and the source terminal).

[0194] More specifically, to place the Doherty power amplifier in the full-power state, the switching elements 352, 353 are simultaneously controlled to be in a closed (low-impedance) state. In this full-power state, both the harmonic frequency resonant circuits 359, 359’ and the fundamental frequency tuning circuits 356, 356’ are electrically connected to the reconfigurable impedance inversion circuit 340, 340’, 340” at the point between the third transmission line section 347 and the fourth transmission line section 348. Moreover, the reconfigurable quasi- line of the reconfigurable impedance inversion circuit 340, 340’, 340” comprises the transmission line sections 342, 347, 348, and 346, with the inductive element 344 (or the transmission line section 344’) coupled in parallel with the transmission line sections 347 and 348. Conversely, to place the Doherty power amplifier in the reduced-power state, the switching elements 352, 353 are simultaneously controlled to be in an open (high-impedance) state. In this reduced-power state, both the harmonic frequency resonant circuits 359, 359’ and the fundamental frequency tuning circuits 356, 356’ are electrically disconnected from the reconfigurable impedance inversion circuit 340, 340’, 340”. Moreover, the reconfigurable quasi-line of the reconfigurable impedance inversion circuit 340, 340’, 340” comprises only the transmission line section 342, the inductive element 344 (or the transmission line section 344’), and the transmission line section 346. In other words, in the reduced-power state, the inductive element 344 is activated to remove the load from the part of the quasi-line corresponding to the transmission line sections 347, 348.

[0195] According to embodiments, a reconfigurable output impedance transformer 382 is coupled between the combining node 380 and the RF output 110. During operation of the amplifier 300, the reconfigurable output impedance transformer 382 is configured to transform the impedance at the RF output 110 to an impedance at the combining node 380. Thus, the impedance at the combining node 380 is set up by the reconfigurable output impedance transformer 382. In particular, the impedance at the combining node 380 depends on the need to have a first efficiency peak (e.g., 50% efficiency) at a first frequency (e.g., 2.1 GHz) and a second efficiency peak (e.g., 60% efficiency) at a second frequency (e.g., 2.7 GHz). Figure 2the power level of the combination node 380 (e.g., the point 212, 222). During operation, the control can reconfigure the output impedance transformer 382 to set up the correct combination node impedance for the desired power level under reduced power conditions.

[0196] According to one or more embodiments, the reconfigurable output impedance transformer 382 includes a phase shift element 383 (e.g., a transmission line section or an inductor) having a first end coupled to the combination node 380 and a second end coupled to the RF output 110. The phase shift element 383 is characterized by a characteristic impedance Zl and an electrical length (or phase shift) at the center operating frequency f0 of the amplifier 300. For example, the impedance Zl can be in the range of about 20 to about 100, and the electrical length can be in the range of about 15 to about 90 degrees, although the electrical length can also be shorter or longer.

[0197] In addition to the phase shift element 383, the reconfigurable output impedance transformer 382 includes a shunt capacitor 384 coupled between the first end of the phase shift element 383 and the ground reference node, and a reconfigurable LC circuit 389 coupled between the second end of the phase shift element 383 and the ground reference node. According to one or more embodiments, the reconfigurable LC circuit 389 includes a capacitor 385 and an inductive element 386 coupled in series between the second end of the phase shift element 383 and the ground reference node. In addition, the reconfigurable LC circuit 389 includes a bypass switch element 387 having a first end coupled to a node (not numbered) between the capacitor 385 and the inductive element 386, and a second end coupled to the ground reference node.

[0198] In the full power state, when the switch element 387 is open, the reconfigurable output impedance transformer 382 essentially includes the shunt capacitor 384, the transmission line section 383, and the series coupled shunt capacitor 385 and inductive element 386. This configuration sets up a first characteristic impedance for the reconfigurable output impedance transformer 382. Conversely, in the reduced power state, when the switch element 387 is closed, the inductive element 386 is bypassed by the switch element 387, as shown in Figure 3 Figure 4 In the full power state, when the switch element 387 is open, the reconfigurable output impedance transformer 382 essentially includes the shunt capacitor 384, the transmission line section 383, and the series coupled shunt capacitor 385 and inductive element 386. This configuration sets up a first characteristic impedance for the reconfigurable output impedance transformer 382. Conversely, in the reduced power state, when the switch element 387 is closed, the inductive element 386 is bypassed by the switch element 387, as shown in

[0199] ​The capacitance and inductance values ​​selected for capacitors 384 and 385 and inductor 386 may be based on the operating fundamental frequency f0 of amplifier 300. According to one or more embodiments, each of capacitors 384 and 385 has a capacitance value in the range of about 0.5 pF to about 1.0 pF, and inductor 386 has an inductance value in the range of about 0.25 nH to about 6.0 nH, but the capacitance and / or inductance values ​​may also be lower or higher.

[0200] According to one or more embodiments, the reconfigurable output impedance transformer 382 is controlled to establish a desired impedance Z0 at the combination node 380 corresponding to an amplifier state (e.g., full power state or reduced power state). For example, the reconfigurable output impedance transformer 382 can be controlled to establish a relatively low combination node impedance Z0 (e.g., 10-15 ohms) when the reconfigurable Dougherty power amplifier 300 is in full power state, and can be controlled to establish a relatively high combination node impedance Z0 (e.g., 20-30 ohms) when the reconfigurable Dougherty power amplifier 300 is in reduced power state. According to an embodiment, the reconfigurable output impedance transformer 382 is controlled to double the combination node impedance Z0 in the reduced power state.

[0201] According to one or more embodiments, the reconfigurable carrier output capacitor circuit 334 and peaking output capacitor circuit 374, as well as the reconfigurable output impedance transformer 382, ​​can be reconfigured synchronously with the reconfiguration of the reconfigurable output impedance transformer circuits 340, 340', 340" (e.g., via a switching control signal provided on the switching control line 116). More specifically, in order to place the Dougherty power amplifier in full power mode ( Figure 3 Switching elements 338, 378, and 387 are simultaneously controlled to be in an off (high impedance) state. In this full-power state, inductors 336 and 337 are used to resonate some of the drain-source capacitances 333, and inductors 376 and 377 are used to resonate some of the drain-source capacitances 373. Additionally, inductor 386 affects the characteristic impedance of the reconfigurable output impedance converter circuit 382. Conversely, to put the Dougherty power amplifier into a reduced-power state (… Figure 4 Switching elements 338, 378, and 387 are simultaneously controlled to a closed (low impedance) state. In this reduced power state, only inductor 336 is used to resonate some of the drain-source capacitors 333 (inductor 337 is bypassed), and inductor 376 is used to resonate some of the drain-source capacitors 373 (inductor 377 is bypassed). Additionally, inductor 386 is bypassed, and therefore inductor 386 does not affect the characteristic impedance of the reconfigurable output impedance converter circuit 382.

[0202] As indicated above, at any given time, the Doherty power amplifier 300 can be configured or reconfigured into a full power state or a reduced power state. As previously discussed in connection with Figure 1 and 2 The instantaneous configuration of the Doherty power amplifier 300 can be controlled by the amplifier controller 114 based on the control signal 104 from the base station controller 103 Figure 1 ).

[0203] According to an embodiment, the amplifier controller 114 includes a memory (not shown) configured to store a look-up table that relates the control signal 104 from the base station controller 103 to the switching states of the plurality of switching elements 338, 353, 353, 378, 387 within the Doherty power amplifier 300.

[0204] For purposes of illustration, below is a first example of a look-up table (Table 1) that can be used in connection with the reconfigurable Doherty power amplifier 300. The look-up table below includes entries for two amplifier states (i.e., N = 2, corresponding to a full power state and a single reduced power state).

[0205]

[0206] Table 1 - Switching states for amplifier 300

[0207] As indicated by Table 1, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300 should be configured (or reconfigured) into a full power state Figure 3 , state 1), the amplifier controller 114 will provide the following switching control signals via the switching control lines 116:

[0208] • causes the switching elements 338, 378, 387 to be in an open state (i.e., all inductive elements 336+337, 376+377 contribute to the effective output capacitance of the amplifiers 331, 371, and the circuit 389 sets up a relatively low impedance at the combined node 380); and

[0209] • causes the switching elements 352, 353 to be in a closed state (i.e., the circuits 356, 356' and 359, 359' are coupled to the reconfigurable quasi- line).

[0210] Alternatively, when the amplifier controller 114 receives a control signal 104 from the base station controller 103 indicating that the amplifier 300 should be configured (or reconfigured) into a reduced power state Figure 4 , state 2), the amplifier controller 114 will provide the following switching control signals via the switching control lines 116:

[0211] • placing the switching elements 338, 378, 387 in a closed state (i.e., only the inductive elements 336, 376 contribute to the effective output capacitance of the amplifiers 331, 371, and the circuit 389 sets up a relatively high impedance at the combining node 380); and

[0212] • placing the switching elements 352, 353 in an open state (i.e., the circuits 356, 356' and 359, 359' are decoupled from the reconfigurable quiescent line).

[0213] For the Doherty power amplifier 300, the above configuration provides the correct phase relationship for optimal load modulation and ensures that the amplified signals from the carrier path 330 and the peaking path 370 arrive in phase (or coherently) at the combining node 380. The combining node 380 includes a conductive structure adapted to combine the amplified RF signals produced by the carrier amplification path 330 and the peaking amplification path 370 in order to produce an amplified combined output RF signal.

[0214] According to one or more embodiments, the efficient control of the reconfigurable Doherty power amplifier 300 from the full-power state to a reduced-power state that is about 3 dB below the full-power state includes simultaneously:

[0215] • reconfiguring the variable output impedance transformer 382 to increase (e.g., double) the combining node impedance;

[0216] • reconfiguring the carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 to decrease (e.g., halve) the effective capacitance C EFF at the outputs 332, 372 of the power amplifiers 331, 371; and

[0217] • reconfiguring the reconfigurable impedance inverter circuit 340 to increase (e.g., double) the total inductance L TOT of the reconfigurable impedance inverter circuit 340.

[0218] Conversely, the efficient control of the reconfigurable Doherty power amplifier 300 from the reduced-power state to a full-power state that is about 3 dB above the reduced-power state includes simultaneously:

[0219] • reconfiguring the variable output impedance transformer 382 to decrease (e.g., halve) the combining node impedance;

[0220] • reconfiguring the carrier output capacitance circuit 334 and the peaking output capacitance circuit 374 to increase (e.g., double) the effective capacitance C EFF at the outputs 332, 372 of the power amplifiers 331, 371; and

[0221] • reconfiguring the reconfigurable impedance inverter circuit 340 to reduce (e.g., halve) the total inductance L of the reconfigurable impedance inverter circuit 340 TOT .

[0222] Interestingly, for the Doherty power amplifier 300, the values of C EFF and L TOT are controlled in the opposite manner (i.e., when C EFF is reduced, L TOT is increased, and vice versa).

[0223] Figure 7 is a flowchart of a method of operating a reconfigurable Doherty power amplifier (e.g., the amplifier 300 of Figure 3 , 4 According to one or more embodiments, the method includes two parallel processes, including a process performed by a Doherty power amplifier (e.g., the amplifier 112, 300 of Figure 1 , 3 , 4 and a process performed by a base station controller and an amplifier controller (e.g., the controllers 103, 114 of Figure 1 , 3 , 4. These parallel processes can be performed concurrently (e.g., continuously amplifying an RF signal while performing reconfiguration of a variable network). Alternatively, reconfiguration of the variable network can be performed when amplification of the RF signal is not occurring (e.g., prior to amplification or during a pause in amplification).

[0224] The process performed by a Doherty power amplifier (e.g., the amplifier 112, 300 of Figure 1 , 3 , 4 will be outlined first. According to one or more embodiments, the method begins at block 702, which includes receiving an input RF signal (e.g., at the RF input 108 and the power divider input 322). The input RF signal can be characterized, for example, by an operating frequency fo. In block 704, the input RF signal is divided (e.g., by the power divider 320) into a carrier input RF signal and a peaking input RF signal. The carrier input RF signal is provided (e.g., by the divider output 324) to an input of a carrier amplifier (e.g., the amplifier 331), and the peaking RF signal is provided (e.g., by the divider output 326) to an input of a peaking amplifier 371. One or more phase delays can be applied such that the carrier and peaking input RF signals are approximately 90 degrees out of phase with respect to each other at the carrier and peaking amplifier inputs. In block 706, the carrier input RF signal is amplified by the carrier amplifier (e.g., the amplifier 331), and the peaking input RF signal is amplified by the peaking amplifier (e.g., the amplifier 371).

[0225] According to one or more embodiments, in block 708, the amplified carrier RF signal passes through a reconfigurable impedance inverter circuit (e.g., via...). Figures 3-6 The circuits 340, 340', 340") are transmitted to the combination node (e.g., combination node 380). Simultaneously, an amplified peaked RF signal is transmitted to the combination node (e.g., combination node 380), and the amplified carrier and peaked RF signal are combined at combination node 380. Finally, in block 710, and according to one or more embodiments, the amplified combined RF output signal is transmitted from the combination node to the RF output (e.g., RF output 110) via a reconfigurable output impedance transformer (e.g., reconfigurable output impedance transformer 382).

[0226] Simultaneously with the amplification process performed by the Dougherty power amplifier, various traffic load assessments and amplifier control processes are performed to reconfigure the Dougherty power amplifier to a full-power state or a reduced-power state. According to one or more embodiments, an initial amplifier configuration is established in block 718 before reconfiguring the Dougherty power amplifier. In some embodiments, the initial amplifier configuration may be predetermined to correspond to any amplifier state (e.g., corresponding to a full-power state or a reduced-power state). Establishing the initial amplifier configuration may involve: the base station controller sending an amplifier state control signal to the Dougherty power amplifier (or more specifically, to the amplifier controller, e.g., ...). Figure 1 , 3 The controller 114 of the 4th amplifier, and in response, the Dougherty power amplifier determines and provides a switching control signal corresponding to the initial amplifier state for use in the reconfigurable output circuit (e.g., Figure 3 , 4 According to one or more embodiments, in order to provide a switching control signal, an amplifier controller (e.g., controller 114) may include a plurality of drivers (not shown), wherein each driver is coupled to a switching element (e.g., via a switch control line 116). Figures 3-6 One or more control terminals of switching elements 338, 352, 353, 378, 387.

[0227] After setting the initial amplifier state, the measurement and control process includes block 720 in which the base station controller (or another subsystem) determines the current traffic load condition of the communication system. As previously discussed, the traffic load can be determined based on a measurement or determination of the instantaneous traffic load of the system compared to one or more thresholds. Alternatively, the traffic load can be estimated based on temporal factors (e.g., time of day, day of week, etc.). Either way, the base station controller can determine a desired amplifier state (e.g., full power or reduced power) based on the measured or expected current traffic load. After determining the desired amplifier state, the base station controller generates an amplifier state control signal and sends the amplifier state control signal to the Doherty power amplifier (or more specifically, to the amplifier controller, e.g., controller 114). The amplifier state control signal can indicate at least one of a traffic load condition, a power level (e.g., full power, reduced power), or an amplifier state (e.g., state 1, state 2).

[0228] According to one or more embodiments, in block 722, the amplifier controller (e.g., amplifier controller 114) receives the amplifier state control signal from the base station controller. In block 724, the amplifier controller then determines a control signal for the reconfigurable output circuit (e.g., circuit 390) of the Doherty power amplifier that corresponds to the desired amplifier state. As previously discussed, each reconfigurable output circuit can include a combining node (e.g., combining node 380), a reconfigurable impedance inverter circuit (e.g., circuit 340, 340', 340"), a reconfigurable carrier output capacitance circuit (e.g., circuit 334), a reconfigurable peaking output capacitance circuit (e.g., circuit 374), and a reconfigurable output impedance transformer (e.g., circuit 370) coupled between the combining node and the amplifier output (e.g., RF output 110). Figure 3 , 4 Figure 3 , 4 Figures 3-6 , Figure 3 , 4 Figure 3 , 4 Figure 3 , 4 Figure 3 Figure 3 , 4 ​​​​​The control signals generated by the amplifier controller can include control signals that cause the reconfigurable circuitry (e.g., circuitry 334, 340, 340', 340", 374, 382) to be reconfigured so as to implement the desired amplifier state. For example, the control signals can include switch control signals (e.g., for changing the state of the switching elements 338, 352, 353, 378, 387). The amplifier controller can determine the particular control signals, for example, using one or more lookup tables that relate values of the control signals to switch states (for the switching elements 338, 352, 353, 378, 387). Alternatively, other suitable control circuitry can be utilized. Once the control signals are determined, in block 726, the amplifier controller provides the control signals to the reconfigurable circuitry (e.g., circuitry 334, 340, 340', 340", 374, 382). According to one or more embodiments, the reconfigurable circuitry is reconfigured in a synchronized manner with one another to set up each amplifier state. The amplification and network control processes are continuously repeated throughout the operation of the Doherty power amplifier.

[0229] An embodiment of a Doherty power amplifier includes a first amplifier having a first amplifier output, a second amplifier having a second amplifier output, a combining node, and a reconfigurable impedance inverter circuit coupled between the first amplifier output and the combining node. The first amplifier is configured to produce an amplified first output signal and the second amplifier is configured to produce an amplified second output signal. The combining node is configured to combine the amplified first output signal and the amplified second output signal. The reconfigurable impedance inverter circuit includes a first node coupled to the first amplifier output, a second node coupled to the second amplifier output, a first inductive element having a first end coupled to the first node and a second end coupled to the second node, and a switching circuit having a first switching circuit end coupled to the first node and a second switching circuit end coupled to the second node. The switching circuit is configured to be controlled to a first state and a second state. The reconfigurable impedance inverter circuit further includes a fundamental frequency tuning circuit coupled between the switching circuit and a ground reference node, and a harmonic frequency resonant circuit coupled between the switching circuit and the ground reference node. The fundamental frequency tuning circuit is configured to resonate at or near an operating fundamental frequency, and the harmonic frequency resonant circuit is configured to resonate at or near a second harmonic frequency of the operating fundamental frequency. When the switching circuit is configured to be in the first state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first and second nodes through the switching circuit, and when the switching circuit is configured to be in the second state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically disconnected from the first and second nodes.

[0230] According to another embodiment, the reconfigurable impedance inverter circuit further includes a first transmission line segment coupled between the first amplifier output and the first node, a second transmission line segment coupled between the second amplifier output and the second node, a third transmission line segment coupled between the first node and a first terminal of the switching circuit, and a fourth transmission line segment coupled between the second node and a second terminal of the switching circuit. The first transmission line segment is characterized by a first electrical length and a first characteristic impedance. The second transmission line segment is characterized by a second electrical length and a second characteristic impedance. The third transmission line segment is characterized by a third electrical length and a third characteristic impedance. The fourth transmission line segment is characterized by a fourth electrical length and a fourth characteristic impedance.

[0231] According to yet another embodiment, the Doherty power amplifier further includes an amplifier controller coupled to the switching circuit. The amplifier controller is configured to receive a signal indicative of a full power state and, in response, provide a first control signal to the switching circuit to set the switching circuit to the first state. In addition, the amplifier controller is configured to receive a signal indicative of a reduced power state and, in response, provide a second control signal to the switching circuit to set the switching circuit to the second state.

[0232] According to yet another embodiment, the first amplifier output is characterized by a first amplifier output capacitance, the second amplifier output is characterized by a second amplifier output capacitance, and the combined node is characterized by a combined node impedance. In addition, the Doherty power amplifier further includes a reconfigurable carrier output capacitance circuit coupled to the first amplifier output, a reconfigurable peaking output capacitance circuit coupled to the second amplifier output and the combined node, and an output impedance transformer coupled between the combined node and an output of the Doherty power amplifier. The reconfigurable carrier output capacitance circuit and the first amplifier output capacitance set a first amplifier effective output capacitance that is less than the first amplifier output capacitance. The reconfigurable peaking output capacitance circuit and the second amplifier output capacitance set a second amplifier effective output capacitance that is less than the second amplifier output capacitance. The output impedance transformer is configured to set the combined node impedance.

[0233] An embodiment of a method of operating a Doherty power amplifier includes generating, by a first amplifier, an amplified first output signal at a first amplifier output, generating, by a second amplifier, an amplified second output signal at a second amplifier output, and transferring the amplified first output signal to a combining node through a reconfigurable impedance inverter circuit coupled between the first amplifier output and the combining node. The reconfigurable impedance inverter circuit includes a first node coupled to the first amplifier output, a second node coupled to the second amplifier output, a first inductive element having a first end coupled to the first node and a second end coupled to the second node, and a switching circuit having a first switching circuit end coupled to the first node and a second switching circuit end coupled to the second node. The switching circuit is configured to be controlled to a first state and a second state. The reconfigurable impedance inverter circuit further includes a fundamental frequency tuning circuit coupled between the switching circuit and a ground reference node, and a harmonic frequency resonant circuit coupled between the switching circuit and the ground reference node. The fundamental frequency tuning circuit is configured to resonate at or near an operating fundamental frequency. The harmonic frequency resonant circuit is configured to resonate at or near a second harmonic frequency of the operating fundamental frequency. The fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first and second nodes through the switching circuit when the switching circuit is configured to be in the first state, and the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically disconnected from the first and second nodes when the switching circuit is configured to be in the second state. The method additionally includes transferring the amplified second output signal to the combining node, combining the first and second amplified output signals at the combining node to produce an amplified combined output signal, and transferring the amplified combined output signal through an output impedance transformer coupled between the combining node and an output of the Doherty power amplifier.

[0234] According to another embodiment, the method further includes configuring the switching circuit to be in the first state, wherein the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first and second nodes through the switching circuit.

[0235] According to yet another embodiment, the method further includes configuring the switching circuit to be in the second state, wherein the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically disconnected from the first and second nodes.

[0236] The connecting lines shown in the various figures contained herein are intended to represent example functional relationships and / or physical couplings between the various elements. It should be noted that many alternatives or additional functional relationships or physical connections can be present in a

[0237] As used herein, a "node" means any internal or external reference point, connection point, junction point, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current, or quantity exists. Moreover, two or more nodes can be implemented by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even if received or output at a common node).

[0238] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated to the contrary, "connected" means that one element is directly connected to another element (or directly communicates with another element) and not necessarily mechanically. Likewise, unless expressly stated to the contrary, "coupled" means that one element is either directly or indirectly connected to (or directly or indirectly communicates with) another element, either electrically or otherwise, and not necessarily mechanically. Therefore, although the schematic diagrams illustrated in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components can be present in an embodiment of the depicted subject matter.

[0239] As used herein the word "exemplary" or "illustrative" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary or illustrative is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the foregoing description of various aspects of the subject matter discloses the best mode contemplated at present but is further offered for informational use only as modifications can suggest themselves to those skilled in the art.

[0240] While at least one exemplary embodiment has been presented in the foregoing detailed description of the specific embodiments, it should be appreciated that a vast number of modifications can be made to the exemplary embodiments without departing from the scope disclosed herein. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the claimed subject matter, which is defined by the appended claims and their equivalents.

Claims

1. A Dougherty power amplifier, characterized in that, include: A first amplifier having a first amplifier output, wherein the first amplifier is configured to generate an amplified first output signal; A second amplifier having a second amplifier output, wherein the second amplifier is configured to generate an amplified second output signal; A combination node configured to combine the amplified first output signal with the amplified second output signal; A reconfigurable impedance inverter circuit coupled between the first amplifier output and the combined node, wherein the reconfigurable impedance inverter circuit includes The first node is coupled to the output of the first amplifier. The second node is coupled to the output of the second amplifier. A first inductor element having a first end coupled to the first node and a second end coupled to the second node. A switching circuit having a first switching circuit terminal coupled to the first node and a second switching circuit terminal coupled to the second node, wherein the switching circuit is configured to be controlled to a first state and a second state. A fundamental frequency tuning circuit, coupled between the switching circuit and the ground reference node, wherein the fundamental frequency tuning circuit is configured to resonate at or near the operating fundamental frequency. A harmonic frequency resonant circuit, coupled between the switching circuit and the ground reference node, wherein the harmonic frequency resonant circuit is configured to resonate at or near the second harmonic frequency of the operating fundamental frequency, and When the switching circuit is configured to be in the first state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first node and the second node through the switching circuit, and when the switching circuit is configured to be in the second state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are disconnected from the first node and the second node.

2. The Dougherty power amplifier according to claim 1, characterized in that, The reconfigurable impedance inverter circuit further includes: A first transmission line segment coupled between the first amplifier output and the first node, wherein the first transmission line segment is characterized by a first electrical length and a first characteristic impedance. A second transmission line segment is coupled between the output of the second amplifier and the second node, wherein the second transmission line segment is characterized by a second electrical length and a second characteristic impedance. A third transmission line segment, coupled between the first node and the first terminal of the switching circuit, wherein the third transmission line segment is characterized by a third electrical length and a third characteristic impedance; and A fourth transmission line segment coupled between the second node and the second terminal of the switching circuit, wherein the fourth transmission line segment is characterized by a fourth electrical length and a fourth characteristic impedance.

3. The Dougherty power amplifier according to claim 1, characterized in that: The fundamental frequency tuning circuit includes a second inductor and a first capacitor connected in series between the switching circuit and the ground reference node; and The harmonic frequency resonant circuit includes a third inductor and a second capacitor connected in series between the switching circuit and the ground reference node.

4. The Dougherty power amplifier according to claim 1, characterized in that, In addition, including: A first DC blocking capacitor is coupled between the output of the first amplifier and the first node; as well as A second DC blocking capacitor is coupled between the output of the second amplifier and the second node.

5. The Dougherty power amplifier according to claim 1, characterized in that, In addition, including: The amplifier controller is coupled to the switching circuit, wherein The amplifier controller is configured to receive a signal indicating a full-power state, and in response, to provide a first control signal to the switching circuit to set the switching circuit to the first state. The amplifier controller is configured to receive a signal indicating a reduced power state, and in response, to provide a second control signal to the switching circuit to set the switching circuit to the second state.

6. The Dougherty power amplifier according to claim 5, characterized in that, The switching circuit includes: A first switching element, coupled between the first switching circuit terminal and the intermediate node; and A second switching element is coupled between the intermediate node and the second switching circuit terminal, and The fundamental frequency tuning circuit and the harmonic frequency resonant circuit are both coupled between the intermediate node and the ground reference node. When the switching circuit is configured to be in the first state, the first switching element and the second switching element are configured to be in a closed state, and When the switching circuit is configured to be in the second state, the first switching element and the second switching element are configured to be in the off state.

7. The Dougherty power amplifier according to claim 5, characterized in that, The switching circuit includes: A first switching element, coupled between the first switching circuit terminal and the intermediate node; and A second switching element is coupled between the intermediate node and the second switching circuit terminal, and The fundamental frequency tuning circuit is coupled between the intermediate node and the ground reference node. The harmonic frequency resonant circuit is coupled between the second switching circuit terminal and the ground reference node. When the switching circuit is configured to be in the first state, the first switching element and the second switching element are configured to be in a closed state, and When the switching circuit is configured to be in the second state, the first switching element and the second switching element are configured to be in the off state.

8. The Dougherty power amplifier according to claim 1, characterized in that: The characteristic of the first amplifier output lies in the first amplifier output capacitance; The characteristic of the output of the second amplifier lies in the output capacitance of the second amplifier; The combined node is characterized by its combined node impedance. and The Dougherty power amplifier mentioned above further includes A reconfigurable carrier output capacitor circuit is coupled to the output of the first amplifier, wherein the reconfigurable carrier output capacitor circuit and the first amplifier output capacitor are configured to form a first amplifier effective output capacitor smaller than the first amplifier output capacitor. A reconfigurable peaking output capacitor circuit, coupled to the second amplifier output and the combined node, wherein the reconfigurable peaking output capacitor circuit and the second amplifier output capacitor establish a second amplifier effective output capacitance smaller than the second amplifier output capacitance, and An output impedance transformer coupled between the combined node and the output of the Dougherty power amplifier, wherein the output impedance transformer is configured to establish the impedance of the combined node.

9. The Dougherty power amplifier according to claim 8, characterized in that: The reconfigurable carrier output capacitor circuit includes a first bypass switch having a first terminal and a second terminal, a first capacitor and a second inductor coupled in series between the first amplifier output and the first terminal of the first bypass switch, and a third inductor coupled between the first terminal of the first bypass switch and the ground reference node, wherein the second terminal of the first bypass switch is coupled to the ground reference node. The reconfigurable peaked output capacitor circuit includes a second bypass switch having a first terminal and a second terminal, a second capacitor and a fourth inductor coupled in series between the second amplifier output and the first terminal of the second bypass switch, and a fifth inductor coupled between the first terminal of the second bypass switch and the ground reference node, wherein the second terminal of the second bypass switch is coupled to the ground reference node; and The output impedance transformer includes a transmission line segment having a first end coupled to the combined node and a second end coupled to the output of the Dougherty power amplifier, a third capacitor coupled between the first end and the ground reference node, and a reconfigurable inductor-capacitor circuit coupled between the second end and the ground reference node. The reconfigurable inductor-capacitor circuit includes a third bypass switch having a first end and a second end, a fourth capacitor coupled between the second end and the first end of the third bypass switch, and a sixth inductor coupled between the first end of the third bypass switch and the ground reference node, wherein the second end of the third bypass switch is coupled to the ground reference node. When the switching circuit is configured to be in the first state, the first, second, and third bypass switches are configured to be in the open state, and When the switching circuit is configured to be in the second state, the first, second and third bypass switches are configured to be in the closed state.

10. A method for operating a Dougherty power amplifier, characterized in that, include: The first amplifier generates an amplified first output signal at the output of the first amplifier; The amplified second output signal is generated at the output of the second amplifier by the second amplifier; The amplified first output signal is transmitted to the combination node via a reconfigurable impedance inverter circuit coupled between the first amplifier output and the combination node, wherein the reconfigurable impedance inverter circuit includes... The first node is coupled to the output of the first amplifier. The second node is coupled to the output of the second amplifier. A first inductor element having a first end coupled to the first node and a second end coupled to the second node. A switching circuit having a first switching circuit terminal coupled to the first node and a second switching circuit terminal coupled to the second node, wherein the switching circuit is configured to be controlled to a first state and a second state. A fundamental frequency tuning circuit, coupled between the switching circuit and the ground reference node, wherein the fundamental frequency tuning circuit is configured to resonate at or near the operating fundamental frequency. A harmonic frequency resonant circuit, coupled between the switching circuit and the ground reference node, wherein the harmonic frequency resonant circuit is configured to resonate at or near the second harmonic frequency of the operating fundamental frequency, and When the switching circuit is configured to be in the first state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are electrically coupled to the first node and the second node through the switching circuit, and when the switching circuit is configured to be in the second state, the fundamental frequency tuning circuit and the harmonic frequency resonant circuit are disconnected from the first node and the second node. The amplified second output signal is transmitted to the combined node; The amplified first and second output signals are combined at the combination node to produce an amplified combined output signal; and The amplified combined output signal is transmitted via an output impedance transformer coupled between the combined node and the output of the Dougherty power amplifier.

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