Silicon carbide super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with floating column region

Abstract

The invention discloses a silicon carbide super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a floating column region in the technical field of semiconductor power devices, which comprises an N-type substrate, an N-type epitaxial layer is formed above the N-type substrate, a floating P column region is formed in the center of the N-type epitaxial layer, a gate trench is formed above the floating P column region, an N + source region and a P-body region are respectively formed on two sides of the gate trench, and a P-body region is formed in the N + source region. A P + contact region is formed on the side face of the N + source region, the P + contact region and the N + source region are in short circuit through a source electrode, and a drain electrode is arranged below the N-type substrate. By arranging the floating P column region, the highly nonlinear capacitance characteristic of the device is improved, voltage overshoot and oscillation are suppressed, and the anti-electromagnetic interference capability of the device is improved; the FOM (figure of merit) of the device is improved by designing an alternating variable doping column region and widening a floating P column region structure, and the single event burnout resistance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, specifically a silicon carbide superjunction MOSFET device with a floating pillar region. Background Technology

[0002] Power semiconductor devices, as core components of power conversion systems, directly determine energy conversion efficiency, system size, and cost. In recent years, third-generation wide-bandgap semiconductors, represented by silicon carbide (SiC), have gradually become a research hotspot in power devices due to their superior material properties. Compared to traditional silicon (Si) materials, silicon carbide possesses a higher critical breakdown electric field, a wider bandgap, and higher thermal conductivity. These characteristics enable silicon carbide devices to operate at higher voltages, higher frequencies, and higher temperatures while achieving lower power losses. However, with the increasing demands for power density and efficiency in power electronic systems, the inherent contradiction between the on-resistance (Rds(on)) and blocking voltage (BV) of traditional silicon carbide devices means their performance can no longer meet current application requirements. Especially in medium- and high-voltage applications such as traction inverters for new energy vehicles, photovoltaics, energy storage, smart grids, and rail transit, how to further reduce device conduction losses while maintaining a high blocking voltage has become a key challenge for technological development.

[0003] To overcome this limitation, a superjunction structure can be introduced into traditional silicon carbide (SiC) devices. The alternating P-pillars and N-pillars in the drift region can completely deplete each other in the blocking state, forming an approximately rectangular electric field distribution, significantly improving the device's breakdown voltage. Simultaneously, in the conducting state, current can flow through the highly doped N-pillar region, reducing the device's on-resistance, thus breaking through the theoretical limits of SiC materials. However, the introduction of the superjunction structure also brings related reliability issues to SiC devices. On the one hand, during device switching, the depletion regions of the alternating pillar regions in the SiC superjunction structure rapidly overlap in the center of the N-pillars, causing a sudden change in the gate-drain capacitance. The resulting highly nonlinear capacitance can cause current-voltage overshoot and oscillation, mis-conduction, electromagnetic interference, and complex drive design. On the other hand, for trench SiC MOSFETs, the introduction of the superjunction structure introduces a transverse electric field within the device. This transverse electric field, combined with the longitudinal electric field, enhances the electric field at the trench corners and bottom, and a high electric field is also generated at the pillar interface. This is detrimental to improving the long-term reliability of the device, including gate oxide dielectric properties, short-circuit capability, and resistance to single-event burn-out. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon carbide superjunction MOSFET device with a floating P-pillar region. By setting the floating P-pillar region, the highly nonlinear capacitance characteristics of the superjunction device are improved, which can suppress voltage overshoot and oscillation, prevent the device from being falsely turned on, improve the device's immunity to electromagnetic interference, and simplify the design of the drive circuit. By designing an alternating doped pillar region and a widened floating P-pillar region structure, the figure of merit (FOM) between the device's breakdown voltage and on-resistance is improved, which can improve the device's resistance to single-event burn-out, reduce the device's saturation current, and thus enhance the device's short-circuit withstand capability and long-term reliability.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A silicon carbide superjunction MOSFET device with a floating pillar region includes an N-type substrate, an N-type epitaxial layer formed on top of the N-type substrate, a floating P-pillar region formed at the center of the N-type epitaxial layer, a gate trench oxide formed above the floating P-pillar region, a polysilicon gate disposed inside the gate trench oxide, P-body regions formed on both sides of the gate trench oxide, an N+ source region formed above each of the two P-body regions, a P+ contact region formed on the side of the N+ source region, the P+ contact region and the N+ source region being shorted by a source electrode, an oxide dielectric layer formed at the center of the source electrode, a drain electrode disposed below the N-type substrate, and the top pillar region of the floating P-pillar region being shorted to the source electrode through a selective P-type semi-enclosed structure.

[0006] As a further aspect of the present invention: the N-type epitaxial layer includes a first N-type epitaxial layer and a second N-type epitaxial layer. The first N-type epitaxial layer is formed above the N-type substrate, and the second N-type epitaxial layer is formed above the first N-type epitaxial layer. The first N-type epitaxial layer and the second N-type epitaxial layer are doped N-type epitaxial layers. The doping concentration of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer. The second N-type epitaxial layer is used to optimize the on-resistance of the top cell.

[0007] As a further aspect of the present invention: the floating P-pillar region is a floating highly doped P-pillar region, which is formed through multiple epitaxy and ion implantation processes.

[0008] As a further aspect of the present invention: the first N-type epitaxial layer includes N-type epitaxial layer-a, N-type epitaxial layer-b, N-type epitaxial layer-c, N-type epitaxial layer-d, N-type epitaxial layer-e, N-type epitaxial layer-f, N-type epitaxial layer-g, N-type epitaxial layer-h and N-type epitaxial layer-i, N-type epitaxial layer-a is formed above the N-type substrate, N-type epitaxial layer-b is formed above N-type epitaxial layer-a, N-type epitaxial layer-c is formed above N-type epitaxial layer-b, N-type epitaxial layer-d is formed above N-type epitaxial layer-c, N-type epitaxial layer-e is formed above N-type epitaxial layer-d, N-type epitaxial layer-f is formed above N-type epitaxial layer-e, N-type epitaxial layer-g is formed above N-type epitaxial layer-f, and a second N-type epitaxial layer is formed above N-type epitaxial layer-g.

[0009] As a further aspect of the present invention: the floating P-pillar region includes a first floating P-pillar region, a second floating P-pillar region, a third floating P-pillar region, and a fourth floating P-pillar region. The first floating P-pillar region is formed in the center of the N-type epitaxial layer-a, the second floating P-pillar region is formed in the center of the N-type epitaxial layer-c, the third floating P-pillar region is formed in the center of the N-type epitaxial layer-e, and the fourth floating P-pillar region is formed in the center of the N-type epitaxial layer-g. The gate trench oxide and the P-type semi-enclosed structure are located above the fourth floating P-pillar region.

[0010] As a further aspect of the present invention, the doping concentrations of the N-type epitaxial layers-a,-b,-c,-d,-e,-f,-g,-h, and-i decrease sequentially.

[0011] As a further aspect of the present invention, the doping concentrations of the first floating P-pillar region, the second floating P-pillar region, the third floating P-pillar region, and the fourth floating P-pillar region increase sequentially.

[0012] As a further aspect of the present invention: the top two ends of the floating P-pillar area are symmetrically widened to form a top widened area.

[0013] As a further aspect of the present invention: the central part of the floating P-pillar area is symmetrically widened at both ends to form a central widened area.

[0014] As a further aspect of the present invention: the P-type semi-enclosed structure is short-circuited with the source electrode to suppress the electric field strength at the bottom and corners of the trench.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention improves the highly nonlinear capacitance characteristics of superjunction devices by setting floating P-pillar regions, which can suppress voltage overshoot and oscillation, prevent device mis-conduction, improve the device's electromagnetic interference resistance, and simplify the design of the drive circuit. By designing alternating doped pillar regions and widening the floating P-pillar region structure, the figure of merit (FOM) between the device's breakdown voltage and on-resistance is improved, which can enhance the device's resistance to single-event burn-out, reduce the device's saturation current, and thus strengthen the device's short-circuit withstand capability.

[0016] 2. This invention optimizes the arrangement of P-pillars and N-pillars, placing the floating P-pillars below the trench and selectively shorting them to the source via a semi-enclosed structure. This effectively suppresses the electric field at the bottom of the trench, significantly reducing the on-resistance and gate-drain capacitance of the device while maintaining a high blocking voltage. This improves the device's switching speed and reliability, reduces switching losses, and facilitates the fabrication of high-quality silicon carbide superjunction MOSFETs. It also enhances the long-term reliability of the device's gate oxide dielectric, short-circuit capability, and resistance to single-particle burn-off, providing a feasible technical path for the commercial application of silicon carbide superjunction devices.

[0017] 3. This invention provides a floating pillar region silicon carbide trench superjunction MOSFET device. The floating superjunction pillar region of the device is formed by multiple epitaxial and ion implantation processes, which can simplify the number of epitaxial steps, reduce the difficulty and cost of device manufacturing process, and solve technical problems such as P-pillar alignment and surface stress in multiple epitaxial and ion implantation processes.

[0018] 4. This invention improves the device's resistance to single-particle burn-out and short-circuit withstand capability by setting alternating doped floating pillar regions and widening the floating pillar region structure. Furthermore, by adjusting the position of the widened floating pillar region, the figure of merit (FOM) between the device's breakdown voltage and on-resistance is improved, thereby enhancing the device's performance. As a result, the proposed silicon carbide superjunction device with floating pillar regions possesses both high performance and high reliability. Attached Figure Description

[0019] Figure 1A This is a schematic diagram of the cell structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 1 of the present invention; Figure 1B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 1 of the present invention. Figure 2A This is a schematic diagram of the cell structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 2 of the present invention; Figure 2B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 2 of the present invention. Figure 3AThis is a schematic diagram of the cell structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 3 of the present invention; Figure 3B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 3 of the present invention. Figure 4A This is a schematic diagram of the cell structure of a silicon carbide superjunction MOSFET device with a floating pillar region according to Embodiment 4 of the present invention; Figure 4B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure of a silicon carbide superjunction MOSFET device with a floating pillar region, according to Embodiment 4 of the present invention. Figure 5 This is a comparison diagram of the capacitance characteristics of traditional and floating pillar structures of silicon carbide trench superjunction MOSFETs.

[0020] In the figure: 101, N-type substrate; 102, first N-type epitaxial layer; 1021, N-type epitaxial layer-a; 1022, N-type epitaxial layer-b; 1023, N-type epitaxial layer-c; 1024, N-type epitaxial layer-d; 1025, N-type epitaxial layer-e; 1026, N-type epitaxial layer-f; 1027, N-type epitaxial layer-g; 1028, N-type epitaxial layer-h; 1029, N-type epitaxial layer-i; 103, floating P-pillar region; 1 031. First floating P-pillar region; 1032. Second floating P-pillar region; 1033. Third floating P-pillar region; 1034. Fourth floating P-pillar region; 104. Second N-type epitaxial layer; 105. P-body region; 106. N+ source region; 107. P+ contact region; 108. P-type semi-enclosed structure; 109. Gate trench oxide; 110. Polysilicon gate; 111. Oxide dielectric layer; 112. Source electrode; 113. Drain electrode. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] In this embodiment of the invention, a silicon carbide superjunction MOSFET device having a floating pillar region includes...

[0023] Example 1: Please see Figure 1A-Figure 1BA silicon carbide superjunction MOSFET device with a floating pillar region is provided, including an N-type substrate 101, an N-type epitaxial layer formed on the N-type substrate 101, a floating P-pillar region 103 formed at the center of the N-type epitaxial layer, a gate trench oxide 109 formed above the floating P-pillar region 103, a polysilicon gate 110 disposed inside the gate trench oxide 109, P-body regions 105 formed on both sides of the gate trench oxide 109, an N+ source region 106 formed above each of the two P-body regions 105, a P+ contact region 107 formed on the side of the N+ source region 106, the P+ contact region 107 and the N+ source region 106 shorted by a source electrode 112, an oxide dielectric layer 111 formed at the center of the source electrode 112, a drain electrode 113 disposed below the N-type substrate 101, and the top pillar region of the floating P-pillar region 103 shorted to the source electrode 112 by a selective P-type semi-enclosed structure 108.

[0024] Preferably, the N-type epitaxial layer includes a first N-type epitaxial layer 102 and a second N-type epitaxial layer 104. The first N-type epitaxial layer 102 is formed above the N-type substrate 101, and the second N-type epitaxial layer 104 is formed above the first N-type epitaxial layer 102. The first N-type epitaxial layer 102 and the second N-type epitaxial layer 104 are doped N-type epitaxial layers. The doping concentration of the second N-type epitaxial layer 104 is higher than that of the first N-type epitaxial layer 102. The second N-type epitaxial layer 104 is used to optimize the on-resistance of the top cell.

[0025] Preferably, the floating P-pillar region 103 is a floating highly doped P-pillar region, which is formed through multiple epitaxy and ion implantation processes.

[0026] In this embodiment, on the one hand, by setting a floating P-pillar region 103 in the superjunction structure, the drastic changes in the shape and effective area of ​​the depletion region of the alternating N-pillars and P-pillars during the voltage build-up process are avoided, suppressing or even eliminating the highly nonlinear capacitance region of the silicon carbide superjunction device. This effectively solves reliability problems such as device current and voltage overshoot and oscillation, device mis-conduction, and electromagnetic interference. On the other hand, by placing the floating P-pillar 103 in the superjunction structure below the trench and shorting the top pillar region of the floating P-pillar region 103 to the source electrode 112 through a selective P-type semi-enclosed structure 108, the electric field strength at the bottom of the device trench can be effectively suppressed. At the same time, this structure can reduce the cell size of the trench superjunction silicon carbide to an extremely small size, significantly reducing the device's on-resistance while maintaining a high blocking voltage. By shorting the top pillar region of the floating P-pillar region 103 to the source electrode 112, most of the device's gate-drain capacitance can be converted into drain-source capacitance, reducing the device's Miller capacitance, improving the device's switching speed, and reducing the device's switching losses. Secondly, the high-voltage silicon carbide superjunction structure formed through multiple epitaxial and ion implantation processes also faces the following technical challenges: First, the alignment of the P-pillar regions must be ensured during the two epitaxial ion implantations, therefore the thickness of each epitaxial layer cannot be too thick; second, subsequent epitaxy can cause stress on the surface of the P-pillar region formed by the previous epitaxial ion implantation. Therefore, forming deep superjunction pillar regions through multiple epitaxial and ion implantations is a challenge for silicon carbide high-voltage devices. However, using floating P-pillar regions can effectively solve these problems, simplifying the epitaxial steps and reducing the difficulty and cost of device manufacturing processes.

[0027] In this embodiment, the manufacturing process of a full superjunction structure for silicon carbide MOSFET high-voltage devices spanning the entire drift region is challenging and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing the device's on-resistance and increasing the risk of premature breakdown. Simultaneously, the deeper the device pillar region, the stronger the bottom electric field, leading to poorer short-circuit withstand capability. Therefore, a bottom auxiliary layer can be added above the first N-type substrate 101 to form a semi-superjunction structure, reducing manufacturing difficulty and cost while further improving device reliability. The high-performance, high-reliability silicon carbide MOSFET device with a floating P-pillar region proposed in this invention provides a feasible technical path for the commercial application of silicon carbide superjunction devices.

[0028] In Embodiment 1 of the present invention, the N-type substrate 101, the first N-type epitaxial layer 102, the second N-type epitaxial layer 104, the P-body region 105, the N+ source region 106, the source electrode 112, and the drain electrode 113 are used for conducting electricity.

[0029] Example 2: Silicon carbide superjunction MOSFETs generate a high electric field at the bulk pillar interface, which is detrimental to the device's resistance to single-event burn-out. When incident particles in outer space have extremely high energy, they will penetrate the entire silicon carbide superjunction device, generating a large number of electron-hole pairs along the incident path. The high electric field at the pillar interface will cause more holes to accelerate through the P-bulk region to the source, which can easily trigger the conduction of parasitic transistors. Excessive current causes the temperature of the sensitive area of ​​the device to rise, leading to burn-out. To solve the above problems, this embodiment provides a high-performance, high-reliability silicon carbide MOSFET device with alternating doped floating P-pillar regions, such as... Figure 2A-2BAs shown, the system includes an N-type substrate 101, an N-type epitaxial layer formed on top of the N-type substrate 101, a floating P-pillar region 103 formed at the center of the N-type epitaxial layer, a gate trench oxide 109 formed above the floating P-pillar region 103, a polysilicon gate 110 disposed inside the gate trench oxide 109, P-body regions 105 formed on both sides of the gate trench oxide 109, N+ source regions 106 formed above each of the two P-body regions 105, P+ contact regions 107 formed on the side of the N+ source regions 106, and the P+ contact regions 107 and N+ source regions 106 short-circuited by a source electrode 112. An oxide dielectric layer 111 is formed in the center. A drain electrode 113 is disposed below the N-type substrate 101. The top pillar region of the floating P-pillar region 103 is shorted to the source electrode 112 through a selective P-type semi-enclosed structure 108. The first N-type epitaxial layer 102 includes N-type epitaxial layers -a1021, -b1022, -c1023, -d1024, -e1025, -f1026, -g1027, -h1028, and -i1029. The N-type epitaxial layer -a1021 is formed on the N-type substrate 101. Above layer 01, N-type epitaxial layer -b1022 is formed above N-type epitaxial layer -a1021, N-type epitaxial layer -c1023 is formed above N-type epitaxial layer -b1022, N-type epitaxial layer -d1024 is formed above N-type epitaxial layer -c1023, N-type epitaxial layer -e1025 is formed above N-type epitaxial layer -d1024, N-type epitaxial layer -f1026 is formed above N-type epitaxial layer -e1025, N-type epitaxial layer -g1027 is formed above N-type epitaxial layer -f1026, and a second N-type epitaxial layer 104 is formed above N-type epitaxial layer -g1027. The empty P-pillar region 103 includes a first floating P-pillar region 1031, a second floating P-pillar region 1032, a third floating P-pillar region 1033, and a fourth floating P-pillar region 1034. The first floating P-pillar region 1031 is formed in the center of the N-type epitaxial layer -a1021, the second floating P-pillar region 1032 is formed in the center of the N-type epitaxial layer -c1023, the third floating P-pillar region 1033 is formed in the center of the N-type epitaxial layer -e1025, and the fourth floating P-pillar region 1034 is formed in the center of the N-type epitaxial layer -g1027. The gate trench oxide 109 and the P-type semi-enclosed structure 108 are located above the fourth floating P-pillar region 1034.

[0030] Preferably, the doping concentrations of the N-type epitaxial layers -a1021, -b1022, -c1023, -d1024, -e1025, -f1026, -g1027, -h1028, and -i1029 decrease sequentially.

[0031] Preferably, the doping concentrations of the first floating P-pillar region 1031, the second floating P-pillar region 1032, the third floating P-pillar region 1033, and the fourth floating P-pillar region 1034 increase sequentially.

[0032] In this embodiment, by setting an alternating doped pillar structure, with a highly doped floating P-pillar surrounded by a low-doped N-pillar and a low-doped floating P-pillar surrounded by a highly doped N-pillar, the charge balance of the superjunction structure is optimized, reducing the electric field strength at the pillar interface within the device, thereby improving the device's resistance to single-event burn-out. Simultaneously, the P-pillars located below the trench are highly doped, and a selective P-type semi-enclosed structure shorts the P-pillars to the source electrode, effectively suppressing the electric field strength at the bottom of the trench. The remaining P-pillars are completely floating. Therefore, this structure also possesses advantages such as high breakdown voltage, low on-resistance, low parasitic capacitance, low switching loss, and high reliability.

[0033] Manufacturing a full superjunction structure for silicon carbide MOSFET high-voltage devices, spanning the entire drift region, is challenging and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing on-resistance and increasing the risk of premature breakdown. Additionally, the deeper the pillar region, the stronger the bottom electric field, leading to poorer short-circuit withstand capability. Therefore, a bottom auxiliary layer can be added above the N-type substrate 101 to form a semi-superjunction structure, reducing manufacturing difficulty and cost while further improving device reliability. This embodiment presents a high-performance, high-reliability silicon carbide MOSFET device with alternating doped floating P-pillar regions, providing a feasible technical path for the commercial application of silicon carbide superjunction devices.

[0034] Example 3: While silicon carbide superjunction structures reduce device on-resistance, they also present new challenges to short-circuit reliability under high bus voltages. This challenge stems from the high electric field and large current within the device. In silicon carbide superjunction devices, the current is confined to a narrow N-pillar channel, resulting in extremely high current density. Furthermore, the electric field is highly concentrated at the bottom of the P-pillar. The simultaneous presence of extremely high current density and electric field strength creates a heat source within the device, causing the device temperature to rise until thermal runaway. The deeper the pillar region, the greater the electric field strength at the bottom, and the greater the risk of short-circuit failure. To address these issues, this invention provides a third silicon carbide superjunction device structure: a high-performance, high-reliability silicon carbide MOSFET device with a widened, floating P-pillar region at the top, such as... Figures 3A-3BAs shown, the structure includes an N-type substrate 101, an N-type epitaxial layer formed on top of the N-type substrate 101, a floating P-pillar region 103 formed in the center of the N-type epitaxial layer, the top two ends of the floating P-pillar region 103 being symmetrically widened, a gate trench oxide 109 formed above the floating P-pillar region 103, a polysilicon gate 110 disposed inside the gate trench oxide 109, P-body regions 105 formed on both sides of the gate trench oxide 109, an N+ source region 106 formed above each of the two P-body regions 105, a P+ contact region 107 formed on the side of the N+ source region 106, the P+ contact region 107 and the N+ source region 106 being shorted by a source electrode 112, an oxide dielectric layer 111 formed in the center of the source electrode 112, a drain electrode 113 disposed below the N-type substrate 101, and the top pillar region of the floating P-pillar region 103 being shorted to the source electrode 112 by a selective P-type semi-enclosed structure 108.

[0035] Compared to the previous embodiments, this embodiment widens the top P-pillar region and shorts it to the source electrode through a P-type semi-enclosed structure. Widening the P-pillar region has two effects: firstly, it better encloses the bottom and corners of the trench, further suppressing the electric field strength at the bottom and corners; secondly, after the device is turned on, the current is confined to a very narrow area by the widened P-pillar region, thereby reducing the device's saturation current and enhancing its short-circuit withstand capability. Simultaneously, the structure of Embodiment 3 also possesses the same advantages as the structure of Embodiment 1, namely, significantly reducing the device's on-resistance and Miller capacitance while maintaining a high blocking voltage, increasing the device's switching speed, reducing switching losses, suppressing or even eliminating the highly nonlinear capacitance region, effectively mitigating reliability issues such as current and voltage overshoot and oscillation, mis-conduction, and electromagnetic interference, simplifying epitaxy cycles, and reducing the difficulty and cost of device manufacturing processes.

[0036] Manufacturing a full superjunction structure for silicon carbide MOSFET high-voltage devices, spanning the entire drift region, is challenging and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing on-resistance and increasing the risk of premature breakdown. Additionally, the deeper the device pillar region, the stronger the bottom electric field, leading to poorer short-circuit withstand capability. Therefore, a bottom auxiliary layer can be added above the N-type substrate 101 to form a semi-superjunction structure, reducing manufacturing difficulty and cost while further improving device reliability. The high-performance, high-reliability silicon carbide MOSFET device with a widened floating P-pillar region proposed in this invention provides a feasible technical path for the commercial application of silicon carbide superjunction devices.

[0037] Example 4: In the third type of silicon carbide superjunction device described above, the widened P-pillar region is located at the top of the superjunction structure and is shorted to the source electrode through a P-type semi-enclosed structure. After the device is turned on, the current flows through the P-body, the widened P-pillar region, and the narrow region between the two widened P-pillar regions. Although this can minimize the device's saturation current and improve its short-circuit withstand capability, it also increases the device's on-resistance. To solve the above problems, this invention provides a fourth type of silicon carbide superjunction device structure: a high-performance, high-reliability silicon carbide MOSFET device with a centrally widened floating P-pillar region, such as... Figures 4A-4B As shown, the structure includes an N-type substrate 101, an N-type epitaxial layer formed on top of the N-type substrate 101, a floating P-pillar region 103 formed in the center of the N-type epitaxial layer, the central part of the floating P-pillar region 103 being symmetrically widened at both ends, a gate trench oxide 109 formed above the floating P-pillar region 103, a polysilicon gate 110 disposed inside the gate trench oxide 109, P-body regions 105 formed on both sides of the gate trench oxide 109, an N+ source region 106 formed above each of the two P-body regions 105, a P+ contact region 107 formed on the side of the N+ source region 106, the P+ contact region 107 and the N+ source region 106 being shorted by a source electrode 112, an oxide dielectric layer 111 formed in the center of the source electrode 112, a drain electrode 113 disposed below the N-type substrate 101, and the top pillar region of the floating P-pillar region 103 being shorted to the source electrode 112 by a selective P-type semi-enclosed structure 108.

[0038] Compared to the structure of Embodiment 3, the structure of Embodiment 4 proposed in this invention widens the central floating P-pillar region instead of the top P-pillar region. The top P-pillar region also uses a P-type semi-enclosed structure to short-circuit with the source electrode to suppress the electric field strength at the bottom and corners of the trench. However, by widening the central floating P-pillar region, the current exhibits an "8"-shaped distribution after the device is turned on. The current is confined to an extremely narrow region in the center of the superjunction, reducing the device's saturation current, enhancing its short-circuit withstand capability, and eliminating the narrow region through which current flows through the P-body and the widened P-pillar region. This improves the figure of merit (FOM) of the device's breakdown voltage and on-resistance. Simultaneously, the structure of Embodiment 4 also has the following advantages: reduced Miller capacitance, increased switching speed, reduced switching losses, suppression or even elimination of highly nonlinear capacitance regions, effective mitigation of reliability issues such as current and voltage overshoot and oscillation, mis-conduction, and electromagnetic interference, simplified epitaxy cycles, and reduced manufacturing process difficulty and cost.

[0039] Manufacturing a full superjunction structure for silicon carbide MOSFET high-voltage devices, spanning the entire drift region, is challenging and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing on-resistance and increasing the risk of premature breakdown. Additionally, the deeper the device pillar region, the stronger the bottom electric field, leading to poorer short-circuit withstand capability. Therefore, a bottom auxiliary layer can be added above the N-type substrate 101 to form a semi-superjunction structure, reducing manufacturing difficulty and cost while further improving device reliability. The high-performance, high-reliability silicon carbide MOSFET device with a centrally widened floating P-pillar region proposed in this invention provides a feasible technical path for the commercial application of silicon carbide superjunction devices.

[0040] like Figure 5 The figure shows a comparison of the capacitance characteristics of a conventional silicon carbide trench superjunction MOSFET structure and a floating P-pillar region structure. The dashed line represents the Coss curve of the output capacitance of the floating P-pillar region structure in Example 1, while the solid line represents the Coss curve of the output capacitance of the conventional silicon carbide trench superjunction MOSFET structure. The conventional structure consists of a single P-pillar region shorted to the source electrode, with other structural parameters consistent with the example. It can be seen that the structure with a floating P-pillar region proposed in this invention avoids drastic changes in the shape and effective area of ​​the depletion region of the alternating N-pillars and P-pillars during voltage build-up, suppressing or even eliminating the highly nonlinear capacitance region of the silicon carbide superjunction device. This effectively solves reliability problems such as device current and voltage overshoot and oscillation, device mis-conduction, and electromagnetic interference.

[0041] This invention optimizes the arrangement of P-pillars and N-pillars by placing the floating P-pillars below the trench. Simultaneously, by selectively shorting the top pillars to the source using a semi-enclosed structure, it effectively suppresses the electric field at the bottom of the trench. While maintaining a high blocking voltage, it significantly reduces the device's on-resistance and gate-drain capacitance, improving switching speed and reliability, and reducing switching losses. Furthermore, it facilitates the fabrication of high-quality silicon carbide superjunction MOSFETs, enhancing the long-term reliability of the device's gate oxide dielectric, short-circuit capability, and resistance to single-event burn-off. This provides a feasible technical path for the commercial application of silicon carbide superjunction devices. By placing the superjunction P-pillar region at the bottom of the trench to suppress the high electric field, and by selectively shorting the top pillar region to the source using a P-type semi-enclosed structure... Shorting eliminates most of the gate-drain face-to-face area, greatly reducing the device's Miller capacitance, thus better eliminating the highly nonlinear capacitance of the superjunction device; by setting up a floating pillar region silicon carbide trench superjunction MOSFET device, the floating superjunction pillar region of the device is formed through multiple epitaxial and ion implantation processes, which simplifies the number of epitaxial steps, reduces the difficulty and cost of device manufacturing process, and solves technical problems such as P-pillar alignment and surface stress in multiple epitaxial and ion implantation processes; by setting up alternating doped floating pillar regions and widening the floating pillar region structure, the device's resistance to single-particle burn-in and short-circuit withstand capability is improved, and by adjusting the position of the widened floating pillar region, the figure of merit (FOM) between the device's breakdown voltage and on-resistance is improved, thus enhancing device performance.

[0042] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A silicon carbide super junction MOSFET device having a floating column region, characterized by, The N-type substrate is formed with an N-type epitaxial layer on top, a floating P-column region is formed at the center of the N-type epitaxial layer, a gate trench oxide is formed on top of the floating P-column region, a polysilicon gate is arranged inside the gate trench oxide, a P-body region is formed on both sides of the gate trench oxide, an N+ source region is formed on top of each of the two P-body regions, a P+ contact region is formed on the side of the N+ source region, the P+ contact region and the N+ source region are short-circuited by a source electrode, an oxide dielectric layer is formed at the center of the source electrode, a drain electrode is arranged below the N-type substrate, and the top column region of the floating P-column region is short-circuited with the source electrode by a selective P-type half-enclosure structure.

2. The silicon carbide super junction MOSFET device with floating pillar regions of claim 1, wherein: The N-type epitaxial layer includes a first N-type epitaxial layer and a second N-type epitaxial layer, the first N-type epitaxial layer is formed on top of the N-type substrate, the second N-type epitaxial layer is formed on top of the first N-type epitaxial layer, the first N-type epitaxial layer and the second N-type epitaxial layer are N-type doped epitaxial layers, the doping concentration of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer, and the second N-type epitaxial layer is used to optimize the on-resistance of the top cell.

3. The silicon carbide super junction MOSFET device with floating pillar regions of claim 2, wherein: The floating P-column region is a floating high-doped P-column region, which is formed by multiple epitaxial growth and ion implantation.

4. The silicon carbide super junction MOSFET device with floating pillar regions of claim 2, wherein: The first N-type epitaxial layer includes an N-type epitaxial layer-a, an N-type epitaxial layer-b, an N-type epitaxial layer-c, an N-type epitaxial layer-d, an N-type epitaxial layer-e, an N-type epitaxial layer-f, an N-type epitaxial layer-g, an N-type epitaxial layer-h, and an N-type epitaxial layer-i, the N-type epitaxial layer-a is formed on top of the N-type substrate, the N-type epitaxial layer-b is formed on top of the N-type epitaxial layer-a, the N-type epitaxial layer-c is formed on top of the N-type epitaxial layer-b, the N-type epitaxial layer-d is formed on top of the N-type epitaxial layer-c, the N-type epitaxial layer-e is formed on top of the N-type epitaxial layer-d, the N-type epitaxial layer-f is formed on top of the N-type epitaxial layer-e, the N-type epitaxial layer-g is formed on top of the N-type epitaxial layer-f, and the second N-type epitaxial layer is formed on top of the N-type epitaxial layer-g.

5. The silicon carbide super junction MOSFET device with floating pillar regions of claim 4, wherein: The floating P-column region includes a first floating P-column region, a second floating P-column region, a third floating P-column region, and a fourth floating P-column region, the first floating P-column region is formed at the center of the N-type epitaxial layer-a, the second floating P-column region is formed at the center of the N-type epitaxial layer-c, the third floating P-column region is formed at the center of the N-type epitaxial layer-e, the fourth floating P-column region is formed at the center of the N-type epitaxial layer-g, and the gate trench oxide and the P-type half-enclosure structure are arranged on top of the fourth floating P-column region.

6. The silicon carbide super junction MOSFET device with floating pillar regions of claim 5, wherein: The doping concentrations of the N-type epitaxial layer-a, the N-type epitaxial layer-b, the N-type epitaxial layer-c, the N-type epitaxial layer-d, the N-type epitaxial layer-e, the N-type epitaxial layer-f, the N-type epitaxial layer-g, the N-type epitaxial layer-h, and the N-type epitaxial layer-i decrease in turn.

7. The silicon carbide super junction MOSFET device with floating pillar regions of claim 6, wherein: The doping concentrations of the first floating P-column region, the second floating P-column region, the third floating P-column region, and the fourth floating P-column region increase in turn.

8. The silicon carbide super junction MOSFET device with floating pillar regions of claim 1, wherein: The floating P-column region is provided with symmetrical top widening regions at both ends of the top thereof.

9. The silicon carbide super junction MOSFET device with floating pillar regions of claim 1, wherein: The floating P-column region is provided with symmetrical central widening regions at both ends of the center thereof.

10. The silicon carbide super junction MOSFET device with floating pillar regions of claim 1, wherein: The P-type half-enclosure structure is short-circuited with the source electrode to suppress the electric field intensity at the bottom and corners of the trench.

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