Quantum bit mapping optimization method for hardware guidance and fidelity perception and related device

Abstract

The invention discloses a quantum bit mapping optimization method for hardware guidance and fidelity perception and a related device, and belongs to the field of quantum computing, and the method comprises the steps: defining each node in a hardware coupling graph of a target quantum processor as an initial community; evaluating all adjacent community pairs according to a reward function defined based on modularity and fidelity of candidate communities, selecting an optimal community pair for fusion, and taking the community with the largest current scale as an optimal candidate area; iteratively executing a community fusion step until a converged single community is obtained; and selecting an optimal candidate region with the physical quantum bit number greater than or equal to the logic quantum bit number of the quantum circuit to be mapped and the minimum scale, and outputting a mapping sub-graph. According to the method, through a recursive community fusion strategy, the operation range of the solver is restrained in a subspace with the scale greatly reduced and the quality better, the problem of combinatorial explosion caused by global search is fundamentally avoided, and the calculation overhead is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of quantum computing, and in particular to a hardware-guided and fidelity-aware method and apparatus for optimizing qubit mapping. Background Technology

[0002] Quantum computing is a disruptive computing model based on the principles of quantum mechanics. Its inherent parallelism provides unprecedented capabilities for solving specific types of computational problems. With continuous breakthroughs in quantum hardware technology, physical systems, represented by superconducting quantum chips, have made significant progress in both integration scale and coherence performance, laying the hardware foundation for exploring quantum computing applications. Quantum compilers, as the core link connecting abstract quantum algorithms with concrete physical implementations, function to transform high-level algorithmic languages ​​into low-level instruction sequences that can be precisely executed on specific quantum processors—that is, quantum circuits.

[0003] In this compilation process, qubit mapping constitutes a fundamental and crucial step. The essence of this technique is to establish an optimal correspondence between the logical qubits in the algorithm description and the physical qubits on the physical processor. Simultaneously, it must be ensured that all quantum gate operations conform to the processor's inherent, finite topology of physical bit connectivity. For example... Figure 1 As shown, a typical qubit mapping process includes: (a) the original quantum circuit to be mapped; (b) a physical hardware coupling graph with a specific connectivity topology and different link fidelity values; and (c) the final circuit after mapping, which may have had swap gates inserted to satisfy connectivity constraints. A high-performance qubit mapping strategy can fundamentally reduce auxiliary gate operations, thereby effectively compressing the overall depth and execution time of quantum circuits. This is crucial for improving the overall fidelity of algorithms in the current era of Noisy Intermediate-Scale Quantum (NISQ).

[0004] Despite the continuous evolution of existing quantum bit mapping technology in theory and practice, its inherent limitations are becoming increasingly apparent when faced with the ever-growing scale of quantum hardware and increasingly stringent fidelity requirements. These limitations are mainly manifested in the following two core technical bottlenecks: First, existing methods face significant scalability challenges. As the number of physical qubits on quantum processors increases, the solution space for mapping problems expands exponentially. Existing techniques require a dramatic increase in the number of variables and constraints to manage during the solution process, leading to excessive computational overhead. When dealing with complex mapping tasks for large-scale quantum architectures, these methods are often extremely time-consuming and may even fail to converge to a feasible solution within a reasonable timeframe, posing a major obstacle to the efficient utilization of quantum computing resources.

[0005] Secondly, existing optimization paradigms fail to effectively integrate key hardware physical characteristics. A significant feature of the NISQ era is the non-ideality of the hardware; the fidelity of quantum gate operations exhibits significant non-uniformity across different physical locations on the chip (e.g., Figure 1 (as shown by the values ​​on each side in (b)). However, existing mapping techniques often focus on structural indicators such as line depth and number of switching gates in their optimization objectives, failing to incorporate this underlying, heterogeneous fidelity distribution information into their decision-making models. This paradigmatic deficiency may result in logic lines being deployed in a physically connected but noisy hardware region, thereby compromising the physical reliability and final accuracy of the calculation results at the source. Summary of the Invention

[0006] The purpose of this invention is to overcome the problems of the prior art and to provide a hardware-guided and fidelity-aware quantum bit mapping optimization method and related apparatus.

[0007] The objective of this invention is achieved through the following technical solution: a hardware-guided and fidelity-aware quantum bit mapping optimization method, which includes the following steps: Obtain the physical property specification of the target quantum processor, including the hardware coupling graph and the fidelity dataset, and define each node representing a physical qubit in the hardware coupling graph as an initial community; All adjacent community pairs are evaluated based on the reward function. The optimal community pair is selected for fusion based on the evaluation results. The community with the largest current size is selected as the optimal candidate region. The number of nodes, node set, and internal edge set of the optimal candidate region are then grouped into triples. The candidate region is stored in the form of a candidate region library; the above community fusion steps are executed iteratively until all communities are aggregated into a single community, resulting in a candidate region library that includes optimal candidate regions of different sizes; the reward function is defined as a weighted combination of the modularity and fidelity of the candidate community, where modularity is used to quantify the structural strength of the community; Based on the number of logical qubits of the quantum circuit to be mapped Traverse the candidate region pool and select those that meet the requirements. The optimal candidate region with the smallest constraint size is used as the basic mapping region; Output a mapping subgraph based on the base mapping region.

[0008] In one example, before outputting the mapping subgraph based on the base mapping region, the following is also included: Set expansion factor Connect all nodes in the base mapping region External nodes of the layer are merged into the base mapping region to obtain the optimized mapping region; The optimized mapping subgraph is output based on the optimized mapping region.

[0009] In one example, the hardware coupling diagram , A node set is a collection of physical qubits. An edge set is a set of physical connections between physical qubits that can perform two-bit gate operations.

[0010] In one example, the reward function is defined as a weighted combination of the modularity of the candidate community and its average fidelity.

[0011] In one example, the reward function The calculation expression is: ; in, Indicates modularity; This represents the average fidelity of the candidate region; This represents the weight hyperparameter.

[0012] In one example, the modularity The calculation expression is: ; in, This indicates that edges in the hardware coupling graph exist in the community. i Internal probability, Indicates the connection between communities i With the community j The probability of.

[0013] In one example, the expansion factor .

[0014] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.

[0015] The present invention also includes a computer program product comprising a computer program that, when executed by a processor, implements the steps of the hardware-guided and fidelity-aware quantum bit mapping optimization method formed by any or a combination of the above examples.

[0016] The present invention also includes a storage medium storing computer instructions that, when executed, perform the steps of the hardware-guided and fidelity-aware quantum bit mapping optimization method formed by any or more of the above examples.

[0017] The present invention also includes a terminal comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, and the processor, when executing the computer instructions, performs the steps of the hardware-guided and fidelity-aware qubit mapping optimization method formed by any or more of the above examples.

[0018] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention achieves a polynomial-level reduction in computational complexity.

[0019] This invention employs a hardware-guided regionalization strategy, specifically a recursive community fusion step, to identify high-quality sub-regions (optimal candidate regions of different sizes) from the complete hardware graph that possess both topological compactness (measured by modules) and physical reliability (measured by fidelity). This constrains the solver's computational scope to a significantly smaller but higher-quality subspace, fundamentally avoiding the combinatorial explosion problem caused by global search, greatly reducing computational overhead, improving computational efficiency, and providing a significant performance acceleration for existing mapping techniques.

[0020] 2. This invention constructs a direct optimization path from physical layer fidelity to logic layer mapping strategy.

[0021] This invention innovatively quantifies the heterogeneous fidelity information of the hardware and integrates it into the core decision function of region selection, ensuring that the quantum circuit is preferentially configured in hardware regions with higher physical reliability (good physical connectivity and low noise level). This not only improves the success rate of a single calculation, but also enhances the robustness of the mapping method, and guarantees the physical reliability and final accuracy of the calculation results.

[0022] 3. The method of the present invention has a highly modular design and forward-looking scalability.

[0023] This invention can serve as a universal front-end optimization module, seamlessly integrating with various existing qubit mapping technologies to comprehensively improve their efficiency and fidelity. Furthermore, as the scale of quantum processors continues to grow in the future, the core idea of ​​this invention based on local optimization will demonstrate increasingly powerful advantages. Attached Figure Description

[0024] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0025] Figure 1 This is a schematic diagram of a typical quantum bit mapping process; Figure 2 A flowchart illustrating a method provided as an example of the present invention; Figure 3 This is a schematic diagram of a recursive community fusion process on an IBM QX2 hardware coupling graph, provided as an example of the present invention, wherein each arrow indicates a reward function-based process. The optimal community merger; Figure 4 This is a schematic diagram of the SWAP gate mapping in the absence of auxiliary qubits, as provided in an example of the present invention. Figure 5 This is a schematic diagram illustrating the community expansion effect when the expansion factor is 1, as provided in an example of the present invention. Figure 6 A method flowchart is provided as a preferred example of the present invention; Figure 7 A comparison diagram of the mapping regions selected by the traditional method and the method of the present invention. Detailed Implementation

[0026] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] In one example, such as Figure 2 As shown, a hardware-guided and fidelity-aware qubit mapping optimization method is applied to a medium-scale quantum computing device with noise to establish an efficient correspondence between logical qubits and physical qubits. The method includes the following steps: S10: Obtain the physical property specification of the target quantum processor, including the hardware coupling graph and the fidelity dataset, and define each node in the hardware coupling graph as an initial community.

[0029] Specifically, hardware coupling diagram , , is the node set of the coupling graph, representing the collection of physical qubits. Physical qubits are the basic computing units that constitute the target quantum processor and can be independently addressed and manipulated. In a specific superconducting quantum chip implementation scenario, each physical qubit corresponds to a miniature superconducting circuit fabricated on a silicon chip by photolithography. The quantum state of this miniature superconducting circuit can be manipulated by applying microwave pulses of a specific frequency. The edge set of a coupling graph represents the set of physical connections between physical qubits that allow for two-bit gate operations. In the aforementioned superconducting quantum chip scenario, an edge corresponds to a capacitive or inductive coupling element implemented on the chip, enabling controlled logic operations such as CNOT gates or CZ gates to be performed on the physical qubits. Figure 1 (b) shows an example of such a coupled graph, where nodes represent physical qubits and edges represent physical connections.

[0030] Furthermore, the fidelity of quantum gate operations is used to quantify how close the actually executed quantum gate is to the ideal target quantum gate. Higher fidelity indicates a more precise and reliable gate operation; lower fidelity indicates a larger operational error and a less reliable result. The fidelity dataset includes precise measurements of the fidelity of two-bit gate operations corresponding to each edge in the coupling graph. These values ​​reflect the performance heterogeneity of the hardware at different physical locations, such as... Figure 1 The values ​​on the edges in (b) are shown. Each physical qubit in the coupling diagram C is represented by... After defining it as an independent initial community, the community list Includes n A community containing only a single node.

[0031] S20: Evaluate all adjacent community pairs according to the reward function, select the optimal community pair for fusion based on the evaluation results, and take the community with the largest current size as the optimal candidate region. Then, combine the number of nodes, node set, and internal edge set of the optimal candidate region into a triplet. The community fusion steps described above are iteratively executed until all communities are aggregated into a single community, resulting in a candidate region library that includes optimal candidate regions of different sizes. The reward function is defined as a weighted combination of the modularity and fidelity of the candidate community, with the modularity used to quantify the structural strength of the community.

[0032] Step S20 identifies optimal regions through recursive community fusion, aiming to identify high-quality sub-regions with both topological compactness and physical reliability from the complete hardware graph using a bottom-up iterative clustering algorithm. Figure 3 As shown, the process begins by initializing each physical qubit as an independent micro-community, followed by an iterative merging phase. In each iteration, the current community list is... All adjacent communities in The process involves evaluation and merging communities that maximize the reward function. After each merge, the largest community in the current partitioning scheme is selected as the optimal candidate region for that size, and its number of nodes, node set, and internal edge set are grouped into triples. Stored in a candidate region library The iterative process continues until all nodes converge into a single macroscopic community.

[0033] S30: Based on the number of logical qubits of the quantum circuit to be mapped Traverse the candidate region pool and select those that meet the requirements. The optimal candidate region with the smallest constraint size is used as the base mapping region.

[0034] By defining the basic mapping region, the search range is limited to a region close to the number of logical qubits (usually only slightly more than the number of logical qubits), thereby constraining the solver's computational range to a subspace of significantly smaller size but better quality. This fundamentally avoids the combinatorial explosion problem caused by global search and greatly reduces computational overhead.

[0035] S40: Output a mapping subgraph based on the base mapping region.

[0036] Among them, the mapping subgraph This serves as an effective hardware topology constraint, provided to downstream qubit mapping algorithms. This means that subsequent mapping solutions will no longer be oriented towards the entire large and complex physical hardware graph, but rather only towards... By searching within a significantly smaller and physically superior subspace, the computationally intractable global mapping problem is transformed into an efficient optimization problem within a optimized, controllable-sized local subgraph, thereby improving quantum computing efficiency. Both theoretical analysis and experimental results demonstrate that this method significantly accelerates the performance of existing mapping techniques.

[0037] Optionally, the reward function is defined as a weighted combination of the modularity and average fidelity of the candidate community. The calculation expression is: ; in, Modularity is a topological metric that quantifies the structural strength of a network community. The average fidelity of the candidate region is a quantifiable metric for physical performance, representing the average two-bit gate fidelity of all edges within the fused new community. This metric ensures that the fusion process tends to select regions containing high-fidelity physical connections. This represents the weight hyperparameter, used to adjust the relative importance of topology and physical fidelity in decision-making.

[0038] In one example, modularity The calculation expression is: ; in, This indicates that edges in the hardware coupling graph exist in the community. i Internal probability, Indicates the connection between communities i With the community j The probability of a high Q value. A high Q value means that the internal connections of the merged new community are much tighter than its external connections, and it has a superior topological structure.

[0039] In the examples above, to reduce computational overhead, the size of the mapping region is strictly limited to the number of logical qubits. However, this may lead to the need to introduce too many swapping gates due to a lack of sufficient auxiliary qubits. For example... Figure 4 As shown, due to the mapping region ( , , , , The lack of auxiliary bits necessitates the introduction of a long series of swap gates (SWAP1, SWAP2, SWAP3) for long-distance operations, significantly increasing circuit complexity. To address this issue and establish an optimal balance between solution quality and computational efficiency, this example introduces an adaptive community expansion mechanism. After selecting the optimal base region, this adaptive community expansion mechanism is as follows: Set expansion factor The k-layer physical qubits directly connected to the boundary of the basic mapping region are included to obtain the optimized mapping region, and the optimized mapping subgraph is output based on the optimized mapping region.

[0040] Specifically, the neighborhood expansion operation in this example is performed by setting an expansion factor. , will the basic area The first-order neighborhood (i.e., all neighborhoods with) The nodes are directly connected but do not belong to The external nodes and their related connections are all incorporated into the basic mapping region to obtain the optimized mapping region. Preferably, k=1 has been proven to have the best overall performance, such as... Figure 5 As shown, when the expansion factor At that time, the nearest physical bits Once included in the base mapping region, operations that previously required multiple swaps can now be completed with a single swap (SWAP1), simplifying complex multi-step swap operations into single-step operations and significantly optimizing potential mapping paths. The final output of this example is an optimized mapping subgraph. It retains the high-quality characteristics of the core area while also possessing ample topological flexibility.

[0041] Combining the above examples yields preferred examples of the present invention, such as... Figure 6 As shown, it includes the following steps: S1: Obtain the physical property specification of the target quantum processor, including the hardware coupling graph and the fidelity dataset, and define each node in the hardware coupling graph as an initial community; S2: Evaluate all adjacent community pairs according to the reward function, select the optimal community pair for fusion based on the evaluation results, and take the community with the largest current size as the optimal candidate region. Then, combine the number of nodes, node set, and internal edge set of the optimal candidate region into a triplet. The candidate regions are stored in the form of a candidate region library; the above community fusion steps are iteratively executed until all communities are aggregated into a single community, resulting in a candidate region library that includes optimal candidate regions of different sizes. S3: Based on the number of logical qubits of the quantum circuit to be mapped Traverse the candidate region pool and select those that meet the requirements. The optimal candidate region with the smallest constraint size is used as the basic mapping region; Set expansion factor Connect all nodes in the base mapping region External nodes of the layer are merged into the base mapping region to obtain the optimized mapping region; S4: Output the optimized mapping subgraph based on the optimized mapping region.

[0042] The optimized mapping subgraph combines excellent topology quality with hardware operational reliability, and the optimized mapping path does not introduce excessive switches. As an effective hardware topology constraint provided to downstream qubit mapping algorithms, the subsequent mapping solution process will no longer be geared towards the entire large and complex physical hardware graph, but only towards... The search is performed within a defined subspace of significantly reduced size and superior physical properties. In this way, the invention guides the mapping algorithm to converge quickly to a high-quality solution. Its ultimate goal is to find a solution such as... Figure 7 (2) shows the mapping region, where all two-bit gate operations have high fidelity (represented by darker edge colors), thus systematically avoiding... Figure 7 (1) may be a suboptimal mapping scheme that includes low-fidelity links (lighter colored edge regions).

[0043] In summary, the method of this invention, through a systematic and phased optimization process, deeply integrates the topology and fidelity information of the hardware into the preprocessing of the mapping problem, successfully transforming a large-scale, global problem into an efficient, localized optimization task, thereby achieving significant technical progress in both improving solution efficiency and final execution fidelity.

[0044] The present invention also provides a computer program product, comprising a computer program that, when executed by a processor, implements the steps of the hardware-guided and fidelity-aware quantum bit mapping optimization method formed by any or a combination of the above examples. The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement the present invention.

[0045] The present invention also provides a storage medium having the same inventive concept as the hardware-guided and fidelity-aware quantum bit mapping optimization method formed by any or more of the above examples, wherein computer instructions are stored thereon, and the computer instructions, when executed, perform the steps of the hardware-guided and fidelity-aware quantum bit mapping optimization method formed by any or more of the above examples.

[0046] Based on this understanding, the technical solution of this embodiment, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0047] This invention also provides a terminal that shares the same inventive concept as any or more examples corresponding to the aforementioned hardware-guided and fidelity-aware qubit mapping optimization method, including a memory and a processor. The memory stores computer instructions executable on the processor, and the processor, when executing the computer instructions, performs the steps of the aforementioned hardware-guided and fidelity-aware qubit mapping optimization method. The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement this invention.

[0048] In one example, the terminal, i.e., the electronic device, is represented in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one processing unit (processor) mentioned above, at least one storage unit mentioned above, and a bus connecting different system components (including storage units and processing units).

[0049] The storage unit stores program code that can be executed by the processing unit, causing the processing unit to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit can execute the aforementioned hardware-guided and fidelity-aware quantum bit mapping optimization method.

[0050] The storage unit may include a readable medium in the form of a volatile storage unit, such as a random access memory (RAM) 3201 and / or a cache storage unit, and may further include a read-only memory (ROM).

[0051] The storage unit may also include a program / utility having a set (at least one) of program modules, including but not limited to: an operating system, one or more applications, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0052] A bus can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus that uses any of the various bus structures.

[0053] The electronic device can also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., routers, modems, etc.). This communication can be performed via input / output (I / O) interfaces. Furthermore, the electronic device can communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter. The network adapter communicates with other modules of the electronic device via a bus. It should be understood that other hardware and / or software modules can be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0054] Through the above description, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to this exemplary embodiment can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method of the exemplary embodiment of this application.

[0055] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A hardware-guided and fidelity-aware quantum bit mapping optimization method, characterized in that, Includes the following steps: Obtain the physical property specification of the target quantum processor, including the hardware coupling graph and the fidelity dataset, and define each node representing a physical qubit in the hardware coupling graph as an initial community; All adjacent community pairs are evaluated based on the reward function. The optimal community pair is selected for fusion based on the evaluation results. The community with the largest current size is selected as the optimal candidate region. The number of nodes, node set, and internal edge set of the optimal candidate region are then grouped into triples. The candidate region is stored in the form of a candidate region library; the above community fusion steps are executed iteratively until all communities are aggregated into a single community, resulting in a candidate region library that includes optimal candidate regions of different sizes; the reward function is defined as a weighted combination of the modularity and fidelity of the candidate community, where modularity is used to quantify the structural strength of the community; Based on the number of logical qubits of the quantum circuit to be mapped Iterate through the candidate region pool and select those that meet the requirements. The optimal candidate region with the smallest constraint size is used as the basic mapping region; Output a mapping subgraph based on the base mapping region.

2. The hardware-guided and fidelity-aware quantum bit mapping optimization method according to claim 1, characterized in that, Before outputting the mapping subgraph based on the base mapping region, the following steps are also included: Set expansion factor Connect all nodes in the base mapping region External nodes of the layer are merged into the base mapping region to obtain the optimized mapping region; The optimized mapping subgraph is output based on the optimized mapping region.

3. The hardware-guided and fidelity-aware quantum bit mapping optimization method according to claim 1, characterized in that, The hardware coupling diagram , A node set is a collection of physical qubits. An edge set is a set of physical connections between physical qubits that can perform two-bit gate operations.

4. The hardware-guided and fidelity-aware quantum bit mapping optimization method according to claim 1, characterized in that, The reward function is defined as a weighted combination of the modularity of the candidate community and its average fidelity.

5. The hardware-guided and fidelity-aware quantum bit mapping optimization method according to claim 4, characterized in that, The reward function The calculation expression is: ； in, Indicates modularity; This represents the average fidelity of the candidate region; This represents the weight hyperparameter.

6. The hardware-guided and fidelity-aware quantum bit mapping optimization method according to claim 1 or 3, characterized in that, modularity The calculation expression is: ； in, This indicates that edges in the hardware coupling graph exist in the community. i Internal probability, Indicates the connection between communities i With the community j The probability of.

7. The hardware-guided and fidelity-aware quantum bit mapping optimization method according to claim 2, characterized in that, The expansion factor .

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the hardware-guided and fidelity-aware quantum bit mapping optimization method according to any one of claims 1-7.

9. A storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed, they perform the steps of the hardware-guided and fidelity-aware quantum bit mapping optimization method according to any one of claims 1-7.

10. A terminal comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, characterized in that, When the processor executes the computer instructions, it performs the steps of the hardware boot and fidelity-aware quantum bit mapping optimization method according to any one of claims 1-7.

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