Test structure and test method for a semiconductor device

Abstract

The application provides a test structure and a test method of a semiconductor device, and relates to the technical field of semiconductors. The application constructs a via test structure for testing a target via in a semiconductor structure in a scribe groove of the semiconductor device. In the via test structure, a to-be-tested via and the target via are formed by the same process, so that the to-be-tested via can reflect the process parameters of the target via. In the via test structure, the application utilizes the feature that the target via is exposed relative to the dielectric layer when penetrating the dielectric layer, constructs two capacitors on the two sides of the exposed end of the to-be-tested via relative to the dielectric layer, and thus the distance between the to-be-tested via and the capacitors can be reflected by measuring the capacitance value of the capacitors and the to-be-tested via, so as to quantitatively determine the offset of the to-be-tested via. In addition, the via test structure can form a hierarchical structure to measure the offset of the via between different levels in the semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor technology, specifically to a test structure and test method for a semiconductor device. Background Technology

[0002] With the development of integrated circuits, the size of transistors and back-end metal interconnects inside chips is becoming smaller and smaller. Interlayer connections between metal interconnects are generally made using vias (vias). The increasingly smaller metal and via sizes place more stringent demands on the alignment accuracy of these vias. Misalignment of vias can lead to thinning of the dielectric layer between vias, thereby affecting electrical performance or reliability.

[0003] To inspect the connectivity of vias, semiconductor manufacturing processes can incorporate test structures on the dicing grooves of the wafer to perform wafer acceptance testing (WAT). The dicing grooves are narrow strips on the wafer used for subsequent dicing, typically between 60 μm and 150 μm in width. The primary purpose of WAT is to monitor process stability and quality during wafer manufacturing by measuring the electrical parameters of these test structures, ensuring that the wafer meets electrical specifications.

[0004] Specifically, in WAT (Wafer Test Assembly), the test structure within the dicing groove and the actual structure in the semiconductor device can be formed simultaneously using the same process. This allows for the testing of the actual semiconductor device structure by testing the test structure within the dicing groove. For example, in WAT for vias, the vias in the test structure and the vias in the semiconductor device are formed simultaneously using the same process. The test structure for vias in semiconductor devices is relatively simple, making it difficult to accurately measure the specific offset and direction of the via structure. Therefore, how to achieve accurate measurement of the via structure offset in WAT is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, embodiments of this application provide a test structure and test method for a semiconductor device, which uses the capacitance value to reflect the distance between the via and the capacitor, so as to quantitatively measure the offset of the via structure.

[0006] In a first aspect, this application provides a test structure for a semiconductor device. The test structure includes at least one via test structure disposed in a dicing groove of the semiconductor device. The via test structure includes a dielectric layer, at least one via to be tested, and at least one capacitor bank. The at least one via to be tested is disposed within the dielectric layer and connects a first surface and a second surface of the dielectric layer, wherein the via to be tested reflects a target via in the semiconductor device. The at least one capacitor bank is disposed on the second surface, wherein the capacitor bank includes a first capacitor and a second capacitor respectively disposed on both sides of a second end of the at least one via to be tested, and the second end of the via to be tested is located between the first capacitor and the second capacitor.

[0007] Secondly, this application provides a testing method for a semiconductor device. The testing method is applied to a testing structure of the semiconductor device described in the first aspect. For a via testing structure within the testing structure, the testing method includes: detecting a first capacitance value between the via to be tested and a first capacitor in the testing structure, wherein the first capacitance value reflects the distance between the first capacitor and the via to be tested; detecting a second capacitance value between the via to be tested and a second capacitor in the testing structure, wherein the second capacitance value reflects the distance between the second capacitor and the via to be tested; and determining an offset value of the via to be tested based on the first capacitance value and the second capacitance value.

[0008] Based on the test structure and test method for semiconductor devices provided in this application, this application constructs a via test structure in the dicing groove of a semiconductor device for testing target vias in the semiconductor structure. In the via test structure, the via to be tested and the target via are formed using the same process, so that the via to be tested can reflect the process parameters of the target via. In the via test structure, this application utilizes the characteristic that the target via is exposed relative to the dielectric layer when penetrating it. Two capacitors are constructed on both sides of the exposed end of the via to be tested relative to the dielectric layer. The distance between the via to be tested and the capacitors can be reflected by measuring the capacitance values ​​of the capacitors and the via to be tested, thereby quantitatively determining the offset of the via to be tested. Furthermore, the via test structure can form a hierarchical structure to measure the offset of vias between different layers in the semiconductor device. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the single-layer through-hole test structure provided in some embodiments of this application.

[0011] Figure 2 This is an exemplary flowchart of a testing method provided in some embodiments of this application.

[0012] Figure 3 This is a schematic diagram of the through-hole test structure provided in some embodiments of this application when there are offsets and dimensional differences.

[0013] Figure 4 This is a schematic diagram of the test structure provided in some embodiments of this application from a top-down perspective.

[0014] Figure 5 This is another schematic diagram of the test structure provided in some embodiments of this application from a top-down perspective.

[0015] Figure 6 This is a schematic diagram of the multilayer through-hole test structure provided in some embodiments of this application.

[0016] Among them, 100 is the through-hole test structure; 110 is the dielectric layer; 111 is the first surface; 112 is the second surface; 120 is the through-hole to be tested; 121 is the first end; 122 is the second end; 131 is the first capacitor; 132 is the second capacitor; and 140 is the connector. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0019] In this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0020] Exemplary single-layer through-hole test structure and its test method: In via-hole (WAT) testing, related techniques generally employ a comb-based test structure for via offset testing. Specifically, the test structure often consists of two comb-like structures, each composed of two layers of metal and a via between them. Different voltages are applied to the comb-like structures, and the via offset is determined by the withstand voltage test.

[0021] The aforementioned testing method is essentially a through-hole in-situ test, meaning the test process determines whether the through-hole is located in its correct position based on pressure resistance. If the test results do not meet the requirements, the through-hole structure is considered to be out of place. This process does not measure the direction or amount of through-hole offset. Furthermore, the influence of the manufacturing process on the through-hole size (such as expansion / shrinkage) can also affect the aforementioned measurement results, leading to inaccurate measurements.

[0022] To accurately determine the offset of vias, this application constructs a via test structure in the dicing groove of a semiconductor device for testing target vias in the semiconductor structure. In the via test structure, the via to be tested and the target via are formed using the same process, so that the via to be tested can reflect the process parameters of the target via. In the via test structure, this application utilizes the characteristic that the target via is exposed relative to the dielectric layer when penetrating it. Two capacitors are constructed on both sides of the exposed end of the via to be tested relative to the dielectric layer. By measuring the capacitance value between the capacitors and the via to be tested, the distance between the via to be tested and the capacitors can be reflected, thereby quantitatively determining the offset of the via to be tested. In addition, the via test structure can be formed into a hierarchical structure to measure the offset of vias between different layers in the semiconductor device.

[0023] Specifically, to further illustrate the through-hole testing structure provided in this application, this application also provides a schematic diagram of a single-layer through-hole testing structure ( Figure 1 ).

[0024] in, Figure 1 A schematic diagram of the through-hole testing structure at the cross-section of the dicing groove can be shown. That is, this application can perform cross-sectional processing of the dicing groove along the stacking direction of the semiconductor device to obtain... Figure 1 The diagram shown is a structural schematic.

[0025] like Figure 1 As shown, a single-layer via test structure 100 reflecting a target via may include a dielectric layer 110 and at least one via 120 to be tested. The dielectric layer 110 includes a first surface 111 and a second surface 112, and the via 120 to be tested penetrates the dielectric layer 110 to connect the first surface 111 and the second surface 112.

[0026] The via under test 120 can reflect the target via in the semiconductor structure. That is, on the wafer, the via under test 120 and the target via are formed based on the same fabrication process (although the actual fabrication processes of the two generally have some differences in parameters). Therefore, the via under test 120 can reflect the relevant parameters of the target via.

[0027] A target via can refer to a via structure in a semiconductor device that needs to be tested. The semiconductor device can include via structures formed between metal layers in back-end processes and metal lines formed in front-end processes connecting the first metal layer to transistors (such as the source, drain, and gate of a transistor).

[0028] Considering the fabrication process of the target vias, the aforementioned via testing structures generally correspond one-to-one with the target vias. Therefore, when multiple vias in a semiconductor device need to be tested, this application can construct multiple single-layer via testing structures.

[0029] In some embodiments, to reflect the vias at various levels within a semiconductor device, the aforementioned plurality of single-layer via test structures can be formed into a multi-layer stacked via test structure along the stacking direction of the vias. More information on multi-layer via test structures can be found at [link to relevant documentation]. Figure 6 And related content.

[0030] Similar to the via 120 under test, the dielectric layer 110 can also be the same dielectric as the target via, reflecting the hierarchical structure penetrated by the target via. In semiconductor devices, the target via can penetrate the hierarchical structure it resides in, thereby electrically connecting the structures to be connected on both sides of that hierarchical structure. Similarly, the corresponding via 120 under test can also penetrate the dielectric layer 110, thereby electrically connecting the structure on the first surface 111 to the structure on the second surface 112. For example, a via between metal layers can penetrate the dielectric between the metal layers to achieve the connection between the metal layers on the upper and lower surfaces of the dielectric.

[0031] To achieve the aforementioned connection, the length of the target via in the stacking direction of the semiconductor device is greater than the thickness of the dielectric layer it is in, so that it can be embedded in the structure to be connected, achieving a stable electrical connection. For example, when forming the metal line of a transistor, it is often necessary to first etch the dielectric between the metal layer and the transistor. After penetrating the dielectric, it is often necessary to continue etching in the corresponding region of the transistor (such as the region where the source, drain, and gate are located) to form a groove, and then fill it with conductive dielectric to form a metal line, so as to ensure a stable connection between the metal line and the corresponding region of the transistor.

[0032] Therefore, the through hole 120 to be tested also has a similar structure. For example... Figure 1As shown, the through hole 120 to be tested has a first end 121 and a second end 122. The first end 121 is formed at the first surface 111 and protrudes relative to the first surface 111. The second end 122 is formed at the second surface 112 and protrudes relative to the second surface 112.

[0033] It should be noted that the aforementioned "electrically connecting the structure on the first surface 111 with the structure on the second surface 112" is only an explanation of the actual capability of the through hole 120 under test, and does not involve setting corresponding structures on the first and second surfaces of the through hole test structure to connect them through the through hole under test.

[0034] Based on the aforementioned protrusion of the via 120 under test on the dielectric layer 110, this application creatively discovers that a capacitance test structure can be formed at the protruding end of the via 120 relative to the dielectric layer 110. The capacitance value reflects the distance between the test structure and the via 120 under test, thereby resolving the offset of the via 120 under test. For ease of description, the following content of this application constructs the capacitance test structure based on the second end 122 of the via 120 under test.

[0035] Therefore, the aforementioned through-hole test structure 100 may further include at least one capacitor assembly. The capacitor assembly is disposed on the second surface 112 and includes a first capacitor 131 and a second capacitor 132 respectively disposed on both sides of the second end 122 of the through-hole 120 to be tested. The second end 122 has gaps with both the first capacitor 131 and the second capacitor 132 and is located between the first capacitor 131 and the second capacitor 132.

[0036] The first capacitor 131 and the second capacitor 132 can be fabricated based on the conductive structure connected by the target via. For example, in later processes, the target via often connects two metal layers, so the first capacitor 131 and the second capacitor 132 can be generated based on a fabrication method for a metal layer connected by the target via.

[0037] During actual testing, the test hole 120 and one of the first capacitor 131 and the second capacitor 132 can be connected to the WAT capacitance testing device to measure the corresponding capacitance value.

[0038] It should be noted that since the aforementioned capacitor assembly can measure the offset of the via under test in the target direction, for the direction perpendicular to the target direction (non-stacking direction), an additional via test structure can be constructed along the perpendicular direction of the target direction, or another capacitor assembly can be constructed in the perpendicular direction of the target direction to achieve measurement in the corresponding direction. Those skilled in the art can make adjustments according to actual needs, and the specific configuration method will not be elaborated here.

[0039] To facilitate the connection between the capacitance testing device and the through-hole 120 under test, the through-hole testing structure 100 further includes at least one connector 140 disposed on the first surface 111. The connector 140 contacts the first end 121 of the through-hole 120 under test and is electrically connected to at least one through-hole 120 under test through the first end 121.

[0040] Therefore, during testing, the probes of the capacitance testing device only need to contact the connector 140, without needing to align them with each test hole 120.

[0041] The aforementioned connector 140, similar to the aforementioned first capacitor 131 and second capacitor 132, can also be fabricated based on the conductive structure connected to the target through-hole. The conductive structure corresponding to the connector 140 is generally different from the conductive structures corresponding to the aforementioned first capacitor 131 and second capacitor 132.

[0042] It should be noted that the structure of the aforementioned connector 140 is generally similar to that of the aforementioned capacitor (i.e., theoretically it should be a black-filled pattern). In order to clearly show the first end of the through hole 120 to be tested, the connector 140 is presented as a white-filled black-edge pattern in some of the drawings of this application.

[0043] In some embodiments, in order to accurately measure the capacitance value, the greater the height (H) of the aforementioned through-hole 120 protruding from the second end 122 relative to the second surface 112, the more likely the capacitor assembly can be corresponding to the conductive structure located below the target through-hole along the stacking direction of the semiconductor device during fabrication, and fabricated based on the corresponding conductive structure.

[0044] As an example only, when the aforementioned test hole 120 reflects the through hole between the first metal layer and the second metal layer, the connector 140 is generally formed based on the manufacturing process of the second metal layer, while the first capacitor 131 and the second capacitor 132 are generally formed based on the manufacturing process of the first metal layer.

[0045] In some embodiments, considering that the aforementioned through-hole test structure is disposed inside the scribe line, to facilitate the connection of each specific structure with the capacitance testing device, the through-hole test structure 100 may further include a plurality of test pads formed on the surface of the scribe line. When measuring capacitance, the capacitance testing device can be connected to the test pads to achieve connection with the corresponding internal structure. Specifically, the through-hole test structure may include a connection test pad electrically connected to a connector, a first capacitance test pad electrically connected to a first capacitor, and a second capacitance test pad electrically connected to a second capacitor.

[0046] Based on the above-mentioned through-hole test structure, during actual testing, the capacitance value between the through-hole 120 to be tested and the first capacitor 131 (referred to as the first capacitance value) and the capacitance value between the through-hole 120 to be tested and the second capacitor 132 (referred to as the second capacitance value) can be determined.

[0047] Combined with the formula for calculating capacitance ( Where C is the capacitor. (where S is the dielectric constant, S is the area of ​​the plates forming the capacitor, and d is the distance between the plates forming the capacitor). The aforementioned first capacitance value can reflect the distance d1 between the through hole 120 to be tested and the first capacitor 131, and the second capacitance value can reflect the distance d2 between the through hole 120 to be tested and the second capacitor 132.

[0048] To further illustrate the specific process of measuring the offset of the via 120 under test, this application also provides an exemplary flowchart of a semiconductor device testing method ( Figure 2 ).

[0049] like Figure 2 As shown, based on the aforementioned Figure 1 The through-hole test structure provided in this application, the test method P200, may include the following steps: S210. Detect the first capacitance value between the through hole to be tested and the first capacitor in the test structure.

[0050] S220, Detect the second capacitance value between the through hole to be tested and the second capacitor in the test structure.

[0051] S230. Determine the offset value of the through hole to be tested based on the first capacitance value and the second capacitance value.

[0052] The aforementioned steps S210 and S220 can be performed using a capacitance testing device for a through-hole test structure. Specifically, when performing S210, one end of the capacitance testing device is connected to the through-hole 120 to be tested, and the other end is connected to the first capacitor 131, thereby determining the first capacitance value of both. When performing S220, one end of the capacitance testing device is connected to the through-hole 120 to be tested, and the other end is connected to the second capacitor 132, thereby determining the second capacitance value of both.

[0053] After determining the first and second capacitance values, the offset value can be analyzed based on their correspondence with the position to achieve the aforementioned S230. In some embodiments, the analysis of the offset value can be based on the measurement value under standard conditions. That is, the parameters and capacitance values ​​under a certain condition (denoted as the standard condition) can be determined in advance, and then the capacitance value determined in P200 is compared with the standard value to determine the offset value when P200 is executed.

[0054] For example, the first standard capacitance value under standard conditions can be predetermined. and its corresponding first standard distance Therefore, when executing S230, the value of the first capacitor can be used as a reference. By combining the aforementioned capacitance calculation formula, the first current distance between the first capacitor and the through-hole to be measured when the first capacitance value is measured can be calculated. Similarly, based on the same operational logic, and based on the second capacitor value... Determine the second current distance This allows for the comprehensive determination of the offset value of the through hole to be measured (such as the change in the first distance and the change in the second distance).

[0055] As one possible implementation, after determining the aforementioned current distance and desired distance, the difference between the current distance and the standard distance can be further calculated (e.g., This allows us to determine the offset value of the through hole to be tested.

[0056] To simplify the calculation process, the desired location of the through-hole 120 to be tested is located at the midpoint between the first capacitor 131 and the second capacitor 132. That is, under the standard case (i.e., ideal state). Then the corresponding first standard capacitance value is the same as the second standard capacitance value. This is directly recorded as the standard capacitance value. .

[0057] Therefore, the offset of the via under test can be directly calculated at this point. That is, we can first determine the first capacitance ratio between the ideal capacitance value and the first capacitance value, and the second capacitance ratio between the ideal capacitance value and the second capacitance value. Then, based on the first capacitance ratio and the second capacitance ratio, we can determine the offset of the via under test.

[0058] Among them, the first capacitance ratio The second capacitor ratio .

[0059] Based on the capacitance calculation formula combined with the aforementioned first capacitance ratio and second capacitance ratio, the offset value of the through-hole to be measured is obtained. It can be calculated directly using the following formula: .

[0060] in, This refers to the distance between the through-hole to be tested and either the first or second capacitor when the through-hole is located at the midpoint between the first and second capacitors. Wherein, in the aforementioned... In the calculation results, the positive and negative values ​​can reflect the offset direction of the through hole to be measured, and the specific data can reflect its offset amount.

[0061] Specifically, considering that the calculation process involves The result can reflect the first current distance. Distance to the second current distance The difference. If it is positive, it indicates the first current distance. The larger the value, the more the through-hole 120 is shifted towards the second capacitor. A negative value indicates that the current distance to the second capacitor is greater. Larger, the through-hole 120 to be tested is offset towards the first capacitor component. (Subsequent...) The offset direction is similar to that in this case, so it will not be repeated here.

[0062] This application further discovers that during the actual fabrication of semiconductors, the semiconductor structure may expand or shrink during the manufacturing process. For example, the actual size of the via to be tested may differ from its designed size. As another example, the actual dimensions of the first and second capacitor components may differ from their fabricated dimensions.

[0063] In actual calculations, the aforementioned difference will affect the calculation process of the aforementioned offset value. To further illustrate the offset calculation of the through hole under test in this case, this application also provides a structural schematic diagram when the through hole test structure has offset and dimensional differences ( Figure 3 ).

[0064] like Figure 3 As shown, the through hole 120 to be tested has an offset. And the dimensional change 'a'. Where 'a' is the through-hole expansion parameter. The through-hole expansion parameter reflects the change in the size of one edge of the through-hole 120 relative to its design size after the dimensional change. Figure 3 The black filling part of the through hole 120 to be tested can reflect its original size (width is W), while its white filling part can reflect the part that has expanded this time (width is a). Therefore, the overall width of the through hole 120 after expansion is W + 2a.

[0065] Similar to the aforementioned through-hole 120, the dimensional changes of the first capacitor 131 and the second capacitor 132 are b (capacitor expansion parameter b). It is noted that the first capacitor 131 and the second capacitor 132 are manufactured using the same process, and therefore their dimensional changes are identical. Similar to the aforementioned through-hole 120, the black filler portion of the capacitor reflects its original size, while the white filler portion reflects the current expansion (width b).

[0066] It should be noted that the dimensional changes caused by semiconductor fabrication processes are generally manifested as overall expansion or contraction. The via expansion parameter can be determined as expansion (a is a positive value) or contraction (a is a negative value) based on its actual value.

[0067] In addition, to further calculate the capacitance, Figure 3 This also includes the protrusion height H of the second end 122 protruding from the second surface 112. Furthermore, the opening length (i.e., perpendicular to) the via forming the capacitor in the test via is also included. Figure 3 The length in the parallel inward / outward direction is denoted as L (not shown). Figure 3 See also Figure 4 , Figure 5 ).

[0068] Therefore, the capacitance value under standard conditions Meanwhile, considering the standard situation and d and the changed , The correlation between them ( ),but Figure 3 The first capacitance value in the equation can be interpreted as: The second capacitance value can be analyzed as follows: For more information on the opening length L in the formula, please refer to [link / reference needed]. Figure 4 Related descriptions.

[0069] Based on the above relationship, we can deduce that: Offset value of the through hole to be tested .

[0070] Furthermore, considering that the through-hole expansion parameter of the through-hole to be tested is generally small, when the opening length of the through-hole to be tested is large, the influence of the aforementioned through-hole expansion parameter of the through-hole to be tested can be ignored.

[0071] Then at this time, the offset value of the through hole to be measured This is consistent with the aforementioned case where expansion is not considered.

[0072] In summary, considering both scenarios, when taking into account the through-hole expansion parameters, the through-hole expansion parameters can be measured first (e.g., by scanning electron microscopy), thereby allowing for the determination of the parameters based on the aforementioned considerations. Calculate the offset value. Without considering expansion (e.g., the opening length of the through-hole being measured meets the neglect condition), it can be based on... Calculate the offset value.

[0073] The neglect condition refers to the condition that the through-hole expansion parameter does not affect the opening length of the through-hole under test. It is generally characterized by whether the opening length of the through-hole is significantly greater than its through-hole expansion parameter. For example, when the opening length L of the through-hole under test is greater than 10 times the through-hole expansion parameter a, the opening length of the through-hole under test satisfies the neglect condition.

[0074] Considering that a test hole corresponding to only one target through hole is generally difficult to meet the aforementioned requirements, the test hole in this application can be specially configured so that the test hole has a larger opening length in the extension direction of the capacitor.

[0075] At the implementation level, there are two methods to increase the opening length: ① Adjust the shape of the through hole to give it a larger opening length.

[0076] ② A larger opening length is formed by arranging multiple through holes side by side.

[0077] Therefore, in order to achieve a larger opening length, the aforementioned through hole to be tested can be characterized as an elongated through hole (corresponding to the adjustment shape) and / or multiple isolated through holes (corresponding to parallel arrangement).

[0078] To further illustrate the aforementioned two via configurations, this application also provides two top-view structural diagrams of the via test structure along the stacking direction. Among them, Figure 4 This can be a top view of a through-hole test structure with an elongated through-hole. Figure 5 This can be a top view of a through-hole test structure with multiple isolated through holes.

[0079] like Figure 4 As shown in the top view of the structure along the stacking direction, the elongated through-hole presents a rectangular structure, specifically having a long side extending along the direction of the capacitor and a short side perpendicular to the direction of the capacitor's extension. The length of the long side can be denoted as the hole length L, and the length of the short side can be denoted as the hole width W. Because the hole width W is perpendicular to the direction of the capacitor's extension, it does not affect the area S within the capacitor.

[0080] based on Figure 4 The top view shown illustrates that the elongated through-hole can be understood as an improved form of the through-hole, which is elongated in the extension direction of the capacitor component, resulting in a larger opening length. The longer side of the rectangular projection of the elongated through-hole is typically several times the shorter side, so that the opening length of the through-hole under test satisfies the neglect condition.

[0081] It should be noted that when the via to be tested is configured as an elongated via, the shape of the via to be tested will generally differ from that of the target via. Therefore, the corresponding parameters (such as the etching pattern) can be adjusted accordingly during fabrication, but the specific fabrication process is basically the same.

[0082] like Figure 5 As shown in the top view of the structure along the stacking direction, the connector 140 connects multiple isolated through holes distributed along the extension direction of the capacitor, so that the isolated through holes can be connected together during testing to measure the capacitance value, thus having a large opening length L.

[0083] In some embodiments, the shape of the aforementioned isolated via can be consistent with that of the target via (e.g., presented as...). Figure 5 (circular through-holes in the image) to further accurately reflect the parameters of the target through-hole.

[0084] It should be noted that the capacitance calculation for circular through holes and multiple circular through holes may differ slightly from the above. However, the actual calculation process involves comparing the measured value with the standard value and does not involve the analysis of specific parameters. Generally, the above process can be used as a reference.

[0085] Exemplary multilayer through-hole test structure and its test method: The foregoing has described in detail the specific structure and testing process of a single-layer through-hole test structure. To further describe the through-hole test structures corresponding to target through-holes in different layered structures and multi-layer through-hole test structures, this application also provides a schematic diagram of a multi-layer through-hole test structure (…). Figure 6 ).

[0086] like Figure 6 As shown, the multilayer via test structure can measure the metal lines between transistors and metal layers, as well as the vias between metal layers. Figure 6 The dashed box in the diagram can reflect the through-hole test structure of a target through-hole.

[0087] Specifically, for the metal line (CT line) between the transistor and the metal layer, the first and second capacitors in the through-hole test structure are formed based on the polysilicon structure (poly on the substrate, such as control gate, floating gate, etc.) fabrication process of the semiconductor device. The connectors are formed based on the fabrication process of the first metal layer of the semiconductor device. For the via between metal layers, the first and second capacitors in the through-hole test structure are formed based on the fabrication process of the lower metal layer (along the stacking direction of the semiconductor device), and the connectors of the through-hole test structure can be formed based on the fabrication process of the upper metal layer.

[0088] In some embodiments, to further improve integration, some structures in adjacent via test structures can be reused. Optionally, for adjacent first and second test structures in a multilayer via test structure, the connector of the first test structure can be reused as a first or second capacitor of the second test structure. For example, the connector of the metal wire can also serve as a capacitor for the via between the first and second metal layers.

[0089] Unexpected technical effects: In summary, the test structure and test method for the semiconductor device provided in this application have achieved the following unexpected effects: ①This application creatively utilizes the property of a through-hole penetrating the dielectric layer, and uses its protrusion relative to the dielectric layer to construct a capacitor for measuring its offset. The overall structure is simple, the test is convenient, and the hole offset can be measured and calculated.

[0090] ② Through-hole test structures can form hierarchical structures, allowing measurement of the offset of through-holes between different layers in a semiconductor device. Each through-hole test structure can also reuse adjacent structures to improve the overall integration of the test structure.

[0091] ③ In addition to the traditional vias between metal layers, this application can also creatively configure the polycrystalline silicon structure deposited on the substrate as a capacitor, thereby measuring the CT lines formed in the front-end process, breaking through the testing limitations of vias in the traditional WAT technology.

[0092] ④ This application takes into account the expansion caused by the manufacturing process when measuring the through hole offset, and correspondingly analyzes a suitable offset calculation formula so that the test results are not affected by the changes in the size of the through hole and the metal interconnect.

[0093] ⑤ This application also adjusts the test structure based on the dimensional expansion caused by the process, so that the test hole has a larger opening length, so that the opening length is much larger than the expansion parameter, satisfying the corresponding neglect condition, thereby simplifying the test process (no need to measure the expansion parameter with scanning electron microscope) and the test results.

[0094] The embodiments of the present invention disclosed above are merely illustrative of the invention. These embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A test structure for a semiconductor device, characterized in that, The test structure includes at least one through-hole test structure disposed in the dicing groove of the semiconductor device, the through-hole test structure comprising: Dielectric layer; At least one via under test (TUT) is disposed within the dielectric layer and connecting the first and second surfaces of the dielectric layer, wherein the second end of the TUT protrudes relative to the second surface, wherein the TUT and a target via in the semiconductor device are formed using the same fabrication process, and the via is used to characterize the process parameters of the target via; the via expansion parameter of the TUT reflects the dimensional expansion effect of the target via caused by the fabrication process, and the via expansion parameter indicates the change of the TUT relative to the design size; and At least one capacitor assembly disposed on the second surface, wherein the capacitor assembly includes a first capacitor and a second capacitor respectively disposed on both sides of the second end of the at least one through hole to be tested, and the second end of the through hole to be tested has a gap with the first capacitor and the second capacitor respectively and is located between the first capacitor and the second capacitor; The first capacitance value between the first capacitor and the through-hole to be tested reflects the distance between the through-hole to be tested and the first capacitor, and the second capacitance value between the second capacitor and the through-hole to be tested reflects the distance between the through-hole to be tested and the second capacitor; wherein, the change in the first capacitance value and the change in the second capacitance value are used to characterize the change in distance between the through-hole to be tested and the corresponding capacitor, and the change in distance corresponds to the offset of the through-hole to be tested and the effect of the through-hole expansion.

2. The test structure according to claim 1, characterized in that, The through-hole test structure further includes at least one connector disposed on the first surface, wherein the connector contacts the first end of the through-hole to be tested and is electrically connected to the at least one through-hole to be tested through the first end.

3. The test structure according to claim 2, characterized in that, The target via is configured as a metal line between a transistor and a metal layer in the semiconductor device. The first capacitor and the second capacitor are formed based on the polysilicon structure fabrication process of the semiconductor device, and the connector is formed based on the first metal layer fabrication process of the semiconductor device.

4. The test structure according to claim 2, characterized in that, The at least one layer of through-hole test structure includes an adjacent first test structure and a second test structure; The connector of the first test structure is reused as the first capacitor or the second capacitor of the second test structure.

5. The test structure according to claim 2, characterized in that, The through-hole test structure also includes: A connection test key electrically connected to the connector; The first capacitance test key is electrically connected to the first capacitor; and A second capacitor test key that is electrically connected to the second capacitor.

6. The test structure according to claim 1, characterized in that, The at least one through-hole to be tested includes an elongated through-hole and / or multiple isolated through-holes arranged along the extension direction of the first capacitor, wherein the multiple isolated through-holes are connected to the same connector.

7. A method for testing semiconductor devices, characterized in that, The testing method is applied to the test structure of the semiconductor device according to any one of claims 1 to 6. For the through-hole test structure in the test structure, the testing method includes: Determine the first standard capacitance value when the test hole and the first capacitor are at a first standard distance in the test structure under standard conditions, and the second standard capacitance value when the test hole and the second capacitor are at a second standard distance; The first capacitance value between the through hole to be tested and the first capacitor in the test structure is detected, wherein the first capacitance value reflects the distance between the first capacitor and the through hole to be tested; The second capacitance value between the through hole to be tested and the second capacitor in the test structure is detected, wherein the second capacitance value reflects the distance between the second capacitor and the through hole to be tested; Measure the through-hole expansion parameters of the through-hole to be tested; The offset value of the through hole to be tested is determined based on the through hole expansion parameters, the first capacitance value, the second capacitance value, the first standard capacitance value, and the second standard capacitance value.

8. The test method according to claim 7, characterized in that, When the through hole to be tested is located at the midpoint between the first capacitor and the second capacitor under the standard condition, the first standard distance and the second standard distance are equal, and the first standard capacitance value and the second standard capacitance value are equal and recorded as the ideal capacitance value; The step of determining the offset value of the through-hole to be tested based on the through-hole expansion parameter, the first capacitance value, the second capacitance value, the first standard capacitance value, and the second standard capacitance value includes: Determine a first capacitance ratio between the ideal capacitance value and the first capacitance value, and a second capacitance ratio between the ideal capacitance value and the second capacitance value; The offset value of the test hole is determined based on the through-hole expansion parameters, the first capacitance ratio, and the second capacitance ratio.

9. The test method according to claim 8, characterized in that, The step of determining the offset value of the test hole based on the via expansion parameter, the first capacitance ratio, and the second capacitance ratio. ； in, The offset value of the through hole to be tested; The distance between the through hole to be tested and the first capacitor or the second capacitor when the through hole to be tested is located at the midpoint between the first capacitor and the second capacitor; The opening length of the through hole to be measured; The through-hole expansion parameter is the through-hole diameter of the through-hole to be tested; This is the first capacitance ratio; This is the second capacitance ratio; The ideal capacitance value; The first capacitance value; This is the second capacitance value.

10. The test method according to claim 9, characterized in that, In response to the condition that the opening length of the through-hole to be tested meets the neglect condition, the step of determining the offset value of the through-hole to be tested based on the through-hole expansion parameter, the first capacitance ratio, and the second capacitance ratio is calculated according to the following formula: ； The neglect condition is whether the opening length of the through-hole to be tested is much greater than the determination condition of the through-hole expansion parameter, so that the neglect condition is met that the aforementioned through-hole expansion parameter will not affect the opening length of the through-hole to be tested, and thus... Simplified to 1.

Images