Pulse per second time difference measuring system and method based on field programmable gate array
By generating a clock signal with opposite phase and sampling on both sides of a double data rate trigger through the clock management module in the field programmable gate array, and combining coarse time counting with fine time interpolation, the problem of difficulty in balancing accuracy and range in existing second pulse time difference measurement methods is solved, and high-precision and wide-range measurement is achieved.
Patent Information
- Application Number
- CN202610198826.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-11
- Publication Date
- 2026-05-01
AI Technical Summary
Existing methods for measuring the time difference of a second pulse cannot achieve both high measurement accuracy and a wide measurement range. They typically improve accuracy by increasing the clock frequency, which in turn reduces the measurement range.
The clock management module in the field-programmable gate array generates two clock signals with opposite phases. Double-edge sampling is performed within the same clock cycle through a double data rate trigger. Combined with coarse time counting and fine time interpolation, high-precision and wide-range measurement is achieved.
Without changing the clock cycle, the measurement accuracy was improved and the measurement range was expanded, achieving a minimum resolution time interval of half a clock cycle, thus balancing high accuracy and wide range measurement.
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Figure CN121956477A_ABST
Abstract
Description
A Second Pulse Time Difference Measurement System and Method Based on Field Programmable Gate Array (FPGA) Technical Field
[0001] This invention relates to the field of time measurement technology, specifically to a second pulse time difference measurement system and method based on a field-programmable gate array (FPGA). Background Technology
[0002] 1-Pulse-Per-Second (1PPS) time difference measurement refers to measuring the time interval between the rising (or falling) edges of two 1PPS signals. Essentially, it compares the time reference deviation between the two 1PPS signals and is a core testing and calibration method in the field of high-precision time synchronization. The key to the 1PPS time difference measurement process is to identify the characteristic edges (such as the rising edge) of the 1PPS signal and determine the time synchronization accuracy of the two 1PPS signal sources by calculating the time difference between the arrival of the two edges at the same detection device.
[0003] Currently, the second pulse time difference measurement method typically uses reference clock pulses to fill the time interval under test and counts them. Essentially, it uses clock pulses as a scale to measure the interval under test; that is, how many complete clock pulses are contained within the time interval under test, and the product of the pulse count and the clock period is used as the measurement result. It is evident that this method can only count complete clock pulses, and the minimum resolvable time interval is a single clock period. To improve measurement accuracy, the clock period needs to be reduced (using a high-frequency clock). Since the measurement range is determined by the product of the counter's maximum count value (counter bit width) and the clock period, improving measurement accuracy will result in a reduction in the measurement range.
[0004] In summary, existing second pulse measurement methods suffer from the problem of not being able to simultaneously achieve high measurement accuracy and a wide measurement range. Summary of the Invention
[0005] The purpose of this invention is to provide a second pulse time difference measurement system and method based on field-programmable gate array (FPGA). By using a double data rate trigger to sample the second pulse twice within the same clock cycle, the measurement accuracy is improved without changing the clock cycle. Furthermore, based on coarse time counting and fine time interpolation, a wide range of measurements is achieved, solving the problem that existing second pulse measurement methods cannot simultaneously achieve high measurement accuracy and a wide measurement range.
[0006] This invention is achieved through the following technical solution:
[0007] The first aspect of this application provides a second pulse time difference measurement system based on a field-programmable gate array (FPGA), including an FPGA and a clock management module, a sampling model, a timestamp generation module, and a time difference calculation and output module integrated within the FPGA;
[0008] The clock management module is used to generate two clock signals with opposite phases and input the two clock signals to the rising edge sampling port and falling edge sampling port of the double data rate trigger, respectively.
[0009] The sampling model is based on the double data rate trigger sampling the input second pulse at both the rising and falling edges of the same clock cycle to obtain the sampled signal of the second pulse.
[0010] The timestamp generation module is used to determine a coarse count value of the sampled signal using a clock counter when an edge signal appears in the sampled signal; to determine a fine time interpolation value for quantizing the phase difference between the edge signal and the nearest clock edge using a pre-built delay chain; and to concatenate the coarse count value and the fine time interpolation value into a timestamp; the delay chain is composed of cascaded delay units in the field programmable gate array.
[0011] The time difference calculation output module is used to calculate the difference between the two generated timestamps to determine the time difference measurement result; the two timestamps are a first timestamp generated based on the first second pulse of the input, and a second timestamp generated based on the second second pulse of the input.
[0012] In one feasible implementation, the system further includes a clock calibration engine, which is used for:
[0013] When the calibration trigger condition is met, the error data between the measured timestamp and the reference value is determined;
[0014] When the error data exceeds a preset threshold, a phase adjustment signal is sent to the clock management module to calibrate the clock phase.
[0015] In one feasible implementation, the system further includes a signal conditioning module for converting the raw second pulse into a second pulse adapted to the field-programmable gate array.
[0016] A second aspect of this application provides a method for measuring the second pulse time difference based on a field-programmable gate array (FPGA), the method comprising:
[0017] Two clock signals with opposite phases are generated by the clock management module in the field programmable gate array, and the two clock signals are input to the rising edge sampling port and falling edge sampling port of the double data rate trigger.
[0018] The double data rate trigger samples the input second pulse on both the rising and falling edges of the same clock cycle to obtain the sampled signal of the second pulse;
[0019] When an edge signal appears in the sampled signal, a clock counter is used to determine the coarse count value of the sampled signal; and a pre-built delay chain is used to determine the fine time interpolation of the phase difference between the quantized edge signal and the nearest clock edge; the delay chain is composed of cascaded delay units in the field programmable gate array.
[0020] The coarse count value and the fine time interpolation are concatenated to form a timestamp;
[0021] The difference between the two generated timestamps is calculated to determine the time difference measurement result; the two timestamps are a first timestamp generated based on the first second pulse of the input, and a second timestamp generated based on the second second pulse of the input.
[0022] In one feasible implementation, the method further includes:
[0023] When the calibration trigger condition is met, the error data between the measured timestamp and the reference value is determined;
[0024] When the error data exceeds a preset threshold, a phase adjustment signal is sent to the clock management module to calibrate the clock phase.
[0025] In one feasible implementation, the calibration triggering conditions include powering on the field-programmable gate array (FPGA), the temperature of the FPGA exceeding a threshold, and reaching the calibration cycle.
[0026] In one feasible implementation, the method further includes:
[0027] The time difference measurement results and calibration status are uploaded to the host computer; the calibration status represents the progress of the clock phase calibration process.
[0028] In one feasible implementation, the coarse count value and the fine time interpolation are concatenated to form a timestamp, including:
[0029] The product of the coarse count value and the clock period is used as the coarse time value;
[0030] The product of the fine-time interpolation and the resolution of the delay unit is used as the fine-time value; the resolution of the delay unit is the time delay increment of the delay unit.
[0031] The sum of the coarse time value and the fine time value serves as a timestamp.
[0032] A third aspect of this application provides an electronic device, including: a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the above-described method.
[0033] A fourth aspect of this application provides a storage medium, comprising: storing a program or instructions on the storage medium, wherein the program or instructions, when executed by a processor, implement the steps of the above-described method.
[0034] Compared with the prior art, the present invention has the following advantages and beneficial effects:
[0035] This embodiment generates two clock signals with opposite phases, one for the rising edge sampling port and the other for the falling edge sampling port of a double data rate trigger (DFR), through a clock management module within the field-programmable gate array (FPGA). This allows the DFR trigger to sample the second pulse twice within the same clock cycle, resulting in a minimum resolvable time interval of half a clock cycle. This improves measurement accuracy without changing the clock cycle. Simultaneously, it employs a timestamp calculation method combining coarse time counting and fine time interpolation. Since coarse time counting uses the aforementioned low-frequency clock signal, it can cover a wide measurement range (second-level range), achieving a broad measurement range. Furthermore, fine time interpolation further quantizes the phase difference (less than a sub-cycle of one clock cycle) between the edge signal and the nearest clock edge through a preset delay chain, improving measurement accuracy while decoupling from the clock signal. In summary, this embodiment achieves both high measurement accuracy and a wide measurement range without excessively consuming FPGA resources. Attached Figure Description
[0036] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:
[0037] Figure 1 is a schematic diagram of a second pulse time difference measurement system based on a field-programmable gate array provided in an embodiment of this application;
[0038] Figure 2 is a schematic diagram of the topology of a second pulse time difference measurement system based on a field-programmable gate array provided in an embodiment of this application;
[0039] Figure 3 is a schematic diagram of the sampling principle of a sampling module of a second pulse time difference measurement system based on a field-programmable gate array provided in an embodiment of this application;
[0040] Figure 4 is a schematic diagram illustrating the functional implementation principle of a timestamp generation module in a second pulse time difference measurement system based on a field-programmable gate array provided in an embodiment of this application.
[0041] Figure 5 is a schematic diagram illustrating the implementation principle of a clock calibration engine for a second pulse time difference measurement system based on a field-programmable gate array provided in an embodiment of this application.
[0042] Figure 6 is a flowchart illustrating a second pulse time difference measurement method based on a field-programmable gate array provided in an embodiment of this application;
[0043] Figure 7 is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation
[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are for explanation only and are not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this application.
[0045] As will be known to those skilled in the art, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0046] The terms “comprising” and “having”, and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, product, or apparatus.
[0047] Example 1:
[0048] Embodiment 1 of this application provides a second pulse time difference measurement system based on field-programmable gate array (FPGA) to solve the problem that existing second pulse measurement methods cannot simultaneously achieve high measurement accuracy and wide measurement range.
[0049] The specific structure of the system is shown in Figure 1, which includes a field-programmable gate array (FPGA) 1 and a clock management module 11, a sampling model 12, a timestamp generation module 13 and a time difference calculation and output module 14 integrated in the FPGA 1.
[0050] As shown in Figure 2, the clock management module 11 is used to generate two clock signals with opposite phases and input the two clock signals to the rising edge sampling port and falling edge sampling port of the Double Data Rate (DDR) trigger, respectively.
[0051] The clock management module generates a pair of clock signals with opposite phases, namely a positive clock and an inverted clock, from the PLL (Phase-Locked Loop) or DCM (Digital Clock Manager) within the FPGA, which serve as the reference clock for the sampling module.
[0052] The clock management module generates a positive clock (e.g., 200MHz) and an inverted clock, which are output to the rising edge sampling port and falling edge sampling port of the double data rate trigger, respectively.
[0053] Sampling model 12, based on the double data rate trigger, samples the input second pulse at both the rising and falling edges of the same clock cycle to obtain the sampled signal of the second pulse.
[0054] As shown in Figure 3, the working principle of the sampling module includes: acquiring the externally input second pulse signal, which is connected to the DDR pin of the FPGA, i.e., connected to the DDR flip-flop. In addition, the DDR flip-flop also receives the positive and negative clocks generated by the clock management module 11 as sampling time references; for the acquired rising edge sampling data and falling edge sampling data, the DDR flip-flop captures the transition time signal based on edge detection and data synchronization logic, i.e., obtains the second pulse sampling signal.
[0055] Since the clock management module 11 generates a pair of clock signals with opposite phases, when the edge of the second pulse signal arrives, the DDR flip-flop samples once at each of the two edges of the same clock cycle. For a 200MHz clock signal, this is equivalent to increasing the sampling rate to 400MHz and improving the time resolution from 5ns to 2.5ns.
[0056] In this embodiment, the DDR trigger can be implemented using the DDR register in the FPGA's I / O (input / output) block (such as Xilinx's IDDR or Altera's DDIO).
[0057] In one feasible implementation, to ensure the stability of the second pulse signal input to the FPGA, the measurement system of this embodiment also includes a signal conditioning module located outside the FPGA. This signal conditioning module is used to convert the raw second pulse into a second pulse adapted to the field-programmable gate array (FPGA).
[0058] The signal conditioning module includes a level shifter and a Schmitt trigger, converting the raw second pulse into a digital signal that can be processed internally by the FPGA. Specifically, the level shifter (such as SN74LVC1T45) converts the LVTTL (Low-Voltage Transistor-Transistor Logic) / LVCMOS (Low-Voltage Complementary Metal-Oxide-Semiconductor) level of the raw second pulse signal to a voltage supported by the FPGA I / O (such as 1.8V), matching the interface voltage standard. The distorted waveform is corrected into a standard square wave by a Schmitt trigger (such as 74HC14). An RC (Resistor Capacitor) low-pass filter circuit can be used to suppress high-frequency noise, making the signal edges steeper and avoiding false triggering.
[0059] Additionally, here is an example of the core code logic for DDR sampling:
[0060] / / Example: IDDR sampling module implemented in Verilog;
[0061] module DDR_1PPS_Capture (
[0062] input clk_200M, / / 200MHz master clock;
[0063] input clk_200M_inv, / / 200MHz inverting clock;
[0064] input pps_signal, / / 1PPS input;
[0065] output reg pps_rise_edge_detected
[0066] );
[0067] reg pps_rise_ff1, pps_rise_ff2; / / Rising edge sampling register;
[0068] reg pps_fall_ff1, pps_fall_ff2; / / Falling edge sampling register;
[0069] always @(posedge clk_200M) pps_rise_ff1 <= pps_signal;
[0070] always @(posedge clk_200M_inv) pps_fall_ff1 <= pps_signal;
[0071] / / Edge detection: triggered by any edge transition;
[0072] assign pps_edge_detected = (pps_rise_ff1 && !pps_rise_ff2) ||
[0073] (pps_fall_ff1 && !pps_fall_ff2);
[0074] endmodule.
[0075] It should be noted that traditional sampling methods all use single-edge sampling, and the resolution is limited by the clock cycle. This embodiment uses double-edge sampling of DDR flip-flops to double the resolution without increasing the clock frequency, significantly reducing the power consumption and signal integrity challenges brought by high-frequency clocks.
[0076] The timestamp generation module 13 is used to determine a coarse count value of the sampled signal using a clock counter when an edge signal appears in the sampled signal; to determine a fine time interpolation value for quantizing the phase difference between the edge signal and the nearest clock edge using a pre-built delay chain; and to concatenate the coarse count value and the fine time interpolation value into a timestamp; the delay chain is composed of cascaded delay units in the field programmable gate array.
[0077] The edge signal (or transition moment signal) in the sampled signal is the trigger of the timestamp generation module.
[0078] The timestamp generation module 13 includes three functional units: coarse time counting, fine time interpolation, and timestamp fusion.
[0079] As shown in Figure 4, coarse time counting uses a 32-64 bit counter driven by a low-frequency clock (e.g., 10-100MHz) to measure time ranges in the second range. Specifically, a clock counter is used to determine the coarse count value of the sampled signal; that is, whenever the edge of the second pulse is detected, the current value of the low-frequency counter (e.g., a 100MHz clock with a resolution of 10ns) is latched, and the product of the coarse count value and the clock period is used as the coarse time value.
[0080] Fine time difference analysis, based on the FPGA's internal delay chain or time-to-digital converter (TDC), resolves the time details of sub-clock cycles (the phase difference between the edge signal and the nearest clock edge).
[0081] The delay units inside the FPGA (such as Xilinx IDELAYE2 and Altera LAB) support configuring tiny delay increments (i.e., delay unit resolution, typically 10ps-50ps / level) via registers. Multiple delay units are cascaded to form a delay chain, covering the entire sub-cycle range (e.g., 0-2.5ns). In this embodiment, the sub-clock cycle phase difference is quantized by pre-configuring the delay chain.
[0082] The delay chain can be constructed as follows: using the reference clock of the DDR flip-flop (e.g., 200MHz, period 5ns) as a reference, the internal delay units of the FPGA are cascaded into an N-level delay chain (N = clock period / delay unit resolution, e.g., 2.5ns / 50ps = 50 levels), ensuring that the total delay of the delay chain is greater than or equal to the maximum range of a single sub-cycle.
[0083] When the transition signal of the second pulse arrives, the delay chain is triggered to start transmitting the signal. The signal generates a time delay increment (e.g., 50ps) as it passes through each unit in the delay chain. The output terminals of all delay chain terminals are sampled simultaneously using the edge of the reference clock (e.g., rising edge) to record the output state (high level / low level) of each delay unit. Since the transition signal is transmitted step by step in the delay chain, the sampled signal will form a binary code of "high for the previous stage and low for the next stage" (e.g., "11110000").
[0084] The transition boundary between "high level" and "low level" in the binary code is identified by the encoding logic (such as a priority encoder). The delay level corresponding to this boundary is the "number of stages in which the 1PPS transition signal is transmitted in the delay chain", which is used as a fine time interpolation.
[0085] Combined with the delay unit resolution (i.e., the time delay increment, such as 50 ps), calculate the sub-cycle phase difference: fine time value = fine time interpolation × delay unit resolution.
[0086] The sum of the coarse and fine time values is used as the timestamp of the measurement.
[0087] By combining coarse time counting with fine time interpolation, a second-level range can be achieved using a low-frequency counter, while nanosecond or even picosecond-level resolution can be achieved through fine interpolation, thus resolving the contradiction between measurement range and measurement accuracy.
[0088] The time difference calculation output module 14 is used to calculate the difference between the two generated timestamps to determine the time difference measurement result; the two timestamps are a first timestamp generated based on the input first second pulse and a second timestamp generated based on the input second second pulse.
[0089] The time difference calculation output module includes a subtractor and a FIFO (First-In-First-Out) buffer.
[0090] The subtractor uses a hardware subtractor within the FPGA to calculate the difference in timestamps corresponding to two second pulses. One of the two second pulses can be a reference second pulse.
[0091] The FIFO buffer is a dual-clock domain FIFO that coordinates the clock difference between the subtractor and the output interface (UART (Universal Asynchronous Receiver / Transmitter, also known as "serial port"), Ethernet, or USB (Universal Serial Bus) 2.0 / 3.0 physical layer controller).
[0092] To ensure the long-term stable operation of the measurement system, the system in this embodiment also includes a clock calibration engine. The clock calibration engine is used to: determine the error data between the measured timestamp and the reference value when the calibration trigger condition is met; and send a phase adjustment signal to the clock management module when the error data exceeds a preset threshold to calibrate the clock phase.
[0093] The clock calibration engine includes an error measurement unit, a calibration control state machine, and a calibration sequence generator.
[0094] The error measurement unit includes a hardware comparator and a difference calculator, which are used to compare the deviation between the timestamp generated by the timestamp generation module and the reference clock source, and output error data.
[0095] The reference clock source uses a high-stability temperature-compensated crystal oscillator (TCXO) or an oven-controlled crystal oscillator (OCXO) to provide a low-jitter clock.
[0096] The calibration control state machine, implemented based on FPGA hardware logic, is the control center of the entire calibration process, scheduling the orderly operation of each module; and it has a built-in calibration algorithm: using the binary search method or gradient descent algorithm, it generates PLL phase adjustment instructions based on error data.
[0097] Calibration sequence generator: Composed of FPGA programmable logic, it is used to generate standard calibration pulses with known time intervals (such as 1ns or 10ns fixed delay pulses) as a reference for error measurement.
[0098] Calibration triggering conditions include powering on the field-programmable gate array (FPGA), the temperature of the FPGA exceeding a threshold, and reaching the calibration cycle.
[0099] As shown in Figure 5, the calibration control state machine is normally in the IDLE state, initializing the PLL phase control word (default initial value), calibration threshold (e.g., error allowable ±50ps), timing calibration cycle (e.g., 1 minute), and temperature trigger threshold (e.g., ±5℃).
[0100] When the calibration trigger condition is met, the calibration control state machine switches from the IDLE state to the MEASURE state and sends a start command to the calibration sequence generator. The calibration sequence generator generates a standard calibration pulse with preset parameters: the pulse time interval is a known fixed value (such as 1ns, 10ns, denoted as T_ref). This pulse is directly injected into the sampling module to ensure that the measurement environment is consistent with the actual working scenario.
[0101] The error measurement unit measures the error data between the timestamp generated by the timestamp generation module and the reference clock source. When the error data exceeds a preset threshold, an adjustment signal is sent to the calibration control state machine. The calibration control state machine switches to the ADJUST state and calls the calibration algorithm: based on the error data and the current PLL phase control word, parameter optimization is initiated.
[0102] If the binary method is used: take the current phase control word as the midpoint, define the phase adjustment range (e.g., ±100ps), and adjust the PLL phase by taking the midpoint each time to gradually reduce the error range;
[0103] If gradient descent is used: generate a phase adjustment command with a gradient step size (e.g., 10 ps / step) based on the error direction;
[0104] The phase adjustment command is written to the phase offset register of the PLL through the FPGA internal configuration bus to dynamically fine-tune the phase of the sampling clock (200MHz main clock and inverted clock for DDR sampling), thereby correcting the delay deviation of the system measurement link (such as compensating for the temperature drift of the fine interpolation delay unit).
[0105] After phase adjustment is completed, the calibration control state machine switches to the VERIFY state: the calibration sequence generator injects the same standard calibration pulse again, the system repeats the measurement process, and obtains new error data;
[0106] If the new error data is not greater than the threshold, the verification status controller switches to the LOCK state: the current PLL phase control word is fixed to the FPGA non-volatile register (or dynamic cache) to avoid loss when power is off, and the status information such as calibration time, temperature and error value is recorded at the same time.
[0107] If the new error data is still greater than the threshold, return to the ADJUST state and repeat the "adjust-verify" process (set the number of iterations to avoid infinite loops) until the error meets the standard; if the number of iterations is exhausted and the standard is still not met, trigger an alarm signal (uploaded to the host computer through the output module).
[0108] After calibration is complete, the calibration status controller returns to the IDLE state, continues to monitor trigger conditions, and waits for the next calibration.
[0109] A closed-loop adaptive calibration mechanism is introduced to correct the clock phase in real time through hardware reconfiguration, thereby overcoming the PVT (process, voltage, temperature) drift problem in the FPGA delay path and ensuring long-term stability.
[0110] In one feasible implementation, the time difference calculation output module of this embodiment is also used to: upload the time difference measurement result and calibration status to the host computer; the calibration status represents the execution progress of the calibration clock phase process, that is, the status of the calibration status controller.
[0111] It should also be noted that the FPGA in this embodiment is a field-programmable gate array (FPGA) supporting DDR I / O (such as Xilinx Artix-7 or later, or Altera Cyclone IV or later); the reference clock source used can be a 100-500MHz low-jitter crystal oscillator (phase noise <-100dBc / Hz@1kHz); the achieved measurement range can be from 1ns to 10 seconds (determined by the counter bit width); the measurement accuracy can reach: ±500ps at room temperature, ±1ns across the entire temperature range (-40℃~+85℃) (after calibration); resource consumption: typically less than 1000 LUTs (Look-Up Tables, which serve as the core programmable logic units inside the FPGA and are the basic carrier for implementing various digital logic functions of the solution), 2 PLLs, and 1 DSP (Digital Signal Processor) block (based on Xilinx xc7a35t evaluation). In addition, the sampling module, timestamp generation module, clock management module, time difference calculation and output module, and clock calibration engine in this embodiment are all implemented on the FPGA chip, reducing external components and thus reducing costs.
[0112] This embodiment generates two clock signals with opposite phases, one for the rising edge sampling port and the other for the falling edge sampling port of the double data rate trigger (DFR), through the clock management module within the field-programmable gate array (FPGA). This allows the DFR trigger to sample the second pulse twice within the same clock cycle, resulting in a minimum resolvable time interval of half a clock cycle. This improves measurement accuracy without changing the clock cycle. Simultaneously, it employs a timestamp calculation method combining coarse time counting and fine time interpolation. Since coarse time counting uses the aforementioned low-frequency clock signal, it can cover a wide measurement range (second-level range), achieving a broad measurement range. Furthermore, fine time interpolation further quantizes the phase difference (less than a sub-cycle of one clock cycle) between the edge signal and the nearest clock edge through a preset delay chain, improving measurement accuracy while decoupling from the clock signal. In summary, this embodiment achieves both high measurement accuracy and a wide measurement range without excessively consuming FPGA resources.
[0113] Example 2:
[0114] To address the problem that existing second pulse measurement methods cannot simultaneously achieve high measurement accuracy and a wide measurement range, this application also provides a second pulse time difference measurement method based on a field-programmable gate array (FPGA), drawing on the same inventive concept as Embodiment 1.
[0115] The execution entity of this method can be a field-programmable gate array (FPGA).
[0116] Furthermore, the embodiments of this application do not limit the execution order of different steps. When using the method provided in the embodiments of this application, the execution order of different steps can be adjusted according to actual needs.
[0117] Figure 6 shows a flowchart of a second pulse time difference measurement method based on a field-programmable gate array provided in this application embodiment, including the following steps 61 to 65:
[0118] Step 61: Use two clock signals with opposite phases generated by the clock management module in the field programmable gate array, and input the two clock signals to the rising edge sampling port and falling edge sampling port of the double data rate trigger.
[0119] Step 62: The double data rate trigger samples the input second pulse on both the rising and falling edges of the same clock cycle to obtain the sampled signal of the second pulse.
[0120] Step 63: When an edge signal appears in the sampled signal, a clock counter is used to determine the coarse count value of the sampled signal; and a pre-built delay chain is used to determine the fine time interpolation of the phase difference between the quantized edge signal and the nearest clock edge; the delay chain is composed of cascaded delay units in the field programmable gate array.
[0121] Step 64: Concatenate the coarse count value and the fine time interpolation to form a timestamp.
[0122] The product of the coarse count value and the clock period is used as the coarse time value;
[0123] The product of the fine-time interpolation and the resolution of the delay unit is used as the fine-time value; the resolution of the delay unit is the time delay increment of the delay unit.
[0124] The sum of the coarse time value and the fine time value serves as a timestamp.
[0125] Step 65: Calculate the difference between the two generated timestamps to determine the time difference measurement result; the two timestamps are a first timestamp generated based on the first second pulse of the input, and a second timestamp generated based on the second second pulse of the input.
[0126] In one feasible implementation, to ensure the long-term stability of the measurement process, this embodiment further includes calibrating the clock signal, specifically including: when the calibration trigger condition is met, determining the error data between the measured timestamp and the reference value; when the error data exceeds a preset threshold, sending a phase adjustment signal to the clock management module to calibrate the clock phase.
[0127] The calibration triggering conditions include powering on the field-programmable gate array (FPGA), the temperature of the FPGA exceeding a threshold, and reaching the calibration cycle.
[0128] In addition, this embodiment also includes uploading the time difference measurement results and calibration status to the host computer; the calibration status represents the execution progress of the calibration clock phase process.
[0129] This embodiment generates two clock signals with opposite phases, one for the rising edge sampling port and the other for the falling edge sampling port of a double data rate trigger (DFR), through a clock management module within the field-programmable gate array (FPGA). This allows the DFR trigger to sample the second pulse twice within the same clock cycle, resulting in a minimum resolvable time interval of half a clock cycle. This improves measurement accuracy without changing the clock cycle. Simultaneously, it employs a timestamp calculation method combining coarse time counting and fine time interpolation. Since coarse time counting uses the aforementioned low-frequency clock signal, it can cover a wide measurement range (second-level range), achieving a broad measurement range. Furthermore, fine time interpolation further quantizes the phase difference (less than a sub-cycle of one clock cycle) between the edge signal and the nearest clock edge through a preset delay chain, improving measurement accuracy while decoupling from the clock signal. In summary, this embodiment achieves both high measurement accuracy and a wide measurement range without excessively consuming FPGA resources.
[0130] Based on the same inventive concept as the foregoing embodiments of this application, this application also provides a computing device.
[0131] As shown in Figure 7, the computing device includes a memory 71 and a processor 72. The memory 71 can be configured to store various other data to support operation on the electronic device. Examples of this data include instructions for any application or method used to operate on the electronic device. The memory 71 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0132] The processor 72, coupled to the memory 71, is used to execute the computer program stored in the memory 71 to perform a second pulse time difference measurement method based on a field-programmable gate array as described in the foregoing embodiments.
[0133] When processor 72 executes the computer program to perform a second pulse time difference measurement method based on a field-programmable gate array (FPGA), the clock management module within the FPGA generates two clock signals with opposite phases, one for the rising edge sampling port and the other for the falling edge sampling port of the double data rate trigger. This allows the double data rate trigger to sample the second pulse twice within the same clock cycle, resulting in a minimum resolution time interval of half a clock cycle. This improves measurement accuracy without changing the clock cycle. Simultaneously, the use of a timestamp calculation method combining coarse time counting and fine time interpolation allows for wider measurement ranges. Since coarse time counting uses the aforementioned low-frequency clock signal, it covers a broad measurement range (second-level range). Furthermore, fine time interpolation further quantizes the phase difference (less than a sub-cycle of one clock cycle) between the edge signal and the nearest clock edge through a preset delay chain, improving measurement accuracy while decoupling from the clock signal. In summary, this embodiment achieves both high measurement accuracy and a wide measurement range without excessively consuming FPGA resources.
[0134] When the processor 72 executes the computer program in the memory 71, in addition to the functions described above, it can also perform other functions, as detailed in the descriptions of the preceding embodiments.
[0135] Furthermore, as shown in Figure 7, the computing device also includes other components such as a display 74, a communication component 73, a power supply component 75, and an audio component 76. Figure 7 only schematically shows some of the components and does not imply that the computing device includes only the components shown in Figure 7.
[0136] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a computer, can implement the methods provided in the above embodiments.
[0137] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.
[0139] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A second pulse time difference measurement system based on a field-programmable gate array (FPGA), characterized in that, It includes a field-programmable gate array (FPGA) and a clock management module, sampling model, timestamp generation module, and time difference calculation and output module integrated within the FPGA; The clock management module is used to generate two clock signals with opposite phases and input the two clock signals to the rising edge sampling port and falling edge sampling port of the double data rate trigger, respectively; the sampling model is based on the double data rate trigger sampling the input second pulse at both the rising edge and falling edge of the same clock cycle to obtain the sampling signal of the second pulse; A timestamp generation module is used to determine a coarse count value of the sampled signal using a clock counter when an edge signal appears in the sampled signal; to determine a fine time interpolation value for quantizing the phase difference between the edge signal and the nearest clock edge using a pre-built delay chain; and to concatenate the coarse count value and the fine time interpolation value into a timestamp; the delay chain is composed of cascaded delay units in the field-programmable gate array. A time difference calculation output module is used to calculate the difference between the two generated timestamps to determine the time difference measurement result; the two timestamps are a first timestamp generated based on the input first second pulse and a second timestamp generated based on the input second second pulse.
2. The system according to claim 1, characterized in that, The system also includes a clock calibration engine, which is used to: determine the error data between the measured timestamp and the reference value when the calibration trigger condition is met; When the error data exceeds a preset threshold, a phase adjustment signal is sent to the clock management module to calibrate the clock phase.
3. The system according to claim 1, characterized in that, The system also includes a signal conditioning module, which is used to convert the raw second pulse into a second pulse adapted to the field programmable gate array.
4. A method for measuring the time difference of a second pulse based on a field-programmable gate array (FPGA), characterized in that, The method includes: using two clock signals with opposite phases generated by the clock management module in a field-programmable gate array (FPGA), and inputting the two clock signals to the rising edge sampling port and falling edge sampling port of a double data rate (DFR) trigger; the DFR trigger samples the input second pulse at both the rising and falling edges of the same clock cycle to obtain the sampled signal of the second pulse; when an edge signal appears in the sampled signal, a clock counter is used to determine the coarse count value of the sampled signal; and a pre-built delay chain is used to determine the fine time interpolation that quantizes the phase difference between the edge signal and the nearest clock edge; the delay chain is composed of cascaded delay units in the FPGA; the coarse count value and the fine time interpolation are concatenated to form a timestamp; the difference between the two generated timestamps is calculated to determine the time difference measurement result; the two timestamps are a first timestamp generated based on the first input second pulse and a second timestamp generated based on the second input second pulse.
5. The method according to claim 4, characterized in that, The method further includes: when the calibration trigger condition is met, determining the error data between the measured timestamp and the reference value; when the error data exceeds a preset threshold, sending a phase adjustment signal to the clock management module to calibrate the clock phase.
6. The method according to claim 5, characterized in that, The calibration triggering conditions include powering on the field-programmable gate array (FPGA), the temperature of the FPGA exceeding a threshold, and reaching the calibration cycle.
7. The method according to claim 5, characterized in that, The method further includes: uploading the time difference measurement results and calibration status to a host computer; the calibration status characterizes the execution progress of the calibration clock phase process.
8. The method according to claim 4, characterized in that, The process of concatenating the coarse count value and the fine time interpolation to form a timestamp includes: multiplying the coarse count value by the clock period to obtain the coarse time value; multiplying the fine time interpolation by the delay unit resolution to obtain the fine time value; the delay unit resolution being the time delay increment of the delay unit; and using the sum of the coarse time value and the fine time value as the timestamp.
9. An electronic device, characterized in that, include: A processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method as described in any one of claims 4-8.
10. A storage medium, characterized in that, include: The storage medium stores a program or instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 4-8.