Binary translation optimization method, binary translator and electronic device

By maintaining a pre-defined state table in the binary translator and delaying or merging zeroing operations, the code bloat problem caused by narrow write operations between AArch64 and LoongArch or RISC-V architectures is solved, thus improving the execution efficiency of the binary translation system.

CN122018920BActive Publication Date: 2026-07-21LOONGSON TECH CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
LOONGSON TECH CORP
Filing Date
2026-04-09
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

In binary translation between the AArch64 architecture and LoongArch or RISC-V architecture, due to the semantic differences in high-bit processing of narrow write operations, traditional dynamic binary translators need to generate zeroing instructions after each narrow write operation, resulting in target code bloat and performance loss, especially in vector-intensive applications such as audio and video encoding and decoding, and machine learning, where they are inefficient.

Method used

By maintaining a preset status table in the binary translator to record the status flag and effective bit width of each register, a clear instruction is inserted only when the bit width of the read operation is greater than the effective bit width indicated by the status flag. This delays or merges the physical clear operation, avoiding the generation of a clear instruction after each narrow write operation in the traditional method.

Benefits of technology

This greatly reduces redundant operations, improves the execution efficiency of the translation system, reduces the expansion of the target machine code sequence, and enhances the performance of the dynamic binary translation system.

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Abstract

The embodiment of the present application provides a binary translation optimization method, a binary translator and an electronic device, wherein the method comprises: when a narrow write operation instruction is translated, updating a state mark of a first register in a preset state table according to a write bit width of the narrow write operation on the first register; the state mark is used for indicating whether high bits of a corresponding register need to be cleared and recording an effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to the read operation from the preset state table; if it is determined that a read bit width of the read operation is greater than the effective bit width indicated by the state mark of the second register, inserting a first clear instruction before a translation result of the read operation instruction; the first clear instruction is used for clearing specified high bits of the second register. The present application can simplify a target machine code sequence generated by translation, greatly reduce redundant operations, and improve execution efficiency of a translation system.
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Citation Information

Patent Citations

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  • Binary translation system and method applied to X86 program

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