Resistance-type digital-to-analog converter, successive approximation register analog-to-digital converter and device

Abstract

The embodiment of the invention provides a resistive digital-to-analog converter, a successive approximation register analog-to-digital converter and equipment, a first switch array comprises a plurality of first switches, the first ends of the plurality of first switches are connected with a plurality of continuous voltage taps in a first group in a one-to-one correspondence manner, and the second ends of the plurality of first switches are connected with a first output node; the second switch array comprises a plurality of second switches, the first ends of the plurality of second switches are connected with the second group of continuous voltage taps in a one-to-one correspondence mode, and the second ends of the plurality of second switches are connected with the second output node. As the number of switches of the first switch array is one more than that of switches of the second switch array, the decoder can only control the first switch array to switch the connected voltage taps when the least significant bit of the received digital code is changed, so that the differential voltage between the first output node and the second output node is monotonically changed; therefore, on the premise that the number of the resistor string taps and the total area of the switch array are not increased, the resolution of the resistance-type digital-to-analog converter is effectively improved.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital conversion, and more particularly to a resistive digital-to-analog converter, a successive approximation register analog-to-digital converter, and an apparatus. Background Technology

[0002] The currently used hybrid capacitor-resistor digital-to-analog converter (DAC) architecture includes both capacitive and resistive DACs. For example, in a 10-bit successive approximation register DAC, the high 5 bits are implemented by a capacitive DAC, and the low 5 bits are supplemented by a resistive DAC.

[0003] However, this architecture leads to a significant increase in the number of resistors and switches when a higher resolution is required, resulting in a significant increase in circuit area and wiring complexity. Summary of the Invention

[0004] This application provides a resistive digital-to-analog converter, a successive approximation register-based analog-to-digital converter, and an apparatus to effectively improve the resolution of the resistive digital-to-analog converter without increasing the number of resistor string taps or the total area of ​​the switch array.

[0005] In a first aspect, the resistive digital-to-analog converter provided in the embodiments of this application includes:

[0006] The resistor string is configured to provide multiple voltage taps;

[0007] The first switch array includes multiple first switches, the first ends of the multiple first switches are connected one-to-one with a first group of multiple consecutive voltage taps, and the second ends of each first switch are connected to a first output node.

[0008] The second switch array includes multiple second switches, the first ends of which are connected one-to-one with a second group of multiple consecutive voltage taps, and the second ends of each second switch are connected to a second output node; wherein, the number of first switches is one more than the number of second switches.

[0009] The decoder, connected to the control terminal of the first switch array and the second switch array, is configured as follows:

[0010] When the least significant bit of the received input digital code changes, the first switch array is controlled to switch the connected voltage taps so that the differential voltage between the first output node and the second output node changes monotonically.

[0011] When the non-least significant bit of the input digital code changes, the first switch array and the second switch array are controlled to synchronously switch the connected voltage taps so that the differential voltage changes symmetrically.

[0012] Optionally, the decoder is configured as follows:

[0013] When the input digital code corresponds to the conversion of the most significant bit to the second least significant bit of the successive approximation register analog-to-digital converter, a control signal is generated to synchronously switch the first switch array and the second switch array.

[0014] When the input digital code corresponds to the least significant bit of the successive approximation register analog-to-digital converter, a control signal is generated that causes the first switch array to switch only one voltage tap.

[0015] Optionally, the decoder is configured as follows:

[0016] When the least significant bit of the received input digital code changes, if the previous comparison result is the first logic value, control the first switch array to switch to the adjacent low voltage tap.

[0017] If the previous comparison result is the second logic value, control the first switch array to switch to the adjacent high-voltage tap.

[0018] Optionally, the first switch array is connected to 2 n +1 consecutive voltage taps, the second switch array is connected to 2 n A series of voltage taps, where n is the nominal number of bits of the resistive digital-to-analog converter.

[0019] Optionally, the change in differential voltage caused by switching a voltage tap on the first switch array is half the change in differential voltage caused by the simultaneous switching of a voltage tap on the first switch array and the second switch array.

[0020] Secondly, this application provides a successive approximation register analog-to-digital converter, including the resistive digital-to-analog converter described in the first aspect.

[0021] Optional, also includes:

[0022] A capacitive digital-to-analog converter includes a non-inverting capacitor array and a reverse-inverting capacitor array. The first plates of the non-inverting capacitor array are connected to a first common node, and the first plates of the reverse-inverting capacitor array are connected to a second common node.

[0023] A comparator, whose first input is connected to the first common node and whose second input is connected to the second common node;

[0024] A logic controller, the input of which is connected to the output of the comparator, the first control terminal of which is connected to the capacitive digital-to-analog converter, and the second control terminal of which is connected to the resistive digital-to-analog converter;

[0025] The logic controller is configured as follows:

[0026] The capacitive digital-to-analog converter is controlled to sample the input voltage and perform successive approximation conversion of the high-order bits; and the resistive digital-to-analog converter is controlled to output a compensation voltage based on the output of the comparator.

[0027] The first output node of the resistive digital-to-analog converter is connected to the first common node through the second plate of the in-phase capacitor array to provide a first compensation voltage to the first common node; the second output node of the resistive digital-to-analog converter is connected to the second common node through the second plate of the in-phase capacitor array to provide a second compensation voltage to the second common node.

[0028] Optionally, the capacitive digital-to-analog converter further includes: a third switch array and a fourth switch array; the control terminals of the third switch array and the fourth switch array are connected to the first control terminal of the logic controller;

[0029] The third switch array includes a plurality of third switches, each of which selectively connects the second plate of a corresponding capacitor in the in-phase capacitor array to a first input voltage, a common-mode voltage, a positive reference voltage, or a negative reference voltage.

[0030] The fourth switch array includes a plurality of fourth switches, each of which selectively connects the second plate of a corresponding capacitor in the inverting capacitor array to the second input voltage, the common-mode voltage, the positive reference voltage, or the negative reference voltage; the common-mode voltage is generated based on the positive reference voltage and the negative reference voltage.

[0031] Optionally, the logic controller is configured to:

[0032] During the sampling phase, the third switch array is controlled to connect the second plates of all capacitors in the in-phase capacitor array to the first input voltage to sample the first input voltage, and the fourth switch array is controlled to connect the second plates of all capacitors in the in-phase capacitor array to the second input voltage to sample the second input voltage.

[0033] During the M-bit high-order bit successive approximation conversion stage, based on the output of the comparator, each switch in the third switch array and the fourth switch array is controlled sequentially to switch the second plate voltage of the corresponding capacitor in the corresponding capacitor array, and to perform the conversion of the highest M bits.

[0034] In the N-bit low-bit compensation conversion stage, after the M-bit high-bit conversion is completed, the comparator outputs the corresponding compensation voltage, and the first compensation voltage is applied to the second plate of the in-phase capacitor array through the third switch array, and the second compensation voltage is applied to the second plate of the in-phase capacitor array through the fourth switch array, so as to complete the conversion of the remaining N bits.

[0035] Where M and N are both positive integers, and M+N equals the total resolution of the analog-to-digital converter.

[0036] Thirdly, this application provides a chip including the resistive digital-to-analog converter described in the first aspect, or the successive approximation register-based analog-to-digital converter described in the second aspect.

[0037] Fourthly, this application provides an electronic device including the chip described in the third aspect.

[0038] The resistive digital-to-analog converter, successive approximation register analog-to-digital converter, and device provided in this application include a resistor string, a first switch array, a second switch array, and a decoder. The resistor string is configured to provide multiple voltage taps. The first switch array includes multiple first switches, the first ends of which are connected one-to-one with a first group of consecutive voltage taps, and the second ends of each first switch are connected to a first output node. The second switch array includes multiple second switches, the first ends of which are connected one-to-one with a second group of consecutive voltage taps, and the second ends of each second switch are connected to a second output node. The decoder, a control terminal connected to the first and second switch arrays, is configured to: control the first switch array to switch the connected voltage taps when the least significant bit of the received input digital code changes, so that the differential voltage between the first and second output nodes changes monotonically; and control the first and second switch arrays to synchronously switch the connected voltage taps when the non-least significant bit of the input digital code changes, so that the differential voltage changes symmetrically. Since the number of switches in the first switch array is one more than the number of switches in the second switch array, the decoder can control only the first switch array to switch the connected voltage taps when the least significant bit of the received digital code changes, so that the differential voltage between the first output node and the second output node changes monotonically. This allows the resolution of the resistive digital-to-analog converter to be effectively improved without increasing the number of resistor string taps and the total area of ​​the switch array. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0040] Figure 1This is a schematic diagram of the resistive digital-to-analog converter provided in this application;

[0041] Figure 2 A schematic diagram of the resistive digital-to-analog converter provided in this application;

[0042] Figure 3 This is a schematic diagram of the successive approximation register analog-to-digital converter provided in this application.

[0043] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is an analog-to-digital converter that narrows the input voltage range through successive approximation logic, ultimately outputting a digitally encoded value. SAR ADCs can employ either a capacitive digital-to-analog converter (CDAC) or a resistive digital-to-analog converter as their core structure.

[0046] Among them, capacitive digital-to-analog converters achieve charge redistribution through switching of capacitor arrays, which has the advantages of low power consumption and high precision, but its capacitor area increases exponentially with resolution; while resistive digital-to-analog converters achieve voltage quantization through resistive voltage divider networks, and its area growth is relatively slow, but the number of switches and wiring complexity are higher.

[0047] To balance area and accuracy, a hybrid capacitor-resistor digital-to-analog converter (DAC) architecture is commonly used. This means that the high-order bits use a capacitor-based DAC to reduce area, while the low-order bits use a resistor-based DAC to improve accuracy. For example, in a 10-bit successive approximation register DAC, the high 5 bits are implemented by a capacitor-based DAC, and the low 5 bits are supplemented by a resistor-based DAC.

[0048] However, this architecture leads to a significant increase in the number of resistors and switches when a higher resolution is required. For example, when increasing the resolution of the digital-to-analog converter from 10 bits to 11 bits, the resolution of the resistive digital-to-analog converter needs to increase by 1 bit, causing the number of resistors and switches in the resistive digital-to-analog converter to double. n+1 The increase, where n is the number of original resistors (e.g., from 32 resistors and 64 switches to 64 resistors and 128 switches), significantly increases the circuit area and wiring complexity.

[0049] To address this, this application proposes a resistive digital-to-analog converter (DAC). In this DAC, the number of switches in the first switch array is one more than the number of switches in the second switch array. Accordingly, the decoder can control only the voltage taps connected to the first switch array to change when the least significant bit of the received digital code changes, so that the differential voltage between the first output node and the second output node changes monotonically. This effectively improves the resolution of the resistive DAC without increasing the number of resistor string taps or the total area of ​​the switch array, and without causing a loss of accuracy.

[0050] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0051] Figure 1 This is a schematic diagram of the resistive digital-to-analog converter provided in this application, as shown below. Figure 1 As shown, the resistive digital-to-analog converter provided in this application embodiment includes:

[0052] Resistor string 101 is configured to provide multiple voltage taps;

[0053] The first switch array 102 includes multiple first switches, the first ends of the multiple first switches are connected one-to-one with a first group of multiple consecutive voltage taps, and the second ends of each first switch are connected to a first output node.

[0054] The second switch array 103 includes multiple second switches, the first ends of which are connected one-to-one with a second group of multiple consecutive voltage taps, and the second ends of each second switch are connected to a second output node; wherein, the number of first switches is one more than the number of second switches.

[0055] Decoder 104, connected to the control terminals of the first switch array 102 and the second switch array 103, is configured as follows:

[0056] When the least significant bit of the received input digital code changes, the first switch array 102 is controlled to switch the connected voltage taps so that the differential voltage between the first output node and the second output node changes monotonically.

[0057] When the non-least significant bit of the input digital code changes, the first switch array 102 and the second switch array 103 are controlled to synchronously switch the connected voltage taps so that the differential voltage changes symmetrically.

[0058] In this embodiment, the resistive digital-to-analog converter includes a first output node Vrefp_RDAC, a second output node Vrefn_RDAC, a resistor string 101, a first switch array 102, a second switch array 103, and a decoder 104. The resistor string 101 provides multiple voltage taps, thereby providing a first group of consecutive voltage taps and a second group of consecutive voltage taps. The first switch array 102 includes multiple first switches, each with a first terminal and a second terminal. The first terminal of each first switch is connected to a voltage tap, meaning that the first terminals of the multiple first switches are connected one-to-one with the first group of consecutive voltage taps, and the second terminal of each first switch is connected to the first output node. The second switch array 103 includes multiple second switches, each with a first terminal and a second terminal. The first terminal of each second switch is connected to a voltage tap, meaning that the first terminals of the multiple second switches are connected one-to-one with the second group of consecutive voltage taps, and the second terminal of each second switch is connected to the second output node.

[0059] Decoder 104 is connected to the control terminals of each first switch in the first switch array 102 and the control terminals of each second switch in the second switch array 103. Responding to changes in the least significant bit of the input digital code, it switches only the voltage taps connected to the first switch array 102, causing a monotonic change in the differential output voltage between the first and second output nodes with a minimum voltage step. This effectively improves the resolution of the resistive digital-to-analog converter without increasing the number of taps in the resistor string 101 or the total area of ​​the switch array, without causing accuracy loss. Decoder 104 can also respond to changes in other bits of the input digital code besides the least significant bit by synchronously switching the voltage taps connected to the first switch array 102 and the second switch array 103, causing the differential output voltage to change symmetrically.

[0060] It should be noted that in a resistive digital-to-analog converter, resistor string 101 is composed of multiple identical resistors connected end-to-end, with a reference voltage applied across its terminals (e.g., Vref connected to the high end and GND to the low end). According to Ohm's law and the voltage divider principle, when current flows through this resistor string 101, a fixed, stepped voltage is generated at each resistor connection point (node). Voltage taps are used to extract the voltages from these nodes, allowing them to be selected by a switch.

[0061] Optionally, encoder 104 is configured to generate a control signal for synchronous switching of first switch array 102 and second switch array 103 when the input digital code corresponds to the transition from the most significant bit to the second least significant bit of the successive approximation register analog-to-digital converter; and to generate a control signal for switching only one voltage tap of first switch array 102 when the input digital code corresponds to the transition from the least significant bit of the successive approximation register analog-to-digital converter.

[0062] The decoding logic is explicitly mapped to the successive approximation process of the successive approximation register analog-to-digital converter (the most significant bit to the second least significant bit corresponds to synchronous switching, and the least significant bit corresponds to unilateral switching). This directly corresponds the switching mode of the resistive digital-to-analog converter to the high-to-low bit conversion process of the successive approximation register analog-to-digital converter, making the resistive digital-to-analog converter applicable to the successive approximation register analog-to-digital converter.

[0063] For example, in the conversion process of a successive approximation register analog-to-digital converter (ADC), the high 10 bits are converted according to normal differential logic (e.g., if the voltage on the P-side of the comparator input is greater than the voltage on the N-side, then the voltage on the P-side decreases by 0.5MSB, and the voltage on the N-side increases by 0.5MSB, MSB = 1 / 2N × VREFP), which is a symmetrical flip logic on both sides. Towards the last LSB, only the resistive ADC on the P-side switches to the next level; the N-side remains unchanged. Therefore, for the comparator input, the last flip only changes the level on one side, achieving half the weight. Furthermore, since this scheme only changes the comparator's input common-mode voltage in the least significant bit, it has no negative impact on the normal operation of the comparator.

[0064] Meanwhile, for decoder 104, the first 10 bits are the regular decoder logic. However, before performing the final flip, the decoder logic first checks the result of the previous comparator. If the result is 1, the P-side is shifted down by one LSB (SWP). <1> Switch to SWP <0> ),like Figure 2 As shown, if the result is 0, the P side is shifted up by one LSB, while the N side remains unchanged (still only a 5-bit decoder 104).

[0065] Optionally, the decoder 104 is configured to, when the least significant bit of the received input digital code changes, control the first switch array 102 to switch to the adjacent low-voltage tap if the previous comparison result is a first logic value, and control the first switch array 102 to switch to the adjacent high-voltage tap if the previous comparison result is a second logic value.

[0066] In this example, it is determined that when the least significant bit changes, the voltage tap should be switched to high or low based on the previous comparison result. This enables the resistive digital-to-analog converter to make trial-and-error adjustments based on comparator feedback. This is the core of the successive approximation register algorithm, avoiding errors that may be introduced by arbitrary switching and ensuring the determinism and correctness of the conversion process.

[0067] For example, the first logical value is 0 and the second logical value is 1, or the first logical value is 1 and the second logical value is 0.

[0068] For example, when other valid bits of the input digital code change, if the previous comparison result corresponding to the other valid bits is a first logic value, the first switch array 102 is controlled to switch to the adjacent low voltage tap, and at the same time, the second switch array 103 is controlled to switch to the adjacent high voltage tap; if the previous comparison result corresponding to the other valid bits is a second logic value, the first switch array 102 is controlled to switch to the adjacent high voltage tap, and at the same time, the second switch array 103 is controlled to switch to the adjacent low voltage tap.

[0069] It should be noted that when the voltage tap is already at the lowest boundary, it will not switch to a lower voltage tap; when the voltage tap is already at the highest boundary, it will not switch to a higher voltage tap. Instead, it will directly lock the current voltage tap.

[0070] Optionally, the first switch array is connected to 2 n +1 consecutive voltage taps, the second switch array 103 is connected to 2 n A series of consecutive voltage taps, where n is the nominal bit width of the resistive digital-to-analog converter (DAC), i.e., the number of bits of binary digital input that the DAC can distinguish, directly determining the quantization accuracy and the fineness of the output voltage. This is achieved by clarifying the relationship between the number of switches and the nominal bit width (the first array connects to 2...). n +1 tap, second array connected to 2 n (One tap), providing quantifiable design parameters that facilitate direct circuit construction based on the target resolution n, making it highly feasible.

[0071] For example, the resistor string 101 in the resistive digital-to-analog converter includes 32 resistors and provides 33 voltage taps, a first switch array 102 is connected to the 33 voltage taps, and a second switch array 103 is connected to the 32 voltage taps.

[0072] Optionally, the change in differential voltage caused by switching a voltage tap in the first switch array 102 is half the change in differential output voltage caused by the simultaneous switching of a voltage tap by the first switch array 102 and the second switch array 103.

[0073] By achieving half-step capability through unilateral switching, the voltage resolution capability is doubled (i.e., one bit of effective resolution is added) without increasing the accuracy of the reference voltage and resistor string 101.

[0074] The resistive digital-to-analog converter provided in this application has a first switch array with one more switch than the second switch array. Accordingly, the decoder can control only the first switch array to switch the connected voltage taps when the least significant bit of the received digital code changes, so that the differential voltage between the first output node and the second output node changes monotonically. This effectively improves the resolution of the resistive digital-to-analog converter without increasing the number of resistor string taps or the total area of ​​the switch array, and without causing a loss of accuracy.

[0075] Figure 3 A schematic diagram of the successive approximation register analog-to-digital converter provided in this application is shown below. Figure 3 As shown, the successive approximation register analog-to-digital converter provided in this application includes:

[0076] The aforementioned resistive digital-to-analog converter 10.

[0077] Because the resistive digital-to-analog converter 10 can effectively improve the resolution of the resistive digital-to-analog converter without increasing the number of resistor string taps or the total area of ​​the switch array, and without causing a loss of accuracy, the resolution of the successive approximation register analog-to-digital converter can be improved without increasing the number of resistor string taps or the total area of ​​the switch array.

[0078] It should be noted that the successive approximation register analog-to-digital converter is an analog-to-digital converter architecture that achieves analog voltage to digital signal conversion through bit-by-bit probing and comparison feedback. The core is the logic control of the successive approximation register, the voltage reconstruction of the digital-to-analog converter, and the deviation determination of comparator 30.

[0079] Optionally, the successive approximation register analog-to-digital converter further includes a capacitive digital-to-analog converter 20, a comparator 30, and a logic controller 40; the capacitive digital-to-analog converter 20 includes a non-inverting capacitor array 201 and an inverting capacitor array 202, the first plate of the non-inverting capacitor array 201 is connected to a first common node TOP-P, and the first plate of the inverting capacitor array 202 is connected to a second common node TOP-N; the comparator 30 includes a first input terminal and a second input terminal, the first input terminal of the comparator 30 is connected to the first common node TOP-P, and the second input terminal of the comparator 30 is connected to the second common node TOP-N; the logic controller 40 includes an input terminal, a first control terminal, and a second control terminal, the input terminal of the logic controller 40 is connected to the output terminal of the comparator 30, the first control terminal of the logic controller 40 is connected to the capacitive digital-to-analog converter 20, and the second control terminal of the logic controller 40 is connected to the resistive digital-to-analog converter 10.

[0080] The logic controller 40 is configured to: control the capacitive digital-to-analog converter 20 to sample the input voltage and perform successive approximation conversion of the high-order bits; and control the resistive digital-to-analog converter 10 to output a compensation voltage according to the output of the comparator 30. The first output node of the resistive digital-to-analog converter 10 is connected to the first common node TOP-P through the second plate of the in-phase capacitor array 201 to provide a compensation voltage Vrefp_RDAC to the first common node TOP-P; the second output node of the resistive digital-to-analog converter 10 is connected to the second common node TOP-N through the second plate of the in-phase capacitor array 202 to provide a second compensation voltage Vrefn_RDAC to the second common node TOP-N.

[0081] Accordingly, comparator 30 can continuously compare the real-time voltage on the common node throughout the conversion process and output the comparison result to logic controller 40 to control the high-order conversion logic of capacitive digital-to-analog converter 20 and the compensation voltage output logic of resistive digital-to-analog converter 10.

[0082] The capacitive digital-to-analog converter 20 handles high-order conversion and can use a smaller capacitor array 201, significantly reducing area and drive power consumption. The resistive digital-to-analog converter 10 handles low-order fine-tuning. The resistor string 101 structure is typically more area-efficient than the capacitor array 201 for achieving the same precision when implementing fine voltage steps, and has extremely low static power consumption. Based on this, an optimized balance between area, power consumption, and precision is achieved.

[0083] Optionally, the capacitive digital-to-analog converter 20 further includes: a third switch array 203 and a fourth switch array 204, the control terminals of the third switch array 203 and the fourth switch array 204 being connected to the first control terminal of the logic controller 40; the third switch array 203 includes a plurality of third switches, each third switch selectively connecting the second plate of a corresponding capacitor in the in-phase capacitor array 201 to a first input voltage Vip, a common-mode voltage Vcm, a positive reference voltage Vrefp, or a negative reference voltage Vrefn; the fourth switch array 204 includes a plurality of fourth switches, each fourth switch selectively connecting the second plate of a corresponding capacitor in the in-phase capacitor array 202 to a second input voltage Vin, a common-mode voltage Vcm, a positive reference voltage Vrefp, or a negative reference voltage Vrefn; wherein, the common-mode voltage Vcm is generated based on the positive reference voltage Vrefp and the negative reference voltage Vrefn.

[0084] During the successive approximation process, based on the result of comparator 30, the second plate of the corresponding capacitor is switched from the first input voltage Vip to the differential voltage Vcm, positive reference voltage Vrefp, or negative reference voltage Vrefn via the third switch, and the second plate of the corresponding capacitor is switched from the second input voltage Vin to the differential voltage Vcm, positive reference voltage Vrefp, or negative reference voltage Vrefn via the fourth switch.

[0085] It should be noted that, for the in-phase capacitor array 201, the last switch in the third switch array 203 can selectively connect the last capacitor in the in-phase capacitor array 201 to the first input voltage Vip, the common-mode voltage Vcm, or the first compensation voltage Vrefp_RDAC. For the inverting capacitor array 202, the last switch in the fourth switch array 204 can selectively connect the last capacitor in the inverting capacitor array 202 to the second input voltage Vin, the common-mode voltage Vcm, or the second compensation voltage Vrefn_RDAC.

[0086] Optionally, the logic controller 40 is configured to: during the sampling phase, control the third switch array 203 to connect the second plates of all capacitors in the non-inverting capacitor array 201 to the first input voltage Vip for sampling the first input voltage Vip; and control the fourth switch array 204 to connect the second plates of all capacitors in the inverting capacitor array 202 to the second input voltage Vin for sampling the second input voltage Vin; during the M-bit high-order successive approximation conversion phase, according to the output of the comparator 30, sequentially control each switch in the third switch array 203 and the fourth switch array 204 to the corresponding capacitor arrays. The corresponding capacitors in the middle are switched on the second plate voltage to perform the conversion of the highest M bits; in the N-bit low-bit compensation conversion stage, after the M-bit high-bit conversion is completed, according to the output of comparator 30, the resistor-type digital-to-analog converter 10 is controlled to output the corresponding compensation voltage, and the first compensation voltage is applied to the second plate of the non-inverting capacitor array 201 through the third switch array 203, and the second compensation voltage is applied to the second plate of the inverting capacitor array 202 through the fourth switch array 204 to complete the conversion of the remaining N bits; where M and N are both positive integers, and M+N is equal to the total resolution of the analog-to-digital converter.

[0087] A complete conversion is divided into two stages: coarse adjustment of the M-bit (high-bit) capacitor and fine adjustment of the N-bit (low-bit) resistor. This allows for flexible and optimal allocation of resources based on system requirements such as total resolution, bandwidth, and power consumption budget.

[0088] For example, during the sampling phase, each third switch in the third switch array 203 is controlled to close to connect the second plates of all capacitors in the in-phase capacitor array 201 to the first input voltage to sample the first input voltage, and each fourth switch in the fourth switch array 204 is controlled to close to connect the second plates of all capacitors in the in-phase capacitor array 202 to the second input voltage to sample the second input voltage.

[0089] During the M-bit high-order successive approximation conversion stage, based on the output of comparator 30, one of the third switches in the third switch array 203 is closed sequentially to switch the second plate voltage of the corresponding high-order capacitor in the in-phase capacitor array 201 sequentially, and one of the fourth switches in the fourth switch array 204 is closed sequentially to switch the second plate voltage of the corresponding high-order capacitor in the inverting capacitor array 202 sequentially, so as to perform the conversion of the highest M bits.

[0090] During the N-bit low-order compensation conversion stage, based on the output of comparator 30, the first switch in the first switch array 101 is controlled to close, and a first compensation voltage is provided to the first common node through the second plate of the capacitor in the in-phase capacitor array 201. The second switch in the second switch array 102 is controlled to close, and a second compensation voltage is provided to the second common node through the second plate of the capacitor in the inverting capacitor array 202, so as to perform the conversion of the remaining N bits.

[0091] For example, the third and fourth switches mentioned above can both be multiplexer switches, which select one voltage path.

[0092] To facilitate understanding of the scheme in this application, an example is given of a 11-bit analog-to-digital converter implemented by combining a 5-bit high-order capacitive digital-to-analog converter and a 5-bit low-order resistive digital-to-analog converter (wherein, the 5-bit resistive digital-to-analog converter achieves 6-bit precision):

[0093] Both the in-phase and out-of-phase capacitor arrays of a capacitive digital-to-analog converter include a binary weighted capacitor array (16C, 8C, 4C, 2C, C), and a final capacitor C.

[0094] The first plates of all capacitors in the in-phase capacitor array are connected to the first common node (i.e., the non-inverting input of the comparator). The second plates of the capacitors in the binary weighted capacitor array of the in-phase capacitor array are selectively connected to the first input voltage Vip, the common-mode voltage Vcm, the positive reference voltage Vrefp, or the negative reference voltage Vrefn through the corresponding third switch. The second plate of the last capacitor in the in-phase capacitor array is selectively connected to the first input voltage Vip, the common-mode voltage Vcm, or the first compensation voltage Vrefp_RDAC through the corresponding third switch.

[0095] The first plates of all capacitors in the inverting capacitor array are connected to the second common node (i.e., the inverting input of the comparator). The second plates of the capacitors in the binary weighted capacitor array of the inverting capacitor array are selectively connected to the second input voltage Vin, the common-mode voltage Vcm, the positive reference voltage Vrefp, or the negative reference voltage Vrefn through the corresponding fourth switch. The second plate of the last capacitor in the inverting capacitor array is selectively connected to the second input voltage Vin, the common-mode voltage Vcm, or the second compensation voltage Vrefn_RDAC through the corresponding fourth switch.

[0096] Among them, the positive reference voltage Vrefp=1.2V, the negative reference voltage Vrefn=0V, the common-mode voltage Vcm(Vrefp+Vrefn) / 2=0.6V, the first input voltage Vip=1.2V, and the second input voltage Vin=0V.

[0097] The bit processing procedure for approximation is as follows:

[0098] 1. Sampling stage

[0099] The first and second common nodes are connected to the differential-mode voltage Vcm, initializing it to the common-mode voltage Vcm (0.6V). The second plates of all capacitors in the in-phase capacitor array are connected to the first input voltage Vip (1.2V), and the second plates of all capacitors in the anti-phase capacitor array are connected to the second input voltage Vin (0V). At this time, charge is stored in the capacitor array.

[0100] 2. Maintenance Phase

[0101] After sampling, the second plates of all capacitors in the in-phase capacitor array switch from the first input voltage Vip to the common-mode voltage Vcm. According to the principle of charge conservation, the voltage at the first common node becomes V1 = 2 × Vcm - Vip = 2 × 0.6V - 1.2V = 0V. Simultaneously, the second plates of all capacitors in the inverting capacitor array switch from the second input voltage Vip to the common-mode voltage Vcm. Similarly, the voltage at the second common node becomes V2 = 2 × Vcm - Vin = 2 × 0.6V - 0V = 1.2V. At this point, the differential input voltage (i.e., the first input voltage Vip and the second input voltage Vin) is converted into the voltages of the two common nodes.

[0102] 3. Transition Phase

[0103] (1) High-level successive approach to the transition stage

[0104] This stage starts with the largest capacitor (16C) and determines the digital code step by step.

[0105] The voltage of the first common node is 0V, and the voltage of the second common node is 1.2V; the comparator outputs the comparison result of the first common node and the second common node, indicating that V2 > V1.

[0106] The logic controller switches the second plate of the 16C capacitor in the non-inverting capacitor array from the common-mode voltage Vcm to the positive reference voltage Vrefp, and simultaneously switches the second plate of the 16C capacitor in the inverting capacitor array from the common-mode voltage Vcm to the negative reference voltage Vrefn. The voltage change ΔV = (Vrefp - Vcm) × (16C / 32C) = (0.6V) × 0.5 = 0.3V. Correspondingly, the voltage at the first common node becomes 0 + 0.3V = 0.3V, and the voltage at the second common node becomes 1.2V - 0.3V = 0.9V, so this bit is 1.

[0107] Repeat this process, processing capacitors 8C, 4C, 2C, and C in sequence. The voltage change caused by each switch decreases in binary weights, at 0.15V, 0.075V, 0.0375V, and 0.01875V respectively.

[0108] The specific voltage change sequences of the first common node and the second common node are as follows:

[0109] After processing at 8C: V1 = 0.45V, V2 = 0.75V;

[0110] After processing 4C: V1=0.525V, V2=0.675V;

[0111] After processing 2C: V1 = 0.5625V, V2 = 0.6375V;

[0112] After processing C: V1 = 0.58125V, V2 = 0.61875V;

[0113] At this point, the top 5 digits are confirmed to be 11111.

[0114] Correspondingly, after the capacitive digital-to-analog converter flips, the residual error of the first common node is 0 + 0.3 + 0.15 + 0.075 + 0.0375 + 0.01875 = 0.58125V, and the residual error of the second common node is 1.2 - 0.3 - 0.015 - 0.075 - 0.0375 - 0.01875 = 0.61875V. At this time, the second plate of the last capacitor in the in-phase capacitor array switches from the common-mode voltage Vcm to the first compensation voltage Vrefp_RDAC (corresponding to the 0.6V voltage tap), and the second plate of the last capacitor in the inverting capacitor array switches from the common-mode voltage Vcm to the second compensation voltage Vrefn_RDAC (corresponding to the 0.6V voltage tap).

[0115] (2) Low-level compensation conversion stage

[0116] Since the residual difference of the first common node is 0.5875V and the residual difference of the second common node is 0.61875V, the voltage of the first common node is less than that of the second common node. The logic controller switches the first compensation voltage tap from 0.6V to 0.9V, and the second compensation voltage tap from 0.6V to 0.3V. At this time, the voltage change ΔV_rdac = (0.9V - 0.6V) × (C / 32C) = 0.3V / 32 = 0.009375V. Therefore, V1 becomes 0.58125V + 0.009375V = 0.590625V; V2 becomes 0.61875V - 0.009375V = 0.609375V, so this bit is 1.

[0117] Following this pattern, with voltage changes of 0.009375V, 0.0046875V, 0.00234375V, 0.001171875V, and 0.001171875V respectively, the voltages of the first common node are 0.58125, 0.590625, 0.5953125, 0.59765626, 0.598828125, and 0.6 respectively; and the voltages of the second common node are 0.61875, 0.609375, 0.6046875, 0.60234375, and 0.601171875 respectively. Correspondingly, the first compensation voltages are 0.6, 0.9, 1.05, 1.125, 1.1625, 1.1625 + 0.0375 (1.2), and the second compensation voltages are 0.6, 0.3, 0.15, 0.075, 0.0375.

[0118] Thus, a 5-bit resistive digital-to-analog converter can be used to achieve 6-bit precision, and the 11 bits are determined to be 11111111111.

[0119] This application provides a chip including the above-described resistive digital-to-analog converter or the above-described successive approximation register-based analog-to-digital converter.

[0120] This application provides an electronic device including the chip described above.

[0121] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A resistive digital-to-analog converter, characterized by include: The resistor string is configured to provide multiple voltage taps; The first switch array includes multiple first switches, the first ends of the multiple first switches are connected one-to-one with a first group of multiple consecutive voltage taps, and the second ends of each first switch are connected to a first output node. The second switch array includes multiple second switches, the first ends of which are connected one-to-one with a second group of multiple consecutive voltage taps, and the second ends of each second switch are connected to a second output node; wherein, the number of first switches is one more than the number of second switches. The decoder, connected to the control terminal of the first switch array and the second switch array, is configured as follows: When the least significant bit of the received input digital code changes, the first switch array is controlled to switch the connected voltage taps so that the differential voltage between the first output node and the second output node changes monotonically. When the non-least significant bit of the input digital code changes, the first switch array and the second switch array are controlled to synchronously switch the connected voltage taps so that the differential voltage changes symmetrically.

2. The resistive digital-to-analog converter of claim 1, wherein, The decoder is configured as follows: When the input digital code corresponds to the conversion of the most significant bit to the second least significant bit of the successive approximation register analog-to-digital converter, a control signal is generated to synchronously switch the first switch array and the second switch array. When the input digital code corresponds to the least significant bit of the successive approximation register analog-to-digital converter, a control signal is generated that causes the first switch array to switch only one voltage tap.

3. The resistive digital-to-analog converter of claim 1, wherein, The decoder is configured as follows: When the least significant bit of the received input digital code changes, if the previous comparison result is the first logic value, control the first switch array to switch to the adjacent low voltage tap. If the previous comparison result is the second logic value, control the first switch array to switch to the adjacent high-voltage tap.

4. The resistive digital-to-analog converter according to claim 1, characterized in that, The first switch array is connected to 2 n + 1 consecutive voltage taps, the second switch array is connected to 2 n consecutive voltage taps, where n is the nominal number of bits of the resistive digital-to-analog converter.

5. The resistive digital-to-analog converter according to claim 4, characterized in that, The change in differential voltage caused by switching a voltage tap on the first switch array is half the change in differential voltage caused by the simultaneous switching of a voltage tap on the first switch array and the second switch array.

6. A successive approximation type register analog-to-digital converter, characterized by include: The resistive digital-to-analog converter according to any one of claims 1-5.

7. The analog-to-digital converter of claim 6, wherein, Also includes: A capacitive digital-to-analog converter includes a non-inverting capacitor array and a reverse-inverting capacitor array. The first plates of the non-inverting capacitor array are connected to a first common node, and the first plates of the reverse-inverting capacitor array are connected to a second common node. A comparator, whose first input is connected to the first common node and whose second input is connected to the second common node; A logic controller, the input of which is connected to the output of the comparator, the first control terminal of which is connected to the capacitive digital-to-analog converter, and the second control terminal of which is connected to the resistive digital-to-analog converter; The logic controller is configured as follows: The capacitive digital-to-analog converter is controlled to sample the input voltage and perform successive approximation conversion of the high-order bits; and the resistive digital-to-analog converter is controlled to output a compensation voltage based on the output of the comparator. The first output node of the resistive digital-to-analog converter is connected to the first common node through the second plate of the in-phase capacitor array to provide a first compensation voltage to the first common node; the second output node of the resistive digital-to-analog converter is connected to the second common node through the second plate of the in-phase capacitor array to provide a second compensation voltage to the second common node.

8. The analog-to-digital converter according to claim 7, characterized in that, The capacitive digital-to-analog converter further includes: a third switch array and a fourth switch array; the control terminals of the third switch array and the fourth switch array are connected to the first control terminal of the logic controller; The third switch array includes a plurality of third switches, each of which selectively connects the second plate of a corresponding capacitor in the in-phase capacitor array to a first input voltage, a common-mode voltage, a positive reference voltage, or a negative reference voltage. The fourth switch array includes a plurality of fourth switches, each of which selectively connects the second plate of a corresponding capacitor in the inverting capacitor array to the second input voltage, the common-mode voltage, the positive reference voltage, or the negative reference voltage; the common-mode voltage is generated based on the positive reference voltage and the negative reference voltage.

9. The analog-to-digital converter according to claim 8, characterized in that, The logic controller is configured as follows: During the sampling phase, the third switch array is controlled to connect the second plates of all capacitors in the in-phase capacitor array to the first input voltage to sample the first input voltage, and the fourth switch array is controlled to connect the second plates of all capacitors in the in-phase capacitor array to the second input voltage to sample the second input voltage. During the M-bit high-order bit successive approximation conversion stage, based on the output of the comparator, each switch in the third switch array and the fourth switch array is controlled sequentially to switch the second plate voltage of the corresponding capacitor in the corresponding capacitor array, and to perform the conversion of the highest M bits. In the N-bit low-bit compensation conversion stage, after the M-bit high-bit conversion is completed, the comparator outputs the corresponding compensation voltage, and the first compensation voltage is applied to the second plate of the in-phase capacitor array through the third switch array, and the second compensation voltage is applied to the second plate of the in-phase capacitor array through the fourth switch array, so as to complete the conversion of the remaining N bits. Where M and N are both positive integers, and M+N equals the total resolution of the analog-to-digital converter.

10. A chip, characterized in that, It includes a resistive digital-to-analog converter according to any one of claims 1-5, or a successive approximation register-based analog-to-digital converter according to any one of claims 6-9.

11. An electronic device, characterized in that, Includes the chip described in claim 10.

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