Terminal structure and method of manufacturing the same, power device

Abstract

The application provides a terminal structure and a preparation method thereof and a power device. The terminal structure comprises a drift layer, an equipotential ring, a first insulating layer, a gate switching structure, a second insulating layer and a gate line. The drift layer comprises opposite first and second surfaces, the equipotential ring extends into the drift layer from the first surface, the first insulating layer comprises a first part and a second part and is arranged on the first surface, the gate switching structure is arranged on a side of the first insulating layer away from the drift layer, the orthographic projection of the first part on the first surface does not overlap the orthographic projection of the gate switching structure on the first surface, the orthographic projection of the second part on the first surface is located in the range of the orthographic projection of the gate switching structure on the first surface, and the maximum thickness of the first part is less than the maximum thickness of the second part. The terminal structure can be applied to the power device to improve the withstand voltage performance and reliability of the power device.

Description

Technical Field

[0001] This application relates to the field of silicon-based and silicon carbide-based power device technology, and in particular to a terminal structure and its fabrication method, and a power device. Background Technology

[0002] In the design of silicon-based and silicon carbide-based power devices, the termination structure is a crucial component. Currently, at the connection between the cell structure and the termination structure, a wider equipotential ring can be designed to alleviate electric field concentration and improve the breakdown voltage performance of silicon-based and silicon carbide-based power devices. However, this structure suffers from breakdown due to equipotential ring potential instability and gate oxide susceptibility, thus reducing the breakdown voltage performance and reliability of silicon-based and silicon carbide-based power devices.

[0003] Therefore, how to reduce the failure rate of terminal structures in order to improve the withstand voltage performance and reliability of silicon-based and silicon carbide-based power devices has become an urgent problem to be solved in the field. Summary of the Invention

[0004] This application proposes a terminal structure and its fabrication method, as well as a power device, with the aim of improving the voltage withstand performance and reliability of the power device.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a terminal structure, which includes a drift layer, an equipotential ring, a first insulating layer, a gate transition structure, a second insulating layer, and a gate line. The drift layer includes opposing first and second surfaces. The equipotential ring extends from the first surface into the drift layer. The first insulating layer is disposed on the first surface. The gate transition structure is disposed on the side of the first insulating layer away from the drift layer. The second insulating layer is disposed on the side of the gate transition structure away from the drift layer. The gate line is disposed on the side of the second insulating layer away from the drift layer, and the gate line is electrically connected to the gate transition structure.

[0007] The first insulating layer includes a first part and a second part. The orthographic projection of the first part on the first surface does not overlap with the orthographic projection of the gate transfer structure on the first surface. The orthographic projection of the second part on the first surface is within the range of the orthographic projection of the gate transfer structure on the first surface. The maximum thickness of the first part is less than the maximum thickness of the second part.

[0008] In the above embodiments of this application, the terminal structure includes a drift layer, an equipotential ring, a first insulating layer, a gate transition structure, a second insulating layer, and a gate line. The equipotential ring extends from the first surface of the drift layer into the drift layer. The first insulating layer is disposed on the first surface. A gate transition structure is also disposed on the side of the first insulating layer away from the drift layer. The gate line is electrically connected to the gate transition structure. During the turn-off process of the power device including the terminal structure, carrier accumulation and current flow occur within the equipotential ring. Therefore, there is a voltage difference between the gate transition structure and the equipotential ring.

[0009] Furthermore, the first insulating layer includes a first part and a second part. The orthographic projection of the first part on the first surface does not overlap with the orthographic projection of the gate transition structure on the first surface. The orthographic projection of the second part on the first surface is located within the range of the orthographic projection of the gate transition structure on the first surface, i.e., the second part is located between the gate transition structure and the equipotential ring, achieving electrical isolation between the gate transition structure and the equipotential ring. When the potential of the equipotential ring increases, the voltage difference between the gate transition structure and the equipotential ring increases. By setting the maximum thickness of the first part to be less than the maximum thickness of the second part, i.e., setting the portion of the first insulating layer between the gate transition structure and the equipotential ring to be thicker, the voltage difference that the gate transition structure and the equipotential ring can accommodate is larger. This reduces the failure rate of the second part being broken down, improves the reliability of the first insulating layer between the gate transition structure and the equipotential ring, thereby enhancing the withstand voltage performance of the termination structure and improving the reliability of the power device including the termination structure.

[0010] In some embodiments, the first part includes a third surface in contact with the first surface, and the second part includes a fourth surface in contact with the first surface, at least a portion of the fourth surface being located on the side of the third surface closer to the second surface.

[0011] In some embodiments, the maximum thickness of the second part ranges from 5,000 angstroms to 50,000 angstroms.

[0012] In some embodiments, the terminal structure further includes a dummy gate extending from the first surface into the drift layer and located inside the equipotential ring.

[0013] In some embodiments, the terminal structure includes a plurality of dummy gates arranged at intervals along a first direction from the inside out, the first direction being parallel to the first surface.

[0014] In some embodiments, the number of dummy gates ranges from 1 to 3.

[0015] In some embodiments, the terminal structure further includes a trap region extending from the first surface into the drift layer, and the trap region is located on at least one side of the dummy gate.

[0016] In some embodiments, the terminal structure further includes a first electrode disposed on the side of the second insulating layer away from the drift layer. A through first contact hole is provided in the first insulating layer and the second insulating layer, and the first electrode is electrically connected to the equipotential ring through the first contact hole.

[0017] In some embodiments, a through second contact hole is further provided in the first insulating layer and the second insulating layer, and the first electrode is electrically connected to the well region through the second contact hole. Along the first direction, the width of the first contact hole is 8 to 10 times the width of the second contact hole.

[0018] Secondly, embodiments of this application also provide a method for fabricating a terminal structure. The method includes forming a drift layer, the drift layer including opposing first and second surfaces; forming an equipotential ring extending from the first surface into the drift layer; forming a first insulating layer on the first surface, the first insulating layer including a first part and a second part, the thickness of the first part being less than the thickness of the second part; forming a gate transition structure, the gate transition structure being located on the side of the first insulating layer away from the drift layer; the orthographic projection of the first part on the first surface not overlapping with the orthographic projection of the gate transition structure on the first surface; the orthographic projection of the second part on the first surface being within the range of the orthographic projection of the gate transition structure on the first surface; forming a second insulating layer, the second insulating layer being located on the side of the gate transition structure away from the drift layer; and forming a gate line, the gate line being located on the side of the second insulating layer away from the drift layer, and the gate line being electrically connected to the gate transition structure.

[0019] The preparation method provided in the above embodiments of this application forms an equipotential ring extending from the first surface into the drift layer after forming the drift layer, and forms a first insulating layer on the first surface. The first insulating layer includes a first part and a thicker second part. The gate transition structure is located on the side of the first insulating layer away from the drift layer. The orthographic projection of the first part on the first surface does not overlap with the orthographic projection of the gate transition structure on the first surface. The orthographic projection of the second part on the first surface is within the range of the orthographic projection of the gate transition structure on the first surface. That is, the gate transition structure is formed on the side of the second part away from the drift layer and covers the second part.

[0020] During the turn-off process of a power device including a termination structure, carrier accumulation and current flow occur within the equipotential ring. Therefore, a voltage difference exists between the gate transition structure and the equipotential ring. Since the portion of the first insulating layer between the gate transition structure and the equipotential ring is thicker, the voltage difference that can be accommodated between the gate transition structure and the equipotential ring is larger. This reduces the failure rate of the second part and improves the reliability of the first insulating layer between the gate transition structure and the equipotential ring, thereby improving the withstand voltage performance of the termination structure and thus enhancing the withstand voltage performance and reliability of the power device including the termination structure.

[0021] In some embodiments, the first surface includes a first region and a second region, the second region being located outside the first region. Forming a first insulating layer includes forming a protective layer that covers the first region and exposes the second region, forming a second portion in the second region using a thermal oxidation process, removing the protective layer, and forming a first portion in the first region using a thermal oxidation process.

[0022] Thirdly, embodiments of this application provide a power device comprising a plurality of cell structures and a terminal structure as shown in any of the above embodiments, wherein the terminal structure is disposed on the outside of the plurality of cell structures.

[0023] The power devices described above have the same structure and beneficial technical effects as the terminal structures provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1 A structural diagram of a power device provided in an embodiment of this application;

[0026] Figure 2 A voltage withstand comparison diagram between the power device provided in the embodiments of this application and power devices in related technologies;

[0027] Figure 3 A structural diagram of another power device provided in an embodiment of this application;

[0028] Figure 4 This is a structural diagram of another power device provided in an embodiment of this application;

[0029] Figure 5 A flowchart illustrating the fabrication process of the power device provided in this application embodiment;

[0030] Figure 6 for Figure 5 The detailed flowchart of step S3;

[0031] Figures 7-15 The diagram shows the steps of the preparation process provided in the embodiments of this application. Detailed Implementation

[0032] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0033] In a first aspect, embodiments of this application provide a power device. Figure 1 A structural diagram of a power device provided in an embodiment of this application is shown below. Figure 1 As shown, the power device 4 is an insulated-gate bipolar transistor (IGBT). For example, the power device 4 can also be a fast recovery diode (FRD) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The power device 4 includes multiple cell structures 2 and a termination structure 1 as shown in any of the following embodiments. Along the first direction X, the termination structure 1 is disposed on the outside of the multiple cell structures 2. The power device 4 provided in this application embodiment has improved voltage withstand performance and reliability.

[0034] Secondly, embodiments of this application provide a terminal structure 1 that can be applied to a power device 4. Figure 2 A voltage withstand comparison diagram between the power device provided in the embodiments of this application and power devices in related technologies; Figure 3 A structural diagram of another power device provided in an embodiment of this application; Figure 4 This is a structural diagram of another power device provided in an embodiment of this application.

[0035] like Figure 1 As shown, the terminal structure 1 includes a drift layer 10, an equipotential ring 11, a first insulating layer 12, a gate transition structure 13, a second insulating layer 14, and a gate line 15. The drift layer 10 includes a first surface 101 and a second surface 102 facing each other. A gate trench is provided on the first surface 101, and the second surface 102 can contact the substrate. Exemplarily, the conductivity type of the drift layer 10 can be N-type or P-type. The embodiments of this application are described using the N-type conductivity type of the drift layer 10 as an example.

[0036] The equipotential ring 11 extends from the first surface 101 into the drift layer 10. The equipotential ring 11 is located near the cell structure 2 in the terminal structure 1 to reduce the electric field concentration at the edge of the power device 4, thereby improving the withstand voltage capability of the power device 4 and optimizing the electric field distribution, thereby improving the overall performance and reliability of the power device 4.

[0037] A first insulating layer 12 is disposed on a first surface 101, and a gate transfer structure 13 is disposed on the side of the first insulating layer 12 away from the drift layer 10. The first insulating layer 12 includes a first part 121 and a second part 122. The orthographic projection of the first part 121 on the first surface 101 does not overlap with the orthographic projection of the gate transfer structure 13 on the first surface 101. That is, along the first direction X, the first part 121 is located to the left of the gate transfer structure 13. The first part 121 includes a portion disposed on the first surface 101 and a portion located in the gate trench. The orthographic projection of the second part 122 on the first surface 101 is located within the range of the orthographic projection of the gate transfer structure 13 on the first surface 101. That is, along the direction Z, the second part 122 is located below the gate transfer structure 13. The maximum thickness of the first part 121 is less than the maximum thickness of the second part 122. It can be understood that, along the Z direction, the maximum thickness of the portion of the first part 121 disposed on the first surface 101 and the portion of the first part 121 located at the bottom of the gate trench is less than the maximum thickness of the second part 122. In addition, the maximum thickness of the portion of the first part 121 located on the inner sidewall of the gate trench along the first direction X is less than the maximum thickness of the second part 122 along the Z direction.

[0038] The second insulating layer 14 is disposed on the side of the gate transition structure 13 away from the drift layer 10, and the second insulating layer 14 covers the gate transition structure 13 and the first insulating layer 12. For example, the first insulating layer 12 and the second insulating layer 14 are made of the same material, silicon oxide. The gate line 15 is disposed on the side of the second insulating layer 14 away from the drift layer 10. For example, along the Z direction, the gate line 15 can be disposed above the gate transition structure 13, and the gate line 15 is electrically connected to the gate transition structure 13.

[0039] In this embodiment, the terminal structure 1 includes an equipotential ring 11, a first insulating layer 12, a gate transition structure 13, a second insulating layer 14, and a gate line 15. The equipotential ring 11 extends from the first surface 101 of the drift layer 10 into the drift layer 10. The first insulating layer 12 is disposed on the first surface 101. The gate transition structure 13 is also disposed on the side of the first insulating layer 12 away from the drift layer 10. The gate line 15 is electrically connected to the gate transition structure 13. During the turn-off process of the power device 4 including the terminal structure 1, there is carrier accumulation and current flow in the equipotential ring 11. Therefore, there is a voltage difference between the gate transition structure 13 and the equipotential ring 11.

[0040] Furthermore, the first insulating layer 12 includes a first part 121 and a second part 122. The orthographic projection of the first part 121 on the first surface 101 does not overlap with the orthographic projection of the gate transition structure 13 on the first surface 101. The orthographic projection of the second part 122 on the first surface 101 is located within the range of the orthographic projection of the gate transition structure 13 on the first surface 101. That is, the second part 122 is located between the gate transition structure 13 and the equipotential ring 11, thereby achieving electrical isolation between the gate transition structure 13 and the equipotential ring 11. When the potential of the equipotential ring 11 increases, the voltage difference between the gate transition structure 13 and the equipotential ring 11 increases. By setting the maximum thickness of the first part 121 to be less than the maximum thickness of the second part 122, that is, by setting the portion of the first insulating layer 12 located between the gate transition structure 13 and the equipotential ring 11 to be thicker, the voltage difference that the gate transition structure 13 and the equipotential ring 11 can accommodate is larger. This can reduce the failure rate of the second part 122, improve the reliability of the first insulating layer 12 between the gate transition structure 13 and the equipotential ring 11, thereby improving the withstand voltage performance of the termination structure 1, and further improving the reliability of the power device 4 including the termination structure 1.

[0041] In some embodiments, such as Figure 1 As shown, the first part 121 includes a third surface 123 in contact with the first surface 101, and the second part 122 includes a fourth surface 124 in contact with the first surface 101. At least a portion of the fourth surface 124 is located on the side of the third surface 123 closest to the second surface 102. In this embodiment, along the plane XY, with the second surface 102 as a reference, a portion of the fourth surface 124 closest to the third surface 123 is connected to the third surface 123 and is in the same plane. The remaining portion of the fourth surface 124 is located below the third surface 123, and at least a portion of the surface of the second part 122 opposite to the fourth surface 124 is located above the surface of the first part 121 opposite to the third surface 123. That is, along the direction Z, the thickness of the second part 122 is greater than the thickness of the first part 121. The thicker second part 122 can withstand a larger voltage difference between the gate transition structure 13 and the equipotential ring 11, thus improving the reliability of the first insulating layer 12.

[0042] like Figure 2 As shown, with the increase of drain voltage (in volts / V), it has... Figure 1The drain current ID (in amperes / A) of the power device with the terminal structure 1 shown in the illustration rises vertically when the drain voltage is 875V. That is, the breakdown voltage of the power device 4 with the terminal structure 1 provided in this embodiment is 877V, while the breakdown voltage of power devices with terminal structures in related technologies is only 539V. This further illustrates that the potential of the equipotential ring 11 of the terminal structure 1 provided in this embodiment is more stable, and the withstand voltage performance of the power device 4 with the terminal structure 1 is significantly improved, thereby improving the reliability of the power device 4.

[0043] In some embodiments, such as Figure 1 As shown, the maximum thickness of the second part 122 ranges from 5000 angstroms to 50000 angstroms. For example, along the Z direction, the thickness of the second part 122 can be 5000 angstroms, 16250 angstroms, 27500 angstroms, 38750 angstroms, or 50000 angstroms. When the thickness of the second part 122 is within the range of 5000 angstroms to 50000 angstroms, not only is the withstand voltage performance of the terminal structure 1 improved, but the stability and reliability of the power device 4 including the terminal structure 1 can also be improved.

[0044] In some embodiments, such as Figure 1 As shown, the terminal structure 1 also includes a dummy gate 16. For example, two trench gates 18 are provided in the cell region 2. Along the first direction X, the dummy gate 16 is located outside the trench gates 18. The dummy gate 16 extends from the first surface 101 into the drift layer 10 and is located inside the equipotential ring 11. In this embodiment, the dummy gate 16 is provided on the side of the equipotential ring 11 near the trench gates 18, so that when the power device switches, the holes (positive ions) in the drift layer 10 are moved away from the equipotential ring 11 under the control of the dummy gate 16, thereby reducing the rise in the potential of the equipotential ring 11 and keeping the equipotential ring 11 stably at a low potential. This prevents the second part 122 from failing due to a large voltage difference, thereby improving the withstand voltage performance and reliability of the second part 122.

[0045] In some embodiments, such as Figure 3 As shown, the terminal structure 1 includes multiple virtual gates 16. Figure 2 The diagram illustrates a terminal structure 1 comprising a first dummy gate 161 and a second dummy gate 162. Multiple dummy gates 16 are spaced apart along a first direction X from the inside out, parallel to the first surface 101. By increasing the number of dummy gates 16, holes within the drift layer 10 can be further moved away from the equipotential ring 11 under the control of the dummy gates 16, thereby reducing the potential rise of the equipotential ring 11 to a greater extent. This improves the withstand voltage performance and reliability of the second part 122, and consequently enhances the withstand voltage performance and reliability of the power device equipped with the terminal structure 1.

[0046] In some embodiments, such as Figure 1 and Figure 3 As shown, the number of virtual gates 16 ranges from 1 to 3, meaning that the number of virtual gates can be set to 1, 2, or 3. Figure 1 The number of virtual gates 16 shown in Figure 1 is 1, and the number of virtual gates 16 shown in Figure 2 is 2. When the number of virtual gates 16 is set to 1 to 3, the holes are moved away from the equipotential ring 11, and the electric field distribution in the equipotential ring 11 is made uniform, effectively reducing the rise of the potential of the equipotential ring 11.

[0047] For example, along the first direction X, the distance between the rightmost side of the first virtual gate 161 and the left side of the second virtual gate 162 ranges from 4,000 angstroms to 60,000 angstroms, that is, the distance between any two virtual gate structures 16 can be 4,000 angstroms, 18,000 angstroms, 32,000 angstroms, 46,000 angstroms or 60,000 angstroms.

[0048] In some embodiments, such as Figure 1 , Figure 3 and Figure 4 As shown, the terminal structure 1 also includes a well region 104, which extends from the first surface 101 into the drift layer 10 and is located on at least one side of the dummy gate 16. The type of ions injected into the well region 104 is different from that of the drift layer 10. When the conductivity type of the drift layer 10 is N-type, the type of ions injected into the well region 104 is P-type, so the well region 104 can also be called a "P-well". The well region 104, which forms a floating P-well structure on at least one side of the dummy gate 16, can store holes, further reducing the potential of the equipotential ring 11, thereby improving the withstand voltage performance and reliability of the power device 4 equipped with the terminal structure 1.

[0049] like Figure 1 and Figure 3 As shown, along the first direction X, the well region 104 is located outside the dummy gate 16. In the terminal structure 1, the well region 104 is located on the side of the dummy gate 16 (second dummy gate 162) away from the trench gate 18. A well region also exists in the cell structure 2, located between the two trench gates 18. Along the direction Z, the ion implantation depth of the well region 104 in the terminal structure 1 is greater than the ion implantation depth of the well region in the cell structure 2. Figure 4 As shown, along the first direction X, the well region 104 is located on both the inner and outer sides of the dummy gate 16, and the ion implantation depth of the well region 104 located on the outer side of the dummy gate 16 is greater than the ion implantation depth of the well region 104 located on the inner side of the dummy gate 16.

[0050] In some embodiments, such as Figure 1 , Figure 3 and Figure 4As shown, the terminal structure 1 also includes a first electrode 17, which is disposed on the side of the second insulating layer 14 away from the drift layer 10. A through-hole 171 is provided in both the first insulating layer 12 and the second insulating layer 14, extending into the equipotential ring 10. The first electrode 17 is electrically connected to the equipotential ring 10 via the first contact hole 171. The first contact hole 171 increases the contact area between the first electrode 17 and the equipotential ring 10, accelerating the discharge of holes within the equipotential ring 11 region, thereby reducing the potential rise of the equipotential ring 11 and improving the withstand voltage performance and reliability of the power device 4 with the terminal structure 1.

[0051] In some embodiments, such as Figure 4 As shown, a through second contact hole 172 is also provided in the first insulating layer 12 and the second insulating layer 14. The first electrode 17 is also electrically connected to the well region 104 through the second contact hole 172. It can be understood that the first electrode 17 is electrically connected to the well region 104 between the dummy gate 16 and the trench gate 18 through the second contact hole 172. The first electrode 17 is also electrically connected to the well region 104 on the side of the dummy gate 16 away from the trench gate 18 through the first contact hole 171. The provision of the second contact hole 172 further increases the electrical conductivity of the well region 104. The contact area between the first electrode 17 and the equipotential ring 10 is such that, along the first direction X, the width of the first contact hole 171 is 8 to 10 times the width of the second contact hole 172. The narrower second contact hole 172 leads out the holes located between the dummy gate 16 and the trench gate 18, while the wider first contact hole 171 leads out the holes located outside the dummy gate 16. This helps to stabilize the potential of the equipotential ring 11, keeping its potential at a lower level, thereby improving the withstand voltage performance and reliability of the power device 4 equipped with the termination structure 1.

[0052] Thirdly, embodiments of this application also provide a method for preparing a terminal structure. Figure 5 A flowchart illustrating the fabrication process of the terminal structure provided in this application embodiment; Figure 6 for Figure 5 The detailed flowchart of step S3; Figures 7-15 The diagram shows the steps of the preparation process provided in the embodiments of this application.

[0053] like Figure 5 As shown, the preparation method includes the following steps S1 to S6:

[0054] Step S1: As Figure 7 As shown, a drift layer 10 is formed. The drift layer 10 includes a first surface 101 and a second surface 102 facing each other. The conductivity type of the drift layer 10 can be N-type or P-type. The embodiments of this application are described with the drift layer 10 having an N-type conductivity type as an example.

[0055] Step S2: As Figure 8As shown, an equipotential ring 11 is formed, which extends from the first surface 101 into the drift layer 10. The equipotential ring 11 includes a well region 104 formed by ion implantation and a high-temperature process. The conductivity type of the well region 104 is different from that of the drift layer 10. For example, P-type ions can be implanted into the well region 104, so the well region 104 can also be called a "P-type well region (P-well)".

[0056] Step S3: As Figures 9-12 As shown, a first insulating layer 12 is formed on the first surface 101. The first insulating layer 12 includes a first part 121 and a second part 122. The thickness of the first part 121 is less than the thickness of the second part 122. That is, along the direction Z, the maximum thickness of the portion of the first part 121 disposed on the first surface 101 is less than the maximum thickness of the second part 122.

[0057] In some embodiments, the first surface 101 includes a first region M and a second region N, wherein the second region N is located outside the first region M. For example... Figure 6 As shown, the formation of the first insulating layer 12 in step S3 specifically includes the following steps S301 to S304:

[0058] Step S301: As Figure 9 As shown, a protective layer 3 is formed, which covers the first region M and exposes the second region N.

[0059] Step S302: As Figure 10 As shown, a thermal oxidation process is used to form the second part 122 in the second region N. The drift layer 10 is made of silicon. Under certain process conditions, the silicon in the second region N, which is not covered by the protective layer 3, is oxidized at high temperature to form silicon oxide (SiO2), thus forming the second part 122. Due to the difference between the crystal structure of silicon oxide and the crystal structure of silicon, the thickness of the silicon in the second region N increases along the Z direction after it becomes silicon oxide, resulting in an irregular morphology.

[0060] Step S303: As Figure 11 As shown, the protective layer 3 is removed, exposing the first region M, and a trench 160 is formed on the side of the first region M away from the second region N.

[0061] Step S304: As Figure 12 As shown, a thermal oxidation process under different process conditions than that used to form the second part 122 is employed to form the first part 121 in the first region M, such that the thickness of the first part 121 is less than the thickness of the second part 122 along the direction Z, and the first part 121 and the second part 122 together form the first insulating layer 12.

[0062] The first insulating layer 12, formed by two thermal oxidation processes, has a second part 122 with a thickness greater than the first part 121, which gives the second part 122 better insulation and pressure resistance.

[0063] Step S4: As Figure 13 As shown, a gate transition structure 13 is formed. The gate transition structure 13 is located on the side of the first insulating layer 12 away from the drift layer 10. In this embodiment, the gate transition structure 13 is located on the side of the second part 122 away from the drift layer 10. For example, the gate transition structure 13 is polycrystalline silicon. The orthographic projection of the first part 121 on the first surface 101 does not overlap with the orthographic projection of the gate transition structure 13 on the first surface 101. That is, along the first direction X, the first part 121 is located to the left of the gate transition structure 13. The first part 121 includes a portion disposed on the first surface 101 and a portion located within the trench 160. The orthographic projection of the second part 122 on the first surface 101 is within the range of the orthographic projection of the gate transition structure 13 on the first surface 101. That is, along the direction Z, the second part 122 is located below the gate transition structure 13.

[0064] The first insulating layer 12 formed by the above steps has a maximum thickness of the first part 121 that is less than the maximum thickness of the second part 122. It can be understood that, along the Z direction, the maximum thickness of the part of the first part 121 disposed on the first surface 101 and the part of the first part 121 located at the bottom of the gate trench is less than the maximum thickness of the second part 122. Also, the maximum thickness of the part of the first part 121 located on the inner sidewall of the gate trench along the first direction X is less than the maximum thickness of the second part 122 along the Z direction.

[0065] In some embodiments, after forming the gate transition structure 13, as Figure 14 As shown, the above-mentioned preparation method further includes ion implantation within the cell structure 2 to form a well region and a source region 103 in the device region. The conductivity type of the well region is P-type, and the conductivity type of the source region 103 is N-type. Along the Z direction, the depth of ion implantation in the well region 104 is greater than the depth of ion implantation in the source region 103.

[0066] Step S5: As Figure 15 As shown, a second insulating layer 14 is formed. The second insulating layer 14 is located on the side of the gate transition structure 13 away from the drift layer 10. In this embodiment, the second insulating layer 14 covers the surface of the gate transition structure 13 and the first part 121 away from the drift layer 10. The second insulating layer 14 and the first insulating layer 12 are made of the same material, which is silicon oxide.

[0067] Step S6: Form the gate line 15 and the first electrode 17 to form as shown in the figure. Figure 1 The power device 4 shown includes a termination structure 1. The gate line 15 and the first electrode 17 are located on the side of the second insulating layer 14 away from the drift layer 10. In this embodiment, along direction Z, the gate line 15 is located on the side of the second insulating layer 14 away from the drift layer 10 and above the gate transition structure 13, which facilitates the electrical connection between the gate line 15 and the gate transition structure 13. A through-hole 171 is provided in the first insulating layer 12 and the second insulating layer 14. The first electrode 17 is electrically connected to the well region 104 in the termination structure 1 through the first contact hole 171. When the power device 4 with the termination structure 1 is forward-biased, the first contact hole 171 drains the holes located in the equipotential ring 11, which helps stabilize the potential of the equipotential ring 11, keeping its potential at a lower level, thereby improving the withstand voltage performance and reliability of the power device 4 with the termination structure 1.

[0068] The preparation method provided in this application embodiment forms a drift layer 10, then an equipotential ring extending from the first surface 101 into the drift layer 10, and a first insulating layer 12 is formed on the first surface 101. The first insulating layer 12 includes a first part 121 and a thicker second part 122. The gate transition structure 13 is located on the side of the first insulating layer 12 away from the drift layer 10. The orthographic projection of the first part 121 on the first surface 101 does not overlap with the orthographic projection of the gate transition structure 13 on the first surface 101. The orthographic projection of the second part 122 on the first surface 101 is within the range of the orthographic projection of the gate transition structure 13 on the first surface 101, that is, the gate transition structure 13 is formed on the side of the second part 122 away from the drift layer 10 and covers the second part 122.

[0069] During the turn-off process, carriers accumulate and current flows within the equipotential ring 11 of the power device 4, including the terminal structure 1. Therefore, there is a voltage difference between the gate transition structure 13 and the equipotential ring 11. Since the portion of the first insulating layer 12 located between the gate transition structure 13 and the equipotential ring 11 is thicker, the voltage difference that can be accommodated between the gate transition structure 13 and the equipotential ring 11 is larger. This can reduce the failure rate of the second part 122, improve the reliability of the first insulating layer 12 between the gate transition structure 13 and the equipotential ring 11, thereby improving the withstand voltage performance of the terminal structure 1, and further enhancing the reliability and withstand voltage performance of the power device 4 including the terminal structure 1.

[0070] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A terminal structure, characterized in that, include: The drift layer includes opposing first and second surfaces; An equipotential ring extends from the first surface into the drift layer; A first insulating layer is disposed on the first surface; A gate junction structure is disposed on the side of the first insulating layer away from the drift layer; A second insulating layer is disposed on the side of the gate junction structure away from the drift layer; A gate line is disposed on the side of the second insulating layer away from the drift layer, and the gate line is electrically connected to the gate junction structure. The first insulating layer includes a first part and a second part. The orthographic projection of the first part on the first surface does not overlap with the orthographic projection of the gate transition structure on the first surface. The orthographic projection of the second part on the first surface is within the range of the orthographic projection of the gate transition structure on the first surface. The maximum thickness of the first part is less than the maximum thickness of the second part.

2. The terminal structure according to claim 1, characterized in that, The first part includes a third surface in contact with the first surface, and the second part includes a fourth surface in contact with the first surface; At least a portion of the fourth surface is located on the side of the third surface closest to the second surface.

3. The terminal structure according to claim 1, characterized in that, The maximum thickness of the second part ranges from 5,000 angstroms to 50,000 angstroms.

4. The terminal structure according to claim 1, characterized in that, The terminal structure further includes a dummy gate that extends from the first surface into the drift layer and is located inside the equipotential ring.

5. The terminal structure according to claim 4, characterized in that, The terminal structure includes a plurality of virtual gates, which are arranged at intervals along a first direction from the inside out, and the first direction is parallel to the first surface.

6. The terminal structure according to claim 4, characterized in that, The number of virtual gates ranges from 1 to 3.

7. The terminal structure according to any one of claims 4 to 6, characterized in that, The terminal structure further includes a trap region extending from the first surface into the drift layer, and the trap region is located on at least one side of the virtual gate.

8. The terminal structure according to claim 7, characterized in that, The terminal structure further includes a first electrode, which is disposed on the side of the second insulating layer away from the drift layer; The first insulating layer and the second insulating layer are provided with a through first contact hole, and the first electrode is electrically connected to the equipotential ring through the first contact hole.

9. The terminal structure according to claim 8, characterized in that, The first insulating layer and the second insulating layer are further provided with a through second contact hole, and the first electrode is also electrically connected to the well region through the second contact hole; Along a first direction from the inside out, the width of the first contact hole is 8 to 10 times the width of the second contact hole, and the first direction is parallel to the first surface.

10. A method for preparing a terminal structure, characterized in that, include: A drift layer is formed, the drift layer comprising opposing first and second surfaces; An equipotential ring is formed, the equipotential ring extending from the first surface into the drift layer; A first insulating layer is formed on the first surface. The first insulating layer includes a first part and a second part, and the thickness of the first part is less than the thickness of the second part. A gate transition structure is formed, wherein the gate transition structure is located on the side of the first insulating layer away from the drift layer; The orthographic projection of the first part on the first surface does not overlap with the orthographic projection of the gate transition structure on the first surface, and the orthographic projection of the second part on the first surface is within the range of the orthographic projection of the gate transition structure on the first surface. A second insulating layer is formed, the second insulating layer being located on the side of the gate transition structure away from the drift layer; A gate line is formed, the gate line being located on the side of the second insulating layer away from the drift layer, and the gate line being electrically connected to the gate transition structure.

11. The preparation method according to claim 10, characterized in that, The first surface includes a first region and a second region, wherein the second region is located outside the first region; Forming the first insulating layer includes: A protective layer is formed, which covers the first area and exposes the second area; The second part is formed in the second region using a thermal oxidation process; Remove the protective layer; The first part is formed in the first region using a thermal oxidation process.

12. A power device, characterized in that, include: Multiple cell structures; The terminal structure as described in any one of claims 1 to 9 is disposed on the outside of the plurality of cell structures.

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