A reconfigurable hybrid-based FFT processor based on the CORDIC algorithm

Abstract

This invention relates to a reconfigurable hybrid-radix FFT processor based on the CORDIC algorithm, belonging to the field of reconfigurable FFT computing technology. It addresses the technical problems of traditional FFT processors, such as insufficient flexibility, high power consumption, low accuracy, and difficulty in adapting to diverse application scenarios. The technical solution includes a configuration information generation module, a multi-level multi-radix FFT computing module, and a two-radix FFT computing module. It employs a novel CORDIC algorithm that removes compensation factors, supporting hybrid-radix butterfly operations (radix 2, 3, 4, and 5), and dynamically reconfigures to adapt to different point count requirements. The technical advantages are reflected in ultra-high flexibility, low power consumption, high accuracy, and efficient utilization of hardware resources.

Description

Technical Field

[0001] This invention belongs to the field of FFT computation reconfigurable technology, specifically relating to a reconfigurable hybrid-based FFT processor based on the CORDIC algorithm. Background Technology

[0002] The Fast Fourier Transform (FFT), as an efficient implementation algorithm of the Discrete Fourier Transform (DFT), has always been a core technology in the field of digital signal processing. Its hardware-implemented FFT processors have become an indispensable key component in modern communication systems. With the rapid development of next-generation information technology, various application scenarios have placed higher demands on signal processing systems, exhibiting a quadruple iterative trend of high speed, high precision, low power consumption, and high flexibility. In the field of sixth-generation mobile communication technology, the extreme pursuit of spectrum utilization and transmission rate necessitates that FFT processors support variable-length transforms from 256 points to 4096 points or even higher, while requiring single transforms to be completed within nanoseconds. In portable smart devices and aerospace, limited energy supply places stringent requirements on processor power density, making low power consumption and high energy efficiency core design indicators. In multi-mode communication and software-defined radio systems, processors need to adapt to the transform length and precision requirements under different communication protocols and possess reconfigurability to improve hardware reuse.

[0003] Current Fast Fourier Transform (FFT) processor designs primarily face a trade-off between the choice of transform basis and hardware implementation. While traditional radix-2 algorithms are simple in structure and easy to pipeline, they are inefficient when processing transforms of integer powers other than 2. Higher-order radix-4 and radix-8 algorithms, although reducing the number of operations and power consumption, significantly increase hardware complexity and reduce flexibility. Hybrid-radix FFT algorithms, such as radix-2, radix-4, and radix-8 hybrid schemes, can balance efficiency and complexity by adapting to different point count requirements; however, traditional hybrid-radix architectures have poor configuration flexibility and struggle to adapt to diverse scenarios. In particular, multi-size hybrid-radix computing architectures require storing multiple sets of configuration information and twiddle factors, resulting in enormous storage resource consumption.

[0004] Coordinate-rotating digital computer algorithms offer an effective technical approach to solving the aforementioned problems. These algorithms can perform operations such as approximate division and trigonometric function calculations through iteration, eliminating the need for dedicated multipliers and requiring only adders and shifters to complete the computation, significantly reducing hardware resource consumption and power consumption. However, traditional coordinate-rotating digital computer algorithms suffer from complex compensation factor calculations and slow convergence speeds. Therefore, researching a reconfigurable hybrid-basis fast Fourier transform processor based on an improved coordinate-rotating digital computer algorithm to address the issues of insufficient flexibility, excessive power consumption, and the imbalance between accuracy and efficiency in existing designs has significant theoretical research value and promising engineering application prospects. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a reconfigurable hybrid-radix FFT processor based on the CORDIC algorithm, which can dynamically adapt to FFT computation requirements with different numbers of points and different radixes.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The reconfigurable hybrid basis FFT processor based on the CORDIC algorithm in this invention includes a configuration information generation module, an L-level multi-basis FFT calculation module, and a first-level bi-basis FFT calculation module. The configuration information generation module generates configuration information based on the CORDIC algorithm and the input FFT parameters. The configuration information loaded into the sixth-level FFT calculation module works with the calculation control unit to complete the reconstruction task of the FFT calculation module. The multi-radix FFT calculation module includes a calculation control unit, a storage unit, a multi-radix butterfly calculation unit, a twitch factor generation unit, and a multiplication unit; The bi-base FFT calculation module includes a calculation control unit, a storage unit, and a bi-base butterfly calculation unit.

[0007] Furthermore, the CORDIC algorithm employs a new set of micro-rotation angles, eliminating the computation of compensation factors. The definition of the micro-rotation angle is given by (1).

[0008] (1) in It is the first The angle of the sub-micro rotation It is the first The angle of the sub-micro rotation. The corresponding sine and cosine values ​​are given by formula (2).

[0009] (2) The coordinate transformation before and after rotation is given by (3).

[0010] (3) in Control the first i The direction of the next rotation Represents counterclockwise rotation , Represents clockwise rotation .

[0011] Furthermore, the configuration information generation module adopts a hardware architecture design, specifically consisting of 3 data selectors, 2 right shifters, 2 left shifters, 1 configurable constant divider, and 1 adder. The core function of this configuration information generation module is to complete L+1 iterations, with each iteration generating a set of configuration parameter information. The configuration parameter information specifically includes the number of group points M, and four parameters calculated based on the number of group points M: M / R, 2M / R, 3M / R, and 4M / R (where R is a preset base). Further, the configuration parameter information generated by the m-th iteration will be loaded into the corresponding m-th level FFT calculation module. It should be noted that the number of group points M corresponding to the first-level FFT calculation module is taken as the total number of points N in the FFT operation.

[0012] The configurable constant divider supports dynamic switching between two operating modes: a 3-integer divider and a 5-integer divider. Its operation mode is selected by a pre-configured control signal.

[0013] The configurable constant divider is designed based on the CORDIC algorithm: Expand the original dividend m The number of decimal places is used as the initial x-coordinate for the integer division algorithm. x 0, initial y-coordinate y Set 0 to 0. The coordinates after micro-rotation are obtained through matrix operations in formula (1).

[0014] The operation of dividing the input data by 3 or 5 is converted into the input data and its corresponding decimal. Multiplication; let Using the approximation concept of micro-angle superposition, Divide into several approximate summation results of micro-rotation angles defined by (1), i.e., formula (4).

[0015] (4) in Based on the above design, the configurable constant divider can be implemented using simple addition, subtraction, and shift operations. Furthermore, to enable the deployment of integer dividers corresponding to the two divisors (3 and 5) on the same circuit, the core parameters of the two dividers should be kept as consistent as possible. To maintain consistency and improve the structural similarity between the two dividers, thereby achieving resource reuse, formula (5) is derived: (5) Furthermore, in the multi-base FFT calculation module, the calculation control unit monitors the working status of the storage unit, the butterfly calculation unit, the twitch factor generation unit, and the multiplication unit; The storage unit includes a two-dimensional FIFO buffer, which adopts a hierarchical cascaded architecture; the first layer, the group-level parallel layer, includes four independent FIFO groups, which use a parallel access mode between the groups; the second layer, the complex data separation layer, includes two dedicated FIFOs, which are used to store the real and imaginary parts of the complex data respectively; the read and write addresses of the storage unit are generated by Gray code; the storage unit can realize the storage reuse of input data and butterfly calculation results; The multi-base butterfly computing unit is compatible with four base modes, supporting radix-2, radix-3, radix-4, and radix-5 butterfly operations. By reconfiguring its circuit topology and input / output ports, it enables switching between different base modes. Specifically, the circuit topology is reconfigured using seven data selectors. The input / output port reconfiguration includes two core aspects: first, reordering the input / output port numbers according to the port mapping rules corresponding to different base operation modes; second, configuring the input signals of redundant input ports to 0 level to ensure the stability of the circuit operation and the accuracy of the calculation results under each base operation mode. Furthermore, the multi-base butterfly computing unit employs a pipelined architecture design, specifically divided into four pipeline stages, to ensure the efficiency and continuity of the computation process.

[0016] The rotation factor generation unit includes an angle generation unit, an angle preprocessing unit, a six-level micro-rotation unit, and an angle restoration unit. The angle generation unit receives the input initial angle and continuously generates target angles according to the angle accumulation rules corresponding to different base modes. The number of generated target angles is controlled by the number of group points M. The angle preprocessing unit performs range compression processing on the target angles and generates corresponding compressed codes. The six-level micro-rotation unit performs matrix transformation operations to obtain the initial sine and initial cosine values ​​corresponding to the target angles. The angle restoration unit swaps or inverts the initial sine and initial cosine values ​​based on the compressed codes to obtain the final sine and cosine values.

[0017] The micro-rotation unit adopts the CORDIC algorithm architecture and utilizes a multi-level micro-rotation iteration mechanism. The first-level micro-rotation configures the rotation angle. Furthermore, the rotation determination rule is based on the input angle. When the angle exceeds the threshold by 16°, a counter-clockwise rotation is performed, and the subsequent five micro-rotation settings configure the rotation angle. At the same time, set a pair of threshold angles Furthermore, the rotation angle determination rule is based on comparing the absolute value of the remaining angle with the threshold angle, while the rotation direction determination rule is based on the sign of the remaining angle. This approach accelerates convergence while maintaining computational accuracy, and the rotation factor generated from the FFT parameters can dynamically adapt to the computational needs of multi-specification FFTs.

[0018] The multiplication unit receives data from the storage unit and the rotation factor generation unit, performs calculations, and outputs the results to the next-level FFT calculation module.

[0019] Furthermore, the dual-radix FFT calculation module includes a calculation control unit, a storage unit, and a dual-radix butterfly calculation unit. The first-level group-parallel layer of the storage unit includes only three independent FIFO groups. The dual-radix butterfly calculation unit supports radix-2 and radix-4 butterfly operations. By reconfiguring its input and output ports, it can switch between different radix modes, a reconfiguration scheme similar to that of the aforementioned multi-radix butterfly calculation unit.

[0020] Furthermore, the computation control unit controls the FFT computation process according to the following strategy: The calculation control unit calculates the number of pre-input data. Number of input data Counting the number of butterfly shapes The system performs counting to monitor the computation status of the FFT computation module and coordinates with FFT parameters and configuration information to control the next computation state; the FFT parameters include the total number of points. N base mode R Number of groups G The configuration information includes the number of group points. M as well as M / R , 2M / R , 3M / R and 4M / R .

[0021] The FFT calculation process is performed serially in groups, with each group consisting of a data input stage, a butterfly calculation stage, a twitch factor generation stage, and a multiplication calculation stage.

[0022] Data input stage according to The value is divided into R input sub-stages, with input sub-stage 1 consisting of... The input data in this stage is stored in the group-level parallel layer FIFO group 1 of the storage unit; the input sub-stage 2 is... The input data in this stage is stored in the group-level parallel layer FIFO group 2 of the storage unit; the input sub-stage 3 is... The input data in this stage is stored in the group-level parallel layer FIFO group 3 of the storage unit; the input sub-stage 4 is... The input data for this stage is stored in the group-level parallel layer FIFO group 4 of the storage unit; the input sub-stage R is determined by... The input data at this stage is stored in the input port of the multi-base butterfly arithmetic unit; The butterfly computation stage coincides with the input sub-stage R in timing. During the butterfly computation stage, the multi-base butterfly computation unit adopts a parallel reading mechanism, reading R data points from the storage unit at once. Then, according to a preset mapping rule, the R data points are input to the R input ports of the multi-base butterfly computation unit to perform butterfly operations. After the operation is completed, one of the computation results is output to the next-level FFT computation module, while the remaining R-1 computation results are written back to the group-level parallel layer FIFO groups 1 to FIFO group (R-1) of the storage unit for temporary storage according to a preset feedback rule.

[0023] The twitch factor generation stage is composed of Specifically, in this stage, after receiving the input initial angle, the rotation factor generation unit continuously generates the target angle according to the angle accumulation rules corresponding to different base modes; the angle preprocessing unit performs range compression processing on the target angle and generates the corresponding compressed code; subsequently, after six levels of micro-rotation operations, the initial sine value and initial cosine value corresponding to the target angle are obtained; finally, the angle restoration unit swaps or inverts the initial sine value and initial cosine value based on the compressed code to obtain the final sine value and cosine value.

[0024] The multiplication calculation stage is composed of In this stage, the multiplication unit reads the data in the R groups of FIFOs in the storage unit in a preset timing sequence and multiplies it with the rotation factor output by the rotation factor generation unit; then the multiplication result is output to the next level FFT calculation module.

[0025] Furthermore, the bi-basic FFT calculation module is similar to the multi-basic FFT calculation module, and will not be described in detail here.

[0026] The beneficial effects of this invention are as follows: (1) This invention possesses excellent flexibility and reconfigurability. The processor can dynamically adapt to computational needs with different numbers of points and different radixes, supporting multiple butterfly operation modes from radix 2 to radix 5. This adaptive capability allows the processor to be widely used in various communication protocols and signal processing scenarios, and configuration switching can be completed without hardware replacement, greatly improving the applicability and practical value of the device.

[0027] (2) This invention demonstrates excellent power consumption control. By replacing the traditional multiplier unit with a coordinate rotation digital computer algorithm, hardware resource consumption and energy consumption are significantly reduced. The iterative characteristics of the algorithm itself, combined with simplified operational logic, enable the processor to achieve low power consumption while maintaining high performance, making it particularly suitable for energy-constrained portable devices and aerospace applications.

[0028] (3) The calculation accuracy is significantly improved. This invention introduces a new set of micro-rotation angles, which effectively eliminates the calculation step of the compensation factor and reduces the accumulation of calculation errors. The improved coordinate rotation digital computer algorithm ensures the accuracy of rotation factor generation through a multi-level micro-rotation iteration mechanism, thereby guaranteeing the calculation accuracy of the overall transformation process.

[0029] (4) The hardware structure has been optimized and simplified. The processor's configuration information generation module adopts an efficient iterative operation scheme, which can generate complex configuration parameters with only basic logic units. The hierarchical cascade architecture of the storage unit and the two-dimensional first-in-first-out cache design realize efficient data storage and reuse, reducing storage resource requirements. The pipeline design of the multi-base butterfly computing unit further improves the continuity and efficiency of data processing.

[0030] (5) This invention has good scalability and versatility. The modular design of the processor allows it to easily adapt to the needs of future technological development and support expansion to more cardinalities and points. This design concept lays a solid foundation for the further development of fast Fourier transform processors and has important engineering application prospects.

[0031] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the overall architecture of the reconfigurable hybrid-based FFT processor based on the CORDIC algorithm in an embodiment of the present invention; Figure 2 This is a schematic diagram of the configuration information generation module in an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the configurable constant divider in an embodiment of the present invention; Figure 4 This is a schematic diagram of two constant division calculation processes based on the CORDIC algorithm in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the multi-base FFT calculation module in an embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit structure of the multi-base butterfly computing unit in an embodiment of the present invention; Figure 7This is a schematic diagram of the rotation factor generation unit in an embodiment of the present invention; Figure 8 is a schematic diagram of the circuit structure of the first-level micro-rotation in the rotation factor generation unit in the embodiment of the present invention; Figure 8(a) is a circuit structure diagram of micro-rotation angle determination and remaining angle calculation; Figure 8(b) is a circuit structure diagram of micro-rotation coordinate transformation. Figure 9 is a schematic diagram of the circuit structure of the second to sixth level micro-rotation in the rotation factor generation unit in the embodiment of the present invention; Figure 9(a) is a circuit structure diagram of micro-rotation angle determination and remaining angle calculation; Figure 9(b) is a circuit structure diagram of the second and third level micro-rotation coordinate transformation; Figure 9(c) is a circuit structure diagram of the fourth to sixth level micro-rotation coordinate transformation. Figure 10 This is a schematic diagram of the structure of the bi-base FFT calculation module in an embodiment of the present invention; Figure 11 This is a schematic diagram of the circuit structure of the dual-base butterfly computing unit in an embodiment of the present invention. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0035] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0036] The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm provided in this embodiment has the following overall architecture: Figure 1 As shown, it specifically includes a configuration information generation module, an L-level multi-radix FFT calculation module, and a first-level bi-radix FFT calculation module. The reconfigurable hybrid-radix FFT processor adopts a pipelined architecture design, with data input and output serially; the data flow transmission path is as follows: the data to be processed flows sequentially through the L-level multi-radix FFT calculation module and the first-level bi-radix FFT calculation module.

[0037] The CORDIC algorithm provided in this embodiment is used to implement and optimize the circuit structure of the configurable constant divider in the configuration information generation module and the micro-rotation circuit structure in the rotation factor generation unit. The CORDIC algorithm adopts a new set of rotation angles and removes the calculation of the compensation factor. The definition formula of the micro-rotation angle is given by (1).

[0038] (1) in It is the first The angle of the sub-micro rotation It is the first The angle of the sub-micro rotation. The corresponding sine and cosine values ​​are given by formula (2).

[0039] (2) List based on (1) and (2) i Angles corresponding to 1 to 11 sine value Sum of cosine values As shown in Table 1.

[0040] Table 1. Micro-rotation angles and trigonometric function values

[0041] The coordinate transformation before and after rotation is given by (3).

[0042] (3) in , Represents counterclockwise rotation , Represents clockwise rotation .

[0043] The structure of the configuration information generation module provided in this embodiment is as follows: Figure 2 As shown, the initial number of group points M (i.e., the number of group points in the first-level FFT calculation module) is pre-stored in the buffer M; Figure 2The data in the five buffers shown is continuously refreshed during iterative calculations, and each FFT calculation module reads the data in the buffers in turn as configuration information. Figure 2 All three data selectors in the array use a base R as their control signal. Specifically, when the base R is 2, data selector 1 selects the data in buffer M as its input signal, while data selectors 2 and 3 both select 0 as their input signal. Figure 2 The one-bit right shifter shown (corresponding to the one in the figure) ), used to perform the operation of dividing the input data by 2; a configurable constant divider (corresponding to / 3 or / 5 in the figure) is used to perform the operation of dividing the input data by 3 or 5; a two-bit right shifter (corresponding to ... in the figure) This is used to perform a division operation on the input data by 4. After performing an OR operation on the output result of the above operation module, the result is stored in buffer M as the input data for the next iteration operation; simultaneously, the OR operation result is stored in buffer M / R as the configuration information M / R corresponding to this iteration; the result of the OR operation result after performing a one-bit left shift operation is stored in buffer 2M / R as the configuration information 2M / R corresponding to this iteration; the result of the OR operation result after performing an adder on 2M / R is stored in buffer 3M / R as the configuration information 3M / R corresponding to this iteration; the result of the OR operation result after performing a two-bit left shift operation is stored in buffer 4M / R as the configuration information 4M / R corresponding to this iteration. Furthermore, the circuit structure of the configurable constant divider provided in this embodiment is as follows: Figure 3 As shown in the diagram, all data selectors use the base R as the control signal. When the base R is 3, all data selectors activate input port 0, allowing a constant divider to be configured to divide the input data by 3. When the base R is 5, all data selectors activate input port 1, allowing a constant divider to be configured to divide the input data by 5. The circuit structure of the configurable constant divider is based on... Figure 4 The diagram shows two constant division calculation flow designs based on the CORDIC algorithm. Specific design details are as follows: In this embodiment, extending the original dividend to 4 decimal places is sufficient to meet the precision requirements of the integer division algorithm. The initial x-coordinate of the integer division algorithm... x 0 represents the result of extending the original dividend to 4 decimal places, and is the initial ordinate. y Set 0 to 0. The coordinates after micro-rotation are obtained through matrix operations in formulas (2) and (3).

[0044] The operation of dividing the input data by 3 or 5 is converted into the input data and its corresponding decimal. Multiplication; let Using the approximation concept of micro-angle superposition, Divide into several approximate summation results of micro-rotation angles defined by (1), i.e., formula (4).

[0045] (4) in Based on the above design, the configurable constant divider can be implemented using simple addition, subtraction, and shift operations. Furthermore, to enable the deployment of integer dividers corresponding to the two divisors (3 and 5) on the same circuit, the core parameters of the two dividers should be kept as consistent as possible. To maintain consistency and improve the structural similarity between the two dividers, thereby achieving resource reuse, formula (5) is derived: (5) Furthermore, the multi-base FFT calculation module provided in this embodiment, such as Figure 5 As shown, it includes a calculation control unit, a storage unit, a butterfly calculation unit, a rotation factor generation unit, and a multiplication unit.

[0046] The computation control unit provided in this embodiment controls the FFT calculation process according to the following strategy: The calculation control unit calculates the number of pre-input data. Number of input data Counting the number of butterfly shapes The system performs counting to monitor the computation status of the FFT computation module and coordinates with FFT parameters and configuration information to control the next computation state; the FFT parameters include the total number of points. N base mode R Number of groups G The configuration information includes the number of group points. M as well as M / R , 2M / R , 3M / R and 4M / R .

[0047] The FFT calculation process is performed serially in groups, with each group consisting of a data input stage, a butterfly calculation stage, a twitch factor generation stage, and a multiplication calculation stage.

[0048] Data input stage according to The value is divided into R input sub-stages, with input sub-stage 1 consisting of... The input data in this stage is stored in the group-level parallel layer FIFO group 1 of the storage unit; the input sub-stage 2 is... The input data in this stage is stored in the group-level parallel layer FIFO group 2 of the storage unit; the input sub-stage 3 is... The input data in this stage is stored in the group-level parallel layer FIFO group 3 of the storage unit; the input sub-stage 4 is... The input data for this stage is stored in the group-level parallel layer FIFO group 4 of the storage unit; the input sub-stage R is determined by... The input data at this stage is stored in the input port of the multi-base butterfly arithmetic unit; The butterfly computation stage coincides with the input sub-stage R in timing. During the butterfly computation stage, the multi-base butterfly computation unit adopts a parallel reading mechanism, reading R data points from the storage unit at once. Then, according to a preset mapping rule, the R data points are input to the R input ports of the multi-base butterfly computation unit to perform butterfly operations. After the operation is completed, one of the computation results is output to the next-level FFT computation module, while the remaining R-1 computation results are written back to the group-level parallel layer FIFO groups 1 to FIFO group (R-1) of the storage unit for temporary storage according to a preset feedback rule.

[0049] The twitch factor generation stage is composed of Specifically, in this stage, after receiving the input initial angle, the rotation factor generation unit continuously generates the target angle according to the angle accumulation rules corresponding to different base modes; the angle preprocessing unit performs range compression processing on the target angle and generates the corresponding compressed code; subsequently, after six levels of micro-rotation operations, the initial sine value and initial cosine value corresponding to the target angle are obtained; finally, the angle restoration unit swaps or inverts the initial sine value and initial cosine value based on the compressed code to obtain the final sine value and cosine value.

[0050] The multiplication calculation stage is composed of The process is further divided into four sub-stages. In each sub-stage, the multiplication unit sequentially reads the data from the R groups of FIFOs in the storage unit according to a preset timing sequence and multiplies it by the rotation factor output by the rotation factor generation unit. The result of the multiplication operation is then output to the next-level FFT calculation module. The first sub-stage is... The first stage is defined as follows: the multiplication unit reads data from FIFO group 1; the second sub-stage is... The limitation is that the multiplication unit in this stage reads data from FIFO group 2; the third sub-stage is... The limitation is that the multiplication unit in this stage reads data from FIFO group 3; the fourth sub-stage is... The limitation is that the multiplication unit reads data from FIFO group 4 at this stage; The storage unit provided in this embodiment includes a two-dimensional FIFO buffer, which adopts a hierarchical cascaded architecture; the first layer, the group-level parallel layer, includes four independent FIFO groups, and each group adopts a parallel access mode; the second layer, the complex data separation layer, includes two dedicated FIFOs, which are used to store the real part and the imaginary part of the complex data respectively; the read and write addresses of the storage unit are generated by Gray code; the storage unit can realize the storage reuse of input data and butterfly calculation results, and the data source written is controlled by the data selector; The multi-base butterfly computing unit circuit structure provided in this embodiment is as follows: Figure 6 As shown, by reconfiguring its circuit topology and input / output ports, dynamic adaptation functions for radix-2, radix-3, radix-4, and radix-5 butterfly operations are achieved. Specifically, the circuit topology reconstruction is implemented through seven data selectors; the input / output port reconstruction includes two core aspects: first, reordering the input / output port numbers according to the port mapping rules corresponding to different radix operation modes; second, configuring the input signals of redundant input ports to 0 level to ensure the stability of the circuit operation and the accuracy of the calculation results under each radix operation mode. The circuit topology reconstruction rules are shown in Table 2, and the input / output port reconstruction rules are shown in Table 3. Furthermore, the multi-radix butterfly computing unit adopts a pipelined architecture design, specifically divided into four pipeline stages, to ensure the efficiency and continuity of the computation process.

[0051] Table 3 Reconstruction Rules for Circuit Topology

[0052] Table 3 Reconfiguration rules for input / output ports

[0053] The structure of the rotation factor generating unit provided in this embodiment is as follows: Figure 7 As shown, it includes an angle generation unit, an angle preprocessing unit, a six-level micro-rotation unit, and an angle restoration unit.

[0054] Furthermore, the angle generation unit receives the input initial angle. Then, target angles are continuously generated according to the angle accumulation rules corresponding to different base patterns. The angle accumulation rule is determined by the number of data groups G, the number of data points in each group M, and the angle accumulation round A. The value of the angle accumulation round A is R-1, where R is the base. The angle accumulation rule for the first round is as follows: When R is 4, When R is 2, 3 or 5, ; Target angle The process continues until M target angles are generated, at which point the second round of angle accumulation begins. Or repeat the above process G times. The rules for the second round of angle accumulation are as follows: When R is 4, When R is 2, 3 or 5, ; Target angle The process continues until M target angles are generated, at which point the third round of angle accumulation begins. Or repeat the above process G times. The rules for the third round of angle accumulation are as follows: ; Target angle The process continues until M target angles are generated, at which point the fourth round of angle accumulation begins. Or repeat the above process G times. The rules for the fourth round of angle accumulation are as follows: ; Target angle Keep refreshing until M target angles are generated. During the angle accumulation calculation, angle errors accumulate continuously, causing a large deviation between the subsequently generated target angle and the true angle, thus severely impacting the calculation accuracy of the processor described in this invention. Therefore, the angle generation unit provided in this embodiment of the invention, upon receiving the initial angle... The data is represented using a fixed-point data format that combines 7 integer digits and 16 decimal digits. The 7 integer digits can fully cover the entire angle range from 0° to 360°, meeting the requirements for representing circumferential angles. The 16 decimal digits can strictly control the cumulative error in the angle accumulation process to within 0.0156.

[0055] Furthermore, the angle preprocessing unit performs angle range compression preprocessing on the target angle output by the angle generation unit and generates the corresponding compressed code; the target angle output by the angle generation unit has a value range of [value missing]. The angle preprocessing unit provided in this embodiment of the invention can preprocess angles that fall into... The target angle within the range is compressed to Within the preset interval, corresponding compressed codes are generated based on the interval mapping rules of angle compression and the symbols inherent in the rotation factor calculation formula. The specific interval mapping relationship and the generated compressed codes are shown in Table 4.

[0056] Table 4. Interval Mapping Relationships and Compression Encoding

[0057] Furthermore, the CORDIC micro-rotation unit generates the initial sine and cosine values ​​corresponding to the target angle by performing matrix transformation operations. The CORDIC micro-rotation unit provided in this embodiment adopts a six-level micro-rotation architecture design, and the specific execution rules for each level of micro-rotation are detailed in Table 5. The core design goal of the CORDIC micro-rotation unit designed in this embodiment is to converge the remaining angle to a preset error tolerance range through iterative calculations of multi-level micro-rotations. Simultaneously, to improve the overall iterative convergence rate, this embodiment specifically configures a pair of micro-rotation angles and a pair of threshold angles in each of the last five micro-rotation stages. The CORDIC micro-rotation unit receives the compressed angle values ​​and initializes the horizontal coordinate. The vertical axis is 1. It is 0.

[0058] Furthermore, regarding the specific execution logic of the six-level micro-rotation architecture, the first-level micro-rotation is configured with a preset rotation angle. Its rotation determination rule is: when the input angle is... greater than the threshold angle At that time, a counter-clockwise rotation operation is performed, with a rotation angle of _____. Otherwise, do not rotate. After performing the rotation operation, you will obtain new coordinate values. .

[0059] The last 5 micro-rotation stages are equipped with preset rotation angles. Its rotation determination rule is: when Angle greater than the threshold At that time, the rotation angle is ;when greater than the threshold angle And less than the threshold angle At that time, the rotation angle is ;when Angle less than the threshold It does not rotate. The direction of rotation is from... The sign determination, when When the clock is positive, perform a counter-clockwise rotation; when... When the value is negative, a clockwise rotation is performed. After completing the final rotation operation, the final coordinate values ​​are obtained. That is, the initial cosine value and the initial sine value.

[0060] Table 5 Rotation rules for sixth-order micro-rotations

[0061] The CORDIC micro-rotation unit provided in this embodiment adopts a six-stage micro-rotation architecture design. Figure 8 shows the circuit structure of the first-stage micro-rotation. This stage circuit includes two core functional sub-modules: one is the micro-rotation angle determination and remaining angle calculation circuit, the specific structure of which is shown in Figure 8(a). Input angle With threshold angle The comparator completes the comparison operation and generates the comparison result. . As the control signal for the digital selector, the remaining angle after the first stage of micro-rotation is output after the logic selection of the digital selector. Secondly, there is a micro-rotation coordinate transformation circuit, the specific structure of which is shown in Figure 8(b). As the control signal of the number selector, different coordinate transformation paths are selected to obtain the coordinates after the first micro-rotation. Figure 9 shows the unified circuit structure of the last five stages of micro-rotation. This circuit also includes two core sub-modules: angle determination and calculation, and coordinate transformation. The micro-rotation angle determination and remaining angle calculation circuit is shown in Figure 9(a). This sub-module receives the remaining angle output from the previous stage as the input angle. Take its absolute value and compare it with the threshold angle. and The comparison generates two independent comparison results. and Both serve as control signals for the digital selector, and after logical selection, they generate the remaining angle of the current stage. At the same time, The sign of the rotation is determined by comparing it with zero. Furthermore, the coordinate transformation circuits for the last five stages of micro-rotation are divided into two specific implementation forms based on the number of rotation stages: the structure of the second and third stage micro-rotation coordinate transformation circuits is shown in Figure 9(b), and the structure of the fourth to sixth stage micro-rotation coordinate transformation circuits is shown in Figure 9(c). In the above two types of coordinate transformation circuits, As a control signal for selecting the rotation angle As a control signal to determine whether to perform a rotation operation. This serves as the control signal for selecting the rotation direction. The final coordinate values ​​are obtained after the final stage of rotation is completed. That is, the initial cosine value and the initial sine value.

[0062] Furthermore, the angle restoration unit swaps or inverts the initial sine and cosine values ​​based on the compressed code to obtain the final sine and cosine values. The angle restoration rule consists of two steps: First, when the least significant bit of the compressed code is 1, the angle is restored... Perform the invert operation; otherwise, do nothing. When the middle bit of the compressed code is 1, perform the invert operation. Perform the invert operation; otherwise, do nothing. After the first step, you will obtain the intermediate restored result. The second step is to process the code when the highest bit of the compression code is 1. By performing the swap, the final restored result is obtained. Otherwise, no operation is performed, and the final restoration result is obtained. .

[0063] Furthermore, the multiplication unit receives data from the storage unit and the twitch factor generation unit, performs calculations, and outputs the results to the next-level FFT calculation module.

[0064] Furthermore, the bi-radical FFT calculation module includes a calculation control unit, a storage unit, and a bi-radical butterfly calculation unit, such as... Figure 10 As shown. The first-level parallel layer of the storage unit includes only three independent FIFO groups; the dual-base butterfly computing unit supports radix-2 and radix-4 butterfly operations, and its circuit structure is as follows. Figure 11 As shown. By reconfiguring its input and output ports, the function of switching between two base modes can be realized.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A reconfigurable hybrid-based FFT processor based on the CORDIC algorithm, characterized in that: It includes a configuration information generation module, an L-level multi-radical FFT calculation module, and a first-level bi-radical FFT calculation module. The configuration information generation module generates configuration information based on the CORDIC algorithm and the input FFT parameters. The multi-radical FFT calculation module includes a calculation control unit, a storage unit, a multi-radical butterfly calculation unit, a rotation factor generation unit, and a multiplication unit. The bi-radical FFT calculation module includes a calculation control unit, a storage unit, and a bi-radical butterfly calculation unit. The CORDIC algorithm uses a set of micro-rotation angles to remove the compensation factor. The CORDIC algorithm defines the set of micro-rotation angles using the following formula: in It is the first The angle of the sub-micro rotation It is the first The angle of the sub-micro rotation; The corresponding sine and cosine values ​​are given by the following formulas: The coordinate transformation before and after rotation is given by the following formula: in , Represents counterclockwise rotation , Represents clockwise rotation .

2. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 1, characterized in that: The configuration information generation module consists of three data selectors, two right shifters, two left shifters, a configurable constant divider, and an adder. The configuration information generation module completes L+1 iterations and generates a set of configuration parameter information in each iteration. The configurable constant divider supports dynamic switching between two working modes: a 3-integer divider and a 5-integer divider.

3. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 2, characterized in that: The configurable constant divider is designed based on the CORDIC algorithm, transforming the operation of dividing the input data by 3 or 5 into the operation of dividing the input data by a decimal. The operation of multiplication, where ,make and The result is approximately the sum of minute rotation angles: in For the division by 3 operation, there is For the division by 5 operation, there is .

4. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 1, characterized in that: The storage unit in the multi-radix FFT calculation module includes a two-dimensional first-in-first-out FIFO buffer and adopts a hierarchical cascaded architecture. The first layer of group-level parallelism includes four independent FIFO groups, and the second layer of complex data separation includes two dedicated FIFOs. The multi-radix butterfly calculation unit supports radix-2, radix-3, radix-4 and radix-5 butterfly operations and is internally divided into four pipeline stages. The rotation factor generation unit includes an angle generation unit, an angle preprocessing unit, a six-level micro-rotation unit and an angle restoration unit.

5. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 4, characterized in that: In the rotation factor generation unit, the six-level micro-rotation unit adopts the CORDIC algorithm architecture, which generates rotation factors through multi-level micro-rotation iterations. The first-level micro-rotation configures the rotation angle. Furthermore, the rotation determination rule is based on the input angle. When the angle exceeds the threshold by 16°, a counter-clockwise rotation is performed, and the subsequent five micro-rotation settings configure the rotation angle. At the same time, set a pair of threshold angles Furthermore, the rotation angle determination rule is based on comparing the absolute value of the remaining angle with the threshold angle, and the rotation direction determination rule is based on the sign of the remaining angle.

6. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 1, characterized in that: The calculation control unit calculates the number of pre-input data. Number of input data Counting the number of butterfly shapes Counting is performed to monitor the computation status of the FFT computation module. The FFT computation process includes a data input stage, a butterfly computation stage, a twitch factor generation stage, and a multiplication computation stage, which are performed serially in groups.

7. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 6, characterized in that: The data input stage is based on The values ​​are divided into R One input sub-stage; Input sub-stage 1 is Limited and R≥2; Input sub-stage 2 by Limited and R≥3; Input sub-stage 3 by Limited and R≥4; Input sub-stage 4 is Limited and R≥5; Input sub-stage R is limited; The butterfly calculation stage and the input sub-stage R coincide in time. The twitch factor generation stage is composed of limited; The multiplication calculation stage is composed of limited.

8. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 1, characterized in that: The first-level parallel layer of the storage unit in the dual-base FFT calculation module includes three independent FIFO groups, and the dual-base butterfly calculation unit supports radix-2 and radix-4 butterfly operations.

9. The reconfigurable hybrid-based FFT processor based on the CORDIC algorithm according to claim 1, characterized in that: The multi-base butterfly computing unit reconstructs the circuit topology through seven data selectors and reorders the input and output ports and configures redundant ports according to the base mode.

Images