Bidirectional transient voltage suppressor and preparation method thereof

Abstract

The invention provides a bidirectional transient voltage suppressor and a preparation method thereof, one embodiment comprises at least one electrically isolated functional region, a first electrode layer and a second electrode layer, the functional region comprises at least one first highly doped region of a second conductivity type extending from the surface of a substrate of a first conductivity type into the substrate, and at least one second highly doped region of a second conductivity type extending from the surface of the substrate of the first conductivity type into the substrate, the at least one first highly doped region is arranged at intervals; a second conductive type first semiconductor layer covering the substrate and the first highly doped region; the at least one second highly doped region of the second conductivity type extends into the first semiconductor layer from the surface, far away from the substrate, of the first semiconductor layer, and the at least one second highly doped region is arranged at intervals; and a second semiconductor layer of the first conductivity type covering the second semiconductor layer and the second highly doped region. The bidirectional transient voltage suppressor provided by the embodiment of the invention has the advantages of low voltage and low loop capacitance by a simple structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology. More specifically, it relates to a bidirectional transient voltage suppressor and a method for fabricating the same. Background Technology

[0002] As semiconductor technology evolves towards the nanometer and even sub-nanometer scale, semiconductor devices are rapidly iterating towards miniaturization, portability, high performance, and low power consumption. Whether in consumer electronics, automotive electronics, industrial communications, or IoT terminals, increasingly stringent performance and reliability requirements are being placed on core chips. With the widespread adoption of high-speed interfaces such as USB 3.0 / 4.0, HDMI 2.0, and PCIe, and the demand for high transmission rates in scenarios such as 5G, 6G communications, and industrial cameras, signal attenuation and interference issues are becoming increasingly prominent.

[0003] Transient current and low-voltage interference protection for circuits such as data interface circuits requires the synergy of low voltage, low loop capacitance, and shallow flyback voltage to adapt to a wider range of application scenarios and advanced process scenarios. Transient Voltage Suppressor (TVS) is a high-efficiency protection device. The core idea of ​​the current design is to use a thyristor unit in series with a Zener diode. The thyristor unit is used to regulate the voltage magnitude, while the Zener diode is used to reduce the loop capacitance. This method is currently the most widely used practical method. It can regulate voltage and capacitance separately. The method is simple and feasible, but the design is complex. It requires the integration of thyristor unit and diode unit on the same substrate chip. In terms of process, it requires multiple deep trench isolation and buried layer designs. Moreover, many applications require bidirectional symmetrical functions. Often, double-layer metal interconnect technology is also required to achieve the design goal of bidirectional low voltage and low capacitance chip. For multi-channel applications, a larger chip area, more complex manufacturing process, and higher cost control are required. Summary of the Invention

[0004] To solve the above problems, the present disclosure adopts the following technical solution: This disclosure provides a bidirectional transient voltage suppressor, comprising at least one electrically isolated functional region, a first electrode layer and a second electrode layer located on opposite sides of the functional region, wherein the functional region includes: At least one first highly doped region of a second conductivity type extends from the surface of a substrate of a first conductivity type into the substrate, and the at least one first highly doped region is spaced apart. A first semiconductor layer of the second conductivity type covering the substrate and the first highly doped region; At least one second highly doped region of the second conductivity type extending into the first semiconductor layer from a surface of the first semiconductor layer away from the substrate, the at least one second highly doped region being spaced apart; and A second semiconductor layer of the first conductivity type covering the first semiconductor layer and the second highly doped region.

[0005] Optionally, the orthographic projection of the at least one first highly doped region in the functional area onto the substrate is at least one closed or unclosed ring that surrounds the substrate in sequence, and the orthographic projection of the at least one second highly doped region onto the substrate is at least one closed or unclosed ring that surrounds the substrate in sequence.

[0006] Optionally, the bidirectional transient voltage suppressor further includes an isolation portion surrounding the functional region, the isolation portion extending from the surface of the second semiconductor layer away from the substrate into the substrate.

[0007] Optionally, the orthographic projection of the isolation portion onto the substrate is selected from one of a circular ring, a polygonal ring, or a polygonal ring with rounded corners.

[0008] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0009] A second aspect of this disclosure provides a bidirectional transient voltage suppressor, comprising at least one electrically isolated functional region, a first electrode layer and a second electrode layer respectively located on both sides of the functional region, wherein the functional region includes: Substrate of the first conductivity type; A third semiconductor layer of a second conductivity type covering the substrate; A fourth semiconductor layer of the first conductivity type at least partially covers the surface of the third semiconductor layer away from the substrate; A fifth semiconductor layer of the second conductivity type covering the surface of the fourth semiconductor layer away from the substrate; and A second semiconductor layer of the first conductivity type covering the fifth semiconductor layer.

[0010] Optionally, the third semiconductor layer and the fifth semiconductor layer are highly doped, with a typical thickness of less than or equal to 10 µm.

[0011] Optionally, the orthographic projection of the at least one first highly doped region in the functional area onto the substrate is at least one closed or unclosed ring that surrounds the substrate in sequence, and the orthographic projection of the at least one second highly doped region onto the substrate is at least one closed or unclosed ring that surrounds the substrate in sequence.

[0012] Optionally, the bidirectional transient voltage suppressor further includes an isolation portion surrounding the functional region, the isolation portion extending from the surface of the second semiconductor layer away from the substrate into the substrate.

[0013] Optionally, the orthographic projection of the isolation portion onto the substrate is selected from one of a circular ring, a polygonal ring, or a polygonal ring with rounded corners.

[0014] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0015] A third aspect of this disclosure provides a method for fabricating a bidirectional transient voltage suppressor, comprising: forming at least one functional region, and forming a first electrode layer and a second electrode layer on both sides of the functional region. The formation of the functional area also includes: Provide a substrate of the first conductivity type; At least one first highly doped region of a second conductivity type is formed extending from the surface of the substrate into the substrate, and the at least one first highly doped region is spaced apart. A first semiconductor layer of the second conductivity type is formed, covering the substrate and the first highly doped region; At least one second highly doped region of the second conductivity type is formed, extending from a surface of the first semiconductor layer away from the substrate and into the first semiconductor layer, the at least one second highly doped region being spaced apart; and A second semiconductor layer of the first conductivity type is formed, covering the first semiconductor layer and the second highly doped region.

[0016] This disclosure provides a fourth aspect of a method for fabricating a bidirectional transient voltage suppressor, comprising: forming at least one functional region, and forming a first electrode layer and a second electrode layer on both sides of the functional region. The formation of the functional area also includes: Provide a substrate of the first conductivity type; A third semiconductor layer of a second conductivity type is formed over the substrate; A fourth semiconductor layer of the first conductivity type is formed, which at least partially covers the surface of the third semiconductor layer away from the substrate; A fifth semiconductor layer of the second conductivity type is formed covering the surface of the fourth semiconductor layer away from the substrate; and A second semiconductor layer of the first conductivity type is formed to cover the fifth semiconductor layer.

[0017] Optionally, forming a fourth semiconductor layer of the first conductivity type that at least partially covers the surface of the third semiconductor layer away from the substrate further comprises: forming a fourth semiconductor layer of the first conductivity type that partially covers the surface of the third semiconductor layer away from the substrate by ion implantation.

[0018] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a bidirectional transient voltage suppressor and its fabrication method. The bidirectional transient voltage suppressor provided in this disclosure provides at least one first highly doped region of a second conductivity type extending from the surface of a substrate of a first conductivity type into the substrate, and at least one second highly doped region of a second conductivity type extending from the surface of a first semiconductor layer away from the substrate into the first semiconductor layer. The first and second highly doped regions are spaced apart, thereby achieving bidirectional anti-interference functionality with both low voltage and low loop capacitance in a simple structure. Furthermore, by providing a third to fifth semiconductor layer stacked between the substrate and the second semiconductor layer, shallow voltage retracement characteristics are provided. The fabrication process is simple, facilitating multi-channel integration, reducing costs, and demonstrating broad application prospects. Attached Figure Description

[0019] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] Figure 1 A schematic top view of a bidirectional transient voltage suppressor according to an embodiment of the present disclosure is shown; Figure 2 A bidirectional transient voltage suppressor according to an embodiment of the present disclosure is shown. Figure 1 A schematic cross-sectional view taken by line AA' in the middle; Figure 3 A schematic top view of a bidirectional transient voltage suppressor according to another embodiment of the present disclosure is shown; Figure 4 A bidirectional transient voltage suppressor according to an embodiment of the present disclosure is shown. Figure 3 A schematic cross-sectional view taken from line BB' in the middle; Figure 5 A bidirectional transient voltage suppressor according to another embodiment of this disclosure is shown along... Figure 1 A schematic cross-sectional view taken by line AA' in the middle; Figure 6 A schematic cross-sectional view of a bidirectional transient voltage suppressor according to another embodiment of this disclosure is shown; Figure 7 A schematic cross-sectional view of a bidirectional transient voltage suppressor according to another embodiment of this disclosure is shown; Figure 8 A schematic cross-sectional view of a bidirectional transient voltage suppressor according to another embodiment of this disclosure is shown; Figure 9 A schematic cross-sectional view of a bidirectional transient voltage suppressor according to another embodiment of this disclosure is shown; Figures 10 to 13 A schematic process flow diagram showing the fabrication method of the bidirectional transient voltage suppressor according to embodiments of the present disclosure; and Figures 14 to 17 A schematic process flow diagram illustrating a method for fabricating a bidirectional transient voltage suppressor according to another embodiment of the present disclosure is shown. Detailed Implementation

[0021] To more clearly illustrate this disclosure, the following description, in conjunction with embodiments and accompanying drawings, further clarifies the subject matter. Similar components in the drawings are indicated by the same or similar reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0022] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0023] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0024] Furthermore, the terms "having", "containing", and "including" used in this disclosure are all open-ended, meaning that when a module is described as "having", "containing", or "including" a first element, a second element, and / or a third element, it indicates that the module includes other elements in addition to the first element, the second element, and / or the third element.

[0025] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0026] In this disclosure, unless otherwise stated, the term "co-layered arrangement" means a layer, component, or other structure formed by patterning two (or more) structures using the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple co-layered arrangements may be made of the same material, while the final materials may be the same or different.

[0027] Currently, the three-layer bidirectional transient voltage suppressor (TPS) structure is a relatively simple anti-interference protection device, consisting of a reverse-biased PN junction connected in series with a forward-biased PN junction. When a forward ESD attack occurs, the reverse-biased junction can provide protection, clamping the entire circuit to a certain voltage, such as around 0.7V, after breakdown. The forward-biased PN junction can also reduce capacitance. However, this structure has significant drawbacks: First, the reverse-biased PN junction is in an avalanche state, and even a small amount of energy can cause permanent thermal breakdown, resulting in poor reliability as a protection device. Second, when a negative ESD attack occurs, the forward-biased PN junction, which was originally used to reduce capacitance, becomes a reverse-biased junction to resist ESD. However, since the voltage and capacitance of a PN junction are negatively correlated, the forward-biased junction will not achieve the low-voltage requirement. In other words, the currently simple three-layer bidirectional transient voltage suppressor cannot simultaneously achieve optimal performance in both low voltage and low loop capacitance.

[0028] Therefore, there is a need for an anti-interference protection device that can simultaneously meet the requirements of excellent low voltage and low loop capacitance, and also has a simple structure.

[0029] To address at least one of the above technical problems, embodiments of this disclosure provide a bidirectional transient voltage suppressor, comprising at least one electrically isolated functional region, a first electrode layer and a second electrode layer located on opposite sides of the functional region, wherein the functional region includes: At least one first highly doped region of a second conductivity type extends from the surface of a substrate of a first conductivity type into the substrate, and the at least one first highly doped region is spaced apart. A first semiconductor layer of the second conductivity type covering the substrate and the first highly doped region; At least one second highly doped region of the second conductivity type extending into the first semiconductor layer from a surface of the first semiconductor layer away from the substrate, the at least one second highly doped region being spaced apart; and A second semiconductor layer of the first conductivity type covering the first semiconductor layer and the second highly doped region.

[0030] In this embodiment, by providing at least one first highly doped region of the second conductivity type extending from the substrate surface of the first conductivity type into the substrate and at least one second highly doped region of the second conductivity type extending from the surface of the first semiconductor layer away from the substrate into the first semiconductor layer, the first highly doped region and the second highly doped region are designed to be spaced apart, thereby enabling bidirectional anti-interference function with low voltage and low loop capacitance in a simple structure. The process is simple and conducive to multi-channel integration.

[0031] The structural advantages of the bidirectional transient voltage suppressor of this disclosure embodiment will be described in detail below with specific examples.

[0032] Reference Figure 1 and Figure 2 As shown, Figure 1 A bidirectional transient voltage suppressor according to an embodiment of the present disclosure is shown. Figure 2 Showing according to Figure 1 An exemplary cross-sectional view of an embodiment is shown by line AA' in the figure.

[0033] Combination Figure 1 and Figure 2 As shown, in this example, the bidirectional transient voltage suppressor includes two electrically isolated functional regions FF-1 and FF-2, and a first electrode layer 207 and a second electrode layer 208 disposed on both sides of functional regions FF-1 and FF-2. Figure 2 As shown, a first electrode 207 can be formed in the first electrode layer 207, which is electrically connected to the functional area one by one. Thus, when the second electrode layer 208 covers two functional areas at the same time, the bidirectional transient voltage suppressor can include two independently operating bidirectional transient voltage suppressor diodes (TVS).

[0034] It should be understood that this disclosure is not intended to limit the number of functional regions included in the bidirectional transient voltage suppressor, which can be any number greater than or equal to 1. In the following text, when no distinction is needed, the functional region is generally referred to as "functional region FF".

[0035] Continue to refer to Figure 1 and Figure 2 As shown, the bidirectional transient voltage suppressor includes a substrate 200 of a first conductivity type, a first semiconductor layer 202 of a second conductivity type, and a second semiconductor layer 204 of a first conductivity type, which are stacked sequentially.

[0036] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type. Those skilled in the art will understand that this disclosure is not intended to limit the substrate material, nor is it intended to limit the specific types of doped impurities; designers can choose as needed, and this will not be elaborated upon herein.

[0037] Continue to refer to Figure 1 and Figure 2 For example, the functional region FF includes: at least one first highly doped region 201 of a second conductivity type extending from the surface of the substrate 200 of a first conductivity type into the substrate 200; a first semiconductor layer 202 of a second conductivity type covering the substrate 200 and the first highly doped region 201; at least one second highly doped region 203 of a second conductivity type extending from the surface of the first semiconductor layer 202 away from the substrate 200 into the first semiconductor layer 202; and a second semiconductor layer 204 of a first conductivity type covering the first semiconductor layer 202 and the second highly doped region 203.

[0038] Optionally, the doping concentration of the first semiconductor layer 202 is lower than the doping concentration of the substrate 200 and the second semiconductor layer 204. For example, the substrate 200 can be a silicon-based material heavily doped with N-type semiconductor material, the first semiconductor layer 202 can be a silicon-based material lightly doped with P-type semiconductor material, and the second semiconductor layer 204 can be a silicon-based material heavily doped with N-type semiconductor material. The specific doping concentrations of the substrate 200, the first semiconductor layer 202, and the second semiconductor layer 204 are not limited, but should satisfy the following relationship with the first highly doped region 201 and the second highly doped region 203.

[0039] Specifically, the doping concentration of the first highly doped region 201 is greater than the doping concentration of the substrate 200, and the doping concentration of the second highly doped region 203 is greater than the doping concentration of the second semiconductor layer 204. For example, the doping concentration of the first highly doped region 201 and the doping concentration of the second highly doped region 203 are 1 × 10⁻⁶. 19 The order of magnitude is approximately 1 / 2. Furthermore, the first highly doped region 201 and the second highly doped region 203 are of the second conductivity type; that is, the doping type of the first highly doped region 201 and the second highly doped region 203 is different from the doping type of the substrate 200 and the second semiconductor layer 204.

[0040] By adding multiple high-concentration injection regions, the space charge region width of the PN junction between the substrate 200 and the first semiconductor layer 202, as well as the space charge region width of the PN junction between the second semiconductor layer 204 and the first semiconductor layer 202, can be expanded, thereby reducing the capacitance.

[0041] Therefore, the embodiments of this disclosure utilize a three-layer structure to achieve a series connection of a reverse-biased PN junction (both top-down and bottom-up) and a forward-biased PN junction. During forward electrostatic discharge (ESD) attacks, the reverse-biased junction provides protection, clamping the entire circuit to a lower voltage amplitude after breakdown. Simultaneously, the forward-biased PN junction reduces capacitance. Thus, the embodiments of this disclosure, with their three-layer integrated structure, achieve an anti-interference protection device that simultaneously provides low reverse-biased voltage and low loop capacitance.

[0042] Optionally, refer to Figure 1 and Figure 2 As shown, the orthographic projection of at least one first highly doped region 201 in the functional region FF onto the substrate 200 is at least one ring that surrounds it in sequence, and the orthographic projection of at least one second highly doped region 203 onto the substrate 200 is at least one ring that surrounds it in sequence.

[0043] It should be noted that, although Figure 1 The diagram shows a ring with a rounded rectangle, but this disclosure is not intended to limit the shape of the ring, which can be arbitrarily set as needed. It should be understood that the shapes of the first highly doped region and the second highly doped region can be adjusted according to the shape of the functional region FF.

[0044] Furthermore, this disclosure is not intended to limit the patterns of the first highly doped region and the second highly doped region to closed rings; any patterns that are spaced apart are within the scope of protection of this disclosure.

[0045] It should be noted that Figure 1 and Figure 2 The diagram shows the overlapping orthographic projections of the first highly doped region 201 and the second highly doped region 203 on the substrate 200, but this disclosure is not limited thereto. That is, this disclosure does not aim to limit the relationship between the orthographic projections of the first highly doped region 201 and the second highly doped region 203 on the substrate 200; their orthographic projections may overlap, intersect, or not overlap. This disclosure also does not aim to limit the quantitative relationship between the first highly doped region 201 and the second highly doped region 203; their quantities may be the same or different. Furthermore, the embodiments of this disclosure do not aim to limit the width of each first highly doped region 201 in the direction parallel to the surface of the substrate 200, nor the width of each second highly doped region 203 in the direction parallel to the surface of the first semiconductor layer 202. It is sufficient that the first highly doped regions 201 and the second highly doped regions 203 are spaced apart. Designers can comprehensively adjust various parameters to ensure that the forward and reverse parameters of the obtained bidirectional transient voltage suppressor are symmetrical.

[0046] Optionally, continue to refer to Figure 1 and Figure 2As shown, the bidirectional transient voltage suppressor also includes an isolation portion 205 surrounding the functional region, which extends from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200.

[0047] For example, refer to Figure 1 and Figure 2 As shown, the bidirectional transient voltage suppressor includes an isolation trench extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200. The isolation portion 205 can be an insulating material such as highly doped polysilicon, silicon oxide, silicon nitride, or silicon nitride disposed in the isolation trench. When considering the absence of additional parasitic resistance, process feasibility, and reliability, highly doped polysilicon can be selected as the filling material.

[0048] It should be understood that this disclosure is not intended to limit the specific structure and formation process of the isolation section. Other isolation structures that can be formed extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200 are also within the scope of protection of this disclosure.

[0049] Optionally, the orthographic projection of the isolation portion 205 onto the substrate 200 is selected from one of a circular ring, a polygonal ring, or a polygonal ring with rounded corners. Therefore, the orthographic projection of the functional region FF defined by the isolation portion 205 onto the substrate 200 can also be one of a circular ring, a polygonal ring, or a polygonal ring with rounded corners. Alternatively, the orthographic projection of all semiconductor film layers of the bidirectional transient voltage suppressor in the direction perpendicular to the substrate 200 can be one of a circular ring, a polygonal ring, or a polygonal ring with rounded corners.

[0050] Additionally, it should be noted that this disclosure is not intended to limit the isolation section 205, the functional area FF, and the orthographic projection patterns of each membrane layer.

[0051] Additionally, refer to Figure 1 and Figure 2 As shown, the orthographic projection of the isolation portion 205 on the substrate 200 is a ring around the functional region FF, and the isolation portion 205 between adjacent functional regions FF is shared.

[0052] However, this disclosure is not intended to be limited thereto. In some alternative embodiments, each functional area FF may be surrounded by an independent isolation section, for example, referring to... Figure 3 As shown, functional area FF-1 is surrounded and defined by an independent annular isolation portion 205-1, and functional area FF-2 is surrounded and defined by an independent annular isolation portion 205-2. Figure 4 It shows Figure 3 The cross-sectional structure of the bidirectional transient voltage suppressor shown in the figure reveals that the isolation between two adjacent functional areas FF-1 and FF-2 consists of two spaced-apart isolation sections.

[0053] For example, if the isolation section is made of insulating material formed in the isolation groove, the portion between two adjacent functional areas FF-1 and FF-2 in the bidirectional transient voltage suppressor should include two isolation grooves, which will not be elaborated here.

[0054] Similarly, when the isolation portions are spaced apart, this disclosure is not intended to limit the orthographic projection shape of the isolation portions on the substrate 200. For example, the orthographic projection shape of the isolation portions on the substrate includes, but is not limited to, a rectangular ring, a circular ring, or a polygonal ring.

[0055] By providing the isolation portion 205, the functional region FF can be defined. At the same time, the portion of the isolation portion located on the periphery of the functional region can extend into the substrate 200 from the surface of the second semiconductor layer 204 away from the substrate 200, thereby isolating the path from the second semiconductor layer 204 to the substrate 200, thus avoiding edge leakage and improving the device stability of the bidirectional transient voltage suppressor.

[0056] It should be noted that when the bidirectional transient voltage suppressor includes a functional area, an isolation portion is also required around the functional area to prevent leakage at the edge of the second semiconductor layer 204 to the substrate 200.

[0057] Continue to refer to Figure 2 and Figure 4 As shown, the bidirectional transient voltage suppressor also includes an insulating layer 206 formed on the surface of the second semiconductor layer 204 away from the substrate 200. The orthogonal projection of the insulating layer 206 onto the substrate 200 covers the orthogonal projection of the isolation portion onto the substrate 200, and at least partially exposes the surface of the functional region FF away from the substrate 200. The material of the insulating layer 206 can be silicon oxide or silicon nitride.

[0058] Optionally, refer to Figure 2 and Figure 4 As shown, the first electrode layer 207 is a patterned metal layer formed on the side of the insulating layer 206 away from the substrate 200 to form a first electrode in contact with the corresponding functional area, thereby enabling independent control of each functional area. A second electrode layer 208 covering the entire surface may be provided on the other side of the substrate 200 to form a second electrode for applying a common electrode.

[0059] Additionally, although not shown, the bidirectional transient voltage suppressor may also include a passivation layer covering the surface of the bidirectional transient voltage suppressor away from the substrate 200. The passivation layer can be used to provide protection against moisture, ion contamination, etc.

[0060] In another alternative embodiment, refer to Figure 1 and Figure 5As shown, the bidirectional transient voltage suppressor includes two electrically isolated functional regions FF-1 and FF-2, and a first electrode layer 207 and a second electrode layer 208 disposed on both sides of the functional regions FF-1 and FF-2.

[0061] The functional area FF includes: a substrate 200 of a first conductivity type, a third semiconductor layer 213 of a second conductivity type, a fourth semiconductor layer 214 of a first conductivity type, a fifth semiconductor layer 215 of a second conductivity type, and a second semiconductor layer 204 of a first conductivity type, which are stacked sequentially.

[0062] The third semiconductor layer 213 covers the substrate 200, the fourth semiconductor layer 214 covers the surface of the third semiconductor layer 213 away from the substrate 200, and the fifth semiconductor layer 215 covers the surface of the fourth semiconductor layer 214 away from the substrate.

[0063] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type. Those skilled in the art will understand that this disclosure is not intended to limit the substrate material, nor is it intended to limit the specific types of doped impurities; designers can choose as needed, and this will not be elaborated upon herein.

[0064] Optionally, the fourth semiconductor layer 214 is a lightly doped, high-resistivity layer. For example, the doping concentration of the fourth semiconductor layer 214' is 1 × 10⁻⁶. 12 Around the same level.

[0065] By providing a third semiconductor layer 213, a fourth semiconductor layer 214, and a fifth semiconductor layer 215 stacked between the substrate 200 and the second semiconductor 204, the improved structure is equivalent to a series-coupled structure of two transistors from top to bottom and bottom to top. The collector of the first transistor is also the emitter of the second transistor. When a voltage is applied, it can provide shallow retrace characteristics of the output characteristics. Compared with the deep retrace characteristics of a thyristor, it can ensure that even during ESD protection, the potential can be clamped to a relatively high operating potential such as 3.3V or 5V, thereby ensuring that subsequent circuits can operate stably within the operating voltage range in the fields of communication or computer.

[0066] Optionally, the third semiconductor layer 213 and the fifth semiconductor layer 215 are highly doped, with a thickness of less than or equal to 10 µm. For example, the doping concentration of the third semiconductor layer 213 and the fifth semiconductor layer 215 is 1 × 10⁻⁶. 18 Around the same level.

[0067] By providing a large concentration gradient between the third semiconductor layer 213 and the fifth semiconductor layer 215 and the fourth semiconductor layer 214, the depletion region width can be extended as much as possible, and the capacitance can be reduced to about 0.2pF.

[0068] In addition, by limiting the thickness range of each of the third semiconductor layer 213 and the fifth semiconductor layer 215, a thin base region design is provided, which can utilize the tunneling effect instead of avalanche breakdown, thereby avoiding permanent damage to the PN junction caused by avalanche breakdown and greatly improving the stability and reliability of the device.

[0069] Optionally, refer to Figure 5 As shown, the bidirectional transient voltage suppressor also includes an isolation portion 205 surrounding the functional region, the isolation portion 205 extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200.

[0070] For example, refer to Figure 1 and Figure 5 As shown, the bidirectional transient voltage suppressor includes an isolation trench extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200. The isolation portion 205 can be an insulating material such as highly doped polysilicon, silicon oxide, silicon nitride, or silicon nitride disposed in the isolation trench. When considering the absence of additional parasitic resistance, process feasibility, and reliability, highly doped polysilicon can be selected as the filling material.

[0071] It should be understood that this disclosure is not intended to limit the specific structure and formation process of the isolation section. Other isolation structures that can be formed extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200 are also within the scope of protection of this disclosure.

[0072] Additionally, refer to Figure 1 and Figure 5 As shown, the orthographic projection of the isolation portion 205 on the substrate 200 is a ring around the functional region FF, and the isolation portion 205 between adjacent functional regions FF is shared.

[0073] Optionally, refer to Figure 6 As shown, each functional area FF can be surrounded by an independent isolation section. Functional area FF-1 is surrounded and defined by an independent annular isolation section 205-1, and functional area FF-2 is surrounded and defined by an independent annular isolation section 205-2. It can be seen that the isolation section between two adjacent functional areas FF-1 and FF-2 is two isolation parts set at intervals.

[0074] In some other possible implementations, refer to Figure 7 As shown, this embodiment is similar to Figure 5 The difference in the illustrated embodiment is that the functional area FF includes: a substrate 200 of a first conductivity type, a third semiconductor layer 213 of a second conductivity type, a fourth semiconductor layer 214' of a first conductivity type, a fifth semiconductor layer 215 of a second conductivity type, and a second semiconductor layer 204 of a first conductivity type, which are stacked sequentially.

[0075] The third semiconductor layer 213 covers the substrate 200, the fourth semiconductor layer 214' partially covers the surface of the third semiconductor layer 213 away from the substrate 200, and the fifth semiconductor layer 21 covers the surface of the fourth semiconductor layer 214' away from the substrate.

[0076] From a fabrication process perspective, the fourth semiconductor layer 214' can be formed by patterning a pattern on the third semiconductor layer 213 to partially cover the surface of the third semiconductor layer 213 away from the substrate 200, and then by deposition or other means to cover the fourth semiconductor layer 214' and the surface of the third semiconductor layer 213 exposed by the fourth semiconductor layer 214'; or it can be formed by creating a trench in the third semiconductor layer 213 and then depositing in the trench to partially cover the surface of the third semiconductor layer 213 away from the substrate 200; or it can be formed by forming the third semiconductor layer 213 and then by ion implantation to form the fourth semiconductor layer 214' that partially covers the third semiconductor layer 213. In this case, the fourth semiconductor layer 214' can be regarded as a buried layer in the third semiconductor layer 213.

[0077] Optionally, the fourth semiconductor layer 214 is a lightly doped, high-resistivity layer. For example, the doping concentration of the fourth semiconductor layer 214' is 1 × 10⁻⁶. 12 Around the same level.

[0078] By providing a third semiconductor layer 213, a fourth semiconductor layer 214', and a fifth semiconductor layer 215 stacked between the substrate 200 and the second semiconductor 204, the improved structure is equivalent to a series-coupled structure of two transistors from top to bottom and bottom to top. The collector of the first transistor is also the emitter of the second transistor. When a voltage is applied, it can provide shallow retrace characteristics of the output characteristics. Compared with the deep retrace characteristics of a thyristor, it can ensure that even during ESD protection, the potential can be clamped to a relatively high operating potential such as 3.3V or 5V, thereby ensuring that subsequent circuits can operate stably within the operating voltage range in the fields of communication or computer.

[0079] Optionally, the third semiconductor layer 213 and the fifth semiconductor layer 215 are highly doped, with a thickness of less than or equal to 10 µm. For example, the doping concentration of the third semiconductor layer 213 and the fifth semiconductor layer 215 is 1 × 10⁻⁶. 18 Around the same level.

[0080] By providing a large concentration gradient between the third semiconductor layer 213 and the fifth semiconductor layer 215 and the fourth semiconductor layer 214', the depletion region width can be expanded as much as possible, and the capacitance can be reduced to about 0.2pF.

[0081] In addition, by limiting the thickness range of each of the third semiconductor layer 213 and the fifth semiconductor layer 215, a thin base region design is provided, which can utilize the tunneling effect instead of avalanche breakdown, thereby avoiding permanent damage to the PN junction caused by avalanche breakdown and greatly improving the stability and reliability of the device.

[0082] The structure and function of other parts in this embodiment are similar to those of the parts described in the previous embodiment, and will not be repeated here.

[0083] Additionally, it can be understood that, although not shown, each functional area FF can also be surrounded by an independent isolation section. Functional area FF-1 is surrounded and defined by an independent annular isolation section, and functional area FF-2 is surrounded and defined by an independent annular isolation section. Thus, the isolation section between two adjacent functional areas FF-1 and FF-2 is two isolated parts provided at an interval, which will not be described in detail here.

[0084] When each functional region is defined by an independent isolation section, the pattern of the fourth semiconductor layer 214' corresponding to each functional region on the substrate 200 can also be an independent pattern arranged at intervals, and each pattern covers the corresponding functional region, which will not be described in detail here.

[0085] In some alternative embodiments, referring to 8, the bidirectional transient voltage suppressor includes two electrically isolated functional regions FF-1 and FF-2, and a first electrode layer 207 and a second electrode layer 208 disposed on both sides of the functional regions FF-1 and FF-2.

[0086] The functional region FF includes: a substrate 200 of a first conductivity type, at least one first highly doped region 201 of a second conductivity type extending from the surface of the substrate 200 into the substrate 200, a third semiconductor layer 213 of a second conductivity type covering the substrate 200 and the first highly doped region 201, a fourth semiconductor layer 214 of a first conductivity type covering the third semiconductor layer 213, a fifth semiconductor layer 215 of a second conductivity type covering the surface of the fourth semiconductor layer 214 away from the substrate 200, at least one second highly doped region 203 of a second conductivity type extending from the surface of the fifth semiconductor layer 215 away from the substrate 200 into the fifth semiconductor layer, and a second semiconductor layer 204 of a first conductivity type covering the fifth semiconductor layer 215 and the second highly doped region 203.

[0087] In other words, this embodiment is equivalent to setting an intermediate layer between the substrate 200 and the second semiconductor layer 204. The intermediate layer includes a third semiconductor layer 213, a fourth semiconductor layer 214 and a fifth semiconductor layer 215 stacked together. At the same time, the functional region FF is also provided with at least one first highly doped region 201 of the second conductivity type extending from the surface of the substrate 200 into the substrate 200 and at least one second highly doped region 203 of the second conductivity type extending from the surface of the fifth semiconductor layer 215 away from the substrate 200 into the fifth semiconductor layer 215.

[0088] For example, the substrate 200 can be made of an N-type doped semiconductor material on a silicon-based material, the third semiconductor layer 202 can be made of a P-type doped semiconductor material on a silicon-based material, the doping concentration of the substrate can be greater than the doping concentration of the third semiconductor layer, and the second semiconductor layer 204 can be made of an N-type doped semiconductor material on a silicon-based material, the doping concentration of the second semiconductor layer 204 can be greater than the doping concentration of the fifth semiconductor layer. However, this disclosure is not intended to limit the specific doping concentrations of the substrate 200, the third semiconductor layer 213, and the second semiconductor layer 204, but they should satisfy the following relationship with the first highly doped region 201 and the second highly doped region 203.

[0089] Optionally, the doping concentration of the first highly doped region 201 is greater than the doping concentration of the substrate 200, and the doping concentration of the second highly doped region 203 is greater than the doping concentration of the second semiconductor layer 204. Furthermore, the doping type of the first highly doped region 201 and the second highly doped region 203 is a second conductivity type; that is, the doping type of the first highly doped region 201 and the second highly doped region 203 is different from the doping type of the substrate 200 and the second semiconductor layer 204.

[0090] By adding multiple high-concentration injection regions, the space charge region width of the PN junction between the substrate 200 and the first semiconductor layer 202, as well as the space charge region width of the PN junction between the second semiconductor layer 204 and the first semiconductor layer 202, can be expanded, thereby reducing capacitance. Simultaneously, by setting the structure between the substrate 200 and the second semiconductor layer 204 as a three-layer stack, with the fourth semiconductor layer 214 in the middle being a low-doped, high-resistivity layer, this structure is equivalent to a series coupling structure of two transistors, one from top to bottom and the other from bottom to top. The collector of the first transistor is also the emitter of the second transistor. When voltage is applied, the dual-transistor coupling structure provides shallow retrace characteristics for the output. Compared to the deep retrace characteristics of a thyristor, this ensures that during ESD protection, the potential can be clamped to a relatively high operating potential such as 3.3V or 5V, thus ensuring that subsequent circuits can operate stably within the operating voltage range in communication or computer applications.

[0091] In other words, the structure in this embodiment, with its simple design, can balance low capacitance and low voltage characteristics during ESD protection, thereby ensuring stable operation of subsequent circuits during the required electrostatic protection. Furthermore, this function is achieved solely within the functional area through the interaction of a doped region and a semiconductor layer, eliminating the need for complex structures and facilitating multi-interface integration applications.

[0092] Optionally, the fourth semiconductor layer 214 is a lightly doped, high-resistivity layer. For example, the doping concentration of the fourth semiconductor layer 214' is 1 × 10⁻⁶. 12 Around the same level.

[0093] Alternatively, the third semiconductor layer 213 and the fifth semiconductor layer 215 may be highly doped, with a thickness of less than or equal to 10 µm. For example, the doping concentration of the third semiconductor layer 213 and the fifth semiconductor layer 215 is 1 × 10⁻⁶. 18 Around the same level.

[0094] By providing a large concentration gradient between the third semiconductor layer 213 and the fifth semiconductor layer 215 and the fourth semiconductor layer 214, the depletion region width can be extended as much as possible, and the capacitance can be reduced to about 0.2pF.

[0095] In addition, by limiting the thickness range of each of the third semiconductor layer 213 and the fifth semiconductor layer 215, a thin base region design is provided, which can utilize the tunneling effect instead of avalanche breakdown, thereby avoiding permanent damage to the PN junction caused by avalanche breakdown and greatly improving the stability and reliability of the device.

[0096] It should also be noted that this embodiment is not intended to limit the projection patterns of the first highly doped region 201 and the second highly doped region 203 on the substrate 200 or the orthographic relationship between them. Their orthographic projection on the substrate can be multiple rings, interrupted rings, or other spaced patterns, and the first highly doped region 201 and the second highly doped region 203 need not be required to overlap in the longitudinal direction.

[0097] Alternatively, the bidirectional transient voltage suppressor may further include an isolation portion 205 surrounding the functional region, the isolation portion extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200. The structure and function of the isolation portion 205 are consistent with those in the above embodiment.

[0098] In addition, although Figure 8 The isolation portion 205 is shown as an orthographic projection on the substrate 200 as a ring surrounding the functional region FF. The isolation portion 205 is partially shared between adjacent functional regions FF, but this disclosure is not limited to this; the isolation portions of adjacent functional regions FF can be separate rings to form... Figure 2 The top view shown is not described in detail here.

[0099] In some other possible implementations, refer to Figure 9 As shown, the difference between this embodiment and the previous embodiment is that the functional region FF includes: a substrate 200 of a first conductivity type, at least one first highly doped region 201 of a second conductivity type extending from the surface of the substrate 200 into the substrate 200, a third semiconductor layer 213 of a second conductivity type covering the substrate 200 and the first highly doped region 201, a fourth semiconductor layer 214' of a first conductivity type covering the third semiconductor layer 213, a fifth semiconductor layer 215 of a second conductivity type partially covering the surface of the fourth semiconductor layer 214' away from the substrate 200, at least one second highly doped region 203 of a second conductivity type extending from the surface of the fifth semiconductor layer 215 away from the substrate 200 into the fifth semiconductor layer, and a second semiconductor layer 204 of a first conductivity type covering the fifth semiconductor layer 215 and the second highly doped region 203.

[0100] From a fabrication process perspective, the fourth semiconductor layer 214' can be formed by patterning a pattern on the third semiconductor layer 213 to partially cover the surface of the third semiconductor layer 213 away from the substrate 200, and then by deposition or other means to cover the fourth semiconductor layer 214' and the surface of the third semiconductor layer 213 exposed by the fourth semiconductor layer 214'; or it can be formed by creating a trench in the third semiconductor layer 213 and then depositing in the trench to partially cover the surface of the third semiconductor layer 213 away from the substrate 200; or it can be formed by forming the third semiconductor layer 213 and then by ion implantation to form the fourth semiconductor layer 214' that partially covers the third semiconductor layer 213. In this case, the fourth semiconductor layer 214' can be regarded as a buried layer in the third semiconductor layer 213.

[0101] Or rather, relative to Figure 1 In the embodiment shown in the cross-sectional view, the fourth semiconductor layer 214' can be regarded as a buried layer disposed in the middle of the first semiconductor layer, so that the first semiconductor layer includes a first portion corresponding to the third semiconductor layer, a buried layer corresponding to the fourth semiconductor layer 214', and a second portion corresponding to the fifth semiconductor layer 215.

[0102] Optionally, the doping concentration of the first highly doped region 201 is greater than the doping concentration of the substrate 200, and the doping concentration of the second highly doped region 203 is greater than the doping concentration of the second semiconductor layer 204. For example, the doping concentration of the first highly doped region 201 and the doping concentration of the second highly doped region 203 are 1 × 10⁻⁶. 19 The order of magnitude is approximately 1 / 2. Furthermore, the first highly doped region 201 and the second highly doped region 203 are of the second conductivity type; that is, the doping type of the first highly doped region 201 and the second highly doped region 203 is different from the doping type of the substrate 200 and the second semiconductor layer 204.

[0103] By adding multiple high-concentration injection regions, the space charge region width of the PN junction between the substrate 200 and the first semiconductor layer 202, as well as the space charge region width of the PN junction between the second semiconductor layer 204 and the first semiconductor layer 202, can be expanded, thereby reducing capacitance. Simultaneously, by setting the substrate 200 and the second semiconductor layer 204 as a three-layer stacked structure, with the fourth semiconductor layer 214' in the middle being a low-doped, high-resistivity layer, this structure is equivalent to a series coupling structure of two transistors, one from top to bottom and the other from bottom to top. The collector of the first transistor is also the emitter of the second transistor. When voltage is applied, the dual-transistor coupling structure provides shallow retrace characteristics for the output. Compared to the deep retrace characteristics of a thyristor, this ensures that during ESD protection, the potential can be clamped to a relatively high operating potential such as 3.3V or 5V, thus ensuring that subsequent circuits can operate stably within the operating voltage range in communication or computer applications.

[0104] In other words, the structure in this embodiment, with its simple design, can balance low capacitance and low voltage characteristics during ESD protection, thereby ensuring stable operation of subsequent circuits during the required electrostatic protection. Furthermore, this function is achieved solely within the functional area through the interaction of a doped region and a semiconductor layer, eliminating the need for complex structures and facilitating multi-interface integration applications.

[0105] Optionally, the fourth semiconductor layer 214' is a lightly doped, high-resistivity layer. For example, the doping concentration of the fourth semiconductor layer 214' is 1 × 10⁻⁶. 12 Around the same level.

[0106] Furthermore, the third semiconductor layer 213 and the fifth semiconductor layer 215 are highly doped, with a thickness of less than or equal to 10 µm. For example, the doping concentration of the third semiconductor layer 213 and the fifth semiconductor layer 215 is 1 × 10⁻⁶. 18 Around the same level.

[0107] By providing a large concentration gradient between the third semiconductor layer 213 and the fifth semiconductor layer 215 and the fourth semiconductor layer 214', the depletion region width can be extended as much as possible, and the capacitance can be reduced to about 0.2pF.

[0108] In addition, by limiting the thickness range of each of the third semiconductor layer 213 and the fifth semiconductor layer 215, a thin base region design is provided, which can utilize the tunneling effect instead of avalanche breakdown, thereby avoiding permanent damage to the PN junction caused by avalanche breakdown and greatly improving the stability and reliability of the device.

[0109] It should be noted that other structures similar to those in the above embodiments are also consistent in structure and function in this embodiment, and will not be described in detail here.

[0110] Another aspect of this disclosure provides a method for fabricating a bidirectional transient voltage suppressor, comprising: forming at least one functional region, and forming a first electrode layer and a second electrode layer on both sides of the functional region, wherein forming the functional region further comprises: S1, Provide a substrate of the first conductivity type; S2. Form at least one first highly doped region of a second conductivity type extending from the surface of the substrate into the substrate, wherein the at least one first highly doped region is spaced apart. S3. Form a first semiconductor layer of the second conductivity type covering the substrate and the first highly doped region; S4. Forming at least one second highly doped region of the second conductivity type extending from a surface of the first semiconductor layer away from the substrate into the first semiconductor layer, wherein the at least one second highly doped region is spaced apart; and S5. Form a second semiconductor layer of the first conductivity type covering the first semiconductor layer and the second highly doped region.

[0111] By providing at least one first highly doped region of a second conductivity type extending into the substrate from the surface of the first conductivity type substrate and at least one second highly doped region of a second conductivity type extending into the first semiconductor layer from the surface of the first semiconductor layer away from the substrate, with the first and second highly doped regions being designed to be spaced apart, it is possible to achieve bidirectional anti-interference function with both low voltage and low loop capacitance in a simple structure. The process is simple and conducive to multi-channel integration.

[0112] The following reference Figures 10 to 13 ,by Figure 1 The fabrication method of the bidirectional transient voltage suppressor shown is illustrated in detail below. For ease of description, the first conductivity type is referred to as N-type and the second conductivity type as P-type, but it should be understood that this disclosure is not limited thereto.

[0113] In step S2, at least one P-type first heavily doped region is formed extending from the surface of the substrate 200 into the substrate 200, with the at least one first heavily doped region spaced apart. Exemplarily, at least one first heavily doped region 201 is formed by ion implantation. The type of ion implantation can be at least one of group III elements such as boron (B), aluminum (Al), indium (In), and gallium (Ga), typically boron (B). The doping concentration of the first heavily doped region 201 is greater than the doping concentration of the substrate 200, for example, its doping concentration is 1 × 10⁻⁶. 19 Magnitude.

[0114] In step S3, refer to Figure 11As shown, a first semiconductor layer 202 of a second conductivity type is formed, covering the substrate 200 and the first heavily doped region 201. For example, the p-type lightly doped first semiconductor layer 202 can be formed by epitaxial growth.

[0115] Next, in step S4, refer to Figure 12 As shown, at least one second highly doped region 203 of a second conductivity type is formed extending from the surface of the first semiconductor layer 202 away from the substrate 200 into the first semiconductor layer 202, and the at least one second highly doped region 203 is spaced apart.

[0116] For example, at least one second highly doped region 203 is formed by ion implantation. The type of ion implantation can be at least one group III element such as boron (B), aluminum (Al), indium (In), and gallium (Ga), typically boron (B). The doping concentration of the second highly doped region 203 is greater than the doping concentration of the second semiconductor layer 204 to be formed, for example, its doping concentration is 1 × 10⁻⁶. 19 Magnitude.

[0117] Reference Figure 13 As shown, in step S5, a second semiconductor layer 204 of the first conductivity type is formed, covering the first semiconductor layer 202 and the second heavily doped region 203. The second semiconductor layer 204 can be an N-type heavily doped semiconductor material on a silicon-based material, but the doping concentration of the second semiconductor layer 204 is less than the doping concentration of the second heavily doped region 203.

[0118] Subsequently, an isolation trench can be formed extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200. The isolation trench is then filled with insulating materials such as highly doped polysilicon, silicon oxide, silicon nitride, and silicon nitride to form an isolation section, thereby forming two functional regions FF-1 and FF-2.

[0119] An insulating layer 206 can then be formed by depositing and patterning an insulating material layer; a first electrode layer 207 can be formed by a patterning process; and a second electrode layer 208 can be formed by a metal sputtering process to cover the other surface of the substrate 200 to form a bidirectional transient voltage suppressor.

[0120] Another aspect of this disclosure provides a method for fabricating a bidirectional transient voltage suppressor, comprising: forming at least one functional region, and forming a first electrode layer and a second electrode layer on both sides of the functional region, wherein forming the functional region further comprises: S1' provides a substrate of the first conductivity type; S2', Forming a third semiconductor layer of a second conductivity type covering the substrate; S3', Forming a fourth semiconductor layer of the first conductivity type that at least partially covers the surface of the third semiconductor layer away from the substrate; S4', forming a fifth semiconductor layer of the second conductivity type covering the surface of the fourth semiconductor layer away from the substrate; and S5', Form a second semiconductor layer of the first conductivity type covering the fifth semiconductor layer.

[0121] With the above configuration, by stacking a third, fourth, and fifth semiconductor layer between the substrate and the second semiconductor, the improved structure is equivalent to a series-coupled structure of two transistors, one from top to bottom and the other from bottom to top. The collector of the first transistor is also the emitter of the second transistor. When a voltage is applied, it can provide shallow retrace characteristics for the output. Compared with the deep retrace characteristics of a thyristor, this ensures that even during ESD protection, the potential can be clamped to a relatively high operating potential such as 3.3V or 5V. This ensures that subsequent circuits can operate stably within the operating voltage range in communication or computer applications.

[0122] The following describes the production process using specific examples. Figure 7 The specific steps in the example shown.

[0123] Reference Figure 14 As shown, in step S1', a first conductivity type is provided on substrate 200, and the material of substrate 200 can be an N-type lightly doped silicon-based substrate material.

[0124] In step S2', a third semiconductor layer 213 of the second conductivity type is formed over the substrate 200. For example, the P-type doped third semiconductor layer 213 can be formed by epitaxial growth. The thickness of the first sub-epitaxy layer 202' can be greater than or equal to 15µm and less than or equal to 18µm.

[0125] In step S3', refer to Figure 15 As shown, a fourth semiconductor layer 214' of the first semiconductor type is formed, which partially covers the surface of the third semiconductor layer 213 away from the substrate 200.

[0126] For example, a fourth semiconductor layer 214' of a first conductivity type is formed extending from the surface of the third semiconductor layer 213 away from the substrate 200 into the third semiconductor layer 213. The fourth semiconductor layer 214' is a lightly doped, high-resistivity layer. Exemplarily, the fourth semiconductor layer 214' can be formed by an ion implantation process, wherein the doping concentration of the fourth semiconductor layer 214' is less than the doping concentration of the fifth semiconductor layer 215 to be formed, thereby forming a high-resistivity region with low resistivity doping. The ion implantation thickness of the fourth semiconductor layer 214' can be, for example, greater than or equal to 5 µm and less than or equal to 15 µm, but it should be ensured that after the fourth semiconductor layer 214' is formed, the distance between the surface of the fourth semiconductor layer 214' near the substrate 200 and the substrate 200 can be less than or equal to 10 µm, thereby forming a thin base region.

[0127] Reference Figure 16 As shown, in step S4', a fifth semiconductor layer 215 of the second conductivity type is formed covering the surface of the fourth semiconductor layer 214' away from the substrate 200.

[0128] For example, a second sub-epitaxial layer with a thickness of less than or equal to 10 µm can be formed by an epitaxial growth process, thereby forming a thin base region.

[0129] Furthermore, by providing a large concentration gradient between the third semiconductor layer 213 and the fifth semiconductor layer 21 and the fourth semiconductor layer 214', the depletion region width can be extended as much as possible, thereby reducing the capacitance to about 0.2pF.

[0130] By utilizing the thickness difference between the third semiconductor layer 213 and the fifth semiconductor layer after the formation of the fourth semiconductor layer 214', a thin base region design is provided. The tunneling effect can be used instead of avalanche breakdown, thereby avoiding permanent damage to the PN junction caused by avalanche breakdown and greatly improving the stability and reliability of the device.

[0131] In step S5', refer to Figure 17 As shown, a second semiconductor layer 204 of the first conductivity type is formed covering the fifth semiconductor layer 215.

[0132] Subsequently, an isolation trench can be formed extending from the surface of the second semiconductor layer 204 away from the substrate 200 into the substrate 200. The isolation trench is then filled with insulating materials such as highly doped polysilicon, silicon oxide, silicon nitride, and silicon nitride to form an isolation section, thereby forming two functional regions FF-1 and FF-2.

[0133] An insulating layer 206 can then be formed by depositing and patterning an insulating material layer; a first electrode layer 207 can be formed by a patterning process; and a second electrode layer 208 can be formed by a metal sputtering process to cover the other surface of the substrate 200 to form a bidirectional transient voltage suppressor.

[0134] It should be noted that the above-described process for forming the fourth semiconductor layer 214' is for illustrative purposes only. Buried layers can also be formed through epitaxial growth, deposition, and other processes, which are not limited in this article.

[0135] In addition, such as Figure 5 and Figure 6 As shown, when the fourth semiconductor layer 214 covers the third semiconductor layer 213 to form a stacked third semiconductor layer 213, the fourth semiconductor layer 214 and the fifth semiconductor layer 215 can be formed by epitaxial growth or direct ion implantation, which is not limited in this article.

[0136] It should also be noted that, although the above process is not specifically described... Figure 8 and Figure 9 The fabrication method of the structure shown is described above. However, those skilled in the art should understand that it only requires adding an ion implantation step after step S1' above to form a first highly doped region 201 with spacing, and adding an ion implantation step after step S4' to form a second highly doped region 203 with spacing. This will not be elaborated here.

[0137] The bidirectional transient voltage suppressor formed by the above facts can be connected in parallel with one or more interfaces during use. When connected in parallel with multiple interfaces, the bidirectional transient voltage suppressor will include multiple functional areas, and each functional area will be electrically isolated and connected in parallel with multiple interfaces, thereby providing bidirectional ESD protection for multiple interfaces.

[0138] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A bidirectional transient voltage suppressor, characterized in that, The functional region includes at least one electrically isolated functional region, a first electrode layer and a second electrode layer located on both sides of the functional region, wherein the functional region includes: At least one first highly doped region of a second conductivity type extends from the surface of a substrate of a first conductivity type into the substrate, and the at least one first highly doped region is spaced apart. A first semiconductor layer of the second conductivity type covering the substrate and the first highly doped region; At least one second highly doped region of the second conductivity type extending into the first semiconductor layer from a surface of the first semiconductor layer away from the substrate, the at least one second highly doped region being spaced apart; and A second semiconductor layer of the first conductivity type covering the first semiconductor layer and the second highly doped region.

2. A bidirectional transient voltage suppressor, characterized in that, The functional region includes at least one electrically isolated functional region, a first electrode layer and a second electrode layer located on both sides of the functional region, wherein the functional region includes: Substrate of the first conductivity type; A third semiconductor layer of a second conductivity type covering the substrate; A fourth semiconductor layer of the first conductivity type at least partially covers the surface of the third semiconductor layer away from the substrate; A fifth semiconductor layer of the second conductivity type covering the surface of the fourth semiconductor layer away from the substrate; and A second semiconductor layer of the first conductivity type covering the fifth semiconductor layer.

3. The bidirectional transient voltage suppressor according to claim 2, characterized in that, The third semiconductor layer and the fifth semiconductor layer are highly doped, and the thickness of each of the third semiconductor layer and the fifth semiconductor layer is less than or equal to 10µm.

4. The bidirectional transient voltage suppressor according to claim 1, characterized in that, The orthographic projection of the at least one first highly doped region in the functional area onto the substrate is at least one closed or unclosed ring that surrounds it in sequence, and the orthographic projection of the at least one second highly doped region onto the substrate is at least one closed or unclosed ring that surrounds it in sequence.

5. The bidirectional transient voltage suppressor according to claim 1 or 2, characterized in that, Also includes: An isolation portion surrounding the functional area extends from the surface of the second semiconductor layer away from the substrate into the substrate.

6. The bidirectional transient voltage suppressor according to claim 5, characterized in that, The orthographic projection of the isolation portion onto the substrate is selected from one of a circular ring, a polygonal ring, or a polygonal ring with rounded corners.

7. The bidirectional transient voltage suppressor according to any one of claims 1-6, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; or The first conductivity type is P-type, and the second conductivity type is N-type.

8. A method for fabricating a bidirectional transient voltage suppressor, characterized in that, include: At least one functional region is formed, and a first electrode layer and a second electrode layer are formed on both sides of the functional region. The formation of the functional area also includes: Provide a substrate of the first conductivity type; At least one first highly doped region of a second conductivity type is formed extending from the surface of the substrate into the substrate, and the at least one first highly doped region is spaced apart. A first semiconductor layer of the second conductivity type is formed, covering the substrate and the first highly doped region; At least one second highly doped region of the second conductivity type is formed, extending from a surface of the first semiconductor layer away from the substrate and into the first semiconductor layer, the at least one second highly doped region being spaced apart; and A second semiconductor layer of the first conductivity type is formed, covering the first semiconductor layer and the second highly doped region.

9. A method for fabricating a bidirectional transient voltage suppressor, characterized in that, include: At least one functional region is formed, and a first electrode layer and a second electrode layer are formed on both sides of the functional region. The formation of the functional area also includes: Provide a substrate of the first conductivity type; A third semiconductor layer of a second conductivity type is formed over the substrate; A fourth semiconductor layer of the first conductivity type is formed, which at least partially covers the surface of the third semiconductor layer away from the substrate; A fifth semiconductor layer of the second conductivity type is formed covering the surface of the fourth semiconductor layer away from the substrate; and A second semiconductor layer of the first conductivity type is formed to cover the fifth semiconductor layer.

10. The preparation method according to claim 9, characterized in that, The fourth semiconductor layer of the first conductivity type, which at least partially covers the surface of the third semiconductor layer away from the substrate, further includes: A fourth semiconductor layer of a first conductivity type is formed by ion implantation, which partially covers the surface of the third semiconductor layer away from the substrate.

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