SF6 density monitoring system with multi-element data communication

Abstract

The application relates to the technical field of power equipment state monitoring, and discloses an SF6 density monitoring system with multi-element data communication, which comprises an electric energy management module, a super capacitor, an acquisition module, a zero-crossing detection circuit, a communication module, a switching circuit and a microcontroller. The zero-crossing detection circuit is connected to a secondary voltage signal loop of a power grid and captures a phase zero-crossing point; the microcontroller synchronously reads temperature and pressure parameters in response to the zero-crossing point signal, so as to suppress power frequency transient interference. The microcontroller compensates the pressure by using the temperature parameter and calculates a change slope, and executes joint determination in combination with the terminal voltage of the super capacitor. The microcontroller controls the switching circuit to be turned on to supply power for the communication module, and uses a direct memory access controller to concurrently transmit data messages to the communication module for sending. The application improves the anti-interference capability of bottom-layer data sampling, eliminates leakage false alarms caused by environmental temperature fluctuation, and effectively reduces the overall operation power consumption of the system.

Description

Technical Field

[0001] This invention relates to the field of power equipment condition monitoring technology, specifically to an SF6 density monitoring system with multi-source data communication. Background Technology

[0002] Sulfur hexafluoride (SF6) gas is widely used in gas-insulated metal-enclosed switchgear in substations due to its excellent insulation and arc-quenching properties. Real-time monitoring of SF6 gas density inside the equipment chambers plays a crucial role in ensuring the safe and stable operation of the power system.

[0003] Existing SF6 density monitoring devices are typically installed directly on the outer metal chamber wall of switchgear. Limited by on-site wiring conditions, they mostly rely on power extraction coils or internal batteries for power, thus imposing strict limitations on the overall system power consumption. Substations have strong 50Hz power frequency AC electric and magnetic fields. This power frequency interference can enter the analog signal conditioning circuit inside the monitoring device through spatial radiation and conduction coupling. Conventional monitoring equipment usually uses a fixed-frequency timing sampling mechanism. The analog-to-digital conversion action time and the phase of the spatial interference field strength are randomly distributed. When the sampling action occurs near the peak of the high-voltage AC interference level, the acquired pressure and temperature raw level data will exhibit transient distortion, thereby reducing the accuracy of the underlying physical quantity acquisition.

[0004] On the other hand, the gas pressure inside a sealed chamber will fluctuate naturally due to thermal expansion and contraction caused by changes in the external ambient temperature. Current leak detection logic relies heavily on a single static absolute pressure exceeding the limit to trigger an alarm. In situations such as a sudden drop in ambient temperature at night, the normal physical depressurization process can easily be identified as a gas leak by the system, leading to false alarm information received by the substation's backend.

[0005] In terms of data transmission, monitoring devices need to send the collected status parameters to the next-level aggregation node or master station. Existing equipment often relies on a single communication hardware interface. In the complex environment of substations with metal equipment obstruction and electromagnetic interference, the anti-fading capability of a single link is weak, and communication interruptions are likely to occur. In order to ensure the data transmission rate, the main control chip needs to keep the communication peripherals in an active state for a long time to execute the retransmission mechanism. This approach consumes a large amount of the system's limited internal energy storage and can easily lead to abnormal resets due to node voltage drops. It is difficult to strike a balance between ensuring communication redundancy and maintaining extremely low power consumption. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides an SF6 density monitoring system with multi-source data communication. This system solves the problems of existing density monitoring devices for gas-insulated metal-enclosed switchgear in substations, which are prone to sampling distortion under low power consumption constraints and power frequency electromagnetic interference. Furthermore, when determining gas leaks, relying solely on a single physical extreme value makes them susceptible to false alarms due to ambient temperature fluctuations. Additionally, a single communication link cannot guarantee the reliability of burst data transmission in complex field environments.

[0007] To achieve the above objectives, the first aspect of the present invention provides an SF6 density monitoring system with multi-source data communication, comprising: The power management module is used to obtain and convert electrical energy from an external DC node; Supercapacitors, connected to the power management module, are used to store converted electrical energy and power the system. The data acquisition module is used to obtain the ambient temperature and pressure parameters of SF6 gas. Zero-crossing detection circuit is used to connect to the secondary voltage signal loop of the power grid and capture the phase zero-crossing signal of the fundamental wave of the power grid; The communication module is used to send data packets to the remote master station. The communication module includes a wired communication unit and a wireless communication unit. A switching circuit, connected in series between the supercapacitor and the power supply circuit of the communication module, is used to control the on / off state of the power supply circuit. The microcontroller is connected to the supercapacitor, the acquisition module, the zero-crossing detection circuit, the switching circuit, and the communication module. It is used to respond to the phase zero-crossing signal to synchronously read the ambient temperature and pressure parameters. It performs joint judgment by combining the terminal voltage of the supercapacitor and the pressure change slope calculated from the ambient temperature and pressure parameters. When the judgment meets the transmission conditions, it controls the switching circuit to conduct to supply power to the communication module and sends data packets through the communication module.

[0008] Furthermore, the microcontroller is internally configured with an external interrupt pin and an analog-to-digital converter; The microcontroller responds to the phase zero-crossing signal output by the zero-crossing detection circuit, wakes up the system kernel through an external interrupt pin, and triggers the analog-to-digital converter to perform discrete data latching on the analog level output by the acquisition module at the captured phase zero-crossing point, so as to eliminate the instantaneous voltage contribution of the power frequency interference fundamental wave at the zero-crossing moment.

[0009] Furthermore, in the joint decision executed by the microcontroller, the microcontroller uses the ambient temperature parameter to perform temperature compensation on the pressure parameter to obtain the equivalent pressure at the standard reference temperature, and obtains the slope of the equivalent pressure change within the continuous sampling period through discrete difference operation. The transmission condition is that the slope of the pressure change is greater than the preset leakage alarm threshold, and the terminal voltage of the supercapacitor is greater than the minimum energy storage mapping threshold required to maintain a single concurrent communication.

[0010] Furthermore, the microcontroller integrates a direct memory access controller. Once the transmission conditions are met, the microcontroller assembles the byte stream containing ambient temperature parameters, pressure parameters, and terminal voltage into a data packet, maps the source memory address to the direct memory access controller, and the direct memory access controller directly transmits the data packet to the data transmission register of the communication module to perform burst transmission. During concurrent bus transmission, the microcontroller's central processing unit core cuts off the peripheral bus clock and enters a deep sleep mode.

[0011] Furthermore, the switching circuit includes a P-channel metal-oxide-semiconductor field-effect transistor and a level-shifting drive stage composed of an NPN transistor; The source of the field-effect transistor is connected to the power supply terminal of the supercapacitor, and the drain is connected to the power input terminal of the communication module. The microcontroller’s general-purpose input / output pins are connected to the gate of the field-effect transistor via a level shifting driver stage, which is used to output a cut-off command during non-communication periods to turn off the field-effect transistor and cut off the static leakage current of the communication module.

[0012] Furthermore, the wired communication unit includes an RS485 module and an Ethernet chip, and the wireless communication unit includes a LoRa module; The microcontroller is equipped with a hardware timer to configure the communication baud rate and bus clock frequency of the RS485 module, LoRa module and Ethernet chip under a unified time base.

[0013] Furthermore, the microcontroller calculates the physical duration required to send a single frame message based on the total number of valid bytes pushed in by the direct memory access controller, the length of the underlying physical frame per byte, and the physical transmission baud rate. The microcontroller configures an independent RF sleep timer based on the calculated physical duration. When the RF sleep timer overflows and the internal transmit shift register is cleared, the microcontroller immediately controls the switching circuit to disconnect the power supply, forcing the communication module to enter a one-way transmission mode that only transmits and does not receive.

[0014] Furthermore, after the microcontroller acquires the data queue formed by discrete data latches in multiple power grid cycles, it performs a composite numerical filter that combines moving average and median elimination to extract the effective temperature smoothing value and effective pressure smoothing value of the current sampling cycle.

[0015] Furthermore, the microcontroller integrates a hardware coprocessor; Before transmitting data packets through the direct memory access controller, the microcontroller uses a hardware coprocessor to generate a cyclic redundancy check code for the byte stream and appends it to the end of the data packet frame.

[0016] Furthermore, the switching circuit is internally configured with a charging current limiting network consisting of a soft-start capacitor and multiple resistors connected in series and parallel, which is used to smooth the surge current by utilizing the capacitor's charging and discharging response when the control field-effect transistor is turned on.

[0017] A second aspect of the present invention provides a method for monitoring SF6 density with multi-source data communication, comprising the following steps: S10, the microcontroller responds to the timer wake-up interrupt and enters the zero-crossing monitoring state. When the zero-crossing detection circuit captures the phase origin of the secondary voltage signal of the power grid and outputs a trigger signal, the microcontroller starts the internal conversion clock, continuously reads the output level of the pressure sensor and temperature sensor within the set phase interval, and stores the corresponding digital quantity into the memory area. S20, the microcontroller executes an alternating cycle of sleep and external interrupt wake-up until a preset number of power grid cycle data acquisitions are completed, and performs arithmetic calculations on the data set in the memory area to obtain the final effective pressure value and the final effective temperature value of the current acquisition cycle. S30: The microcontroller obtains the current terminal voltage value of the supercapacitor, reads the historical effective pressure value stored in the non-volatile memory, calculates the slope of change between the final effective pressure value and the historical effective pressure value, compares the slope of change with a preset threshold, sets the number of consecutive transmissions of communication messages based on the comparison result, and outputs a level control signal to the switching circuit to control the on / off state of the communication power supply circuit. S40, the microcontroller converts the final effective pressure value, the final effective temperature value, and the current terminal voltage value into floating-point format, and encapsulates the floating-point number, preset data header, device identification code, and cyclic redundancy check code into a continuous transmission message; In S50, the microcontroller maps the memory address segment of the transmitted message to the source address register of the direct memory access controller, points the destination address register to the data transmission register of the communication module, and sends a start command to the direct memory access controller. After the kernel enters a sleep state, when the hardware bus generates a transmission completion interrupt, the microcontroller controls the switching circuit to reset to the open state and updates the historical effective pressure value in the non-volatile memory.

[0018] This invention provides an SF6 density monitoring system with multi-source data communication capabilities. It offers the following advantages: 1. This invention captures the phase origin of the secondary voltage signal of the power grid through a zero-crossing detection circuit. The microcontroller responds to the zero-crossing signal and triggers the analog-to-digital converter to sample the data at this moment. Since the instantaneous value of the external 50 Hz power frequency interference voltage approaches zero at the zero-crossing moment, this sampling mechanism suppresses the interference of power grid electromagnetic radiation and conducted coupling on the weak analog signal of the sensor from the hardware source, thereby improving the accuracy of the underlying data acquisition.

[0019] 2. This invention utilizes the collected ambient temperature to perform temperature compensation on the pressure parameter, calculating the equivalent pressure at the standard reference temperature, and obtaining the slope of the equivalent pressure change through discrete difference calculation. The microcontroller combines this dynamic slope with the current terminal voltage of the supercapacitor as a condition for activating communication. This processing method eliminates false alarms caused by gas static pressure changes due to normal fluctuations in ambient temperature, and also avoids unnecessary power consumption caused by the system forcibly activating high-power communication peripherals when energy storage is insufficient.

[0020] 3. In the data transmission phase, this invention employs a direct memory access controller to transmit messages to the data transmission register of the communication module, enabling the microcontroller core to cut off the clock and enter a deep sleep mode during concurrent bus transmission. Simultaneously, the microcontroller calculates the physical transmission time based on the transmission baud rate and message length, and immediately controls the switching circuit to cut off the power supply to the communication module after data transmission is complete. This hardware-coordinated flow mechanism reduces processor wake-up time and eliminates static leakage current from multi-source communication peripherals in idle states, thereby reducing the overall system power consumption. Attached Figure Description

[0021] Figure 1 This is a system architecture diagram of the present invention; Figure 2 This is a flowchart of the method of the present invention.

[0022] Among them, 10 is a microcontroller; 20 is a power management module; 30 is a supercapacitor; 40 is a data acquisition module; 41 is a pressure sensor; 42 is a temperature sensor; 50 is a zero-crossing detection circuit; 60 is a communication module; 61 is an RS485 module; 62 is a LoRa module; 63 is an Ethernet chip; 70 is a switching circuit; 80 is a density relay; and 81 is a DC node. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Example: Please see the appendix Figure 1 This invention provides an SF6 density monitoring system with multi-source data communication, including a microcontroller 10, a power management module 20, a supercapacitor 30, a data acquisition module 40, a zero-crossing detection circuit 50, a communication module 60, and a switching circuit 70.

[0025] The input terminal of the power management module 20 is connected to the DC node 81 of the density relay 80. The output terminal of the power management module 20 is connected to the input terminal of the supercapacitor 30.

[0026] The supercapacitor 30 is connected to the power supply terminals of both the microcontroller 10 and the communication module 60. The microcontroller 10 is equipped with an analog-to-digital converter pin, which is connected to the terminal voltage detection node of the supercapacitor 30.

[0027] The data acquisition module 40 includes a pressure sensor 41 and a temperature sensor 42. The signal output terminals of the pressure sensor 41 and the temperature sensor 42 are connected to the analog-to-digital converter interface of the microcontroller 10. The input terminal of the zero-crossing detection circuit 50 is connected to the secondary voltage signal loop of the power grid, and the output terminal of the zero-crossing detection circuit 50 is connected to the external interrupt pin of the microcontroller 10.

[0028] The communication module 60 includes an RS485 module 61, a LoRa module 62, and an Ethernet chip 63. The serial port transmit pins of the microcontroller 10 are connected to the RS485 module 61 and the LoRa module 62, respectively. The Ethernet media access control interface of the microcontroller 10 is connected to the Ethernet chip 63.

[0029] The switching circuit 70 is connected in series between the supercapacitor 30 and the power supply circuit of the Ethernet chip 63, and the general-purpose input / output pins of the microcontroller 10 are connected to the control terminal of the switching circuit 70.

[0030] Please see the appendix Figure 2 This invention provides a method for monitoring SF6 density with multi-source data communication, comprising the following steps: S10, the microcontroller 10 responds to the timer wake-up interrupt and enters the zero-crossing monitoring state. When the zero-crossing detection circuit 50 captures the phase origin of the secondary voltage signal of the power grid and outputs a trigger signal, the microcontroller 10 starts the internal conversion clock, continuously reads the output level of the pressure sensor 41 and the temperature sensor 42 within the set phase interval, and stores the corresponding digital quantity into the memory area of ​​the microcontroller 10. S20, the microcontroller 10 executes an alternating cycle of sleep and external interrupt wake-up until a preset number of power grid cycle data acquisitions are completed, and performs arithmetic calculations on the data set in the memory area to obtain the final effective pressure value and the final effective temperature value of the current acquisition cycle. S30, the microcontroller 10 obtains the current terminal voltage value of the supercapacitor 30, reads the historical effective pressure value stored in the non-volatile memory, calculates the change slope between the final effective pressure value and the historical effective pressure value, compares the change slope with a preset threshold, sets the number of consecutive transmissions of the communication message according to the comparison result, and outputs a level control signal to the switching circuit 70 to control the on / off state of the power supply circuit of the Ethernet chip 63. S40, the microcontroller 10 converts the final effective pressure value, the final effective temperature value, and the current terminal voltage value into floating-point format, and encapsulates the floating-point number, preset data header, device identification code, and cyclic redundancy check code into a continuous transmission message; S50, the microcontroller 10 maps the memory address segment of the transmitted message to the source address register of the direct memory access controller, points the target address register of the direct memory access controller to the data transmission register of the communication module 60, and sends a start instruction to the direct memory access controller. After the microprocessor core enters a sleep state, when the hardware bus generates a transmission completion interrupt, the microcontroller 10 controls the switch circuit 70 to reset to the open state and updates the historical effective pressure value in the non-volatile memory.

[0031] In this embodiment, the power management module 20 is used to extract power from the field DC system without power interruption. Internally, it includes a high-voltage power extraction network, a current-limiting conversion circuit, and an isolation output circuit. The specific steps for the power management module 20 to acquire power include: S101, the input terminal of the power management module 20 is connected to the DC node 81 of the density relay 80. As a preferred embodiment, the DC node 81 is a normally open 220V DC contact in the field. The positive terminal of the power management module 20 is connected to the DC node 81, and the negative terminal is connected to the grounding grid. This normally open contact is chosen as the voltage input source because a stable potential difference exists between its two ends when the relay is not in operation. This physical connection topology obtains the basic voltage source without affecting the safety of the original mechanical tripping circuit of the density relay 80.

[0032] S102, the current limiting conversion circuit, forces the input-side DC current to be below 20 microamps through hardware impedance matching. The current limiting conversion circuit consists of a voltage divider network composed of multiple high-voltage thick-film resistors connected in series and a low-power step-down regulator chip. The voltage divider network is connected in series between DC node 81 and the input terminal of the low-power step-down regulator chip.

[0033] Based on the general technical principle of Ohm's law for closed circuits, the specific calculation of the DC current drawn from the input side satisfies the following relationship: ; In the formula, This is the DC current drawn from the input side. This is the supply voltage at DC node 81, and its value is typically between 110 volts and 220 volts DC. This is the clamping start voltage at the input of the low-power step-down regulator chip, which is usually fixed to a conventional low voltage value according to the internal specifications and structure of the chip. This is the equivalent total series resistance of the voltage divider network.

[0034] To ensure the physical safety and logical integrity of the division operation, the current limiting switching circuit is equipped with a physical insulation gap and a breakdown protection structure to prevent damage caused by external overvoltage. A sudden change in resistance approaching zero triggers a short-circuit fault. This formula clarifies the physical causal relationship that the tap current is controlled by the high-impedance network at the front end.

[0035] In this embodiment, the system configures the equivalent series total resistance to be greater than 11 megohms, and uses pure hardware physical characteristics to force the input DC current to be clamped within the specified upper limit of 20 microamps. The 20 microamp threshold is determined based on the insensitive dead zone of the substation DC grounding insulation monitoring device, so as to avoid drawing too much current from DC node 81 and triggering the substation DC grounding alarm.

[0036] The S103 low-power step-down regulator chip delivers the stepped-down low-voltage DC power to the isolated output circuit. The isolated output circuit includes a microampere-level isolation transformer and a reverse-biased diode. The low-voltage DC power is electrically isolated between the primary and secondary circuits by the microampere-level isolation transformer. After rectification by the reverse-biased diode, the isolated DC power flows out from the output terminal of the power management module 20.

[0037] The power management module 20 provides a continuous charging current to the subsequent supercapacitor 30 at its output terminal. A reverse-biased diode is used to block the reverse discharge current from the supercapacitor 30 from flowing back to the power management module 20 during concurrent communication in the system, ensuring unidirectional energy transfer.

[0038] The above design effectively avoids the voltage pull and interference of the high-impedance power supply network caused by the instantaneous power consumption peaks generated when the system is in concurrent communication mode. As for the switching frequency modulation logic inside the low-power step-down regulator chip and the specific winding process of the isolation transformer, those skilled in the art can perform conventional matching according to switching power supply design specifications. Its internal topology is well-known in the field and will not be elaborated upon here.

[0039] In this embodiment, the supercapacitor 30 is used to continuously collect and accumulate the meager energy from the power management module 20 during the system's deep sleep period, and to support the transient operation of high-power peripherals after the system wakes up.

[0040] Based on the aforementioned energy throughput requirements, the specific configuration and implementation steps of the supercapacitor 30 include: S201, construct the supercapacitor 30 as the charging and discharging physical node that serves as the sole energy source for bursty concurrent communication within the system. The low-voltage DC node output from the power management module 20 is directly fed into the positive terminal of the supercapacitor 30.

[0041] As a preferred approach, the supercapacitor 30 employs a farad-level double-layer capacitor with low equivalent series resistance. The physical reason for choosing this specific energy storage element is that the limited power supply network at the front end (20 microamps) cannot directly drive the RF components and Ethernet chips with peak power consumption reaching hundreds of milliamps. The system must rely on the instantaneous high current release capability of the supercapacitor 30 to compensate for the power gap.

[0042] In a burst of concurrent communication, the total effective physical energy released by the supercapacitor 30 to complete a single data transmission task is determined by the general technical principle of capacitor energy storage integration: ; In the formula, The total physical energy consumed in a single concurrent communication action; The nominal physical capacitance of the supercapacitor 30, combined with the charging integral and leakage current tolerance during the system's sleep cycle, is set to a range of 0.47 farads to 2.0 farads. The initial terminal voltage of the supercapacitor 30 is instantaneously issued for concurrent communication commands. Its upper limit is constrained by the clamping value of the front-end step-down regulator chip, which is usually 2.5 volts to 3.3 volts. This is the cutoff voltage of supercapacitor 30 when the data packet transmission is complete. It is determined based on the safety threshold triggered by the microcontroller's internal undervoltage reset hardware, typically ranging from 1.8V to 2.0V. This formula clarifies that the system's communication endurance is directly limited by the physical nature of the available voltage drop range at the capacitor's terminals, providing a hardware parameter basis for subsequent dynamic scheduling algorithms based on energy states.

[0043] S202 configures the hardware power supply network connection between the two ends of the supercapacitor 30 and the power pins of the microcontroller 10 and the communication module 60. The positive terminal of the supercapacitor 30 branches out two independent power buses to the subsequent circuitry.

[0044] The first power bus is connected to the power supply pin of the microcontroller 10 via a low-dropout linear regulator. The purpose of this isolated routing design is to shield the voltage drop fluctuations caused by the supercapacitor 30 during violent discharge, and to ensure the absolute stability of the microprocessor core's voltage level during logic operations.

[0045] The second power bus, acting as a high-current network, is connected to the external power supply pins of the communication module 60, which includes an RS485 transceiver and a LoRa RF antenna. Regarding the construction of the error amplifier and the matching mechanism of the reference voltage source within the low-dropout linear regulator, those skilled in the art can perform conventional selection and configuration based on the operating tolerances of the microcontroller. Its voltage regulation closed-loop control circuit is well-known in the field and will not be elaborated upon here.

[0046] S203 establishes a signal attenuation voltage divider structure between the voltage detection circuit led out from the positive terminal of the supercapacitor 30 and the analog-to-digital converter pin of the microcontroller 10. During the wake-up cycle, the system microcontroller 10 must read the available energy storage status in real time to determine the current operating condition. Since the operating voltage of the supercapacitor 30 is typically higher than the safe input threshold of the analog-to-digital converter inside the microcontroller 10, a resistive network is set in the voltage detection circuit for voltage attenuation.

[0047] Based on the general principle of voltage division in series circuits, the mapped test voltage received by the acquisition channel of microcontroller 10 satisfies the following relationship: ; In the formula, The mapped test voltage is the actual sampled pin of the microcontroller's analog-to-digital converter. Its amplitude is strictly constrained by the upper limit of the microcontroller's internal reference voltage, and is typically between 0 and 3.3 volts. This represents the actual physical terminal voltage of supercapacitor 30 at the current moment. This refers to the high-side voltage divider resistor near the voltage input terminal in the signal attenuation voltage divider structure. This is the low-side voltage divider resistor located near the common ground terminal. It's there to cut off the continuous static energy dissipation from the voltage divider circuit on the meager energy stored inside supercapacitor 30. and The values ​​are all set in the megaohm range according to the static power consumption control specifications.

[0048] To ensure the physical safety and logical integrity of division operations, and considering that component failure under extreme conditions may lead to changes in the denominator term... + When the value approaches 0, a current-limiting fuse resistor is connected in series on the input side of the detection circuit to ensure that the denominator is always greater than zero when any single device experiences a hardware breakdown short circuit.

[0049] To ensure the alignment of operating conditions for multi-source heterogeneous data, the microcontroller 10 pairs The sampling action and the acquisition action of physical quantities by the front-end sensors are triggered synchronously within the same time window, ensuring a strict correspondence between the energy state and the physical state in the time dimension. In the final output scheduling determination phase, the system is based on the terminal voltage. The available energy dimension of feedback and the physical change rate dimension acquired by the sensor are jointly weighted for evaluation, avoiding the one-sided judgment that relies on a single extreme value (such as only low voltage or only pressure fluctuation) and causes system deadlock or false alarm.

[0050] After the microcontroller 10 obtains a stable mapped test voltage, it can use internal multiplication instructions to back-calculate the core criterion variables used for state machine scheduling.

[0051] In this embodiment, the acquisition module 40 is used to acquire the physical state of sulfur hexafluoride gas inside the gas-insulated metal-enclosed switchgear in real time, thereby providing basic data support for subsequent characteristic value calculation and system communication scheduling.

[0052] Based on this data acquisition requirement, the specific implementation steps of the data acquisition module 40 include: S301, determine the physical mounting positions of pressure sensor 41 and temperature sensor 42 on the chamber side of the gas-insulated metal-enclosed switchgear.

[0053] As a preferred method, the metal casing of the gas-insulated metal-enclosed switchgear has a standard mechanical measurement tee interface. The pressure sensor 41's pressure port is screwed into the tee interface through a threaded seal, directly contacting the internal sulfur hexafluoride gas to sense physical pressure. The probe of the temperature sensor 42 is attached to the outer wall of the metal base of the tee interface through thermally conductive silicone grease, for equivalent measurement of the temperature environment inside the gas chamber.

[0054] The physical reason for choosing pressure and temperature as specific input parameters is that the actual density of sulfur hexafluoride gas in a closed chamber is affected by the combined effect of gas pressure and ambient temperature. A single pressure drop may only be caused by normal ambient cooling rather than actual gas leakage.

[0055] The system must subsequently be jointly evaluated based on multi-dimensional logic of pressure and temperature to avoid one-sided judgments that rely solely on pressure extreme values. This mounting method ensures the homogeneity of the spatial distribution of multiple physical quantities and avoids joint compensation measurement deviations caused by uneven temperature gradient distribution inside the air chamber.

[0056] S302 configures the circuit routing between the analog level output pins of pressure sensor 41 and temperature sensor 42 and the analog-to-digital converter interface of microcontroller 10. The independent analog signal output pins of pressure sensor 41 and temperature sensor 42 are connected to the corresponding independent analog-to-digital converter input pins of microcontroller 10 via a signal conditioning circuit including an RC low-pass filter. Based on the general principle of analog-to-digital conversion, microcontroller 10 converts the received analog voltage into a digital value in its internal registers, and the conversion relationship satisfies: ; In the formula, This is the final digital conversion result latched in the internal registers of the microcontroller 10. The actual analog voltage output by the sensor and fed into the corresponding pin through a signal conditioning network is typically limited to 0 to 1. between; The reference voltage for the internal analog-to-digital converter of the microcontroller 10 is typically clamped at 3.0 volts or 3.3 volts by a dedicated high-precision voltage regulator, thus eliminating the risk of logical errors where the denominator approaches 0 from the physical circuit perspective. The hardware conversion resolution bits for the analog-to-digital converter, combined with the bus width of an industrial-grade microcontroller, are typically set to 12 or 16. This formula describes the mathematical process of discretizing a continuous physical quantity into digital features that the microcontroller can process.

[0057] Considering the strong electromagnetic environment at the substation site, the wiring design on the printed circuit board implements single-point isolation connection between analog ground and digital ground to prevent high-frequency digital noise from entering the analog sampling front end through the common ground loop. Regarding the specific wiring of the Wheatstone bridge inside the pressure sensor 41 and the selection and matching of the measurement operational amplifier, those skilled in the art can perform conventional design based on the measurement range. Its internal physical sensing mechanism is well-known in the field and will not be elaborated upon here.

[0058] S303 configures the power-on wake-up timing and sampling setup time parameters of the sensor when the microcontroller 10 exits sleep mode. Due to the extremely low input power draw of 20 microamps at the front end, the system cuts off the physical power supply to the acquisition module 40 during non-sampling periods. When the microcontroller 10 responds to the timer wake-up interrupt, the general-purpose input / output pins of the microcontroller 10 output a high-level drive signal, closing the power supply circuit of the sensor.

[0059] To ensure the alignment of multi-source heterogeneous data under operating conditions and to eliminate power-on transient jitter errors, the microcontroller 10 forces its core to execute a microsecond-level hardware delay instruction after the power supply circuit is turned on. This delay time is defined as the sampling setup time, and its value must be strictly greater than the minimum electrical response time required for the sensor's internal sensing element and signal conditioning circuit to establish a stable output. It is typically set between 50 and 200 microseconds, and this time threshold is determined based on the slew rate of the front-end measurement operational amplifier and the charging and discharging time constant of the filter capacitor. After this sampling setup time has elapsed, the analog-to-digital converter of the microcontroller 10 is allowed to trigger the front-end sample-and-hold circuit and start the array conversion.

[0060] After the multi-channel conversion is completed, the microcontroller 10 immediately cancels the power supply drive signal to the acquisition module 40, thereby strictly limiting the working life of the high-power sensing component to an extremely short time window. This fragmented power supply control logic based on forced timing alignment not only ensures the absolute synchronous latching of pressure and temperature data in the time dimension, but also prevents the static energy loss of the system at the source.

[0061] In this embodiment, the zero-crossing detection circuit 50, as an innovative collaborative hardware component supporting multi-source data condition alignment and low-power scheduling in this invention, is used to extract the phase characteristics of power frequency interference in the field power grid and provide the microcontroller 10 with an accurate fragmented synchronous sampling reference.

[0062] Based on the above synchronous triggering requirements, the specific implementation steps of the zero-crossing detection circuit 50 include: S401 is a hardware matching network configured with the zero-crossing detection circuit 50 input terminal connected in parallel to the secondary voltage signal loop of the corresponding phase of the power grid.

[0063] As a preferred approach, the secondary side of the voltage transformer at the substation outputs a standard AC voltage. The input side of the zero-crossing detection circuit 50 is connected in parallel with this secondary voltage signal circuit using a high-impedance attenuation network. The physical reason for choosing a high-impedance network as the specific access structure is that the system must strictly limit the measurement leakage current drawn from the secondary circuit of the voltage transformer to avoid affecting the metering accuracy of the original relay protection device due to load pull-down.

[0064] Meanwhile, the physical reason for choosing the secondary voltage of the power grid as a specific extraction parameter is that the 50 Hz power frequency alternating magnetic field at the substation site is the main common-mode interference source affecting the weak output level of the pressure sensor. By directly extracting the physical phase characteristics of the power grid voltage, the fluctuation pattern of the external interference magnetic field can be accurately mapped in the time dimension.

[0065] This attenuation network utilizes passive voltage divider characteristics to proportionally scale a high-voltage AC sine wave to a low-voltage AC sine wave, thereby satisfying the safe common-mode input range of subsequent semiconductor devices.

[0066] S402 is a hardware comparison logic that converts the acquired 50 Hz power frequency analog sine wave into a digital square wave trigger signal with a phase origin marker. The low-voltage AC sine wave, after passing through an attenuation network, is input to the non-inverting input of a zero-crossing comparator. The inverting input of the zero-crossing comparator is connected to the system's analog reference ground potential.

[0067] Based on the general technical principle of analog signal comparison, the mathematical decision process for the zero-crossing detection circuit 50 to extract phase features satisfies the following piecewise function: ; In the formula, This represents the actual digital level state of the zero-crossing comparator output port; The instantaneously decaying sinusoidal voltage is input to the non-inverting input of the comparator; The absolute zero-phase reference voltage set for the inverting input of the comparator is strictly and fixedly configured to 0 volts in this embodiment; This is the high-level logic threshold of the system, and its value is usually set to 3.3 volts based on the voltage withstand rating of the microcontroller's input and output pins. The system's low-level logic threshold is fixed at 0 volts. This formula clarifies the physical mechanism by which a continuous waveform undergoes discrete level reversals when crossing a zero-potential point.

[0068] To prevent high-frequency oscillations in the comparator output caused by glitches near the zero-crossing point of the mains voltage, a positive feedback hysteresis resistor network is configured around the zero-crossing comparator to form a Schmitt trigger topology. The hysteresis threshold is determined based on the peak value of the fundamental electromagnetic interference noise measured in the field, and is typically set between ±50 millivolts. This hardware conversion logic eliminates the interference of mains voltage amplitude fluctuations on the phase extraction operation, ensuring that the edges of the output digital square wave are strictly aligned with the physical phase origin of the fundamental frequency interference.

[0069] S403 configures the physical bonding and trigger edge polarity between the digital square wave trigger signal pin and the external interrupt pin of the microcontroller 10. The output of the zero-crossing detection circuit 50 is directly connected to the designated external interrupt trigger pin of the microcontroller 10 through a current-limiting resistor. The internal interrupt controller of the microcontroller 10 configures this external interrupt trigger pin in a double-edge capture mode. When the secondary voltage signal of the mains crosses zero from the negative half-cycle into the positive half-cycle, the zero-crossing comparator output transitions from low to high and triggers a rising-edge hardware interrupt. Similarly, when the voltage crosses from the positive half-cycle to the negative half-cycle, a falling-edge hardware interrupt is triggered.

[0070] Through the aforementioned dual-edge capture logic, the system can acquire two phase origin markers with an exact interval of 10 milliseconds within each 50 Hz power grid cycle. The microcontroller 10 forcibly wakes its core from deep sleep state based on this external interrupt signal, thereby strictly locking the subsequent analog-to-digital conversion operation within a very small phase window near the zero-crossing point of the interference fundamental frequency.

[0071] This operating condition forced alignment logic based on pure hardware interrupts not only completely eliminates the time delay and phase jitter caused by software polling, but also enables the synchronous extraction of multi-source pressure and temperature data at the optimal physical observation point where the rate of change of external interference magnetic flux approaches zero. The final signal validity determination of the system is based on a multi-dimensional constraint of phase locking and amplitude discrete sampling, effectively avoiding data distortion caused by capturing a single extreme value at a random non-zero phase angle due to external transient electromagnetic shocks.

[0072] For the specific power supply decoupling capacitor configuration of the zero-crossing comparator chip and the parameter matching of the high-frequency bypass capacitor at the input end, those skilled in the art can perform conventional design based on the parasitic parameters of the printed circuit board. Its hardware filtering matching is a well-known technology in the field and will not be described in detail here.

[0073] In this embodiment, the switching circuit 70, as an innovative collaborative hardware component for controlling the lifecycle of high-power communication peripherals in this invention, is used to completely cut off the static leakage current of the Ethernet physical layer chip during non-communication periods, thereby maintaining the overall low-power energy storage balance of the system. Based on the aforementioned requirement for physical layer cutoff, the specific implementation steps of the switching circuit 70 include: S501 constructs a physical isolation topology between the supercapacitor 30 and the power input terminal of the Ethernet chip 63, with the switching circuit 70 connected in series.

[0074] As a preferred approach, the high-current discharge bus of the supercapacitor 30 is connected to the core power supply pin and input / output ring network power supply pin of the Ethernet chip 63 through the switching channel within the switching circuit 70. The physical reason for choosing to implement independent power management for the Ethernet chip 63 is that even when the Ethernet chip is in a deep sleep mode configured by software, its internal phase-locked loop and physical layer bias circuit will still maintain a leakage current in the milliampere range.

[0075] The leakage current is far greater than the 20 microamps of power that the front-end power management module 20 can provide. Without a forced physical isolation, the system's limited energy storage will be quickly depleted. Based on this physically isolated topology, the system has established a hardware power supply gate, which, together with multi-dimensional criteria, performs underlying energy allocation.

[0076] S502 configures the level drive relationship between the gate of the internal metal-oxide-semiconductor field-effect transistor (MOSFET) of the switching circuit 70 and the general-purpose input / output pin of the microcontroller 10. The core actuator of the switching circuit 70 is a low-on-resistance P-channel MOSFET. The source of this MOSFET is connected to the power supply network of the supercapacitor 30, and the drain is connected to the power input terminal of the Ethernet chip 63.

[0077] The general-purpose input / output pins of microcontroller 10 are connected to the gate of the field-effect transistor via a level-shifting driver stage composed of NPN transistors. Based on the general technical principle of the on-resistance characteristics of the field-effect transistor, the static voltage drop loss during the conduction period of the switching circuit 70 satisfies the following relationship: ; In the formula, The static voltage drop loss generated by the switching circuit 70 in the on state is strictly limited to a safety tolerance that ensures the Ethernet chip 63 does not experience undervoltage abnormality. The dynamic load current of Ethernet chip 63 when it is in full-speed transmission mode, combined with the driving requirements of the local area network transformer, usually fluctuates between 50 mA and 150 mA. It is the equivalent on-resistance of the field-effect transistor under a specific gate-source drive voltage.

[0078] To limit static voltage drop within safe tolerances, the selection of MOSFETs is based on the low gate-source voltage range of 1.8V to 3.3V. The value must be less than 50 milliohms. This formula clarifies the physical mechanism for selecting low on-resistance devices to reduce energy transfer losses, ensuring that the effective energy storage of the supercapacitor 30 can be transferred to communication peripherals with maximum efficiency.

[0079] S503 executes the timing sequence of physical layer hard cutoff and asynchronous hard power-on according to the digital instructions output by microcontroller 10. During the system's default fragmented data acquisition cycle, microcontroller 10 continuously outputs low-level digital instructions, controlling the field-effect transistor to be in a reliable cutoff region through the level conversion driver stage, thus executing physical layer hard cutoff. At this time, Ethernet chip 63 is in a zero-power physical power-off state.

[0080] When the microcontroller 10 performs a multi-dimensional weighted evaluation based on the terminal voltage energy state of the supercapacitor and the rate of change of the sensor's physical state, and determines that the high-frequency alarm threshold is met, the microcontroller 10 outputs a high-level digital command to trigger an asynchronous hard power-on action.

[0081] The physical causality of using terminal voltage and physical rate of change as joint criteria is that a simple physical anomaly cannot complete the transmission of a long message without sufficient available energy, while sufficient energy without a real physical anomaly will not trigger high-energy-consuming network actions. The system must be based on a weighted logic of both to avoid invalid power-up and system deadlock caused by fluctuations in a single extreme value.

[0082] To prevent the massive inrush current during a hard power-on from causing a voltage drop at the supercapacitor 30 that could trigger a system core reset, the switching circuit 70 is internally equipped with a soft-start capacitor and a charging current-limiting resistor network. Based on the general principles of dynamic response in first-order RC circuits, the decay law of the inrush current during a hard power-on over time satisfies: ;

[0083] In the formula, The surge current flowing through the MOSFET at power-on instant as a function of time The changing transient value; The duration calculated from the moment the asynchronous hard power-on action is triggered; It is the base of the natural logarithm; The actual physical terminal voltage of supercapacitor 30 at the moment of triggering the asynchronous hard power-on action; This is the equivalent resistance of the power-on current-limiting resistor network; This is the capacitance value of the soft-start capacitor.

[0084] To ensure the physical safety and algorithmic integrity of the division operation, the power-on current-limiting resistor network employs a physical redundancy design with multiple resistors connected in series and parallel. This ensures that even if any single resistor fails and short-circuits under extreme conditions, the denominator term remains constant. The parameters do not approach zero, thus forcibly maintaining the hardware's surge suppression capability. This formula reveals the technical purpose of smoothing surge current spikes by adjusting the hardware's charging and discharging parameters.

[0085] To ensure time alignment between communication tasks and physical states, after issuing a hard power-on command, the microcontroller 10 forces the kernel to suspend and waits for a preset soft-boot setup time before initializing, resetting, and configuring the registers of the Ethernet chip 63 via the media access control interface. Once the underlying data packets have been physically transported and successfully transmitted via the direct memory access controller, the microcontroller 10 immediately cancels the high-level command, and the MOSFETs return to their hard-off state.

[0086] For the configuration of the base bias resistor of the transistor in the level conversion driver stage and the selection of the bleeder resistor between the gate and source of the field-effect transistor, those skilled in the art can make conventional designs based on the output driving capability of the microprocessor. Its switching amplification bias is a well-known technology in the field and will not be described in detail here.

[0087] In this embodiment, the communication module 60 serves as the physical carrier for data interaction between the system and the external system, and is used to burst-up transmit the physical status data of the gas-insulated metal-enclosed switchgear to the remote master station under extremely low power consumption constraints.

[0088] Based on the aforementioned requirement for one-way burst data transmission, the specific implementation steps of the communication module 60 include: S601 clarifies the physical interface definitions between the RS485 module 61, the LoRa module 62, and the Ethernet chip 63 and the external communication medium.

[0089] As a preferred approach, the differential signal output of RS485 module 61 is connected to the twisted-pair bus at the substation site via a transient voltage suppression diode array, utilizing the physical characteristics of differential levels to resist common-mode electromagnetic interference. The RF output port of LoRa module 62 is connected to a spring antenna via an impedance matching network, physically coupling it to the spatial electromagnetic wave medium. The transmit and receive differential pair pins of Ethernet chip 63 are connected to a standard network interface via an internally integrated network isolation transformer, thereby enabling access to the substation's wired local area network.

[0090] The physical reason for choosing the above three heterogeneous media as multi-source physical interfaces is that the communication route at the substation site may be unexpectedly interrupted due to large-scale electromagnetic pulses or line aging. The subsequent judgment of sudden messages output by the system must be based on weighted redundancy transmission of multi-dimensional physical links of wired local area network, wired serial bus and wireless radio frequency, so as to avoid losing the system-level alarm capability in emergency conditions by relying on a single communication link.

[0091] S602 configures the serial bus connection structure between the data receive pins and data transmit pins of each hardware module and the corresponding general-purpose synchronous / asynchronous transceiver and media access control interface of the microcontroller 10. The RS485 module 61 and the LoRa module 62 each have their own independent digital data receive pins and digital data transmit pins, which are cross-connected to the transmit and receive ends of the independent general-purpose synchronous / asynchronous transceiver inside the microcontroller 10.

[0092] To block static leakage current between ports during non-communication periods, a low-power bidirectional level isolation chip is connected in series on the serial bus. The physical layer data transceiver pins and independent interface management clock pins of the Ethernet chip 63 are directly connected to the media access control interface integrated inside the microcontroller 10 using a hard-wired method.

[0093] To ensure strict time alignment of multi-source heterogeneous communication links under concurrent transmission conditions, the communication baud rate and bus clock frequency of multi-source heterogeneous data are independently configured in the microcontroller 10 core under a unified hardware timer alignment reference, thereby ensuring the absolute time synchronization of underlying data packet push when multiple communication interfaces are pulled low in parallel.

[0094] S603 executes the communication module 60's unidirectional RF transmission and level-flipping low-level operation process when it receives a byte stream pushed in by the direct memory access controller.

[0095] When the system performs a joint evaluation based on the energy dimension of the available energy storage state of the supercapacitor and the data dimension of the mutation rate of the internal gas physical parameters, it avoids the one-sided judgment that relies only on a single extreme value. After determining that the burst transmission threshold is met and the underlying environmental data is packaged, the microcontroller 10 asynchronously wakes up the communication module 60.

[0096] To minimize the dynamic power consumption of the microcontroller core caused by prolonged resident transmit interrupts, the microcontroller 10 uses its internal direct memory access controller to directly map the source address of the assembled data frame to the data transmit registers of each communication peripheral. Based on the general technical principles of serial communication underlying timing, the underlying physical duration required for the communication module 60 to complete the transmission of a single frame message satisfies the following relationship: ; In the formula, The total time consumed for communication module 60 to perform a one-way burst transmission task; The total number of valid bytes continuously pushed into the communication data register by the direct memory access controller; The length of a single-byte underlying physical frame, including start bit, data bits, parity bit and stop bit, is fixed at 10 or 11 according to the industry standard serial communication format. The physical transmission baud rate configured for a general synchronous asynchronous transceiver is typically set between 9600 and 115200 bits per second, depending on the field transmission distance and anti-interference requirements.

[0097] To ensure the physical security and algorithmic integrity of division operations, a non-zero baud rate hardware assertion verification logic is forcibly configured in the system initialization firmware layer, completely avoiding the divisor from being corrupted by extreme interference at the underlying memory structure level. The watchdog reset deadlock anomaly is caused by a mutation approaching 0.

[0098] This calculation formula reveals the physical mechanism that in a field electromagnetic environment with limited baud rate, the transmission time is only proportional to the effective message length. The result of this time calculation is directly used by the microcontroller to control the working window duration of external radio frequency components, thereby precisely tailoring the high-power lifecycle of the communication module.

[0099] The microcontroller 10 calculates based on the above physical causality Configure an independent RF sleep timer and trigger the push operation of the direct memory access controller. At this time, RS485 module 61 and LoRa module 62 only perform the underlying differential level switching and RF carrier transmission operations.

[0100] Time to be calculated After the overflow and the internal transmit shift register is cleared, the system immediately cuts off the module drive power and forces the implementation of half-duplex logic that only transmits and does not receive. This unidirectional blind transmission strategy, which abandons the conventional handshake and retransmission mechanism, completely avoids the high energy loss caused by continuously turning on the RF receiver while waiting for the master station's response.

[0101] For the drive delay control of the internal transmit / receive state switching of the RS485 module, and the inductor-capacitor impedance matching network of the LoRa module's RF front-end power amplifier, those skilled in the art can perform conventional circuit layout design according to the actual transmission distance. The impedance matching and frequency shift keying modulation principles are well-known technologies in the field and will not be elaborated here.

[0102] In this embodiment, the microcontroller 10 serves as the core computing and control hub of the system, used to perform multi-source data fusion and underlying energy routing allocation under extremely low power consumption constraints. Based on the aforementioned hardware-software collaborative management requirements, the specific implementation steps of the microcontroller 10 include: The S701 is configured to execute software execution logic for the microcontroller 10 to respond to zero-crossing interrupts, perform fragmented high-frequency synchronous sampling, and complete multi-level composite numerical filtering.

[0103] As a preferred method, when physically installed, the sulfur hexafluoride gas density data acquisition system is usually mounted on the outer wall of a separate metal chamber of a specific phase of a gas-insulated metal-enclosed switchgear. Therefore, its internal weak signal conditioning network is most severely affected by the near-field electromagnetic coupling of the high-voltage AC level of that phase.

[0104] The 50 Hz power frequency interference at the substation site mainly originates from the spatial radiation and conduction coupling of the aforementioned high-voltage bus. This interference component is not only strictly in phase with the system's power supply voltage, but also maintains a relatively fixed in-phase relationship under an ideal physical conduction path.

[0105] Based on the aforementioned electromagnetic coupling mechanism, the microcontroller 10 locks the phase origin of the system power supply voltage through the zero-crossing detection circuit 50, which is equivalent to precisely calibrating the physical zero-crossing point of the interference fundamental wave on the time axis. Based on the general technical principles of sinusoidal steady-state circuit analysis, the instantaneous value of the power frequency interference fundamental wave of this conducted and radiated coupling satisfies the following mathematical model: ; In the formula, The instantaneous power frequency interference voltage value experienced by the sensor's front end and signal traces; The value is the equivalent physical peak amplitude of the fundamental wave of the power frequency interference. Its magnitude is inversely proportional to the relative spatial distance between the acquisition equipment and the shielding effectiveness of the metal casing. Pi is a constant. The fundamental frequency of the power grid system is fixed at 50 Hz in this embodiment. It is the continuous absolute physical time calculated from the moment the system is powered on; The fixed initial phase shift angle of the interference fundamental frequency relative to the reference power supply voltage.

[0106] The external interrupt hardware logic of the microcontroller 10 strictly ensures that the analog-to-digital conversion sampling action occurs at the moment the power supply voltage crosses zero, at which point the time phase alignment condition is met. ,in The integer index represents the number of zero-crossings in a half-cycle of the power frequency, and its value range is all natural numbers. When this equation holds, the mathematical extremum of the sine function term strictly satisfies... .

[0107] The technical purpose of this mathematical model and operation steps is to force the theoretical physical contribution of the 50 Hz fundamental wave interference to zero in a single data extraction by locking discrete levels within an extremely narrow time window when the spatial interference field strength drops to zero. This directly and completely avoids the transient data distortion caused by random interference peaks encountered by the analog-to-digital converter from the signal source.

[0108] The microcontroller 10 then activates its internal analog-to-digital converter to acquire array data of pressure and temperature within an extremely short time window, thus ensuring absolute consistency in the alignment of multiple physical quantities over time. After acquiring the raw data, the microcontroller 10 performs a composite numerical filter combining moving average and median removal, based on the general principles of discrete-time signal smoothing. To ensure consistency in the time-domain processing of multi-source data, the microcontroller 10 performs independent smoothing recursion for pressure and temperature. Taking pressure as an example, the core smoothing recursion mathematical relationship satisfies: ; In the formula, For the current number The final output pressure smoothing value for each sampling period; For the first in the historical buffer queue The original pressure values ​​collected in each sampling period; The window depth of the sliding filter queue is set to a positive integer between 4 and 16, taking into account the upper limit of the microcontroller's static random access memory capacity and the characteristics of the power frequency cycle.

[0109] To ensure the physical safety and logical integrity of division operations, the system uses low-level macro assertions to forcibly set the window coefficient during the firmware compilation phase. The fact that the value is always greater than zero completely eliminates the risk of kernel division-by-zero resetting anomalies caused by the denominator approaching zero. This calculation formula describes the technical purpose of smoothing transient high-frequency pulse spikes through discrete integral averaging in the time dimension, ensuring the reliability of the data source for subsequent extreme value determination. Similarly, the ambient temperature outputs an effective smoothed value after the same logical processing. .

[0110] S702 establishes a mathematical criterion for the microcontroller 10 to extract the slope of pressure change based on historical records and combine it with the voltage at the terminal of the supercapacitor 30 to perform dynamic redundancy scheduling and state control of the switching circuit 70. The microcontroller 10 not only focuses on the absolute static pressure value at the current moment, but also needs to extract dynamic physical characteristics that characterize the gas leakage rate.

[0111] Based on the general technical principle of isochoric gas state change, in order to eliminate measurement interference caused by ambient temperature fluctuations, the microcontroller 10 performs temperature compensation using a temperature smoothing value acquired synchronously with the pressure, converting the static absolute pressure value into an equivalent pressure at a standard reference temperature. Its temperature compensation logic satisfies: ; In the formula, For the current number Standard equivalent pressure value after temperature compensation for each sampling period; This represents the effective smoothed value of the ambient temperature sampled within the corresponding period; The standard reference temperature set for industrial regulations is fixed at 20 degrees Celsius. It is the thermodynamic temperature compensation coefficient for sulfur hexafluoride gas. Its value is physically calibrated based on the specific gas density of the gas chamber of the switchgear at the factory, and is usually set between 0.001 and 0.003 MPa per degree Celsius.

[0112] The technical purpose of this calculation step is to utilize temperature, a strongly correlated physical constraint parameter, to eliminate the normal drop in air pressure caused by sudden cooling of the nighttime environment at the algorithm's source, thus avoiding false alarms in subsequent judgment logic due to the lack of a temperature dimension. Subsequently, based on the general technical principle of using discrete difference to approximate continuous first derivatives, the derivation relationship of the pressure change slope satisfies: ; In the formula, The standardized pressure change slope is used to characterize the true rate of sulfur hexafluoride gas leakage. To delay Effective smoothed value of historical standard equivalent pressure for each sampling period; This is the differential time span coefficient, which is determined to overcome the quantization noise floor of the analog-to-digital converter at extremely low sampling rates. Its value is usually set to 100 to 1000. The fixed physical time interval for zero-crossing hardware interrupt triggering is strictly equal to 10 milliseconds in the 50 Hz power grid environment of this embodiment.

[0113] To ensure the completeness of difference operations, in the denominator term and The product is a fixed non-zero constant constrained by the hardware timer, which effectively avoids the logical loophole that the denominator approaches 0 during the calculation process.

[0114] The physical meaning of this formula is to transform the static absolute pressure parameter into a dynamic gas loss rate parameter, providing a first-order dynamic characteristic for early fault warning.

[0115] Subsequently, the microcontroller 10 executes multi-dimensional weighted judgment logic. The physical reason for choosing the pressure change slope and the supercapacitor terminal voltage as joint inputs is that although thermal expansion and contraction interference has been eliminated after temperature compensation, relying solely on sufficient terminal voltage energy would lead to ineffective network idling consumption. The Boolean logic function for determining whether the underlying communication alarm channel is open satisfies: ; In the formula, Boolean trigger variable for controlling the switching circuit 70 to perform asynchronous hard power-on action; A logical AND operator to characterize the simultaneous satisfaction of multidimensional constraints; The slope of the pressure change is calculated in real time; The set equipment leakage alarm threshold is typically set to 0.01 to 0.05 MPa per hour, based on the standard volume of the switchgear air chamber and the substation safety regulations. The usable terminal voltage test value of the supercapacitor after mapping via a resistor network; To maintain the minimum energy storage mapping threshold required for a single complete concurrent Ethernet communication, it is typically set to the analog-to-digital conversion value corresponding to 1.8 volts. The output result is determined based on the logical intersection of multi-dimensional physical and energy states, avoiding one-sided judgments that rely solely on a single extreme value.

[0116] If and only if When the state is true, the microcontroller 10 outputs an effective drive level to the gate of the switching circuit 70.

[0117] The S703 configures the microcontroller 10 to package valid data into floating-point messages containing cyclic redundancy check codes, and initiates the low-level state machine transition process of concurrent transmission of the multi-channel direct memory access controller and deep kernel sleep.

[0118] When the above-mentioned judgment logic triggers the communication action, the microcontroller 10 assembles the standard equivalent pressure value, ambient temperature value, and supercapacitor terminal voltage representing the system health in a continuous memory space according to the standard industrial protocol frame format.

[0119] Based on the general technical principle of polynomial division error detection, the hardware coprocessor of the microcontroller 10 generates a 16-bit cyclic redundancy check code for the entire byte stream to be transmitted and appends it to the end of the frame. This code is used at the receiving end to verify whether there are bit flipping errors caused by electromagnetic interference during long-distance wired or wireless transmission.

[0120] After packet preparation is complete, the microcontroller 10 assigns the source memory address pointer to the internal multi-channel direct memory access controller and independently configures the target transmit register addresses for RS485, LoRa, and Ethernet peripherals. The microcontroller 10 then raises the burst transmission request flag of the direct memory access controller, physically moving the underlying byte stream directly from memory to the internal shift buffers of each communication module.

[0121] During concurrent push streaming on the bus, the CPU core of the microcontroller 10 immediately executes an assembly-level interrupt-waiting instruction, cuts off the high-speed peripheral bus clock, and enters a deep sleep mode.

[0122] This hardware decoupling and state machine transition mechanism allows the kernel to wait for external communication devices to automatically complete the RF carrier transmission and physical layer level switching of long messages with extremely low power consumption at the microampere level, completely avoiding the dynamic energy waste caused by the central processing unit polling and sending status flags for a long time. Until the underlying hardware completes the transmission and the interrupt wakes up the kernel again, the microcontroller 10 immediately performs register cleanup and immediately cancels the drive level to completely cut off the physical power supply to the high-power communication peripherals.

[0123] For the specific selection of the generating polynomial for the Cyclic Redundancy Check (CRC) code and the bus priority arbitration configuration of the Direct Memory Access Controller (DMI), those skilled in the art can perform conventional register operations based on the microcontroller reference manual. The internal bus matrix scheduling rules are well-known technologies in the field and will not be elaborated here.

[0124] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An SF6 density monitoring system with multi-source data communication, characterized in that, include: The power management module is used to obtain and convert electrical energy from an external DC node; A supercapacitor, connected to the power management module, is used to store the converted electrical energy and supply power to the system; The data acquisition module is used to obtain the ambient temperature and pressure parameters of SF6 gas. Zero-crossing detection circuit is used to connect to the secondary voltage signal loop of the power grid and capture the phase zero-crossing signal of the fundamental wave of the power grid; A communication module is used to send data packets to a remote master station. The communication module includes a wired communication unit and a wireless communication unit. A switching circuit is connected in series between the supercapacitor and the power supply circuit of the communication module to control the on / off state of the power supply circuit. The microcontroller is connected to the supercapacitor, the acquisition module, the zero-crossing detection circuit, the switching circuit, and the communication module, respectively. It is used to respond to the phase zero-crossing signal to synchronously read the ambient temperature parameter and the pressure parameter, and perform joint judgment by combining the terminal voltage of the supercapacitor and the pressure change slope calculated from the ambient temperature parameter and the pressure parameter. When the judgment meets the transmission condition, it controls the switching circuit to conduct to supply power to the communication module, and sends the data message through the communication module.

2. The SF6 density monitoring system with multi-source data communication according to claim 1, characterized in that, The microcontroller is internally configured with an external interrupt pin and an analog-to-digital converter. The microcontroller is specifically used to respond to the phase zero-crossing signal output by the zero-crossing detection circuit, wake up the system kernel through the external interrupt pin, and trigger the analog-to-digital converter to perform discrete data latching on the analog level output by the acquisition module at the captured phase zero-crossing point, so as to avoid the influence of transient peak values ​​of power frequency fundamental wave interference on the sampling results.

3. The SF6 density monitoring system with multi-source data communication according to claim 1, characterized in that, In the joint decision executed by the microcontroller, the slope of the pressure change is specifically as follows: The microcontroller uses the ambient temperature parameter to perform temperature compensation on the pressure parameter to obtain the equivalent pressure at the standard reference temperature, and obtains the slope of the change of the equivalent pressure within a continuous sampling period through discrete difference operation. The transmission condition is that the slope of the pressure change is greater than a preset leakage alarm threshold, and the terminal voltage of the supercapacitor is greater than the minimum energy storage mapping threshold required to maintain a single concurrent communication.

4. The SF6 density monitoring system with multi-source data communication according to claim 1, characterized in that, The microcontroller integrates a direct memory access controller. Once the sending conditions are met, the microcontroller assembles the byte stream containing the ambient temperature parameter, the pressure parameter, and the terminal voltage into the data packet, maps the source memory address to the direct memory access controller, and the direct memory access controller directly and physically transports the data packet to the data transmission register of the communication module for burst transmission. During concurrent bus transmission, the microcontroller's central processing unit core cuts off the peripheral bus clock and enters a deep sleep mode.

5. The SF6 density monitoring system with multi-source data communication according to claim 1, characterized in that, The switching circuit includes a P-channel metal-oxide-semiconductor field-effect transistor and a level conversion drive stage composed of an NPN transistor. The source of the field-effect transistor is connected to the power supply terminal of the supercapacitor, and the drain is connected to the power input terminal of the communication module. The general-purpose input / output pins of the microcontroller are connected to the gate of the field-effect transistor via the level shifting driver stage, and are used to output a cut-off command during non-communication periods to turn off the field-effect transistor, thereby cutting off the static leakage current of the communication module.

6. The SF6 density monitoring system with multi-source data communication according to claim 1, characterized in that, The wired communication unit includes an RS485 module and an Ethernet chip, and the wireless communication unit includes a LoRa module. The microcontroller is equipped with a hardware timer to configure the communication baud rate and bus clock frequency of the RS485 module, the LoRa module, and the Ethernet chip under a unified time base, so as to ensure the time synchronization of data transmission when multiple communication interfaces are pulled low in parallel.

7. An SF6 density monitoring system with multi-source data communication according to claim 4, characterized in that, The microcontroller is also used to calculate the physical duration required to send a single frame message based on the total number of valid bytes pushed in by the direct memory access controller, the length of the single-byte underlying physical frame, and the physical transmission baud rate. The microcontroller configures an independent RF sleep timer based on the calculated physical duration. When the RF sleep timer overflows and the internal transmit shift register is cleared, the microcontroller immediately controls the switching circuit to disconnect the power supply, forcing the communication module to implement half-duplex logic of only transmitting and not receiving.

8. An SF6 density monitoring system with multi-source data communication according to claim 2, characterized in that, After acquiring the data queue formed by the discrete data latch in multiple power grid cycles, the microcontroller executes a composite numerical filtering algorithm that combines moving average and median elimination to extract the effective temperature smoothing value and effective pressure smoothing value of the current sampling cycle.

9. An SF6 density monitoring system with multi-source data communication according to claim 4, characterized in that, The microcontroller integrates a hardware coprocessor. Before the microcontroller moves the data packet through the direct memory access controller, it uses the hardware coprocessor to generate a cyclic redundancy check code for the byte stream and appends it to the end of the data packet frame.

10. An SF6 density monitoring system with multi-source data communication according to claim 5, characterized in that, The switching circuit is internally configured with a charging current limiting network consisting of a soft-start capacitor and multiple resistors connected in series and parallel. This network is used to smooth out surge current spikes by utilizing the capacitor's charging and discharging response when the field-effect transistor receives a turn-on command and performs an asynchronous hard power-on operation, thereby preventing transient drops in the terminal voltage of the supercapacitor.

Images